Microprocessor

Microcontroller Systems

Chapter 3-2
I/O ADDRESS
DECODING AND
DESIGN
‫ ﻭﺟﺩﻱ ﺳﻠﻳﻣﺎﻥ ﺍﻟﺣﻠﺑﻲ‬.‫ ﻡ‬.‫ ﺩ‬:‫ﻣﺩﺭﺱ ﺍﻟﻣﺳﺎﻕ‬

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 Outline of the Chapter

 3.11 Introduction
 3.12 Using the 74LS373 in an output port design
 3.13 Input port design using the 74LS244
 3.14 Absolute vs. linear select address decoding
 3.15 Peripheral I/O vs. Memory-mapped I/O

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 Introduction

 In this section, we show the design of simple I/O ports

using TTL logic gates 74LS373 and 74LS244.
 For the purpose of clarity we use simple logic gates such as
AND and inverter gates for decoders.
 The concept of address bus decoding for I/O instructions is
exactly the same as for memory.
 The following are the steps:
1. The control signals IOR and IOW are used along
with the decoder. (In memory mapped I/O, RD and
WR signals are used.)
2. The address bus is decoded.

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 Using the 74LS373 in an output port
design
 In every computer, whenever data is sent out by the CPU
via the data bus, the data must be latched by the receiving
device.
 While memories have an internal latch to grab the data,
 But a latching system must be designed for simple I/O
ports.
 The 74LS373 can be used for this purpose.
 in order to make the 74LS373
work as a latch,
the OC pin must be grounded.

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 Using the 74LS373 in an output port
design
 For an output latch, it is common to AND the output of the
address decoder with the control signal IOW to provide the
latching action as shown in Figures.

Design for Output Port Address 99H. Design for Output Port Address 1FH

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 Input port design using the 74LS244

 when data is coming in by way of a data bus, it must come

in through a three-state buffer. This is referred to as
tristated, which comes from the term tri-state buffer
 As was the case for memory chips, such a tri-state buffer is
internal and therefore invisible.
 For the simple input ports we use
the 74LS244 chip.
 For the internal circuitry of
the 74LS244, We notice that since 1G
and 2G each control only 4 bits of
the 74LS244, they both must be
activated for the 8-bit input.
74LS244 Octal Buffer

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 Input port design using the 74LS244

 Examine Figure_A to see the use of the 74LS244 as an

entry port to the system data bus.
 Notice in Figures_A,B how the address decoder and the
IOR control signal together activate the tri-state input.

Figure_A Design for Input Port Address 9FH

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 Input port design using the 74LS244

 Notice in Figures_A,B how the address decoder and the

IOR control signal together activate the tri-state input.

Figure_B Design for Input Port Address 5FH

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 Input port design using the 74LS244

 The 74LS244 not only plays the role of buffer, but also
provides the incoming data with sufficient driving capability
to travel all the way to the CPU.
 Indeed, the 74LS244 chip is widely used for buffering and
providing high driving capability for unidirectional buses.
 In bidirectional buses the 74LS245 can be used.

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 Input port design using the 74LS244

 Example: Using 74LS373 provide an output port for the

system shown in. Assign address 029EH to the device.

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 Input port design using the 74LS244

 Example: Using a 74LS244 connect 8 switches to the bus

of a system. Assign address 0401H to the input device.

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 Absolute vs. linear select address
decoding
 In decoding addresses, either all of them or a selected
number of them are decoded.
 If all the address lines are decoded, it is called absolute
decoding.
 If only selected address pins are used for decoding, it is
called linear select decoding.
 Linear select is cheaper, since the less input there is, the
fewer the gates needed for decoding.
 The disadvantage is, it creates what are called aliases
 In cases where linear select is used, we must document all
devices addresses in the system map (memory and I/O
map) thoroughly.

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 Absolute vs. linear select address
decoding
 Figure shows an output circuit, It decodes just A0 to A10.
This output circuit has 32 aliases including 029EH, 069EH,
..., FE9EH. As you see, using linear decoding results in
simpler circuits but makes aliases and wastes the address
space.

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 Peripheral I/O vs. Memory-mapped I/O
 Communicating with I/O devices using separate control
signals for memory and I/O is referred to as peripheral I/O.
Some designers also refer to it as isolated I/O.
 In many computers and microcontrollers there are not
separate control signals to distinguish I/O from memory.
 The addresses of I/Os and memory are assigned so that
they do not overlap with each other.
 In these computers I/Os are accessed as if they are parts of
memory.
 This kind of bus is called memory-mapped I/O.

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 Peripheral I/O vs. Memory-mapped I/O
 Figure shows a simple system designed by memory-
mapped I/O.

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 Peripheral I/O vs. Memory-mapped I/O
 The differences between peripheral I/O and memory-
mapped I/O for a system with 16 address (A0-A15) pins:

 In peripheral I/O special I/O (Input and Output) instructions

are used to access I/O devices.
 In memory-mapped I/O, we must use instructions that
access memory locations to access the I/O ports instead of
Input and Output instructions. In that way, there is no
difference between memory locations and I/O ports.
 In memory-mapped I/O circuit interfacing, control signals RD
and WR are used to access both I/O and memory devices.
 This is in contrast to peripheral I/O, in which IOR and IOW
are used.

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 Peripheral I/O vs. Memory-mapped I/O
 the differences between peripheral I/O and memory-
mapped I/O for a system with 16 address (A0-A15) pins:

 A major disadvantage of memory-mapped I/O is, it uses

memory address space, which could lead to memory space
fragmentation.
 In memory-mapped I/O, the entire address must be
decoded. Otherwise, the I/O aliases overlap the memory
space. This is in contrast to peripheral I/O, in which linear
decoding can be used. This makes decoding circuitry for
memory-mapped I/O more expensive.

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 Peripheral I/O vs. Memory-mapped I/O
 In Examples to see input and output circuits for a
memory-mapped I/O system.
Using a 74LS373, design an output port for a memory
mapped I/O system. Assign address 029EH to the device.

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 Peripheral I/O vs. Memory-mapped I/O
 In Examples to see input and output circuits for a
memory-mapped I/O system.
Using 74LS244 connect an 8-bit switch to a memory
mapped I/O system. Assign address 0401H to the device.

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