Lecture # 1

E3-238 : Analog VLSI Circuits

Dr. Navakanta Bhat

Associate Professor, ECE Department

Indian Institute of Science, Bangalore-560012

Email: navakant@ece.iisc.ernet.in
URL: http://ece.iisc.ernet.in/~navakant/Navakant_Bhat.html

August 2006
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 Logistics
• Instructor : Navakanta Bhat

• Class timings : Monday, Wednesday and Friday

8:00am-9:00am

• Lab session :
• Involves circuit design, simulation and analysis
using any circuit simulator (Spice3f5, WinSpice,
T-Spice, P-Spice, H-Spice, Spectre, Eldo…)

• Grading :
• Home work (lab assignments) : 20%
• Class tests : 20 %
• Course project : 20 %
• Final exam : 40%
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 List of Reference books
Due to the advent of mixed signal SOCs, numerous books
have been published on Analog Design. A partial list :
1. Analog CMOS Design
Razavi, McGraw Hill Publication

2. CMOS: Circuit Design, Layout , and Simulation

Boise, Baker, Lee, Prentice Hall Publication

3. Analog VLSI : Signal and Information Processing

Ismail and Feiz, McGraw Hill Publication

4. Analysis and Design of Analog Integrated Circuits

Gray and Meyer, Wiley Publication

5. Trade-offs in Analog Circuit Design: The Designer’s

Companion, Ed: C. Toumazou and other, Kluwer
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 Scope of the Course notes
URL: http://ece.iisc.ernet.in/~navakant/E3-238/2006/analog.html

“This course material has been developed to supplement the

the discussions during the lectures in class. You can use this
as the principal reference material. However, this course
material is not a text book. You may still want to read up
some of the books listed in the reference list to gain more
insight or to get alternate explanation for a given topic.”

Your feedback is welcome in terms of any corrections or any

additions to be done to the course notes to improve its utility.

Note: The emphasis in this course is to designs analog circuits

on a digital CMOS technology. Some of the discussions should
be viewed and appreciated with this context in mind.

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 Course details
Logistics, Technology trend, Need for Analog design,
Simple long channel MOSFET theory
Sub-micron transistor theory, SCE, NWE, DIBL, Sub-
threshold conduction, Reliability, Digital metrics,
Analog metrics
SPICE simulator, Transistor models, BSIM3 models,
Model extraction, Models for : Vt, I-V, Capacitance,
Substrate current, S/D parasitics, Temp dependence,
NQS effect, Noise, RF Modeling, Gate leakage
Small signal parameters, Cut-off frequency, Concept of
poles and zeros, Miller’s approximation
Single stage amplifiers, Common source amplifier with
resistive load, diode load, constant current load, Source
degeneration
Source follower, Input and output impedance, Common
gate amplifier, Cascode amplifier, Folded cascode
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 Course details
Current mirrors: Cascode, Nagative feedback, Wilson,
Regulated cascode, Layout issues
Bandgap voltage reference, supply and temperature
independent reference, curvature compensation,
trimming
Differential Amplifier: differential and common mode
response, Input swing, gain, diode load and constant
current load
Gilbert cell and applications, Basic 2 stage OPAMP, 2-
pole system response, active current mirror, common
mode and differential gain
Frequency response of OPAMP, pole splitting, zero
cancellation, slew rate, PSRR, random offset, systematic
offset, Noise, Output stage, OTA and OPAMP circuits

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 Course details
Sample and Hold, Switched capacitor circuits,
Comparator
Sense Amplifier, Effect of transistor mismatch in analog
design, Mismatch compensation, Statistical design
Low voltage design, Wide common mode OPAMP,
Complementary input stage, Body driven input, Lateral
BJTs, Subthreshold analog circuits,
Passives in CMOS: Capacitors and Varactors, Inductors,
Resistor, Quality factor of passives
Transistor mismatch / Variability, Statistical design
Effect of mismatch on sense amplifier
Correcting OPAMP non idealities: Auto zeroing,
Correlated double sampling, Chopper stabilization
Data Converters : DAC and ADC

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 Why Analog ?
Interaction with the Physical World

Input Output

Physical Computing Physical

Environment Platform Environment

Sensing Actuation

Human perception is inherently analog in nature

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 Why Analog ?
An Interesting Comparison…

CMOS Digital Computer Biological Neural System

Transistor / 1ps 100mS
Neuron
Wire / Fibre 108m/sec 2m/sec
Integration ~1 Billion ~ 1 Trillion
Architecture Digital (RISC/CISC …) Analog (Adaptive learning)

• Neural networks outperform the digital computers, in certain class

of applications such as speech recognition, pattern recognition
• The architecture and massive parallelism are distinguishing features
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 The First Transistor : 1947
The baby is born! Bardeen, Brattain, Schokley @ Bell Labs

• First transistor was point contact Ge bipolar junction transistor,

whereas the VLSI today is neither based on Ge nor on BJT!
• The Bell Labs team was in fact trying to make MOS transistor,
but got stuck with surface states and ended up with BJT!
Analog Circuit Design predates the semiconductor transistors!
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 The First IC : 1958
First IC demonstrated by J.S.Kilby of Texas Instruments in 1958
Phase shift oscillator, an analog circuit!
A thin slice of germanium with
1 bipolar transistor (under the large bar of
aluminum in the center),
1 capacitor,
3 resistors (the germanium functioned as its
own so-called bulk resistor)
4 input/output terminals (the small vertical
aluminum bars)
ground pad (the large bar on the far right),
and wires of gold.
Connected together with wax

Blue tinge was created by a light shown on the chip. Actual size: 0.040 x 0.062 inches

First IC using planar process and photolithography was demonstrated by Robert Noyce at Fairchild semiconductors
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 Metal Oxide Semiconductor Field Effect
Transistor (MOSFET)
• Field effect transistor concept proposed in 1930s by Lilienfeld

• First MOSFET fabricated in 1960 by Kahng and Atalla

PMOSFET NMOSFET
metal metal
oxide oxide
p+ n p+ n+ p n+

Silicon Silicon

• Early MOS technology was based on PMOSFETs

MOSFETS were thought to be unfriendly for Analog circuits!
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CMOS (Complementary MOS) technology
•Both NMOSFETs & PMOSFETs are used
•No static power consumption
•Very high integration density
•Very good isolation

•Very low cost

CMOS Inverter

PMOS
IN OUT

NMOS

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 CMOS market share

• CMOS captures more than 90% of electronics market share

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 Moore’s law

“Cramming more Components onto Integrated Circuits” “VLSI: some fundamental challenges”
Gordon E. Moore, Electronics 1965, p. 114. Moore, IEEE Spectrum 1970, p.30.
The bold extrapolation in 1965 by Moore was a challenge
to the industry to show the determination to lead a revolution
Moore proved his vision, by guiding INTEL
along his predicted trajectory
Moore who studied Chemistry in college is yet
another example to reiterate the fact that there
are no hard barriers between different fields
The implicit assumption behind Moore’s
“Moore’s law governs the Silicon revolution” law is the feature size scales continuously
Bandyopadhyay, Proc. of IEEE, 1998, p.78
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 Evolution from SSI to VLSI

• In the the Digital world, MOSFET completely displaced BJT

due to all the advantages offered by CMOS
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 CMOS Technology Today (2006)

• 65nm digital technology in volume production

• Number of transistors per chip is ~ 1 billion( DRAMs),
~ 100 million (microprocessors)
• Technology scaling for future is more challenging and expensive

• State of the art fab set-up costs more than US$2 billion
• Recovering the fab cost requires a modular process technology
approach capable of producing diverse products

What do we do with the technology capable of making

millions of transistor on a tiny area in Si? :

Mixed Signal Systems On Chip (SOC)

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 BJT versus MOSFET speed

metal
oxide
n+ n+ n+
p p p p
n-
Silicon
p

Base width defined by Channel length defined by

diffusion process Photolythography process

•Historically BJT used to be faster than MOSFET

•CMOS scaling has brought MOSFET on par with BJT

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 Cut-off frequency, fT
Cut-off frequency trend

120
100
80
60 ft
ft

40
20
0
0 0.2 0.4 0.6 0.8 1 1.2
Channel length

•MOSFET fT has increased considerably with scaling

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Analog Design on Digital Technology

• Microprocessors are today’s technology drivers

• The most elegant analog designs make use of the

existing digital technology

• Every modification to the baseline technology adds on

to the manufacturing cost

• Design For Manufacturability (DFM)

• CMOS analog circuits are logical choice

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Long channel MOSFET Theory

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 Transistor abstraction
D

G B

S
schematic switch model
gate
n+ n+
A A’
P-well

Si
lay out cross section

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 Simple 3-D picture of MOSFET
Wg
n+ gate
Lg

Tox Oxide
xj n+ source n+ drain

p substrate

Doping concentration = Na

The 2 important dimensional parameters of MOSFET

under circuit designer’s control are:
Lg = Length of the gate
Wg = Width of the gate
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 Simple MOS Theory
Vgs < Vt, MOSFET is in cut off region
Ids = 0
Vgs > Vt, Vds < Vgs-Vt, MOSFET is in linear region
µε oxW  Vds 2 
Ids = (Vgs − Vt )Vds − 
Tox L  2 
Vgs > Vt, Vds > Vgs-Vt, MOSFET is in saturation region

µε oxW (Vgs − Vt )2
Ids =
Tox L 2

where µ is mobility, εox is permittivity of the oxide,

and Vt is the threshold voltage of the MOSFET
Tox 4ε s qN aφb
Vt = V fb + 2φb +
ε ox
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 I-V characteristics
Output Characteristics Transfer Characteristics

Vg3
Saturation
Vds=Vdd

Ids Vg2 Ids

Vg1 Linear
Vds~0.1V

Vds Vgs
•Ids is constant and independent of Vds in saturation
•Ids is zero in sub-threshold region
Both of these idealities are incorrect especially for
the sub-micron MOS transistor
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 Channel length modulation
Vg > Vt Vd > Vg - Vt Ids
∆Vds
Rout =
∆I ds
n+ source ∆L n+ drain
electron channel

p-substrate Vds=Vgs-Vt
Vds
Effective channel length is Leff = L - ∆L, where ∆L=f(Vds)
µε oxW (Vgs − Vt )2 µε oxW (Vgs − Vt )2
I ds = I ds = (1 + λVds )
Tox Leff 2 Tox L 2
Ids increases slightly in saturation region with increasing Vds
This limits the AC output resistance for analog applications
λ is channel length modulation parameter in SPICE
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 Body effect
Vg Vd
Vs
n+ n+
p-substrate
Vbs

Tox 4ε s qN aφb
Vt 0 = V fb + 2φb +
ε ox
Vt = Vt 0 + γ ( Vbs + 2φb − 2φb )
Tox 2qε s N a γ = body effect factor (γ = 0.3-0.7)
γ=
ε ox
• Vt increases due to body effect
• This results in a transconductance term
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 Summary
• Analog design is indispensable in a variety of applications
involving interaction with the physical world

• The semiconductor technology is dominated by Si CMOS

• The system performance continues to increase as predicted by Moore

• Analog circuit designer should choose W & L of the MOSFET

depending on the application requirement

• Channel length modulation impacts the output resistance :

Out put resistance can be increased by choosing large L

• Body effect gives rise to a trans-conductance term

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