‫ن ا ْلعِْلِم إِاَّل قَلِ ًيل‬ِ ‫وما أُوتِيتم‬

‫م‬
3 August 2022 1444 ‫ محرم‬5

َ ُْ ََ

Analog IC Design

Lecture 01
Introduction

Dr. Hesham A. Omran

Integrated Circuits Laboratory (ICL)
Electronics and Communications Eng. Dept.
Faculty of Engineering
Ain Shams University
 Introduction

ENIAC, U.S. Army, 1946 Smart phone

Size → Large hall (> 150m2) Size → Your pocket
Power Consumption ≈ 150kW Power consumption < 1W
01: Introduction 2
 Electronics All Around Us

01: Introduction 3
 Transistor Evolution

First transistor Modern MOSFET

Emitter and Collector contacts Effective channel
separation ≈ 100µm length ≈ 35nm
Bell Labs, 1947 Intel, 2006
01: Introduction [Weste and Harris, 2010] 4
 Integrated Circuit Evolution
≈ 20mm

≈ 11mm

First IC Xeon E5 Microprocessor

Only one transistor (+ R + C)! 2.26 billion transistors!
Texas Instruments (TI), 1958 Intel, 2012

01: Introduction 5
 Sensing Microsystems

3mm 4mm

ADXL350
Analog Devices, 2012
Complete system on a tiny chip
• 3-axis MEMS* accelerometer
• Interface electronics
• Analog-to-digital conversion
• Memory
First accelerometer • Control logic
B&K, 1940s • Power management
• Digital interface
Simple bulky transducer
Acceleration → Voltage *MEMS = Micro-Electro-Mechanical
01: Introduction Systems 6
 Moore’s Law
❑ Moore’s law [1965]: Transistor count doubles every year

“The complexity for minimum component costs has

increased at a rate of roughly a factor of two per
year. Certainly over the short term this rate can be
expected to continue, if not to increase. Over the
longer term, the rate of increase is a bit more
uncertain, although there is no reason to believe it
will not remain nearly constant for at least 10 years.“

[Gordon Moore, Electronics Magazine, 1965]

01: Introduction 7
 Moore’s Law
❑ Moore’s law [1965]: Transistor count doubles every year
❑ Practically: It doubled every 2-3 years since the 4004 [1970s]
❑ At the end of the day: It is exponential!

01: Introduction [Weste and Harris, 2010] 8

 Technology Minimum Feature Size
❑ Minimum feature size shrinking 30% (≈ 1/ 2) every 2-3 years
▪ Transistor area and cost are reduced by a factor of 2
❑ Device scaling brings new opportunities and challenges!

01: Introduction [Weste and Harris, 2010] 9

01: Introduction 10
 The End of Moore’s Law?

01: Introduction 11
 Technology Node
❑ Historically, the process node name referred to the
transistor gate length (same as M1 half-pitch).
❑ Most recently, due to various marketing and discrepancies
among foundries, the number itself has lost its exact
meaning.
❑ Gate length has not scaled proportionately with device pitch
(0.7x per generation) in recent generations.
❑ Recent technology nodes (22 nm and below) does not
correspond to any gate length or half pitch!
▪ Just 70% of whatever the name of the node of the
previous generation was!

[https://en.wikichip.org/wiki/technology_node]
01: Introduction [IRDS ES, 2020] 12
 IBM 2nm Technology
❑ IBM announcement of 2nm technologies does not correspond to 2nm feature size!
▪ The individual nanosheets are 5nm in height, separated from each other by 5 nm.

01: Introduction [https://www.anandtech.com/show/16656/ibm-creates-first-2nm-chip] 13

 FinFET
❑ Planar CMOS cannot be scaled below 20nm due to excess leakage current and severe short
channel effects.
❑ FinFET: Gate has better control on the channel
▪ Intel’s version is called trigate FET
▪ Generally: Multigate transistor

01: Introduction [Weste and Harris, 2010] 14

 The Last Step?

01: Introduction 15
 Or The Next Step?

01: Introduction 16
 Still Too Many Steps! – IRDS 2021

01: Introduction [https://irds.ieee.org/images/files/pdf/2020/2020IRDS_BC.pdf] 17

 The different Ages of Scaling
❑ 1975 – 2000: Geometrical scaling
▪ Reduction of horizontal and vertical dimensions
▪ Improved performance of planar transistors
❑ 2000 – 2025: Equivalent scaling
▪ Reduction of only horizontal dimensions
▪ Introduction of new materials and new physical effects
▪ New vertical structures replace the planar transistor
❑ 2025 – 2040: 3D scaling
▪ Transition to complete vertical device structures
▪ Heterogenous integration
❑ Our current bag of innovations can keep CMOS alive till 2040!

01: Introduction [P. Gargini, IRDS, Intel] 18

 Levels of Abstraction

01: Introduction [Razavi, 2017] 19

 IC Industry in Egypt

01: Introduction 20
 Course Objective
❑ To teach the basic knowledge required for
▪ Analog IC analysis and design using CMOS technology
▪ Moving from specifications (specs) to block design
▪ Simulating analog ICs using professional CAD tools

Specifications

01: Introduction [M. El-Nozahi, ASU] 21

 Your Learning Journey
Material Devices Circuits

Product System

01: Introduction [M. El-Nozahi, ASU] 22

 Course Prerequisites
❑ You should be familiar with
▪ Analysis of electrical circuits
▪ Basic semiconductor physics
▪ Basic MOSFET operation and physics
▪ MOSFT large signal and small signal models
▪ Basic analysis of transistor amplifiers
❑ A review will be provided for all of the above topics
▪ But you will struggle if you have never heard about these topics before

01: Introduction 23
 References
❑ Textbook
▪ B. Razavi, “Design of analog CMOS integrated circuits,” 2nd ed., McGraw-Hill Ed., 2017.

❑ References for beginners

▪ A. Sedra and K. Smith, “Microelectronic circuits,” 7th ed., Oxford University Press, 2015.
▪ T. Floyd, “Electronics Fundamentals, Circuits, Devices, and Applications,” 8th ed.,
Pearson, 2014.
▪ B. Razavi, “Fundamentals of microelectronics,” 2nd ed., Wiley, 2014.

01: Introduction 24
 References
❑ References for professionals
▪ T. C. Carusone, D. Johns, and K. W. Martin, “Analog integrated circuit design,” 2nd ed.,
Wiley, 2012.
▪ P. Gray, P. Hurst, S. Lewis, and R. Meyer, “Analysis and design of analog integrated
circuits,” 5th ed., Wiley, 2009.
▪ P. Jespers and B. Murmann, “Systematic design of analog CMOS circuits using pre-
computed lookup tables,” Cambridge University Press, 2017.
▪ R. J. Baker, “CMOS circuit design,” 3rd ed., Wiley, 2010.
▪ W. Sansen, “Analog design essentials,” Springer, 2006.

01: Introduction 25
 Canvas
❑ Canvas is a learning management system (LMS) used in many universities in the US and
around the world
❑ We will use Canvas for
▪ Posting lectures, notes, etc.
▪ Questions and answers
▪ Announcements and discussions
▪ Quizzes
▪ Submitting and grading assignments, reports, etc.
▪ And more!
❑ Every student must register at Canvas today!
❑ Contact me through Canvas, only in emergency contact me by email:
Hesham.Omran@eng.asu.edu.eg

01: Introduction 26
 Feedback
❑ Don’t hesitate to send me feedback to improve the course quality.
❑ Avoid two common misconceptions
1. Feedback should NOT wait to the end of the course!
• It will be too late to improve anything!
• But anyway, you may still help next generations ☺
2. Feedback should NOT be always negative!
• Too much negative feedback leads to zero output!
• Too much positive feedback causes oscillation!
• Be balanced!

01: Introduction 28
 What is an Integrated Circuit (IC)?
❑ Various circuit elements: transistors, capacitors, resistors, and even small inductances can
be integrated on one chip

01: Introduction 29
 Discrete vs. Integrated Electronics
Circuits using discrete
components Integrated circuit

01: Introduction 30
 Integrated Circuit Components
❑ Transistors:
▪ Billions of tiny transistors can be integrated on the same chip
▪ Very Large Scale Integration (VLSI): > 10,000 transistors
❑ Capacitors:
▪ Capacitors as large as 100s of pF can be integrated on-chip
▪ But they consume a lot of chip area → Use sparingly
❑ Resistors:
▪ Resistors as large as few MOhms can be integrated on-chip
▪ But they consume a lot of chip area → Use sparingly
❑ Inductors:
▪ Small inductors (few nH) can be integrated on-chip
▪ But they consume a lot of area with relatively poor performance → Use only in high
frequency circuits (e.g., RFICs, serial links, etc.)
01: Introduction 31
 Analog vs Digital Signals
❑ Analog: continuous in time and amplitude

❑ Digital: discrete in time and amplitude

01: Introduction [Razavi, 2014] 32

 Why Digital?
❑ Digital circuits are
▪ Less sensitive to noise (robust)
▪ Easier to store (digital memories)
▪ Easier to process (digital signal processing: DSP)
▪ Amenable to automated design
▪ Amenable to automated testing
▪ Easier to port from one technology to another
▪ Direct beneficiary of Moore’s law (down-scaling)

01: Introduction 33
 Why Analog?
❑ All the physical signals in the world around us are analog
▪ Voice, light, temperature, pressure, etc.
❑ We (will) always need an “analog” interface circuit to connect between our physical world
and our digital electronics
❑ There will always be jobs for analog/mixed-signal/RF designers ☺

Digital
Amplifier A/D processing
and storage

01: Introduction 34
 Why Analog?
❑ High speed digital design is actually analog design!
❑ At low speeds, we may directly digitize the signal and perform the signal processing in the
digital domain.
❑ At high speeds, signal processing in the analog domain is much more energy efficient.
❑ The boundary between high and low speed has risen over time.

01: Introduction [Razavi, 2017] 35

 Signal Processing Chain
❑ There will always be jobs for analog/mixed-signal/RF designers ☺

Amp A/D

Physical
world
Digital
(sound,
Power Management processing
temperature,
and storage
pressure,
light, etc.)

Amp D/A

01: Introduction 36
 Example: Mixed-Signal Hearing Aid
❑ There will always be jobs for analog/mixed-signal/RF designers ☺

ΣΔ ΣΔ H-Bridge
DSP
A/D D/A Driver

AGC Decimation
Filter

-50
[dB]

-100

-150
0.001 0.01 0.1 0.5
Normalized frequency

01: Introduction [Y. Chiu, EECT 7327, UTD] 37

 Wireless Signal Processing Chain
❑ There will always be jobs for analog/mixed-signal/RF designers ☺

Rx Amp A/D

EM Waves
Digital
Power Management processing
and storage

Tx Amp D/A

01: Introduction 38
 Why CMOS?
❑ Early integrated circuits primarily used bipolar transistors (BJTs)
❑ CMOS technologies dominated the digital market since the 1980s
→ CMOS = Complementary MOS = NMOS + PMOS
1. Consumed negligible static power
• Was indeed negligible in the past
• But not negligible any more…
2. Required very few devices per gate
3. Can be scaled down more easily
4. Lower fabrication cost
❑ For analog design, BJTs used to be much better than MOSFETs
▪ Faster, less noisy, less variations, more energy efficient, higher gain
❑ Then why analog CMOS?

01: Introduction 39
 Why Analog CMOS?
❑ ICs market is driven primarily by memories and microprocessors
▪ The analog designer needs to survive in a digital driven market
❑ We want to integrate analog and digital on the same chip
▪ Mixed-signal design and system-on-a-chip
❑ BJTs used to be faster, but with continuous scaling, MOSFET speed exceeded BJT
❑ MOSFET can operate with lower supply voltage

01: Introduction 40
 Analog Amplifier

𝑣𝑜𝑢𝑡
❑ The amplifier has finite gain (𝐴𝑣 = ) and finite bandwidth (speed)
𝑣𝑖𝑛

01: Introduction [Razavi, 2014] 41

 Analog IC Design Challenges
❑ Device scaling
▪ Transistors become faster, but the gain declines
❑ Supply voltage scaling
▪ From 12V in 1970s to less than 1V nowadays
❑ Low power consumption
▪ Increase battery lifetime, decrease cost and heat emissions
❑ Complexity
▪ Continuous increase in transistor count and system complexity
❑ PVT variations
▪ Tolerate large process, voltage, and temperature variations
❑ New applications
▪ Wireless standards, wearables, IoT, serial links (e.g., USB), power management

01: Introduction 42
 Analog IC Design Challenges
❑ In digital we have PPA
❑ In analog, we need to worry about many more things
▪ Analog design automation is a difficult task

01: Introduction [Razavi, 2017] 43

 Analog IC Design Flow (Simplified)
Design Specs

Topology Selection Fabrication

Circuit Hand Calculations

Packaging
Design and Analysis Tape-out

Simulation and
Testing
Design Adjustment

Physical Layout and Post No Specs

Design Layout Simulation met?

Yes
Specs
No met? Yes Product

01: Introduction [M. El-Nozahi, ASU] 44

 Tape-Out
❑ The layout is sent to the fab in a format called GDS II
▪ Previously it was sent on a magnetic tape → tape-out
▪ Now by email (small design) or FTP (large design)

01: Introduction [Weste and Harris, 2010] 45

 MPW
❑ ICs are fabricated on silicon wafers
▪ Turnaround time ~ 3months
❑ A fabrication run in 65nm process costs about $3 million
▪ Cost sharing using MPW (multi-project wafer)
• US: MOSIS
• Europe and MENA: Europractice

01: Introduction [Weste and Harris, 2010] 46

 MPW Example
❑ Link: http://www.europractice-ic.com/general_runschedule.php
❑ Foundries include TSMC, UMC, GLOBALFOUNDRIES, …
❑ < 50 samples only!
❑ Example:

01: Introduction 47
 Packaging and Testing
❑ Wafer diced into dies
❑ Gold bond wires from die I/O pads to package
❑ Packaging is now much more advanced than the
simple DIP (dual inline package)

01: Introduction [Weste and Harris, 2010] 48

 Thank you!

01: Introduction 49
 References
❑ A. Sedra and K. Smith, “Microelectronic Circuits,” Oxford University Press, 7th ed., 2015.
❑ B. Razavi, “Fundamentals of Microelectronics,” Wiley, 2nd ed., 2014.
❑ B. Razavi, “Design of Analog CMOS Integrated Circuits,” McGraw-Hill, 2nd ed., 2017.
❑ N. Weste and D. Harris, “CMOS VLSI Design,” Pearson, 4th ed., 2010.

01: Introduction 50
 Modern “Moore” Concepts
❑ More Moore
▪ Further miniaturization of transistor as per Moore’s law
▪ New materials for performance enhancement (HK, SOI, III-V)
▪ We are approaching the “physical limits” of the transistor
❑ More than Moore
▪ Adding functionalities not associated with transistor scaling to increase device value
(sensors, MEMS, bio, passives, etc.)
▪ 3D integrated circuits
❑ Beyond Moore (Beyond CMOS)
▪ Exploring new device architectures
▪ Gate-all-around transistors, nanowires (NW-FET), nanotubes (CNT), memristors, spin
electronics, graphene, etc.

01: Introduction [P. Kin Leong, SUTD] 51

 Modern “Moore” Concepts

01: Introduction [Wolfgang Arden et. al., ITRS] 52

 IC Technology Generations
❑ Early integrated circuits primarily used bipolar transistors (BJTs)
❑ 1960s: MOS ICs became attractive for their low cost
▪ MOS transistor occupied less area
▪ The fabrication process was simpler
▪ Early commercial processes used only PMOS transistors and suffered from poor
performance, yield, and reliability
❑ 1970s: Processes using only NMOS transistors became common
❑ Digital circuits in all the previous technologies have quiescent power
▪ Power is dissipated when the circuit is idle, i.e., not switching
▪ This limits the maximum number of transistors that can be integrated on one die

01: Introduction 53
 IC Technology Generations (Cont’d)
❑ 1980s: The VLSI era
▪ Power consumption became a major issue
▪ CMOS processes were widely adopted and replaced NMOS and bipolar processes for
nearly all digital logic applications
→ CMOS = Complementary MOS = NMOS + PMOS
▪ A key advantage for “digital” CMOS is that it has negligible idle (static) power
consumption
❑ Nowadays:
▪ With aggressive scaling and billions of transistors, CMOS idle leakage current is not
negligible any more
▪ But no better technology is available yet…

01: Introduction 54
 How to Design a Billion Transistor Chip?
1. Abstraction
▪ Hiding details until they become necessary
2. Structured design
▪ Hierarchy: Block, sub-blocks, … → Tree structure (from root to leaf cells)
▪ Regularity: Min no. of different blocks → Block reuse (e.g., standard cells)
▪ Modularity: Blocks are black boxes that have well-defined interfaces → Combine to
build larger system without surprises!
3. CAD Tools
▪ Automation, automation, automation!
▪ Analog automation is way behind digital automation

01: Introduction 55
 CAD/EDA
❑ Analog design
▪ Design entry (schematic), simulation, layout
▪ Verification (LVS: layout vs schematic, DRC: layout design rule check, parasitic
extraction, post-layout simulation)
❑ Digital design
▪ Design entry (e.g., HDL) and simulation
▪ Automated synthesis (from HDL to gates)
▪ Automated place and route (from gates to transistor layout)
▪ Verification
❑ System design
▪ Behavioral modeling and high level simulation/verification
❑ EM simulation, process simulation, device simulation, etc.

01: Introduction 56
9 August 2020
‫ن ا ْلعِْل ِم إِاَّل قَلِ ًيل‬ ِ ‫وما أُوتِيتُم‬
‫م‬
1441 ‫ ذو الحجة‬19

َ ْ ََ

Analog IC Design

Lecture 02
Review on Circuits and Systems Basics

Dr. Hesham A. Omran

Integrated Circuits Lab (ICL)
Electronics and Communications Eng. Dept.
Faculty of Engineering
Ain Shams University
 Outline
❑ Circuits review
▪ Ohm’s law, KCL, KVL
▪ Thevenin and Norton equivalents
▪ Superposition
▪ Capacitance
❑ Systems review
▪ Laplace transform
▪ Poles and zeros
▪ Frequency response
▪ First-order system
▪ Second-order system

02: Circuits and Systems Basics 2

 Ohm’s Law

+ V –
V

I R I R

𝑉 = 𝐼𝑅

𝑉
𝐼=
𝑅
𝑉
𝑅=
𝐼
02: Circuits and Systems Basics 3
 Kirchhoff’s Current Law (KCL)
❑ The sum of all currents flowing into a node is zero.

Σ𝐼 = 0

𝐼1 + 𝐼2 + 𝐼3 − 𝐼4 = 0

I2
I1 I3

I4

02: Circuits and Systems Basics 4

 Kirchhoff’s Voltage Law (KVL)
❑ The sum of all voltage drops around any closed loop is zero
Σ𝑉 = 0
−𝑉𝐷𝐷 + 𝐼𝐷 𝑅𝐷 + 𝑉𝐷𝑆 + 𝐼𝐷 𝑅𝑆 = 0
𝑉𝐷𝐷 = 𝐼𝐷 𝑅𝐷 + 𝑅𝑆 + 𝑉𝐷𝑆
VDD
ID ID
RD RD
vout vout
I=0 VDD I=0
vin VDS vin VDS

RS RS

02: Circuits and Systems Basics 5

 Resistor Combinations
❑ Resistors in series: Largest resistor dominates

R1 R2 R3

𝑅𝑒𝑞 = 𝑅1 + 𝑅2 + 𝑅3

❑ Resistors in parallel: Smallest resistor dominates

R1 R2 R3

1 1 1 1
= + +
𝑅𝑒𝑞 𝑅1 𝑅2 𝑅3
02: Circuits and Systems Basics 6
 Voltage and Current Dividers
❑ Voltage divider → the largest resistor takes most of the voltage
❑ Current divider → the smallest resistor (largest conductance) takes most of the current
▪ Remember that current flows in the least resistance path

𝑅3 𝐺3
𝑉𝑜𝑢𝑡 = 𝑉𝐷𝐷 ⋅ 𝐼𝑜𝑢𝑡 = 𝐼𝑖𝑛 ⋅
𝑅1 + 𝑅2 + 𝑅3 𝐺1 + 𝐺2 + 𝐺3
VDD
Iout
R1
Iin R1 R2 R3
R2
Vout
R3

02: Circuits and Systems Basics 7

 Thevenin Equivalent Circuit
❑ Any one port circuit can be replaced by a voltage source and a series impedance
𝑉𝑇𝐻 = 𝑉𝑜.𝑐.
𝑍𝑇𝐻 = 𝑍𝑒𝑞 (turn OFF all independent sources)

Any circuit
Any circuit VTH=Vo.c. Deactivate
ind. sources ZTH=Zeq

ZTH

VTH

02: Circuits and Systems Basics 8

 Norton Equivalent Circuit
❑ Any one port circuit can be replaced by a current source and a parallel impedance
𝐼𝑁 = 𝐼𝑠.𝑐.
𝑍𝑁 = 𝑍𝑒𝑞 (turn OFF all independent sources)
𝒁𝑵 = 𝒁𝑻𝑯
𝑽𝑻𝑯 = 𝑽𝒐.𝒄. = 𝑰𝑵 × 𝒁𝑵

Any circuit
Any circuit IN=Is.c. Deactivate
ind. sources ZN=Zeq

IN ZN

02: Circuits and Systems Basics 9

 Superposition Theorem
❑ Deactivate all independent sources except one
▪ Independent voltage source → short circuit (s.c.)
▪ Independent current source → open circuit (o.c.)
▪ Do NOT deactivate dependent sources
❑ Solve the circuit
❑ Repeat the previous two steps for every source
❑ Algebraically add all the results

We use this frequently to separate DC and AC solutions

02: Circuits and Systems Basics 10

 Superposition Theorem

DC + AC = DC + AC

VDD VDD

RD RD RD
vout vout vout

vin vin vin

RS RS RS
VGG VGG

02: Circuits and Systems Basics 11

 Capacitance
𝑄 = 𝐶𝑉

𝑑𝑄 𝑑𝑉
𝑖= =𝐶
𝑑𝑡 𝑑𝑡
𝑉 = 𝑉𝑜 cos 𝜔𝑡 = 𝑉𝑜 ⋅ 𝑅𝑒 𝑒 𝑗𝜔𝑡 ⇒ 𝑉𝑜 𝑒 𝑗𝜔𝑡

𝑑𝑉
𝑖=𝐶 = 𝑗𝜔𝐶 𝑉𝑜 𝑒 𝑗𝜔𝑡 = 𝑗𝜔𝐶 ⋅ 𝑉
𝑑𝑡

𝑉 1 1 1
𝑍𝐶 = = = ⇒ 𝑋𝐶 =
𝑖 𝑗𝜔𝐶 𝑠𝐶 𝜔𝐶
𝜔 ↑↑ ⇒ 𝑋𝐶 → 0 ⇒ 𝑠. 𝑐.
𝜔 ↓↓ ⇒ 𝑋𝐶 → ∞ ⇒ 𝑜. 𝑐.
02: Circuits and Systems Basics 12
 Capacitance Combinations
❑ Capacitors in series: Smallest capacitor dominates

C1 C2 C3

1 1 1 1
= + +
𝐶𝑒𝑞 𝐶1 𝐶2 𝐶3

❑ Capacitors in parallel: Largest capacitor dominates

C1 C2 C3

𝐶𝑒𝑞 = 𝐶1 + 𝐶2 + 𝐶3
02: Circuits and Systems Basics 13
 Laplace Transform (LT)

02: Circuits and Systems Basics [D. Rowell, MIT 2.004, 2008] 14
 Laplace Transform (LT)
Time domain Laplace domain
1
𝑒 𝑎𝑡
𝑠−𝑎
𝑡
1
න 𝑓 𝑡 𝑑𝑡 𝐹 𝑠
𝑠
0
𝑑𝑓 𝑡
𝑠𝐹 𝑠
𝑑𝑡
𝛿 𝑡 1
1
𝑢 𝑡
𝑠

02: Circuits and Systems Basics 15

 Impulse Response and Step Response
Time domain Laplace domain
1
𝑒 𝑎𝑡
𝑠−𝑎
𝑡
1
න 𝑓 𝑡 𝑑𝑡 𝐹 𝑠
𝑠
0
𝑑𝑓 𝑡
𝑠𝐹 𝑠
𝑑𝑡
𝛿 𝑡 1
1
𝑢 𝑡
𝑠

System response (output)

System input
in Laplace domain
Unit impulse: 𝛿 𝑡 𝐻 𝑠
1
Unit step: 𝑢 𝑡 𝐻 𝑠
𝑠
02: Circuits and Systems Basics 16
 Poles and Zeros
❑ Transfer function
𝑁 𝑠
𝐻 𝑠 =
𝐷 𝑠
❑ Zeros: roots of the numerator ➔ 𝑁 𝑠 = 0
❑ Poles: roots of the denominator (characteristic eq.) ➔ 𝐷 𝑠 = 0
❑ For physical systems, poles & zeros are real or complex conjugate
❑ Example:

02: Circuits and Systems Basics [D. Rowell, MIT 2.004, 2008] 17
 Real and Complex Poles

02: Circuits and Systems Basics [D. Rowell, MIT 2.004, 2008] 18
 LHP and RHP Poles
❑ Poles in LHP: Decaying exponential ➔ Stable system
▪ BIBO: Bounded input bounded output
❑ Poles in RHP: Growing exponential ➔ Unstable system

02: Circuits and Systems Basics [D. Rowell, MIT 2.004, 2008] 19
 Frequency Response
❑ Transfer function
𝑁 𝑠
𝐻 𝑠 =
𝐷 𝑠
❑ Fourier Transform is a special case of Laplace Transform: 𝑠 ⇒ 𝑗𝜔
▪ 𝜎 = 0 ➔ Steady state response for sinusoidal input
❑ Transfer function ➔ Frequency response: 𝑠 ⇒ 𝑗𝜔
𝑉𝑜𝑢𝑡 𝑗𝜔
𝐻 𝑗𝜔 = = 𝐻 𝑗𝜔 𝑒 𝑗𝜙
𝑉𝑖𝑛 𝑗𝜔
❑ 𝑎 + 𝑗𝑏 = 𝑟𝑒 𝑗𝜃 Im
❑ 𝑟 = Magnitude 𝑎 + 𝑗𝑏 = 𝑎2 + 𝑏 2
−1 𝑏 r
❑ 𝜃 = Phase 𝑎 + 𝑗𝑏 = tan 𝑎 b
θ Re
a
02: Circuits and Systems Basics 20
 Frequency Response
❑ Y-axis: magnitude of frequency response, x-axis: frequency

LPF BPF HPF

02: Circuits and Systems Basics 21

 First-Order LPF
𝑣𝑜𝑢𝑡 𝑠 1/𝑠𝐶 1 1
𝐻 𝑠 = = = =
𝑣𝑖𝑛 𝑠 𝑅 + 1/𝑠𝐶 1 + 𝑠𝑅𝐶 1 + 𝑠𝜏
𝑣𝑜𝑢𝑡 𝑗𝜔 1/𝑗𝜔𝐶 1 1
𝐻 𝑗𝜔 = = = =
𝑣𝑖𝑛 𝑗𝜔 𝑅 + 1/𝑗𝜔𝐶 1 + 𝑗𝜔𝑅𝐶 1 + 𝑗𝜔
𝜔𝑐
❑ 𝜏 = 𝑅𝐶: time constant
R
1 1 Vin Vout
❑ 𝜔𝑐 = = : cutoff/corner frequency
𝜏 𝑅𝐶
1 C
❑ Poles: 𝑠𝑝 = − 𝜏 = −𝜔𝑐
❑ Zeros: ?
1 Vout
❑ 𝐻 𝑗𝜔 =
𝜔 2 Iin
1+
𝜔𝑐 R C
𝜔
❑ 𝑃 𝐻 𝑗𝜔 = −tan−1 𝜔
𝑐
02: Circuits and Systems Basics 22
 Bode Plot Rules
Pole Zero
Magnitude -20 dB/decade +20 dB/decade
Actual Mag @ pole: -3 dB Actual Mag @ zero: +3 dB
Phase -90o LHP zero:
Actual Phase @ pole: -45o +90o
Actual Phase @ zero: +45o
RHP zero:
-90o
Actual Phase @ zero: -45o

→ RHP: Right-half plane (𝑅𝑒 𝑠 > 0)

→ LHP: Left-half plane (𝑅𝑒 𝑠 < 0)

02: Circuits and Systems Basics 23

 First-Order LPF Bode Plot
20 log 𝐻 𝑗𝜔 𝑑𝐵

𝑪 ⇒ 𝒐. 𝒄. 𝑪⇒✓

𝑃 𝐻 𝑗𝜔

02: Circuits and Systems Basics [Sedra/Smith, 2015] 24

 First-Order LPF Impulse and Step Response
𝑣𝑜𝑢𝑡 𝑠 1/𝑠𝐶 1 1
𝐻 𝑠 = = = =
𝑣𝑖𝑛 𝑠 𝑅 + 1/𝑠𝐶 1 + 𝑠𝑅𝐶 1 + 𝑠𝜏

R
Vin Vout
C

Vout
Iin R C

02: Circuits and Systems Basics 25

 First-Order HPF
𝑣𝑜𝑢𝑡 𝑠 𝑅 𝑠𝑅𝐶 𝑠𝜏
𝐻 𝑠 = = = =
𝑣𝑖𝑛 𝑠 𝑅 + 1/𝑠𝐶 1 + 𝑠𝑅𝐶 1 + 𝑠𝜏
𝑗𝜔
𝑣𝑜𝑢𝑡 𝑗𝜔 𝑅 𝑗𝜔𝑅𝐶 𝜔𝑐
𝐻 𝑗𝜔 = = = =
𝑣𝑖𝑛 𝑗𝜔 𝑅 + 1/𝑗𝜔𝐶 1 + 𝑗𝜔𝑅𝐶 1 + 𝑗𝜔
𝜔𝑐
1
❑ Poles: 𝑠𝑝 = − 𝜏 = −𝜔𝑐
C
❑ Zeros: 𝑠𝑧 = 0 Vin Vout
𝜔 R
𝜔𝑐
❑ 𝐻 𝑗𝜔 =
𝜔 2
1+
𝜔𝑐
𝜔
❑ 𝑃 𝐻 𝑗𝜔 = 90o −tan−1
𝜔𝑐

02: Circuits and Systems Basics 26

 Bode Plot Rules
Pole Zero
Magnitude -20 dB/decade +20 dB/decade
Actual Mag @ pole: -3 dB Actual Mag @ zero: +3 dB
Phase -90o LHP zero:
Actual Phase @ pole: -45o +90o
Actual Phase @ zero: +45o
RHP zero:
-90o
Actual Phase @ zero: -45o

→ RHP: Right-half plane (𝑅𝑒 𝑠 > 0)

→ LHP: Left-half plane (𝑅𝑒 𝑠 < 0)

02: Circuits and Systems Basics 27

 First-Order HPF Bode Plot
20 log 𝐻 𝑗𝜔 𝑑𝐵

𝑪⇒✓ 𝑪 ⇒ 𝒔. 𝒄.

𝑃 𝐻 𝑗𝜔

02: Circuits and Systems Basics [Sedra/Smith, 2015] 28

 Second-Order System: LC LPF
𝑍𝐶 1
𝐻 𝑠 = =
𝑅 + 𝑍𝐿 + 𝑍𝐶 𝐿𝐶𝑠 2 + 𝑅𝐶𝑠 + 1

1 𝜔𝑜 𝐿 1 1
𝜔𝑜2 = 𝑎𝑛𝑑 𝑄 = = =
𝐿𝐶 𝑅 𝜔𝑜 𝑅𝐶 2𝜁

❑ Higher 𝑅 means higher damping 𝜁 and lower quality factor 𝑄

1 𝜔𝑜2 𝜔𝑜2
𝐻 𝑠 = 2 = 𝜔 = 2 2
𝑠 𝑠 2 𝑜 2 𝑠 + 2𝜁𝜔 𝑠 + 𝜔
+ + 1 𝑠 + 𝑄 𝑠 + 𝜔𝑜 𝑜 𝑜
𝜔𝑜 𝜔𝑜 𝑄

R L
Vin Vout
C
02: Circuits and Systems Basics 29
 Second-Order Passive LC LPF
1 𝜔𝑜2
𝐻 𝑠 = 2 = 𝜔𝑜
𝑠 𝑠 𝑠 2 + 𝑠 + 𝜔 2
𝜔𝑜 + 𝜔𝑜 𝑄 + 1 𝑄 𝑜

𝜔𝑜
❑ The poles occur at 𝑠 2 + 𝑠 + 𝜔𝑜2 = 0
𝑄

−𝑏 ± 𝑏 2 − 4𝑎𝑐 𝜔𝑜 𝜔𝑜 1
𝑠𝑝1,2 = =− ± 2
−4
2𝑎 2𝑄 2 𝑄

R L
Vin Vout
C
02: Circuits and Systems Basics 30
 Second-Order System Poles
1 1
𝐻 𝑠 = 2 = 2
𝑠 𝑠 𝑠 𝑠
+𝜔 𝑄+1 + +1
𝜔𝑜 𝑜 𝜔𝑜 𝜔𝑜 /2𝜁

𝜔𝑜 𝜔𝑜 1
𝑠𝑝1,2 =− ± 2
−4
2𝑄 2 𝑄
❑ If 𝑄 < 0.5 (𝜁 > 1): overdamped system, roots are real,
negative, and distinct, like two first-order RC filters in
cascade
❑ If 𝑄 = 0.5 (𝜁 = 1): critical damped system, roots are R L
Vin Vout
real, negative, and equal C
❑ If 𝑄 > 0.5 (𝜁 < 1): underdamped system, roots are
complex conjugate

02: Circuits and Systems Basics [Sedra/Smith, 2015] & [Johns and Martin, 2012] 31
 Ringing and Peaking
❑ 𝑄 > 0.5 (𝜁 < 1): Underdamped system (complex conjugate poles)
▪ Ringing (overshoot) in step response (time domain)
−𝜋
% overshoot= 100 𝑒 4𝑄2 −1

1
❑ 𝑄> 2
= 0.707 (𝜁 < 0.707): Peaking in frequency response

02: Circuits and Systems Basics [Sedra/Smith, 2015] & [Johns and Martin, 2012] 32
 Thank you!

02: Circuits and Systems Basics 33

 References
❑ T. Floyd and D. Buchla, “Electronics Fundamentals, Circuits, Devices, and Applications,” 8th
ed., Pearson, 2014.
❑ A. Sedra and K. Smith, “Microelectronic circuits,” Oxford University Press, 7th ed., 2015.
❑ B. Razavi, “Fundamentals of microelectronics,” 2nd ed., Wiley, 2014.

02: Circuits and Systems Basics 34

 Order of a Circuit
❑ The order of a circuit is the order of the differential equation describing the circuit
❑ Viewed in s-domain, it is the order of the denominator of the transfer function (the
characteristic equation)
▪ The number of poles of the system
❑ The order is also the number of state variables in the circuit (the variables that control the
behavior of the circuit)
▪ For C: state variable is voltage
▪ For L: state variable is current
❑ A practical rule of thumb:
▪ Find the number of independent inductor currents and capacitor voltages
▪ Or the number of independent initial conditions that can be assigned to state variables
❑ Beware of pole-zero cancellation (e.g., two capacitors forming a voltage divider)

02: Circuits and Systems Basics 35

 ‫ن ا ْلعِْلِم إِاَّل قَلِ ًيل‬ِ ‫وما أُوتِيتم‬
‫م‬
18 February 2020 1441 ‫ جمادى الثانية‬24

َ ُْ ََ

Analog IC Design

Lecture 03
Review on Semiconductors Basics

Dr. Hesham A. Omran

Integrated Circuits Lab (ICL)
Electronics and Communications Eng. Dept.
Faculty of Engineering
Ain Shams University
 Outline
❑ What are semiconductors?
❑ Electrons and holes
❑ N-type and P-type silicon
❑ Drift and diffusion current
❑ The PN-junction

03: Semiconductors Basics 2

 What are Semiconductors
❑ Conductors → Ex: copper
❑ Insulators → Ex: glass
❑ Semiconductors are materials whose conductivity lies between that of conductors and
insulators
❑ What is so special about semiconductors?
▪ The electrical conductivity can be dramatically changed by introducing extrinsic dopant
atoms
▪ We have two types of carriers: electrons and holes
❑ Silicon (Si) is the semiconductor material used in the majority of today’s electronic devices

03: Semiconductors Basics 3

 Silicon Crystal
❑ Covalent bonds are formed by sharing of the valence electrons
❑ At 0 K, all bonds are intact and no free electrons are available

03: Semiconductors Basics [Sedra/Smith, 2015] 4

 Electrons and Holes
❑ At room temperature, some of the covalent bonds are broken by thermal generation
❑ Each broken bond gives rise to a free electron (𝑒 − ) and a hole (ℎ+ )
▪ Both 𝑒 − and ℎ+ become available for current conduction

03: Semiconductors Basics [Sedra/Smith, 2015] 5

 Intrinsic Silicon
❑ Carrier concentration is the number of charge carriers per unit volume (𝑐𝑚3)
❑ At thermal equilibrium, the recombination rate is equal to the generation rate
❑ The concentration of free electrons (𝑛) is equal to the concentration of holes (𝑝)
𝑛 = 𝑝 = 𝑛𝑖
❑ The product of 𝑛 and 𝑝 is constant (depends only on temperature)
𝑛𝑝 = 𝑛𝑖2

03: Semiconductors Basics 6

 Doped (Extrinsic) Silicon
❑ Doping involves introducing impurity atoms into the silicon crystal
❑ To increase the concentration of free electrons (𝑛) silicon is doped with a pentavalent
(valence = 5) impurity (Ex: Phosphorus)
▪ Each dopant atom (donor) gives a free 𝑒 − and a fixed positive charge (+ve ion)
▪ Electrons become the majority carriers (𝑛 ≫ 𝑝)
▪ The doped silicon is n-type
❑ To increase the concentration of holes (𝑝) silicon is doped with a trivalent (valence = 3)
impurity (Ex: Boron)
▪ Each dopant atom (acceptor) gives a ℎ+ and a fixed negative charge (-ve ion)
▪ Holes become the majority carriers (𝑝 ≫ 𝑛)
▪ The doped silicon is p-type

03: Semiconductors Basics 7

 N-Type Silicon
❑ Each dopant atom (donor) gives a free 𝑒 − and a fixed positive charge (+ve ion)
▪ 𝑁𝐷 : donor concentration
❑ Electrons become the majority carriers (𝑛 ≈ 𝑁𝐷 ≫ 𝑝)

03: Semiconductors Basics [Sedra/Smith, 2015] 8

 P-Type Silicon
❑ Each dopant atom (acceptor) gives a ℎ+ and a fixed negative charge (-ve ion)
▪ 𝑁𝐴 : acceptor concentration
❑ Holes become the majority carriers (𝑝 ≈ 𝑁𝐴 ≫ 𝑛)

03: Semiconductors Basics [Sedra/Smith, 2015] 9

 Current Flow: (1) Drift Current
❑ Current flows due to electrical field (𝐸)
▪ Holes are accelerated in the direction of 𝐸
ℎ+ drift velocity = 𝑣𝑝−𝑑𝑟𝑖𝑓𝑡 = 𝜇𝑝 𝐸
▪ Free electrons are accelerated in the direction opposite to 𝐸
𝑒 − drift velocity = 𝑣𝑛−𝑑𝑟𝑖𝑓𝑡 = −𝜇𝑛 𝐸
❑ 𝜇 is the mobility: 𝜇𝑛 = 2 − 4 times 𝜇𝑝
❑ Note that if there are no carriers, there will be no current, even if there is an electric field

03: Semiconductors Basics [Sedra/Smith, 2015] 10

 Current Flow: (2) Diffusion Current
❑ Current flows due to carrier concentration gradient
▪ Carriers diffuse from the region of high concentration to the region of low concentration

03: Semiconductors Basics [Sedra/Smith, 2015] 11

 The PN Junction (The Diode)

Metal
contact
Anode P-type N-type Cathode

Anode Cathode

03: Semiconductors Basics 12

 PN Junction in Equilibrium (o.c.)
❑ Diffusion current 𝐼𝐷 flows due to concentration gradient
▪ A depletion region of uncovered fixed charges is formed
▪ The uncovered charges create 𝐸 → drift current 𝐼𝑆
❑ 𝐼𝐷 = 𝐼𝑆 → net current (𝐼𝐷 − 𝐼𝑆 ) is zero
𝜖𝐴
❑ Capacitance 𝐶 =
𝑑
ID
IS
E
++holes++ -electrons-
+++++++ -----------
Anode +++++++ ----------- Cathode
+++++++ -----------
+++++++ -----------
Depletion region
03: Semiconductors Basics Fixed charges 13
 PN Junction in Equilibrium (o.c.)
❑ Built-in electric field and barrier voltage due to depletion region
𝑁𝐴 𝑁𝐷 𝑁𝐴 𝑁𝐷
𝑉0 = 𝑉𝑇 ln 2 ≈ 2.3𝑉𝑇 log 2 ≈ 0.6 − 0.9𝑉
𝑛𝑖 𝑛𝑖 VR
❑ The barrier voltage 𝑉0 limits carrier diffusion
ID ID
IS IS
E E
++holes++ -electrons- ++holes++ -electron
A +++++++ ----------- K A +++++++ ---------
+++++++ ----------- +++++++ ---------
+++++++ ----------- +++++++ ---------
+++++++ ----------- +++++++ ---------

03: Semiconductors Basics [Sedra/Smith, 2015] 14

 PN Junction in Reverse (Rvr) Bias
❑ The applied reverse voltage increases diffusion barrier
▪ Opposes diffusion current
❑ Electric field increases
▪ But drift current almost unchanged: no carriers to accelerate
❑ Net current is very small ≈ −𝐼𝑆
❑ Depletion width increases → capacitance decreases
▪ Capacitance at zero bias is larger VR

ID ID
IS IS
E E
++holes++ -electrons- ++holes++ -electrons-
A +++++++ ----------- K A +++++++ ----------- K
+++++++ ----------- +++++++ -----------
+++++++ ----------- +++++++ -----------
+++++++ ----------- +++++++ -----------
03: Semiconductors Basics 15
 PN Junction in Forward (Fwd) Bias
❑ The applied forward voltage decreases diffusion barrier
▪ Dramatically increases diffusion current
𝑉𝐹
❑ Net current is very high = 𝐼𝐷 − 𝐼𝑆 ≈ 𝐼𝐷 = 𝐼𝑆 𝑒 𝑉𝑇

▪ Forward current exponentially increases with voltage across diode 𝑉𝐹

❑ Depletion width decreases

VF

ID ID
IS IS
E E
++holes++ -electrons- ++holes++ -electrons-
A +++++++ ----------- K A +++++++ ----------- K
+++++++ ----------- +++++++ -----------
+++++++ ----------- +++++++ -----------
+++++++ ----------- +++++++ -----------
03: Semiconductors Basics 16
 PN Junction IV Characteristics
𝑉 V
❑ 𝐼 = 𝐼𝑆 (𝑒 − 1) 𝑉𝑇

Anode Cathode
❑ Forward: High diffusion current
exponentially dependent on 𝑉 = 𝑉𝐹 I
❑ Reverse: Very small drift current almost
independent of 𝑉 = −𝑉𝑅
❑ Breakdown: Very high reverse current at
LARGE reverse bias voltage

03: Semiconductors Basics [Sedra/Smith, 2015] 17

 Thank you!

03: Semiconductors Basics 18

 References
❑ A. Sedra and K. Smith, “Microelectronic Circuits,” Oxford University Press, 7th ed., 2015.
❑ B. Razavi, “Fundamentals of Microelectronics,” Wiley, 2nd ed., 2014.

03: Semiconductors Basics 19