S.

R. YOGITHA LAKSHMI
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Digital Logic and system

Design
Assignment Number - 2

Course Code: UEE- 2504

Submitted By
R. YOGITHA LAKSHMI
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Register Number: 3122 22 3001 109

Section; EEE – ‘B’
1. Write the VHDL code for a 4-bit magnitude comparator using Structural modelling and
verify using test bench.
VHDL Code:
library IEEE; use
IEEE.STD_LOGIC_1164.ALL;
entity FouBitComp is
Port ( A : in STD_LOGIC_VECTOR (3 downto 0);
B : in STD_LOGIC_VECTOR (3 downto 0);
Less_than_B : out STD_LOGIC;
Equal_to_B : out STD_LOGIC;
Greater_than_B : out STD_LOGIC); end
FouBitComp;

architecture structural of FouBitComp is

component OneBitComp is
Port ( A : in STD_LOGIC;
B : in STD_LOGIC;
L : out STD_LOGIC;
E : out STD_LOGIC;
G : out STD_LOGIC); end
component;

signal tempL, tempE, tempG:STD_LOGIC_VECTOR (3 downto 0);

begin
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com0 : OneBitComp port map (A(0),B(0),tempL(0),tempE(0),tempG(0));

com1 : OneBitComp port map (A(1),B(1),tempL(1),tempE(1),tempG(1));
com2 : OneBitComp port map (A(2),B(2),tempL(2),tempE(2),tempG(2));
com3 : OneBitComp port map (A(3),B(3),tempL(3),tempE(3),tempG(3));

less_than_B <= tempL(0) or (tempE(0) and tempL(1)) or ((tempE(0) and tempE(1) and
tempL(2)) or (tempE(0) and tempE(1) and tempE(1) and tempE(2) and tempL(3)));
Equal_to_B <= tempE(0) and tempE(1) and tempE(2) and tempE(3);
Greater_than_B <= (((tempG(0) or (tempE(0) and tempG(1)))) or ((tempE(0) and
tempG(2)) or (tempE(0) and tempE(1) and tempE(2) and tempG(3)))); end structural;
Test Bench Code:

begin
-- hold reset state for 100 ns.

A <= "0000";

B <= "0010";

wait for 100 ns;

A <= "0100"; B <=

"0010"; wait

for 100 ns; A <=

"1000"; B <=

"0010"; wait

for 100 ns; A <=

"1000"; B <=

"0100"; wait

for 100 ns;

end process;
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2. Write the VHDL code for a 4-bit ripple carry adder using structural modelling and verify
the result using test bench.
VHDL code:
library IEEE; use
IEEE.STD_LOGIC_1164.ALL;
entity RIPPLE_ADDER is
Port ( A : in STD_LOGIC_VECTOR (3 downto
0); B : in STD_LOGIC_VECTOR (3 downto
0); S : out STD_LOGIC_VECTOR (4 downto
0)); end RIPPLE_ADDER;

architecture Structural of RIPPLE_ADDER is

component FULL_ADDER is
Port ( A : in STD_LOGIC;
B : in STD_LOGIC;
Cin : in STD_LOGIC;
S : out STD_LOGIC;
Cout : out STD_LOGIC); end
component;

signal Ctemp : STD_LOGIC_VECTOR (3 downto 0);

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begin
Ctemp(0) <= '0';

FA0: FULL_ADDER port map (A(0),B(0),Ctemp(0),S(0),Ctemp(1));

FA1: FULL_ADDER port map (A(1),B(1),Ctemp(1),S(1),Ctemp(2));
FA2: FULL_ADDER port map (A(2),B(2),Ctemp(2),S(2),Ctemp(3));
FA3: FULL_ADDER port map (A(3),B(3),Ctemp(3),S(3),S(4));

end Structural;
Test Bench:

begin

A <= "1011";

B <= "1101";
wait for 100 ns;

A <= "1011";

B <= "1001";

wait for 100 ns;

A <= "1011";

B <= "0101";

wait for 100 ns;

A <= "1001";

B <= "0001";

wait for 100 ns;

end process;
OUTPUT:
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3. Write the VHDL code for a 4 to 16 Decoder using 3:8 decoders (Structural modelling –
Package) and verify the result using test bench.
VHDL Code:
library IEEE; use
IEEE.STD_LOGIC_1164.ALL;
entity Four_to_Sixteen_decoder is
Port ( A : in STD_LOGIC_VECTOR (3 downto 0);
Y : out STD_LOGIC_VECTOR (15 downto 0)); end
Four_to_Sixteen_decoder;

architecture structural of Four_to_Sixteen_decoder is

component Three_to_eight_decoder is
Port ( A : in STD_LOGIC_VECTOR(2 downto 0);

E : in STD_LOGIC;
Y : out STD_LOGIC_VECTOR (7 downto 0));
end component;

signal temp1, temp2 : STD_LOGIC;

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begin temp1 <= not A(3); temp2 <= A(3); dec0: Three_to_eight_decoder port
map(A(2 downto 0),temp1, Y(7 downto 0)); dec1: Three_to_eight_decoder port
map(A(2 downto 0),temp2, Y(15 downto 8));

end structural;

TEST BENCH CODE:

A <= "0000";
wait for 100 ns;
A <= "0001";
wait for 100 ns;

A <= "0010";
wait for 100 ns;
A <= "0011";
wait for 100 ns;

A <= "1100";
wait for 100 ns;
A <= "1111";
wait for 100 ns;
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4. Write a VHDL code for 64:1 multiplexer using 8:1 multiplexer (Structural modelling –
Package) and verify the result using test bench.
VHDL Code (Using data flow model):
library IEEE; use
IEEE.STD_LOGIC_1164.ALL; entity
Sixtyfour_to_one_mux is
Port ( A : in STD_LOGIC_VECTOR (63 downto 0);
S : in STD_LOGIC_VECTOR (5 downto
0); Y : out STD_LOGIC); end
Sixtyfour_to_one_mux;

architecture Structural of Sixtyfour_to_one_mux is

component Eight_to_One_mux is
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Port ( A : in STD_LOGIC_VECTOR (7 downto 0);
S : in STD_LOGIC_VECTOR (2 downto
0); Y : out STD_LOGIC); end component;
signal temp : STD_LOGIC_VECTOR (7 downto
0); begin

MUX0: Eight_to_One_MUX port map ( A(7 downto 0), S(2 downto 0), temp(0) );
MUX1: Eight_to_One_MUX port map ( A(15 downto 8), S(2 downto 0), temp(1) );
MUX2: Eight_to_One_MUX port map ( A(23 downto 16), S(2 downto 0), temp(2) );
MUX3: Eight_to_One_MUX port map ( A(31 downto 24), S(2 downto 0), temp(3) );
MUX4: Eight_to_One_MUX port map ( A(39 downto 32), S(2 downto 0), temp(4) );
MUX5: Eight_to_One_MUX port map ( A(47 downto 40), S(2 downto 0), temp(5) );
MUX6: Eight_to_One_MUX port map ( A(55 downto 48), S(2 downto 0), temp(6) );
MUX7: Eight_to_One_MUX port map ( A(63 downto 56), S(2 downto 0), temp(7) );
MUX8: Eight_to_One_MUX port map ( temp, S(5 downto 3), Y );

end Structural;
Test Bench Code:
A <= "0000000000000000000000000000000000000000000000000000000000000001";

S <= "000000";
wait for 100 ns;

A <=
"1111111111111111111111111111111111111111111111111111111111111111";

S <= "000011";
wait for 100 ns;

A <=
"1010101010101010101010101010101010101010101010101010101010101010";
S <= "010101";
wait for 100 ns;

A <=
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"0101010101010101010101010101010101010101010101010101010101010101";
S <= "101010";
wait for 100 ns;
A <=
"0000111100001111000011110000111100001111000011110000111100001111";
S <= "111111";
wait for 100 ns;
OUTPUT:

5. Write the VHDL code for encoder and decoder using dataflow and behavioural modelling and
verify the result using test bench.
1) Encoder (4:2)
VHDL Code (Behavioural):

library IEEE; use

IEEE.STD_LOGIC_1164.ALL;
entity encoder4to2ass is
Port ( a : in STD_LOGIC_VECTOR (3 downto
0); y : out STD_LOGIC_VECTOR (1
downto 0)); end encoder4to2ass; architecture
Behavioral of encoder4to2ass is begin
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Y(0) <= A(2) or A(3);
Y(1) <= A(1) or A(3);
end Behavioral; VHDL
Code (Dataflow):
library IEEE; use
IEEE.STD_LOGIC_1164.ALL;
entity encoder4to2df is
Port ( a : in STD_LOGIC_VECTOR (3 downto 0);
y : out STD_LOGIC_VECTOR (1 downto 0)); end
encoder4to2df;

architecture Behavioral of encoder4to2df is

begin

process(a)

begin

case a is

when "1000" => y <= "00";

when "0100" => y <= "01";

when "0010" => y <= "10";

when "0001" => y <= "11"; when

others => Y <= "UU"; end case;

end process;
end Behavioral;
Test bench Code: a
<= "0001"; wait
for 100 ns;

a <= "0010";
wait for 100 ns;
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a <= "0100";
wait for 100 ns;

a <= "1000";
wait for 100 ns;

OUTPUT:
Behavioural Model:
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Data flow model:

Decoders (2:4):
VHDL (Behavioural Model):
library IEEE; use
IEEE.STD_LOGIC_1164.ALL;
entity decoder4to2ass is
Port ( a : in STD_LOGIC_VECTOR (1 downto 0);
y : out STD_LOGIC_VECTOR (3 downto 0)); end
decoder4to2ass;

architecture Behavioral of decoder4to2ass is

begin

y(0) <= ((not a(0)) and (not

a(1))); y(1) <= ((not a(0)) and (
a(1))); y(2) <= (( a(0)) and (not
a(1))); y(3) <= ((a(0)) and (
a(1))); end Behavioral;
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OUTPUT (Behavioural):

VHDL Code (Dataflow Model):

library IEEE; use
IEEE.STD_LOGIC_1164.ALL;
entity decoders4to2df is
Port ( a : in STD_LOGIC_VECTOR (1 downto 0);
y : out STD_LOGIC_VECTOR (3 downto 0)); end
decoders4to2df;

architecture Behavioral of decoders4to2df is

begin
process(a)

begin

case a is when "00" =>

y <= "0001"; when "01" => y <=

"0010"; when "10" => y <=

"0100"; when "11" => y <=

"1000"; when others => y <=

"UUUU"; end case;

end process;
end Behavioral;
Test Bench Code:
a <= "00";
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wait for 100 ns;
a <= "01";
wait for 100 ns;
a <= "10";
wait for 100 ns;

a <= "11";
wait for 100 ns;
OUTPUT (Data flow);