146 IEEE JOURNAL ON EMERGING AND SELECTED TOPICS IN CIRCUITS AND SYSTEMS, VOL. 6, NO.

2, JUNE 2016

Recent Progress in Phase-Change

Memory Technology
Geoffrey W. Burr, Senior Member, IEEE, Matthew J. Brightsky, Abu Sebastian, Senior Member, IEEE,
Huai-Yu Cheng, Jau-Yi Wu, Sangbum Kim, Member, IEEE, Norma E. Sosa, Nikolaos Papandreou, Member, IEEE,
Hsiang-Lan Lung, Senior Member, IEEE, Haralampos Pozidis, Senior Member, IEEE,
Evangelos Eleftheriou, Fellow, IEEE, and Chung H. Lam

Abstract—We survey progress in the PCM field over the past

five years, ranging from large-scale PCM demonstrations to
materials improvements for high–temperature retention and
faster switching. Both materials and new cell designs that support
lower-power switching are discussed, as well as higher reliability
for long cycling endurance. Two paths towards higher density are
discussed: through 3D integration by the combination of PCM and
3D-capable access devices, and through multiple bits per cell, by
understanding and managing resistance drift caused by structural Fig. 1. Programming of a PCM device involves application of electrical
relaxation of the amorphous phase. We also briefly survey work power through applied voltage, leading to internal temperature changes that
in the nascent field of brain-inspired neuromorphic systems that either melt and then rapidly quench a volume of amorphous material (RESET),
use PCM to implement non-Von Neumann computing. or hold this volume at a slightly lower temperature for sufficient time for
recrystallization (SET). The temperature at which recrystallization is very
Index Terms—Artificial neural networks, content addressable rapid ( ), , is lower than the melting temperature,
storage, data storage systems, materials processing, nonvolatile . A low voltage is used to sense the device
memory, phase change materials, phase change memory. resistance (READ), so that the device state is not perturbed [2].

I. INTRODUCTION operation to dominate power considerations for PCM tech-

nology. The “SET” operation dictates write speed performance,

P HASE-CHANGE memory (PCM) is enabled by the large

resistance contrast between the amorphous and crystalline
states in phase-change materials [1]–[3]. The amorphous phase
since the required pulse duration depends on the material's
crystallization speed. Set pulses shorter than 10 ns have been
demonstrated [4], yet since the crystallization process is many
offers high electrical resistivity, while the crystalline phase ex- orders of magnitude slower at low temperatures ( ),
hibits resistivities that can be three or four orders of magnitude PCM is a Non-Volatile Memory (NVM) technology that can
lower. To “SET” the memory cell into its low-resistance state, offer years of data lifetime. Read operations are performed
an applied electrical pulse heats a large portion of the cell above by measuring the device resistance at low voltage so that the
the crystallization temperature of the material; to “RESET” it, device state is not perturbed (Fig. 1).
a larger electrical current is applied, melting the central portion Important device characteristics for a PCM cell include
of the cell. If the RESET pulse is cut off abruptly enough, the widely separated SET and RESET resistance distributions (nec-
molten material quenches into the amorphous phase, producing essary for sufficient noise margin upon fast readout), the ability
a cell in the high-resistance state. The higher temperatures to switch between these two states with accessible electrical
needed for melting (600 or higher) cause the RESET pulses, the ability to read/sense the resistance states without
perturbing them, high endurance (allowing many switching
Manuscript received July 01, 2015; revised August 31, 2015, and October 15, cycles between SET and RESET), long data retention (usually
2015; accepted November 18, 2015, and December 2, 2015. Date of publication specified as 10 year data lifetime at some elevated temperature),
April 15, 2016; date of current version June 09, 2016. This paper was recom-
and fast SET speed. Data retention usually comes down to the
mended by Guest Editor S. Ghosh.
G. W. Burr is with IBM Research–Almaden, San Jose, CA 95120 USA cell's ability to retain the amorphous RESET state by avoiding
(e-mail:gwburr@us.ibm.com). unintended recrystallization. An additional aspect that can
M. J. BrightSky, S. Kim, N. E. Sosa, and C. Lam are with IBM T. J. Watson
be of significant importance is the ability to store (and retain
Research Center, Yorktowh Heights, NY 10598 USA (e-mail: breitm@us.ibm.
com; sangbum.kim@us.ibm.com; sosa@us.ibm.com; clam@us.ibm.com). over time) more than 1 bit of data per cell, using analog
A. Sebastian, N. Papandreou, H. Pozidis, and E. Eleftheriou are resistance states to store bits per cell. This allows an increase
with IBM Zurich Research Laboratory, 8803 Rüschlikon, Switzerland
in effective density, much like MLC (Multi-Level Cell) Flash,
(e-mail: ase@zurich.ibm.com; npo@zurich.ibm.com; hap@zurich.ibm.com;
ele@zurich.ibm.com). without decreasing the feature size. An unwanted property of
H.-Y. Cheng, J. Y. Wu, and H.-L. Lung are with Macronix, Hsinchu, Taiwan PCM that complicates the implementation of MLC is resistance
(e-mail: hymcheng@us.ibm.com; jywu@mxic.com.tw; lunghl@us.ibm.com).
“drift” after programming, where device resistance increases
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org. after programming due to relaxation of the amorphous phase
Digital Object Identifier 10.1109/JETCAS.2016.2547718 of the material.

2156-3357 © 2016 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.

Authorized licensed use limited to: UNIVERSITE DE SOUSSE. Downloaded on April 15,2022 at 12:40:03 UTC from IEEE Xplore. Restrictions apply.
BURR et al.: RECENT PROGRESS IN PHASE-CHANGE MEMORY TECHNOLOGY 147

In this paper, we summarize progress in the PCM field since

the last set of comprehensive review articles were published in
2010 [2], [3]. During this time, interest in filamentary Resis-
tive RAM (ReRAM) [5], based on filaments of oxygen vacan-
cies in oxides such as and , increased tremendously
[6], [7]. This interest was driven by the perceived advantages
of ReRAM over PCM, such as fab–friendly materials, simple
cell designs, and the decoupling between switching volume and Fig. 2. a) TEM cross-section ( -direction) for a 1 Gbit PCM cell array. b)
lithographic patterning. However, it is now becoming clear [8], Top-down schematic layout of PCM “Wall” architecture and fabrication pro-
cedure of the sidewall heater element and Self-Aligned (“SA”) GST element.
[9] that low-power ( ) switching of ReRAM, enabled c) Resistance vs. programming current ( - ) characteristic demonstrating pro-
by enforcing low current compliance during filament formation grammability. (Reprinted, with permission, from [18].)
and SET, necessarily involves moving only a countable number
of atoms. This unavoidably introduces very large intra-device
variability through Poissonian statistics [8], [9], and makes it
difficult to achieve high endurance [10]. Thus interest in fila-
mentary ReRAM is now beginning to subside among industry
researchers [11], for applications other than low-density em-
bedded storage [12].
Fig. 3. TEM sections along -direction (a) and along -direction (b) show Left,
Instead, increased activity is observed on three fronts: first, Center, Right, Bottom and Top adjacent cells at spacing .
Conductive-Bridging RAM (CBRAM) is receiving significant c) Thermal crosstalk occurs during repeated RESET programming of the central
attention [11], [13], since it can combat otherwise similar vari- cell. d) TEM section in the -direction of an aggressor (yellow) and disturbed
cell (red), showing that a portion of the amorphous GST dome has recrystallized.
ability issues with the larger resistance contrast of its metallic (Reprinted, with permission, from [23]).
filaments. Second, researchers are also returning to non-fila-
mentary RRAM devices [14], [15], within which ions move
across the entire aperture of the device. And finally, PCM is also As companies move towards productization, details of the ma-
experiencing a modest resurgence of interest, since its faults are terials, processing and integration become more guarded, yet
mostly addressable with engineering, rather than being imposed showcase publications still provide a great deal of useful infor-
by underlying physics. The success of PCM will then hinge on mation.
whether such engineering solutions can be developed and their In conventional, planar PCM technologies consisting of a
costs reduced sufficiently. single layer of memory devices, the access device is built di-
This paper is designed as a “Field Guide,” for circuit and rectly on the single-crystalline silicon substrate. These include
systems professionals, to the advances in the materials science, nFET (n-type field effect transistor) [16], [17], vertical pnp-BJT
physics, and engineering of PCM devices over the past 5-6 (Bipolar Junction Transistor) [18], and SEG (Selective Epitaxial
years. Specific circuits for reading and writing PCM devices are Grown) diode [19]–[21]. The planar nFET has the advantage of
beyond the scope of this paper; instead we aim to supply skilled being a readily available CMOS technology, offering lower cost
circuit designers with the information from outside of their at the cost of a larger cell size. (Non-planar access devices al-
domain that they will need for that design task. In Section II, we lowing higher bit density through 3D stacking are discussed in
describe the largest-scale PCM demonstrations performed to Section VII.)
date, and then survey ongoing improvements in high–tempera- A vertical pnp-BJT was utilized as the PCM cell access de-
ture retention (Section III), faster (Section IV) and lower-power vice in a 1 Gbit 45 nm node (effective cell size of 5.5 ) chip
switching (Section V), higher reliability (Section VI), and [18] (Fig. 2). The BJT could deliver 300 at 2.0 V, with
higher density through 3D integration (Section VII) as well a base-emitter leakage current in reverse bias of less than 0.1
as through multiple bits per cell (MLC, Section VIII). We pA/bit at 3 V. In this demonstration, one base contact was shared
then briefly survey work in the nascent fields of neuromorphic by four emitters (Fig. 2(b), top panel). As the number of emit-
(Section IX) and other (Section X) systems that use PCM ters per base contact grows, so does the difference in base resis-
before concluding (Section XI). tance between the end- and the middle-device. This translates
into a variation in drive current across a string of emitters for
a given applied voltage. BJT device optimization studies have
II. CURRENT STATE-OF-THE-ART
shown that up to 32 emitter strings can be utilized while main-
The last five years have seen PCM density improvements (de- taining sufficient and / [22]. This chip used the
vice-to-device pitch scaling) and aggressive scaling of PCM sidewall electrode, or “Wall”–type PCM storage element [18].
device size, leading to a reduction in required programming This element is made by first forming a thin sidewall electrode
power (RESET power), and even to the release of first memory on a tungsten contact, followed by a PVD–deposited GST layer,
products. The trend of device scaling leading directly to lower and then top electrode material directly deposited and etched to
switching power is one of the underlying strengths of PCM form a self-aligned BL (see Fig. 2, and also Fig. 3 for a TEM cut
technology. The largest array demonstrations have grown to along the and directions). The cell can achieve full RESET
the billions of bits per memory chip, bringing PCM technolo- with 200 programming current with a SET resistance of ap-
gies within range of incumbent memory technologies' densities. proximately 10 .

Authorized licensed use limited to: UNIVERSITE DE SOUSSE. Downloaded on April 15,2022 at 12:40:03 UTC from IEEE Xplore. Restrictions apply.
148 IEEE JOURNAL ON EMERGING AND SELECTED TOPICS IN CIRCUITS AND SYSTEMS, VOL. 6, NO. 2, JUNE 2016

Fig. 5. Cross sectional SEM images along (a) BL direction and (b) WL direc-
tion. (c) TEM image of cell module along BL direction. (d) Schematic diagram
Fig. 4. (a) Both the percentage of Ge and Te content inside a memory cell of PRAM cell array and unit cell. (e,f) Cross sectional TEM images of 20
and (b) data retention characteristics can depend on the horizontal dimensions. nm confined cell. (Reprinted, with permission, from [21].)
(Reprinted, with permission, from [26]).

PCM cells that require only physical vapor deposition (PVD)

are preferred over those which require Atomic Layer Deposition
(ALD) or Chemical Vapor Deposition (CVD) for a number of
reasons: maturity of PVD processes, deposition rates (typically,
PVD deposition rates are on the order of nanometers per second
as compared to ALD deposition rates of nanometers per minute Fig. 6. a) Wide-area and b) zoomed-in XTEM images of 58 nm 512 Mbit
PRAM with 32 cells-per-string (CPS). Due to the finite cell active sheet re-
or slower), ease of control of deposited stoichiometry, ease of sistance (RS), the resistance of each cell in 32 CPS is dependent on the distance
incorporating dopants with PVD, and cost of ownership of the from the string contacts, resulting in systematic variability of programming cur-
tool and its consumables. For these reasons, most large scale rent. (SEG indicates the Selective Epitaxial Growth diode.) ( Reprinted, with
permission, from [29].)
demonstrations have used PVD-deposited phase-change mate-
rials [18], [20], [23]–[25]. However, sputtering material by PVD
into high aspect ratio holes or trenches can induce a large void
circuit/system approach introduced to ameliorate a problem in-
in the center of the structure. Even after optimizing the structure
troduced at the device level.
(aspect ratio and angle of sidewall of the hole or trench) and de-
position process such that this void does not occur, it has been
shown that preferential elemental deposition can still occur [26] III. IMPROVEMENTS IN RETENTION
(see Fig. 4) depending on the shape and size of the region being Even though the principle of applying phase-change mate-
filled. rials to electronic memory was demonstrated as long ago as
The largest array-size and also the most advanced technology the 1960s [30], interest in PCM was slow to develop compared
node PCM chip demonstration was achieved using a SEG diode to other NVM candidates. Interest in PCM technology was
as the access devices. ALD-deposited phase-change material renewed by the discovery of fast recrystallizing materials, GeTe
enabled an 8 Gbit PCM chip in 20 nm node with a cell size and , for optical applications [31], [32].
(Fig. 5) [21], [27]. Optimization of the diode integration process This triggered the discovery of pseudo-binary alloys along the
was needed in order to meet both the and the re- GeTe- tie line, such as , and the
quirements. The dash-type confined PCM cell achieved sub-100 most commonly applied material for both optical and electrical
RESET current (SET resistance was not reported). This applications, (GST-225) [33] (see Fig. 7).
PCM cell is fabricated by first forming a sidewall electrode, re- PCM offers a very wide range of materials and compositions,
cessing the electrode and filling with ALD phase-change ma- allowing materials to be developed for specific application re-
terial, followed by removal of the phase-change material from quirements [34]. For example, embedded system memories re-
the surface. Finally a top electrode metal was deposited and quire materials with much better data retention at high tempera-
patterned (see Fig. 5 for a TEM of the PCM cell). The en- tures, either to maintain stored data after soldering [35] or for au-
durance at the conditions explored in the paper was measured tomotive applications [36], [37]. Typically, a material offering
to be , with endurance failure projected to occur high crystallization temperature ( ) generally leads to a better
at . The reduction in programming energy and the thermal stability and thus longer data retention of stored data [1].
ability to melt the entire cell are projected to improve write en- Note that at , crystallization occurs in seconds. In contrast,
durance, potentially to [28], although this is yet to at the higher temperature of shown in Fig. 1 [38], [39],
be experimentally demonstrated. To combat systematic ON-cur- sufficient recrystallization of the amorphitized portion to create
rent (series resistance) variability between edge-of-string and a high-conductance path through a memory cell can occur in
center-of-string devices, an Active Width Modulation (AWM) . This higher temperature is much more difficult
scheme was introduced, in which local selector devices have to measure [40]–[42], yet tends to scale with . Fortunately,
different active device widths and therefore different - char- this “crystallization temperature,” , can be readily measured
acteristics [29]. [29] combined the AWM scheme with a 32 on blanket films of phase-change materials using electrical or
cells-per-string SEG diode architecture in a 512 Mbit 58 nm optical techniques [1], [43]. Thus is widely used to charac-
node PCM chip (Fig. 6). The AWM scheme is an example of a terize new candidate phase-change materials.

Authorized licensed use limited to: UNIVERSITE DE SOUSSE. Downloaded on April 15,2022 at 12:40:03 UTC from IEEE Xplore. Restrictions apply.
BURR et al.: RECENT PROGRESS IN PHASE-CHANGE MEMORY TECHNOLOGY 149

TABLE I
COMPARISON OF PHASE-CHANGE MATERIAL COMPOSITIONS FOR HIGH THERMAL STABILITY. IS DETERMINED FROM RESISTIVITY VERSUS
TEMPERATURE MEASUREMENTS, RESET CURRENT AND SET SPEED FROM 256 MBIT CHIP OPERATION, AND THE RECRYSTALLIZATION
TIME NEEDED TO COMPLETE 90% OF THE PHASE TRANSFORMATION FROM LASER TESTING. (REPRINTED, WITH PERMISSION, FROM [49].)

Despite this significant improvement, the “golden composi-

tion” is still insufficiently stable at the temperatures associated
with automotive and other industrial applications. Material vari-
ants with even higher thermal stability were obtained by in-
corporating nitrogen and by engineering the Ge/N concentra-
tion [49]. Table I compares the performance of GST-225, the
“golden composition,” and variants involving Ge-excess and
Ge/N doping conditions [49]. RESET current is decreased by
extra Ge or Ge/N incorporation, at the cost of slower SET speed,
although N incorporation suppresses elemental segregation (re-
sulting in a better endurance performance).
Variant C (the “golden composition” plus N incorporation
Fig. 7. Crystallization temperatures as a function of compositions in the and Ge-enrichment) demonstrated nearly 100% yield in a
Ge-Sb-Te ternary phase diagram ( of GST-147, GST-124 and GST-225 from
[36]). Here the Ge– tieline is explored, referenced not to GST-225 but 256 Mbit test chip after baking at 160 for 84 hours, with
to a nearby, slightly Sb-enriched, Te-poor composition labelled “Ref. GST.” projected 10-year retention at 120 ( years at 85 )
Starting from the best compromise material (GST-212) on the isoelectronic at only 1% bit-failure, suitable for industrial and some auto-
tie-line (vertical blue line), high-temperature stability is further enhanced by
moving along a second tie-line between Ge and (dashed purple line). motive (in-cabin) applications [49]. A similar improved data
(Reprinted, with permission, from [48].). retention was reported by other groups as well [50], [51]. The
impact of Ge-enrichment of N- or C–doped GST-225 based
materials on both SET and RESET performance have been
While GST-225 has the best performance of materials along studied [50]. Crystallization temperature ( ) increases almost
the GeTe- tie line (Fig. 7) it also has several drawbacks, linearly with Ge content, saturating at 2 at.% N content in
such as high RESET current, slow SET speed (when doped with N-doped Ge-enriched material, while C-doping boosts up
nitrogen or other dopants [44], [45]), and poor data retention at to roughly 400 . However, the best stability is observed
elevated temperatures. for GST-Ge 45%-N 4% devices (10 years at 210 ) [50].
Many efforts have been made to improve the low crystal- Tuning the morphology of phase-change material by forming
lization temperature ( ) of GST-225 ( 150 [33], [43]) by nano-crystalline structure inside GST is another way to im-
materials modification [44]–[46] but fast recrystallization al- prove device performance. Nano-crystalline doped-GST-225
ways seems to be associated with poor thermal stability. In fact, with a low thermal conductivity provides improved thermal
this unpleasant tradeoff appears to hold along the entire isoelec- stability ( ) and reduced RESET current (68%
tronic tie line for Sb-based materials (the blue line lower RESET current than GST-225) [52].
in Fig. 7) [47]. However, by combining two different tie-lines, A particular application requiring high thermal stability in-
materials that can offer better combinations of fast recrystalliza- volves pre–coded data, where PCM devices programmed at the
tion and good thermal stability have been identified [48]. wafer level must survive all packaging processes, including ex-
In that work [48], the best compromise material (GST-212) posure to temperatures of up to 260 during the solder-reflow
on the isoelectronic tie line was selected, and its high temper- process [35], [51]. Materials with higher such as N-doped
ature stability was further enhanced by increasing Ge concen- GeTe [53], C-doped GST with a Ti capping layer [54], and
tration along a second tie line between Ge and (dashed Ge-enriched GST with N doping [50] have had only limited
purple line in Fig. 7). This “golden composition” provides high success for this demanding application. Ge-rich GST shows the
( compared to for GST-225), fast speed capability of improving to beyond [48] or even
(80 ns), lower RESET current, cycling endurance with higher Ge% in GST alloy [55]. could be fur-
and tolerance to up to 190 testing in a 128 Mbit PCM test ther increased up to 413 with appropriate Ge/N concentra-
chip [48]. tion in GST alloy, but at the cost of slower recrystallization [49].

Authorized licensed use limited to: UNIVERSITE DE SOUSSE. Downloaded on April 15,2022 at 12:40:03 UTC from IEEE Xplore. Restrictions apply.
150 IEEE JOURNAL ON EMERGING AND SELECTED TOPICS IN CIRCUITS AND SYSTEMS, VOL. 6, NO. 2, JUNE 2016

Fig. 8. a) - curves shift to higher current as a PCM device experiences addi-

Fig. 9. Shmoo plot (log of ratio of resistance before a single brief SET pulse
tional voltage stress, allowing b) the programming of “background logic” levels
to the resistance afterward) for atomic-level engineered GST PCM cells using
that can remain separated even after baking at 300 for 1 h. Information stored
a thermally confined electrode. 10 resistance ratio can be achieved at 20 ns,
in such levels can withstand the solder-reflow process. (Reprinted, with permis-
RESET current is 150 . (Reprinted, with permission, from [60].).
sion, from [56].).

GBT [61]. While more than 5% Bi doping led to low resistance

Alternatively, it is possible to electrically stress a PCM cell, contrast between RESET and SET states, doping was
storing data in a temperature-persistent way through permanent reported to support resistance contrast, as well as both
yet detectable changes in the - behavior [Fig. 8(a)] [28], [56]. fast switching and high endurance [61].
This data is read by applying moderate RESET pulses after a Post phase-change material deposition processing can also
SET operation, since unstressed bits (exhibiting the original - have a significant effect on device behavior. [34] showed
behavior) will RESET, while stressed bits will not. This “back- that the choice of the dielectric capping layer above the PCM
ground logic” storage shows excellent thermal stability even element could strongly affect the SET speed and retention,
after baking at 300 for 1 h [Fig. 8(b)]. and could permit the integration of memories with different
functions on the same chip. Changes in the SET operation
IV. IMPROVEMENTS IN SWITCHING SPEED which combine the RESET and SET pulses (taking advantage
In addition to long-term data retention, fast switching speed is of the threshold-voltage lowering achieved after RESET) can
always desirable. A material offering both ultrafast SET speed also help produce lower SET resistance without increases in
( ) and very high endurance ( ) could potentially overall pulse duration [50].
be used for DRAM replacement [28]. Storage Class Memory The systems implications of such materials improvements,
(SCM) [57], [58], which would sit just below DRAM in the in terms of either higher thermal retention (previous section)
memory hierarchy, requires reasonably high endurance ( and/or faster switching speed (this section) are the expansion of
, to give a 2 GB chip a system lifecycle of three years new market opportunities for PCM-based systems, while being
[58]) and read and write access times of 100–300 ns [58]. Un- supported with a tractable amount of error–correction coding.
fortunately, the SET speed of GST-225 is barely sufficient for
such high-speed applications, and because of large volume dif- V. IMPROVEMENTS IN SWITCHING POWER
ferences between the crystalline and amorphous phases, this ma- PCM device performance is often directly related to the
terial exhibits limited cycling endurance. properties of phase-change materials. For examples, a material
Doping of GST by PVD co-sputtering process can signifi- offering low heat capacity, low heat of fusion, low melting
cantly improve the endurance [59], but at the cost of even slower point, low thermal conductivity and high electrical resistance
switching speeds. Since such dopants are sputtered as com- in its crystalline phase would lead to significantly less power
pound molecules into the GST matrix, they do not fully interact consumption for the RESET operation, with the caveat that if
and bond with the GST, leading to Ge-Ge covalent bonding and crystalline electrical resistivity is too high, this reduces read
slow switching. By atomic-level engineering (the introduction current and makes it difficult to perform the read operation
of dopants through reactive sputtering of a compound target rapidly. Other technologies explored to reduce RESET power
as opposed to co-sputtering of multiple targets), Ge-Sb/Ge-Te include doped phase-change materials [52], thermally-confined
metallic bonding similar to undoped GST-225 can be observed, cell designs [62], and thermally-confined bottom electrodes
and improved results can be obtained. Atomic-level engineered [63]. [63] investigated the influence of bottom electrode design
films exhibit cycling endurance three orders of magnitude in a typical mushroom cell, finding that a thermally confined
higher than undoped GST-225, without the shifting resistance electrode (TaN/TiN/TaN) could drastically reduce the RESET
window exhibited by GST doped by co-sputtering [60]. Yet current compared to a solid TiN electrode (the effect on SET
the switching speed of such atomic-level engineered GST resistance was not disclosed).
remains very fast (Fig. 9), showing observable switching with Most recent improvements to PCM cell design have been
20 ns pulses in a 128 Mbit PCM chip [60]. This material can aimed at better thermal efficiency, for efficient Joule heating of
satisfy 55 , 20 years retention with failure rate lower than phase-change material in a small programming volume, while
10 ppm, fast switching speed of 20 ns, and an endurance of 1 balancing the cell resistance (lower resistance enables faster
G-cycles suitable for SCM application [60]. Lee et al. showed read speed) against programming current (higher resistance re-
a combination of high endurance (1e9 cycles) and fast SET duces power consumption) [62]–[65]. It has long been known
switching (down to ) by using Bismuth-doped GeTe, or that for a given cross-sectional area, a volume-confined PCM

Authorized licensed use limited to: UNIVERSITE DE SOUSSE. Downloaded on April 15,2022 at 12:40:03 UTC from IEEE Xplore. Restrictions apply.
BURR et al.: RECENT PROGRESS IN PHASE-CHANGE MEMORY TECHNOLOGY 151

Fig. 11. (a) X-ray characterization of in-situ crystallization of an ALD derived

film (23 at. % Ge, 28% Sb , 49% Te) and (b) comparison of crystallization tran-
sition with a PVD film. (© Elsevier, all rights reserved. Reprinted, with permis-
sion, from [80].).

Fig. 10. TEM images of a) Vertical Self-Heating Pillar architecture, b) Vertical,

heater-based, Wall architecture, c) Planar Self-Heating Line-Bridge architecture
(SEM), and d) Vertical Self-Heating Wall (SHW) architecture. e) IPROG-RSET
diagram. (Reprinted, with permission, from [65].).

cell can have a lower RESET current compared to a contact-

minimized PCM cell (for example, see Fig. 7 of [21]). A study
of PCM cell characteristics as a function of cell structure in-
dicates that RESET current vs. SET resistance mostly follows
a certain trend regardless of the cell structure [65] (Fig. 10).
Programming current can even dictate array density by forcing
the use of a large access device. Even in extreme cases where
RESET current is scaled down below 5 with a CNT elec-
trode, this same resistance/power tradeoff is present, resulting in
SET resistances higher than [66]–[68]. [64] introduced
Fig. 12. (a) High-Angle Annular Dark Field (HAADF)-Scanning Transmission
a PVD-deposited GST sidewall cell, showing a substantial im- Electron Microscope (STEM) image of GeTe/ superlattice (Reprinted,
provement in heating efficiency (lower product) with permission, from [87]) and (b) schematic understanding of GeTe/
compared to a thin ring bottom electrode mushroom cell using super-lattice, in which change in resistance is caused by Ge movement between
a Ge 4-fold state (RESET state) and a Ge 6-fold state (SET state) (Copyright
the same phase-change material. [69] introduced a graphene 2013 The Japan Society of Applied Physics. Reprinted, with permission, from
layer to reduce thermal contact resistance and decrease RESET [89].).
current.
Since switching power scales directly with switching
volume, one of the bigger challenges with scaling PCM tech- (C, Cl, H, N, etc.), and even its ease of delivery must all be
nology is optimizing and controlling the desired composition considered. Advanced ALD and CVD can deposit films with
of phase-change materials [70], while achieving reasonable comparable characteristics to PVD-deposited films (Fig. 11)
deposition rates into aggressively-scaled dimensions needed with impressive coverage yet much slower deposition rate.
for the commercialization of future technology nodes [21]. Improved precursors [80], utilization of a plasma [75], [76], or
For technology nodes that require structures with dimensions cyclic sequencing [77], [81] can improve deposition. Improve-
below 50 nm, the PCM materials community has largely ments in compositional and morphology control have produced
shifted from PVD (preferable for flexible materials and device both improved films [81], [82] and devices at aggressive di-
resesarch) to CVD, atomic layer deposition (ALD), and other mensions [21]. Yet key points critical for integration — such
techniques [71]–[73] (Fig. 11) that can fill high aspect ratio as densification, resilience and selectivity to etch processes,
holes. Such techniques include pulsed laser deposition (PLD) and systematic studies of the effect of contaminants on device
[74] (which allows for low temperature deposition), atomic operation — still remain challenges in materials development.
vapor deposition [75]–[77], pulsed deposition followed by Interfacial PCM (iPCM) introduces a superlattice
etching (where redeposition helps improve fill quality) [78], phase-change material stack, formed by alternating two crys-
and electrochemical formation [79]. talline layers with different composition [Fig. 12(a)]. For
There are inherent difficulties with such non-PVD deposi- instance, the alignment of the c-axis of a hexagonal
tion techniques. Ternary systems such as GeSbTe have fairly layer and the direction of a cubic GeTe layer in a
complicated phase diagrams, with composition affecting speed, superlattice can allow Ge atoms to switch between octahedral
crystallization temperature, retention, and chemical stability sites and lower-coordination sites at the interfaces between
under operation (e.g., endurance) [1]. Non–PVD deposition superlattice layers [83]. Previously, the programming power re-
introduces additional considerations due to the need for a duction in a similar superlattice-like structure was attributed to
chemical “precursor”: its reactivity, decomposition profile and the decreased thermal conductivity of the structure [84]. How-
residence time, the ligand’s potential to introduce contaminants ever, Tominaga et al. [85] has proposed that the superlattice

Authorized licensed use limited to: UNIVERSITE DE SOUSSE. Downloaded on April 15,2022 at 12:40:03 UTC from IEEE Xplore. Restrictions apply.
152 IEEE JOURNAL ON EMERGING AND SELECTED TOPICS IN CIRCUITS AND SYSTEMS, VOL. 6, NO. 2, JUNE 2016

stack switches between LRS and HRS without melting the ma-
terial [Fig. 12(b)]. In contrast to conventional PCM switching
achieved by order-disorder transition, iPCM switching is said
to depend on short-range movement of atoms [86], [87], with
the conduction channel of Te-Te inducing the difference in
resistance. In the SET state, the atomic sequence is believed
to be Ge-Te-Te-Ge, while in the RESET state; the sequence is
Te-Ge-Ge-Te [87].
This ability to switch without melting should then lead to
both reduced power consumption and improved endurance [83]. Fig. 13. a) Disturbed cell resistance as a function of disturbing current. Dis-
turbed cell is initially written by program & verify scheme to make 1.0
RESET current as small as 3 has been demonstrated with RESET state. b) RESET volume characterization in the disturbance-induced
/ superlattice PCM cell at a SET resistance of failed bits. Test sequence: odd numbered cells RESET/even numbered cells
30 [88]. Since its first introduction, device performance of RESET/read all (odd and even numbered cells) (Reprinted, with permission,
from [107].).
superlattice PCM stacks has been continuously improved, by
optimizing the superlattice stack design and by decreasing the
cell size [86], [87], [89], [90]. Although the conduction mech- change as its neighbors are repeatedly programmed (Fig. 13),
anism, switching mechanism, and even the precise multilayer and proposed that this issue could be avoided by reducing
structure are still not fully understood, various physical proper- the required RESET current of the PCM cell. It has also been
ties of the superlattice stack such as magnetoelectric property shown that the phase-change material thickness as well as the
are being explored as well [91], [92]. properties of the capping layer on the phase-change material in
Circuit and systems implications of lower switching power the Wall-type PCM cell structure can influence thermal disturb
can be sizeable, since high memory-device switching power can (Fig. 3) [23].
easily lead to unpleasant density reductions that can strongly in- Alternative materials, such as stoichiometric GaSb, can offer
crease memory cost. These can be due to increases in cell size both fast switching speed and good thermal stability [108],
(either to accommodate larger access devices or wider wires of- while showing a decrease in mass density upon crystallization
fering lower resistance losses), losses in area efficiency (larger- ( ) [109]. In contrast, typical phase-change materials
size drive transistors), or in lower write parallelism. such as GST-225 exhibit an increase in mass density 5%–6%,
with the crystalline phase being more dense than amorphous
VI. IMPROVEMENTS IN RELIABILITY phase. At a composition of Ga:Sb = 30:70, no mass density
Although PCM shows excellent endurance characteristics change is observed, which could potentially suppress void
for cycles, cycling-induced degradation can generate formation and thus extend PCM cycling endurance [108].
early tail-bits that trigger read errors, thereby limiting overall As mentioned earlier, higher reliability allows the use of
endurance. Three typical tail-bit behaviors are observed: more efficient ECC (error–correction coding) solutions, so as
cell-open, stuck-high (SET failure) and stuck-low (RESET to minimize the portion of the array used for redundant data,
failure) [93], [94]. Cell-open failure is attributed to void ag- and to maximize the portion available for user data. Efficient
glomeration and accumulation toward the bottom electrode ECC and wear-leveling schemes [110] also help keep area
(BE), leading to an “open” cell once the void completely blocks efficiency—the fraction of CMOS real-estate used for memory
current from reaching the BE. Stuck-low failure is attributed devices as opposed to peripheral circuits—high. As we will
to Sb enrichment in the active volume during repeated cycling see in the next section, 3D access devices can help move the
[95]–[98], which decreases dynamic resistance and increases memory above the front-end silicon real-estate, thus relaxing
RESET current. The onset of this failure mode is observable this tension between utilization of silicon for peripheral cir-
as a “right-shift” of the - characteristics [99] [Fig. 8(a)]. cuitry versus that needed for access devices. However, the
Stuck-high failure is a transitional behavior between stuck-low need for numerous dense-pitch vias between the underlying
and cell-open due to GST phase segregation or voids at the circuitry and the overlying memory layers still imposes strong
interface between GST and BEC [96], [98], [100]. Void forma- constraints on how flexibly the silicon can be utilized.
tion is driven by mechanical stress due to the repeated changes
in volume during SET-RESET switching, while phase sepa- VII. IMPROVEMENTS IN DATA DENSITY: 3D
ration is driven by incongruent melting and recrystallization Besides memory cell engineering, care must be taken to
at the boundary between liquid and solid [96], [100]–[102]. choose an access device capable of delivering high current and
A cell design that promotes complete melting [103] can help power without requiring a significantly larger footprint than
suppress phase segregation. Other techniques for minimizing the PCM element itself. This becomes even more complicated
cycling degradation include reductions in SET pulse width and when designing integration schemes which could allow for
lower SET current [104], [105], to reduce SET-induced elec- higher effective data density (and thus lower cost) through 3D
tromigration and phase segregation. An In-Situ-Self-Anneal memory arrays with multiple layers of PCM cells [111]. Here
(ISSA) healing procedure can extend cycling endurance by the access devices must also be fabricated with temperatures
occasionally rejuvenating stressed PCM cells [106]. commensurate with Back-End-Of-Line processing ( )
As cell-to-cell pitch reduces, thermal write disturb can be a [111]. Polysilicon diodes [112], [113], carbon nanotube tran-
concern. [107] showed that the resistance of a PCM cell can sistors [114], OTS (Ovonic Threshold Switches) [115], [116],

Authorized licensed use limited to: UNIVERSITE DE SOUSSE. Downloaded on April 15,2022 at 12:40:03 UTC from IEEE Xplore. Restrictions apply.
BURR et al.: RECENT PROGRESS IN PHASE-CHANGE MEMORY TECHNOLOGY 153

FAST (Field-Assisted-Superlinear-Threshold) devices [117],

[118], and MIEC (Mixed Ionic Electronic Conduction) access
devices [119]–[122] have been proposed as 3D-stackable
access device candidates.
The main challenge with using a conventional p-n poly-sil-
icon diode in the BEOL is that the dopant activation needed
for high / ratio typically requires temperatures
. A poly-Si diode with an on-current density of 8
and off-current density of 100 was demon-
strated [112], by reducing contact resistances and a low-thermal
budget crystallization of boron-doped Si on tungsten electrode
(exact processing temperature was not disclosed). A much
larger scale, 1 Gbit PCM chip demonstration used a (84 Fig. 14. (a) Resistance distribution of a four-level cell using single-pulse pro-
nm pitch) poly-Si diode and PCM cell architecture [113], with gramming. Variations cause the distributions to overlap because the same ap-
plied voltage pulse can lead to different temperatures in different cells. (b) An
diode and PCM layers inserted between M0 and M1 layers. iterative programming scheme that exploits both left (LPS) and right (RPS) pro-
With the 1TnR architecture proposed in [114], each carbon gramming slopes can produce tight, well-controlled distributions (colors used
nanotube serves both to define the bottom electrode size and to simply to distinguish the different MLC levels). (Reprinted, with permission,
from [131].).
gate the current delivered to a row of devices. However, both
drive and read currents were low and only low endurance (100
SET-RESET cycles) were demonstrated [114]. only on a linear scale (and thus the actual / ratio is un-
Copper-containing MIEC-based access devices have been known). Similar to the FAST devices, large array operation with
shown to scale to less than 30 nm diameter and 12 nm thickness OTS selectors requires tight distributions on both switching and
while maintaining high voltage margin and large ON/OFF hold voltages.
ratios [121], and have exhibited tight margins and 0.5 Mbit Intel and Micron recently announced a new “3D Xpoint
arrays at 100% yield [120]. While read current levels have a memory” technology, which is effectively a crosspoint-based
very fast recovery, higher write currents require a brief ( ) Storage Class Memory. This technology is said to be based on
post-write recovery sequence [122]. A new selector based on an improved OTS-type chalcogenide selector together with a
“multiple filaments” was introduced by Crossbar [117], [118], state–holding element based on “changes in resistance of the
which offers extremely high contrast between an ultra-low bulk material” [125]. Although details of the new technology
leakage regime and an abrupt switch into a conductive state. have not been released, there is significant speculation that the
Considerations for how to terminate the conductive state have state–holding element is in fact phase-change memory [126].
been discussed [118]. The key to this technology will be imple-
menting extremely low device-to-device distributions on both VIII. IMPROVEMENTS IN DATA DENSITY: MLC
switching voltage (affecting when the device turns ON) and The large resistance contrast of PCM provides the multiple
holding voltage (affecting read SNR and increasing worst-case analog levels needed for Multiple Level Cell (MLC) operation
overwrite of the state-holding device). [1], another path to reducing cost per bit. The fraction of amor-
An alternative form of “3D PCM” has also been proposed, phous material (and thus the cell resistance) can be controlled
with a vertical stack of multiple PCM cells between each bit by varying pulse amplitude or the width of the trailing edge of a
line and word line, in series with a single poly-Si selection diode pulse [127]–[129]. However, given device-to-device variations
[123]. Each PCM cell contains a state–bearing PCM element in across an array, it is difficult (if not impossible) to achieve iden-
parallel with a poly-Si pass transistor, with each vertical stack tical states across a large array using blind application of pro-
potentially fitting either within the area of the underlying gramming pulses [Fig. 14(a)]. Inter-cell variability arises from
selector, or in the area required to maintain the minimum thick- distributions in the thickness or lateral (electrode) dimensions
ness of the thin-film layers (projected to be 32 nm once the PCM from device to device; intra-cell, or cycle-to-cycle variability
material is scaled down to 2 nm thickness). However, in this arises from differences in both the atomic configuration of amor-
publication, only a nominal cross-section of a -wide phous regions as well as the distribution of polycrystalline nu-
via and device-results from single PCM cells were shown. clei and grain boundaries from one programming cycle to the
The OTS access device has been utilized in a 64 Mbit cross next [39], [130].
point test chip using a PCMS (PCM + OTS) cell architecture In NAND Flash, MLC is implemented by a uni-directional
[115]. In this demonstration there were rows and columns of write-and-verify algorithm, with threshold voltage slowly
metal lines with a PCMS cell (comprising a PCM cell sitting increased until the desired target is met. However, PCM
on an OTS layer) at each intersection, inserted between M2 and can be programmed either with unidirectional partial-SET
M3 above 90 nm CMOS technology. The OTS material, speci- pulses [amorphous to crystalline phase transition, left side
fied only as a chalcogenide that remains in the amorphous phase of Fig. 14(b)], or with bidirectional partial–RESET pulses
[115], [124], is designed to have a threshold voltage lower than [dominated by melt-quench processes, right side of Fig. 14(b)]
that of the RESET PCM cell. While RESET and SET state dis- [131], [132]. A write-and-verify sequence uses a feedback loop
tributions for the PCMS were shown for a 2 Mbit block demon- to achieve low error between programmed and specified target
strating greater than 1 V margin, - curves were presented resistance levels [Fig. 14(c)] [127], [131]. These sequences can

Authorized licensed use limited to: UNIVERSITE DE SOUSSE. Downloaded on April 15,2022 at 12:40:03 UTC from IEEE Xplore. Restrictions apply.
154 IEEE JOURNAL ON EMERGING AND SELECTED TOPICS IN CIRCUITS AND SYSTEMS, VOL. 6, NO. 2, JUNE 2016

be designed either to minimize the write latency (by measuring

and correcting current errors in the analog domain [131]),
or to reduce energy consumption (by minimizing the use of
high-energy melting pulses). Iterative MLC programming at 2
bits/cell was accomplished on a 512 Mbit PCM chip (90 nm
node) [132], with the programming algorithm converging in
less than 13 iterations for 99.9% of the cells, resulting in a write
access time of 9.8 .
Unfortunately, after almost any PCM device is programmed, Fig. 15. Resistance evolution of a PCM cell as a function of time, during the
temperature profile shown in the inset. A collective relaxation model captures
its resistance tends to increase in time due to a phenomenon the resistance variation remarkably well. (Reprinted, with permission, from
called resistance ‘drift,’ as the amorphous phase of the mate- [135].).
rial undergoes structural relaxation and stress release. When the
molten phase-change material is quenched rapidly, the atomic
configurations are frozen into a highly stressed glass state that
wants to relax to lower energy states [133]–[135]. Resistance
drift is universally observed to follow a power law relationship
[97], [136], [137], , where is the time
elapsed since cell programming, and represents the pro-
grammed resistance level as measured at time . The “drift co-
efficient,” , tends to be largest ( ) for the highest resistance
states, although the amorphous-like material at polycrystalline Fig. 16. An alternative, drift-resilient read metric allows the distinction of high
grain boundaries causes drift to be present in partial–SET states resistance states that would (a) otherwise have very similar low-field resistances.
Because such states (b) exhibit notably different voltage at which read cur-
as well [39]. rent reaches a particular detection current (here 1 ), ramping read
While drift inherently reduces the memory window, its most voltage linearly and recording the time required to reach can distinguish
formidable challenge for PCM MLC technology arises from these levels from each other. (Colors are used simply to distinguish different
programmed states.) (c) The resulting alternate read metric, “ ,” offers more
variability (both intra- and inter-device) in the drift coefficient unique states—here six levels instead of the original four. (Reprinted, with per-
[138]. A simple “refresh” operation (similar to DRAM) could mission, from [148].).
potentially be used to handle PCM resistance drift [139], but re-
fresh timing would be mandated by worst-case cell performance
[140], with short refresh times leading to early exhaustion of de- Such a model can describe the time/temperature dependence
vice endurance as well as the frequent opportunity for decoding of resistance variations remarkably well, as shown in Fig. 15.
errors. At constant ambient temperature, the resistance exhibits the ex-
Significant low-frequency fluctuations are also observed on pected exponential drift relationship (with a typical value of
top of the mean current, , with a constant normalized cur- for highly resistive MLC states), yet undergoes large
rent spectral density and a frequency dependence steps when temperature is changed.
[141], [142]. These fluctuations have been attributed to vari- Although Ge doping of GST-225 was observed to increase
ations in the optimal current path through the polycrystalline the drift coefficient while decreasing the resistance of the cell
grain boundaries, present both in intermediate SET states as well [50], adding dopants tends to reduce drift, with N-doped Ge-en-
as at the edge of the amorphous plug in any RESET state [39]. richment showing a pronounced effect, possibly due to the
These resistance increases in time due to drift will also be suppression of relaxation in the additional Ge amorphous phase
affected by temperature. Because electrical transport in amor- through the presence of stable Ge-N bonds. For MLC storage
phous phase-change materials is thermally activated (with ac- class memory application, a material with wider memory
tivation energies of 0.2–0.4 eV [135], [143], programmed re- window and manageable resistance drift was demonstrated
sistance levels typically exhibit significant temperature depen- [146].
dence. Drift then represents a variation in this activation energy A number of techniques for coping with drift have been pro-
with time. Structural relaxation has previously been described posed. One approach is to choose the original write-target re-
by a two-state defect-relaxation model [144], based on the pop- sistances to take into account the expected broadening of the
ular relaxation model of Gibbs [145]. Here, the idea is that as resistance distributions due to drift [128]. Another approach
relaxation proceeds, defects with lower activation energy will is the design of cell-state metrics that are more representative
be removed first, followed by those with higher activation en- of the drift-invariant phase configuration [147]. Conventional
ergy. The distribution of activation energies would then track low-field resistance at read voltages of 0.1–0.4 V tends to sat-
the state of relaxation of the material at any instant in time. urate at high programming currents [Fig. 16(a)]. For instance,
In an alternative microscopic picture, the atomic configura- in Fig. 16(b), there are a number of resistance states that show
tions collectively relax towards a more favorable equilibrium identical current at low read voltage (say, 0.1 V) which differ
state (a possible ideal glass state), in a sequence of transitions from each other significantly in terms of the voltage at which
between neighboring unrelaxed amorphous states [135]. Here read current reaches a higher current (say, 1 ).
an order parameter, capturing the “distance” between unrelaxed An alternative cell-state metric can use this fact to distinguish
states and the ideal glass state, tracks the state of relaxation. between such high resistance states [148], offering the potential

Authorized licensed use limited to: UNIVERSITE DE SOUSSE. Downloaded on April 15,2022 at 12:40:03 UTC from IEEE Xplore. Restrictions apply.
BURR et al.: RECENT PROGRESS IN PHASE-CHANGE MEMORY TECHNOLOGY 155

Fig. 17. (a) The temporal evolution of resistance corresponding to two

MLC states. (b) The corresponding temporal evolution of a drift-resilient
cell-state metric. (Reprinted with permission from [147]. Copyright 2011, AIP
Publishing.)

for more MLC levels [Fig. 16(c)]. The metric used is the time
needed for the read current to reach a reference value during
a linear voltage ramp, so that no resistance state ever experi-
ences a read condition that would perturb the state. Yet this Fig. 18. (a) Schematic diagram of a PCM cell with metal nitride surfactant in
metric allows the deepest RESET states to be distinguished from the full SET state, in a partial RESET state, and in the full SET state, along with
modest yet equally resistive RESET states. The reference cur- equivalent circuit models. The metal nitride layer provides an alternative read
current path to the amorphous region, with its effective resistance modulated
rent value, —at which the linear voltage ramp terminates, by the thickness of the amorphous region. Median and standard deviation of
defining this alternative “ ” metric by relating the time-delay resistance versus time comparing PCM devices built (b) without and (c) with
to read voltage at —may be fixed or varied as a function the metal nitride surfactant. With the surfactant, resistance contrast is slightly
reduced, but the drift coefficient is reduced 6 . (Reprinted, with permission,
of the instantaneous voltage value [147]–[149]. This ramped from [72].)
read-voltage approach avoids the read disturb that would oth-
erwise occur if the high read voltages needed to distinguish the
deepest RESET levels were applied to all cells. Since this al- is coding and signal processing, which can complement both
ternative cell-state metric is less sensitive to bandgap variations drift-resilient cell-state metrics and drift-resilient cell design.
[147], the effects of drift are strongly reduced as compared to Rather than detect stored data with fixed thresholds, detection
normal drift behavior of the low-field resistance (Fig. 17). thresholds can be adapted according to the changing character-
Kim et al. [72] introduced a PCM cell design integrated istics of the memory cells, not with reference cells, but through
with a metal nitride (“metallic surfactant”) layer to stabilize modulation coding in which small blocks of user data are en-
the resistance of the PCM cell in the RESET state. The metal coded into short codewords [136], [150]. By storing information
nitride layer helps mitigate resistance instabilities such as re- in the relative order of levels (which is maintained over time
sistance drift, noise, and temperature dependence by providing quite well) within each codeword, such codes can offer robust-
an alternative current path around the amorphous region during ness to drift. Balanced codes, where each stored level appears
the read operation [Fig. 18(a)]. In this structure an in-situ (approximately) the same number of times, provide for easier
process of a thin metal nitride layer plus phase-change material parameter estimation and better estimation of the changing level
deposition lines and fills a hole, making contact to a lower thresholds [151]. The combination of coding, adaptive threshold
electrode exposed at the bottom of the hole. The lack of a detection and judicious placement of target programmed levels
vacuum break between the metallic liner and the deposition can lead to remarkable tolerance to drift and variability, even
of the phase-change material helps ensure a strong interface for prolonged periods of time after programming. A PCM array
between the lower electrode and the phase-change material. of 64 k cells, cycled 1 million times and then programmed at 4
Such a design can reduce the effective drift coefficient by 6 levels/cell, could be reliably detected more than 45 days later at
[Fig. 18(b) and (c)], resulting in lower error rate for given error rates close to , using permutation modulation coding
retention time with 2-bit-per-cell MLC PCM. This design does and adaptive threshold detection (Fig. 19) [150]. Further en-
reduce the maximum ON-OFF resistance ratio of the PCM cell, hanced robustness to drift has recently been demonstrated in
because the drift benefits only arise when the resistance of the MLC PCM arrays even after exposure to elevated temperatures,
metallic surfactant is lower than that of the amorphous-GST. by employing advanced readout metrics and coding/detection
However, this structure was also shown to greatly reduce the schemes [149].
number of open failures (compared to a version of the cell To a larger extent than other aspects of PCM technology,
without the metal nitride liner) during a write endurance test MLC operation has already incorporated and involved nu-
[72]. merous circuit and systems advances, ranging from customized
The variability of resistance drift causes stored level-distri- circuitry for rapid iterative write to modulation coding for
butions to shift and broaden over time, seriously affecting the drift-resilient coding to new readout schemes that are drift
ability to accurately retrieve previously-stored information. An- resilient. However, numerous opportunities still exist for ad-
other approach to cope with MLC PCM drift and variability vancing the state-of-the-art in MLC for phase-change memory.

Authorized licensed use limited to: UNIVERSITE DE SOUSSE. Downloaded on April 15,2022 at 12:40:03 UTC from IEEE Xplore. Restrictions apply.
156 IEEE JOURNAL ON EMERGING AND SELECTED TOPICS IN CIRCUITS AND SYSTEMS, VOL. 6, NO. 2, JUNE 2016

Fig. 20. a) Spike Timing Dependent Plasticity (STDP) as observed in rat hip-
pocampal neurons [159] and b) as observed in mushroom-cell PCM devices. (©
ACM, all rights reserved. Reprinted, with permission, from [154].)

Fig. 19. Adaptive threshold detection schemes show lower error rates as a func-
tion of time on a 64 kcell array (previously exercised through 1 million program-
ming cycles). (Reprinted, with permission, from [150].)

IX. NEUROMORPHIC APPLICATION

The goal of neuromorphic engineering is to develop elec-
tronic systems that can mimic the fuzzy, fault-tolerant and
stochastic computation of the human brain, without sacrificing
its space or power efficiency. Here, nanoscale, two-terminal
devices that can emulate the plasticity and energy effi-
ciency of biological synapses may be a key element. Both
PCM [152]–[157] and ReRAM [158] have been proposed
for this application. Most of this work has emphasized the
Spike-Timing-Dependent-Plasticity (STDP) algorithm, moti-
vated by synaptic measurements in real brains. Pulse-timing Fig. 21. Neuro-inspired non-Von Neumann computing, in which neurons acti-
schemes for crossbar arrays of PCM [152], [154], adaptations vate each other through dense networks of programmable synaptic weights, can
be implemented using dense crossbar arrays of nonvolatile memory (NVM) and
to support negative weights [153], and the required device selector device-pairs. (Reprinted, with permission, from [160].)
energetics [155] have been studied. Initial demonstrations
of integrated hardware have demonstrated 256 256 neuron
arrays with 64 000 synapses [157]. vices to act more like a bidirectional NVM with a symmetric,
However, experimental NVM demonstrations of STDP- linear conductance response of high dynamic range [161].
based networks have not reported quantitative performance If competitive classification accuracies can be demonstrated,
metrics such as classification accuracy. The relatively poor met- such systems could potentially offer faster (up to 25 ) and
rics reported to date [when compared to conventional Machine lower power (from 120–2850 ) on-chip machine learning
Learning (ML)] may be due to immaturities or inefficiencies in (ML) of large-scale artificial neural networks (ANN) than
the STDP learning algorithm as it is currently implemented. In conventional Graphics Processing Unit (GPU)-based hardware
this context, it is difficult to discern the specific problems that [162]. An important component of such accelerated ML is
may be introduced by the inherent imperfections of the PCM the design and implementation of circuitry that can integrate
(or memristor) devices. and digitize aggregate (column-wise) read-currents on many
Using two PCM devices per synapse [153], a three-layer per- synaptic bitlines in parallel, minimizing the delay involved
ceptron network with 164 885 synapses was trained on a subset when these operations are implemented by time-multiplexing
(5000 examples) of a database of handwritten digits, using a the same physical circuitry.
backpropagation variant suitable for crossbar arrays, obtaining
training and test accuracies of 82%–83% (Fig. 21) [160]. Un- X. OTHER APPLICATIONS
like STDP, backpropagation is widely used by computer scien- In addition to the data-storage and neuromorphic ap-
tists to train artificial neural networks on handwritten digits, im- plications, several researchers have proposed the use of
ages, and speech recognition data. A neural network simulator phase-change memory to store Look-Up Tables (LUTs) [163],
matched to the experimental demonstrator was used to perform [164] or Ternary Content–Addressable Memories (TCAMs)
tolerancing with respect to variability, yield, and the stochas- [165]–[167]. In an LUT application, each address location reads
ticity, linearity and asymmetry in PCM-conductance response out a small set of digital bits (either for subsequent use [164] or
[160], [161]. This work showed a path towards high classifica- for digital calibration [163]). In a TCAM operation, each row of
tion accuracies if improvements in either phase-change mate- the stored database is correlated against the incoming data, with
rials or the training algorithm [161], [162] can allow PCM de- matching rows indicated on dedicated match-lines [165]–[167].

Authorized licensed use limited to: UNIVERSITE DE SOUSSE. Downloaded on April 15,2022 at 12:40:03 UTC from IEEE Xplore. Restrictions apply.
BURR et al.: RECENT PROGRESS IN PHASE-CHANGE MEMORY TECHNOLOGY 157

Here the design difficulty is in ensuring that the match-lines will [5] Int. Technol. Roadmap Semiconductors, , 2013 [Online]. Available:
NOT trigger for even a single mismatching bit despite the resis- www.itrs.net
[6] R. Waser, R. Dittmann, G. Staikov, and K. Szot, “Redox–based
tance variability between stored PCM elements. Circuit design resistive switching memories—Nanoionic mechanisms, prospects,
issues include achieving high performance (many comparisons and challenges,” Adv. Mater., vol. 21, no. 25-26, pp.
per second) while keeping total chip power low, despite the 263+–2632, 2009.
[7] H. S. P. Wong et al., “Metal–oxide RRAM,” Proc. IEEE, vol. 100, no.
large number of very long match lines. Ref [166] proposed the
6, pp. 1951–1970, 2012.
use of negative differential resistance to ensure significant con- [8] L. Goux et al., “Understanding of the intrinsic characteristics and
trast between the full-match and single-mismatch conditions. memory trade–offs of sub– filamentary RRAM operation,” in
Yet another emerging application is that of performing certain Symp. VLSI Technol., 2013, p. T12.1.
[9] N. Raghavan et al., “Stochastic variability of vacancy filament con-
computational tasks using the physical aspects of PCM devices figuration in ultra–thin dielectric RRAM and its impact on off–state
such as crystallization dynamics [168]. reliability,” in IEDM Tech. Dig., 2013, p. 21.1.
[10] R. Degraeve et al., “Quantitative endurance failure model for filamen-
tary RRAM,” in Symp. VLSI Technol., 2015, p. T14.5.
XI. CONCLUSION [11] N. Ramaswamy, “Panel session: CBRAM, metal oxide RRAM, or
other? Potentials and challenges of the device and material systems,”
We have surveyed recent progress in phase-change memory presented at the 4th Int. Workshop Resistive Memories, Stanford, CA,
(PCM) over the past five years. Initial commercial products Oct. 2014.
have appeared, showing a decided trend towards more compact [12] Y. Hayakawa et al., “Highly reliable TaOx ReRAM with centralized
filament for 28–nm embedded application,” in Symp. VLSI Technol.,
planar access devices and confined cells enabled by continued 2015, p. T2.2.
improvements in Atomic Layer Deposition (ALD). Materials [13] S. Sills et al., “Challenges for high–density 16 gb reram with 27 nm
research continues to improve high-temperature retention, to technology,” in Symp. VLSI Technol., 2015, p. JFS2–2.
the point that precoded applications requiring solder-reflow [14] C. J. Chevallier et al., “A 0.13 64 Mb multi–layered conductive
metal–oxide memory,” in ISSCC 2010, 2010, p. 14.3.
and perhaps even automotive applications may be within reach. [15] B. Govoreanu et al., “a–VMCO: A novel forming–free, self–recti-
Materials and cell-design efforts have worked to decouple fying, analog memory cell with low–current operation, nonfilamentary
the unpleasant tradeoffs between long-term retention and fast switching and excellent variability,” in Symp. VLSI Technol., 2015, p.
T9.3.
switching speed, and between low power and fast reading [16] R. Annunziata et al., “Phase change memory technology for embedded
(low SET resistance). Superlattice materials promise lower non volatile memory applications for 90 nm and beyond,” in IEDM
switching power by avoiding melting, while the role of device Tech. Dig., 2009, pp. 5.3.1–5.3.4.
[17] K. Attenborough et al., “Phase change memory line concept for em-
stress in endurance is being understood and even exploited.
bedded memory applications (invited),” in IEDM Tech. Dig., 2010, p.
Finally, designers move towards higher density through 3D 29.2.
(enabled by Back End of the Line (BEOL)–capable access de- [18] G. Servalli, “A 45 nm generation phase change memory technology,”
vices) and through Multiple Level Cell (MLC) approaches. The in IEDM Tech. Dig., 2009, p. 5.7.1.
[19] K. S. Lee et al., “Selective epitaxial growth of silicon for vertical diode
relaxation of the amorphous phase that causes MLC resistance application,” Jpn. J. Appl. Phys., vol. 49, no. 08, p. 08JF03, 2010.
states to ‘drift’ is better understood, leading to improvements in [20] K. J. Lee et al., “A 90 nm 1.8 V 512 Mb diode–switch PRAM with 266
device programming, device read, cell design, and coding and Mb/s read throughput,” IEEE J. Solid State Circ., vol. 43, no. 1, pp.
150–162, 2008.
signal processing approaches that can ensure reliable retrieval
[21] M. Kang et al., “PRAM cell technology and characterization in 20 nm
of stored data. Finally, early work in using PCM devices as node size,” in IEDM Tech. Dig., 2011, p. 3.1.
plastic synapses in non-Von Neumann computing and for [22] A. Redaelli, L. Laurin, S. Lavizzari, C. Cupeta, G. Servalli,
Look-Up Tables (LUTs) and Ternary Content–Addressable and A. Benvenuti, “High Ion/Ioff ratio BJT selector for 32 cell
string resistive RAM arrays,” in Eur. Solid State Device Res.
Memories (TCAMs) were surveyed. Conf., 2014, pp. 238–241.
The future for PCM is bright, as it continues to evolve and im- [23] A. Redaelli et al., “Interface engineering for thermal disturb immune
prove through the steady efforts of numerous researchers. High phase change memory technology,” in IEDM Tech. Dig., 2013, p. 30.4.
[24] F. Bedeschi et al., “4–mb MOSFET–selected mu trench phase–change
capacity storage class memories are ideal for today's big data memory experimental chip,” IEEE J. Solid State Circ., vol. 40, no. 7,
applications, promising vast memories for fast, business-critical pp. 1557–1565, Jul. 2005.
analytics. Neuromorphic computing may open a path towards [25] J. H. Oh et al., “Full integration of highly manufacturable 512
intelligent machines, improving computing by mimicking the Mb PRAM based on 90 nm technology,” in IEDM Tech. Dig.,
2006, p. 2.6.
incredible energy–efficiency of the human brain. The success [26] S. Ahn et al., “Reliability perspectives for high density PRAM manu-
of PCM requires only that realistic engineering solutions to its facturing (invited),” in IEDM Tech. Dig., 2011, p. 12.6.
now well-known idiosyncracies be developed and then imple- [27] Y. Choi et al., “A 20 nm 1.8 V 8 Gb PRAM with 40 MB/s program
bandwidth,” in ISSCC Tech. Dig., 2012.
mented at reasonable fabrication cost. [28] I. Kim et al., “High performance PRAM cell scalable to sub–20 nm
technology with below cell size, extendable to DRAM applica-
tions,” in Symp. VLSI Technol., 2010, p. T19.3.
REFERENCES
[29] D. Ha et al., “Active width modulation (AWM) for cost–effective and
[1] S. Raoux et al., “Phase–change random access memory: A scalable highly reliable PRAM,” in IEDM Tech. Dig., 2012, p. 31.8.
technology,” IBM J. Res. Develop., vol. 52, no. 4/5, pp. 465–480, 2008. [30] S. R. Ovshinsky, “Reversible electrical switching phenomena in disor-
[2] G. W. Burr et al., “Phase change memory technology,” J. Vacuum Sci. dered structures,” Phys. Rev. Lett., vol. 21, no. 20, p. 1450, 1968.
Technol. B, vol. 28, no. 2, pp. 223–262, 2010. [31] M. Chen, K. A. Rubin, and R. W. Barton, “Compound materials for
[3] H. S. P. Wong et al., “Phase change memory,” Proc. IEEE, vol. 98, no. reversible, phase–change optical–data storage,” Appl. Phys. Lett., vol.
12, pp. 2201–2227, Dec. 2010. 49, no. 9, pp. 502–504, 1986.
[4] G. Bruns et al., “Nanosecond switching in GeTe phase change memory [32] N. Yamada, M. Takenaga, and N. Takao, “Te–Ge–Sn–Au phase change
cells,” Appl. Phys. Lett., vol. 95, no. 4, p. 043108, 2009. recording film for optical disk,” in Proc. SPIE, 1986, vol. 695, p. 79.

Authorized licensed use limited to: UNIVERSITE DE SOUSSE. Downloaded on April 15,2022 at 12:40:03 UTC from IEEE Xplore. Restrictions apply.
158 IEEE JOURNAL ON EMERGING AND SELECTED TOPICS IN CIRCUITS AND SYSTEMS, VOL. 6, NO. 2, JUNE 2016

[33] N. Yamada, E. Ohno, K. Nishiuchi, N. Akahira, and M. Takao, [58] A. Bivens et al., “Architectural design for next generation heteroge-
“Rapid–phase transitions of GeTe– pseudobinary amorphous neous memory systems,” in Proc. 2nd Int. Memory Workshop, May
thin–films for an optical disk memory,” J. Appl. Phys., vol. 69, no. 5, 2010, vol. 1.3, pp. 8–11.
pp. 2849–2856, 1991. [59] C.-F. Chen et al., “Relaxation oscillation in GST–based phase change
[34] H. Lung et al., “Towards the integration of both ROM and RAM func- memory devices,” in Proc. EEE Int. Memory Workshop, May 2009, pp.
tions phase change memory cells on a single die for System–On–Chip 1–2.
(SOC) applications,” in Symp. VLSI Technol., 2014, p. T11.2. [60] H. Cheng et al., “Atomic–level engineering of phase change material
[35] H. Lung et al., “A method to maintain phase–change memory for novel fast–switching and high–endurance PCM for storage class
pre–coding data retention after high temperature solder bonding memory application,” in IEDM Tech. Dig., 2013, p. 30.6.
process in embedded systems,” in Symp. VLSI Technol., 2011, pp. [61] J. Lee et al., “Scalable high–performance phase–change memory em-
T5B–3. ploying CVD gebite,” IEEE Electron Device Lett., vol. 32, no. 8, pp.
[36] E. Morales-Sanchez, E. F. Prokhorov, J. Gonzalez-Hernandez, and 1113–1115, Aug. 2011.
A. Mendoza-Galvan, “Structural, electric and kinetic parameters of [62] S. L. Cho et al., “Highly scalable on–axis confined cell structure for
ternary alloys of GeSbTe,” Thin Solid Films, vol. 471, no. 1-2, pp. high density PRAM beyond 256 Mb,” in Symp. VLSI Technol., 2005,
243–247, 2005. pp. 96–97.
[37] A. Redaelli et al., “Impact of crystallization statistics on data retention [63] J. Wu et al., “A low power phase change memory using thermally con-
for phase change memories,” in IEDM Tech. Dig., 2005, pp. 742–745. fined TaN/TiN bottom electrode,” in IEDM Tech. Dig., 2011, p. 3.2.
[38] M. Salinga et al., “Glass transition and crystallization in phase change [64] S. C. Lai et al., “A scalable volume–confined phase change memory
materials,” in EPCOS 2007, 2007, p. 13. using physical vapor deposition,” in Symp. VLSI Technol., 2013, p.
[39] G. W. Burr et al., “Observation and modeling of polycrystalline grain T9.2.
formation in ,” J. Appl. Phys., vol. 111, no. 10, p. 104308, [65] M. Boniardi et al., “Optimization metrics for phase change memory
2012. (PCM) cell architectures,” in IEDM Tech. Dig., 2014, p. 29.1.
[40] C. Y. Ahn et al., “Crystallization properties and their drift dependence [66] J. Liang, R. G. D. Jeyasingh, H.-Y. Chen, and H. S. P. Wong, “A 1.4
in phase–change memory studied with a micro–thermal stage,” J. Appl. reset current phase change memory cell with integrated carbon nan-
Phys., vol. 110, no. 11, p. 114520, 2011. otube electrodes for cross–point memory application,” in Symp. VLSI
[41] M. Salinga et al., “Measurement of crystal growth velocity in a Technol., 2011, p. T5B–4.
melt–quenched phase–change material,” Nature Commun., vol. 4, p. [67] F. Xiong, A. D. Liao, D. Estrada, and E. Pop, “Low–power switching
2371, 2013. of phase–change materials with carbon nanotube electrodes,” Science,
[42] A. Sebastian, M. Le Gallo, and D. Krebs, “Crystal growth within a vol. 332, pp. 568–570, 2011.
phase change memory cell,” Nature Commun., vol. 5, p. 4314, 2014. [68] C. Ahn et al., “1D selection device using carbon nanotube FETs for
[43] I. Friedrich, V. Weidenhof, W. Njoroge, P. Franz, and M. Wuttig, high–density cross–point memory arrays,” IEEE Trans. Electron De-
“Structural transformations of films studied by elec- vices, vol. 62, no. 7, pp. 2197–2204, Jul. 2015.
trical resistance measurements,” J. Appl. Phys., vol. 87, no. 9, pp. [69] C. Ahn et al., “Energy-efficient phase-change memory with
4130–4134, 2000. graphene as a thermal barrier,” Nano Lett., vol. 15, no. 10,
[44] Y. N. Hwang, “Writing current reduction for high–density pp. 6809–6814, 2015.
phase–change RAM,” in IEDM Tech. Dig., 2003, pp. 37.1.1–37.1.4. [70] M. Wuttig and N. Yamada, “Phase–change materials for rewrite-
[45] N. Matsuzaki et al., “Oxygen–doped GeSbTe phase–change memory able data storage,” Nature Mater., vol. 6, no. 11, pp. 824–832,
cells featuring 1.5–V/100– standard 0.13– CMOS operations,” 2007.
in IEDM Tech. Dig., 2005, pp. 738–741. [71] B. J. Choi et al., “Combined atomic layer and chemical vapor depo-
[46] L. van Pieterson, M. H. R. Lankhorst, M. van Schijndel, A. E. T. sition, and selective growth of films on TiN/W contact
Kuiper, and J. H. J. Roosen, “Phase–change recording materials with a plug,” Chem. Mater., vol. 19, no. 18, pp. 4387–4389, 2007.
growth–dominated crystallization mechanism: A materials overview,” [72] S. Kim et al., “A phase change memory cell with metallic surfactant
J. Appl. Phys., vol. 97, no. 08, p. 083520, 2005. layer as a resistance drift stabilizer,” in IEDM Tech. Dig., 2013, p. 30.7.
[47] H. Y. Cheng, S. Raoux, M. Wuttig, B. Munoz, and J. L. Jordan-Sweet, [73] S. Zastrow et al., “Thermoelectric transport and hall measurements of
“The crystallization behavior of phase–change mate- low defect thin films grown by atomic layer deposition,” Semi.
rials,” in MRS Spring Meet., 2010, p. H6.5. Sci. Tech., vol. 28, no. 3, p. 035010, 2013.
[48] H. Y. Cheng et al., “A high performance phase change memory with [74] A. Velea, C. N. Borca, and G. Socol, “In–situ crystallization of GeTe/
fast switching speed and high temperature retention by engineering the GaSb phase change memory stacked films,” J. Appl. Phys., vol. 116,
phase change material,” in IEDM Tech. Dig., 2011, p. 3.4. no. 23, p. 234306, 2014.
[49] H. Cheng et al., “A thermally robust phase change memory by engi- [75] J. H. Jeong, S. B. An, and D. J. Choi, “Screened remote plasma–en-
neering the Ge/N concentration in phase change ma- hanced atomic vapor deposition of Sb–Te thin film for the improve-
terial,” in IEDM Tech. Dig., 2012, p. 31.1. ment of trench–covering ability,” J. Mater. Sci., vol. 49, no. 14, pp.
[50] G. Navarro et al., “Trade–off between set and data retention perfor- 4765–4772, 2014.
mance thanks to innovative materials for phase–change memory,” in [76] E. Thelander, J. W. Gerlach, U. Ross, F. Frost, and B. Rauschenbach,
IEDM Tech. Dig., 2013, p. 21.5. “Epitaxial growth of Ge–Sb–Te films on KCl by high deposition rate
[51] P. Zuliani et al., “Overcoming temperature limitations in phase change pulsed laser deposition,” J. Appl. Phys., vol. 115, no. 21, p. 213504,
memories with optimized ,” IEEE Trans. Electron De- 2014.
vices, vol. 60, no. 12, pp. 4020–4026, Dec. 2013. [77] J. H. Jeong and D. J. Choi, “New screened plasma–enhanced atomic
[52] T. Morikawa et al., “A low power phase change memory using low vapor deposition to improve trench covering ability of SbTe films,” in
thermal conductive doped– with nano–crystalline struc- Proc. Non–Volatile Memory Technol. Symp., 2014.
ture,” in IEDM Tech. Dig., 2012, p. 31.4. [78] W. C. Ren et al., “Nanoscale gap filling for phase change material
[53] A. Fantini et al., “N–doped GeTe as performance booster for embedded by pulsed deposition and inductively coupled plasma etching,” Appl.
phase–change memories,” in IEDM Tech. Dig., 2010, p. 29.1. Phys. A, Mater. Sci. Process., vol. 112, no. 4, pp. 999–1002, 2013.
[54] L. Perniola et al., “Ti impact in C–doped phase–change memories com- [79] X. H. Liang, N. Jayaraju, C. Thambidurai, Q. H. Zhang, and J. L.
pliant to Pb–free soldering reflow,” in IEDM Tech. Dig., 2012, p. 18.7. Stickney, “Controlled electrochemical formation of
[55] N. Ciocchini et al., “Unified reliability modeling of Ge–rich phase using atomic layer deposition (ALD),” Chem. Mater., vol. 23, no. 7,
change memory for embedded applications,” in IEDM Tech. Dig., pp. 1742–1752, 2011.
2013, p. 22.1. [80] M. Ritala et al., “Atomic layer deposition of thin films,”
[56] J.-Y. Wu et al., “A double–density dual–mode phase change memory Microelectron. Eng., vol. 86, no. 7–9, pp. 1946–1949, 2009.
using a novel background storage scheme,” in Symp. VLSI Technol., [81] H. K. Kim, J. H. Jung, and D. J. Choi, “Role of hydrogen in Sb film
2014, p. T11.1. deposition and characterization of Sb and films deposited
[57] R. Freitas and W. Wilcke, “Storage–class memory: The next storage by cyclic plasma enhanced chemical vapor deposition using metal–or-
system technology,” IBM J. Res. Develop., vol. 52, no. 4/5, pp. ganic precursors,” Thin Solid Films, vol. 520, no. 23, pp. 6947–6953,
439–448, 2008. 2012.

Authorized licensed use limited to: UNIVERSITE DE SOUSSE. Downloaded on April 15,2022 at 12:40:03 UTC from IEEE Xplore. Restrictions apply.
BURR et al.: RECENT PROGRESS IN PHASE-CHANGE MEMORY TECHNOLOGY 159

[82] S. Song et al., “Phase–change properties of GeSbTe thin films de- [106] W. Khwa et al., “A novel inspection and annealing procedure to reju-
posited by plasma–enchanced atomic layer deposition,” Nanoscale venate phase change memory from cycling–induced degradations for
Res. Lett., vol. 10, p. 89, 2015. storage class memory applications,” in IEDM Techn. Dig., 2014, p.
[83] R. E. Simpson et al., “Interfacial phase–change memory,” Nature Nan- 29.8.
otechnol., vol. 6, no. 8, pp. 501–505, 2011. [107] S. Lee et al., “Programming disturbance and cell scaling in phase
[84] T. C. Chong et al., “Phase change random access memory cell with su- change memory: For up to 16 nm based cell,” in Symp. VLSI
perlattice–like structure,” Appl. Phys. Lett., vol. 88, no. 12, p. 122114, Technol., 2010, p. T19.1.
2006. [108] H. Y. Cheng, S. Raoux, K. V. Nguyen, R. S. Shenoy, and M. BrightSky,
[85] J. Tominaga, R. Simpson, P. Fons, and A. Kolobov, “The first prin- “ material for fast switching and Pb–free soldering reflow
ciple computer simulation and real device characteristics of superlat- process complying phase–change memory,” ECS J. Solid State Sci.
tice phase–change memory,” in IEDM Tech. Dig., 2010, p. 22.3. Technol., vol. 3, no. 7, pp. 263–P267, 2014.
[86] T. Ohyanagi et al., “Charge–injection phase change memory with [109] M. Putero et al., “Unusual crystallization behavior in Ga–Sb phase
high–quality GeTe/ superlattice featuring 70 RESET, change alloys,” APL Mater., vol. 1, no. 6, p. 062101, 2013.
10–ns SET and 100 M endurance cycles operations,” in IEDM Tech. [110] M. K. Qureshi et al., “Enhancing lifetime and security of
Dig., 2013, p. 30.5. PCM–based main memory with start–gap wear leveling,” in
[87] N. Takaura et al., “55– / superlattice topolog- Proc. 42nd Annu. IEEE/ACM Int. Symp. Microarchitecture,
ical–switching random–access memory (TRAM) and study of atomic 2009, pp. 14–23.
arrangement in Ge–Te and Sb–Te structures,” in IEDM Tech. Dig., [111] G. W. Burr et al., “Access devices for 3D crosspoint memory,” J.
2014, p. 29.2. Vacuum Sci. Technol. B, vol. 32, no. 4, p. 040802, 2014.
[88] S. Soeya, T. Shintani, T. Odaka, R. Kondou, and J. Tominaga, [112] Y. Sasago et al., “Cross–point phase change memory with cell
“Ultra–low switching power, crystallographic analysis, and switching size driven by low–contact–resistivity poly–Si diode,” in Symp. VLSI
mechanism for / diluted superlattice system,” Technol., 2009, p. T2B–1.
Appl. Phys. Lett., vol. 103, no. 5, p. 053103, 2013. [113] S. Lee et al., “Highly productive PCRAM technology platform and full
[89] N. Takaura et al., “Charge injection super–lattice phase change chip operation: Based on (84 nm pitch) cell scheme for 1 GB and
memory for low power and high density storage device applications,” beyond,” in IEDM Tech. Dig., 2011, p. 3.3.
in Symp. VLSI Technol., 2013, p. T9.1. [114] C. Ahn et al., “A 1 TnR array architecture using a one–dimensional
[90] M. Tai et al., “1T–1R pillar–type topological–switching random ac- selection device,” in Symp. VLSI Technol., 2014, p. T15.4.
cess memory (TRAM) and data retention of GeTe/ super–lat- [115] D. C. Kau et al., “A stackable cross point phase change memory,” in
tice films,” in Symp. VLSI Technol., 2014, p. T22.4. IEDM Tech. Dig., 2009, p. 27.1.
[91] D. Bang et al., “Mirror–symmetric magneto–optical kerr rotation using [116] H. Yang et al., “Novel selector for high density non–volatile memory
visible light in topological superlattices,” with ultra–low holding voltage and 1e7 on/off ratio,” in Symp. VLSI
Sci. Rep., vol. 4, p. 5727, 2014. Technol., 2015, p. T9.2.
[92] J. Tominaga et al., “Giant multiferroic effects in topological [117] S. Jo, T. Kumar, S. Narayanan, W. D. Lu, and H. Nazarian, “3D–stack-
GeTe– superlattices,” Sci. Technol. Adv. Mater., vol. 16, no. able crossbar resistive memory based on field assisted superlinear
1, p. 014402, 2015. threshold (FAST) selector,” in IEDM Tech. Dig., 2014, p. 6.7.
[93] C. Jeong et al., “Switching current scaling and reliability evaluation in [118] S. H. Jo, T. Kumar, C. Zitlaw, and H. Nazarian, “Self–limited RRAM
PRAM,” IEEE NVSMW, pp. 28–29, 2004. with ON/OFF resistance ratio amplification,” in Symp. VLSI Technol.,
[94] B. Gleixner, “Phase change memory reliability,” in NVSMW 2007, 2015, p. T9.1.
2007. [119] R. S. Shenoy et al., “Endurance and scaling trends of novel access–de-
[95] J.-B. Park et al., “Phase–change behavior of stoichiometric vices for multi–layer crosspoint–memory based on Mixed Ionic Elec-
in phase–change random access memory,” J. Elec- tronic Conduction (MIEC) materials,” in Symp. VLSI Technol., 2011,
trochem. Soc., vol. 154, no. 3, pp. H139–H141, 2007. pp. T5B–1.
[96] A. Padilla et al., “Voltage polarity effects in –based phase [120] G. W. Burr et al., “Large–scale (512kbit) integration of multi-
change memory devices,” J. Appl. Phys., vol. 110, no. 5, p. 054501, layer–ready access–devices based on Mixed–Ionic–Electronic–Con-
2011. duction (MIEC) at 100% yield,” in Symp. VLSI Technol., 2012, p.
[97] B. Kim et al., “Current status and future prospect of phase change T5.4.
memory,” in ASICON, 2011, pp. 279–282. [121] K. Virwani et al., “Sub–30 nm scaling and high–speed operation of
[98] G. Novielli, A. Ghetti, E. Varesi, A. Mauri, and R. Sacco, “Atomic fully–confined access–devices for 3–D crosspoint memory based on
migration in phase change materials,” in IEDM Tech. Dig., 2013, p. Mixed–Ionic–Electronic–Conduction (MIEC) materials,” in IEDM
22.3. Tech. Dig., 2012, p. 2.7.
[99] J. Sarkar and B. Gleixner, “Evolution of phase change memory [122] G. W. Burr et al., “Recovery dynamics and fast (sub–50 ns) read
characteristics with operating cycles: Electrical characterization operation with access devices for 3D crosspoint memory based on
and physical modeling,” Appl. Phys. Lett., vol. 91, no. 23, p. mixed–ionic–electronic–conduction (MIEC),” in Symp. VLSI Technol.,
233506, 2007. 2013, p. T6.4.
[100] K. Do, D. Lee, D. H. Ko, H. Sohn, and M. H. Cho, “TEM study on [123] M. Kinoshita et al., “Scalable 3–D vertical chain–cell–type
volume changes and void formation in films, with re- phase–change memory with poly–Si diodes,” in Symp. VLSI
peated phase changes,” Electrochem. Solid State Lett., vol. 13, no. 8, Technol., 2012, p. T5.1.
pp. H284–H286, 2010. [124] W. Czubatyj and S. J. Hudgens, “Invited paper: Thin–film ovonic
[101] N. Nobukuni, M. Takashima, T. Ohno, and M. Horie, “Microstruc- threshold switch: Its operation and application in modern integrated
tural changes in GeSbTe film during repetitious overwriting in circuits,” Electron. Mater. Lett., vol. 8, no. 2, pp. 157–167, 2012.
phase–change optical recording,” J. Appl. Phys., vol. 78, no. 12, pp. [125] 3D XPoint, , 2015 [Online]. Available: en.wikipedia.org/wiki/
6980–6988, 1995. 3D_XPoint
[102] A. Debunne et al., “Evidence of crystallization–induced segregation [126] P. Clarke, Patent search supports view 3D XPoint based on phase-
in the phase change material Te–rich GST,” J. Electrochem. Soc., vol. change 2015 [Online]. Available: www.eetimes.com/author.asp?sec-
158, no. 10, pp. H965–H972, 2011. tion_id=36&doc_id=1327313
[103] D. Kang et al., “Considerations on highly scalable and [127] T. Nirschl et al., “Write strategies for 2 and 4–bit multi–level
easily stackable phase change memory cell array for low–cost phase–change memory,” in IEDM Tech. Dig., 2007, p. 17.5.
and high–performance applications,” in Non–Volatile Memory [128] D.-H. Kang et al., “Two–bit cell operation in diode–switch phase
Technol. Symp., 2014, pp. 1–5. change memory cells with 90 nm technology,” in Symp. VLSI Technol.,
[104] S. Kim et al., “Optimization of programming current on endurance of 2008, pp. 10–2.
phase change memory,” in VLSI–TSA, 2012, p. T9–1. [129] F. Bedeschi et al., “A bipolar–selected phase change memory featuring
[105] P. Y. Du et al., “The impact of melting during reset operation on the multi–level cell storage,” IEEE J. Solid State Circ., vol. 44, no. 1, pp.
reliability of phase change memory,” in IRPS, 2012, p. 6C.2. 217–227, Jan. 2009.

Authorized licensed use limited to: UNIVERSITE DE SOUSSE. Downloaded on April 15,2022 at 12:40:03 UTC from IEEE Xplore. Restrictions apply.
160 IEEE JOURNAL ON EMERGING AND SELECTED TOPICS IN CIRCUITS AND SYSTEMS, VOL. 6, NO. 2, JUNE 2016

[130] B. S. Lee et al., “Distribution of nanoscale nuclei in the amorphous [154] B. L. Jackson et al., “Nanoscale electronic synapses using phase change
dome of a phase change random access memory,” Appl. Phys. Lett., devices,” ACM J. Emerg. Technol. Comput. Syst., vol. 9, no. 2, p. 12,
vol. 104, no. 7, p. 071907, 2014. 2013.
[131] N. Papandreou et al., “Programming algorithms for multilevel [155] B. Rajendran et al., “Specifications of nanoscale devices and circuits
phase–change memory,” in Int. Symp. Circuits Syst., 2011, pp. for neuromorphic computational systems,” IEEE Trans. Electron De-
329–332. vices, vol. 60, no. 1, pp. 246–253, Jan. 2013.
[132] G. F. Close et al., “A 256–Mcell phase–change memory chip operating [156] S. Eryilmaz et al., “Experimental demonstration of array–level learning
at 2 bit/cell,” IEEE Trans. Circuits Syst., vol. 60, no. 6, pp. 1521–1533, with phase change synaptic devices,” in IEDM Tech. Dig., 2013, p.
Jun. 2013. 25.5.
[133] D. Ielmini, S. Lavizzari, D. Sharma, and A. L. Lacaita, “Physical inter- [157] S. Kim et al., “NVM neuromorphic core with 64 k–cell (256–by–256)
pretation, modeling and impact on phase change memory (PCM) reli- phase change memory synaptic array with on–chip neuron circuits for
ability of resistance drift due to chalcogenide structural relaxation,” in continuous in–situ learning,” in IEDM, 2015.
IEDM Tech. Dig., 2007, p. 36.1. [158] D. Querlioz et al., “Bioinspired networks with nanoscale memristive
[134] M. Boniardi and D. Ielmini, “Physical origin of the resistance drift ex- devices that combine the unsupervised and supervised learning ap-
ponent in amorphous phase change materials,” Appl. Phys. Lett., vol. proaches,” in Proc. IEEE/ACM Int. Symp. Nanoscale Architect., 2011,
98, no. 24, p. 243506, 2011. pp. 203–210.
[135] A. Sebastian, D. Krebs, M. LeGallo, H. Pozidis, and E. Eleftheriou, “A [159] G. Q. Bi and M. M. Poo, “Synaptic modifications in cultured hip-
collective relaxation model for resistance drift in phase change memory pocampal neurons: Dependence on spike timing, synaptic strength, and
cells,” in Proc. IEEE Int. Reliabil. Phys. Symp., 2015. postsynaptic cell type,” J. Neurosci., vol. 18, no. 24, pp. 10 464–10 472,
[136] N. Papandreou et al., “Drift–tolerant multilevel phase–change 1998.
memory,” in Proc. IEEE Int. Memory Workshop, May 2011, pp. [160] G. W. Burr et al., “Experimental demonstration and tolerancing of a
147–150. large–scale neural network (165,000 synapses), using phase–change
[137] J. Li, B. Luan, and C. Lam, “Resistance drift in phase change memory,” memory as the synaptic weight element,” in IEDM Tech. Dig., 2014,
in Proc. Int. Reliabil. Phys. Symp., 2012, p. 6C.1. p. 29.5.
[138] H. Pozidis et al., “A framework for reliability assessment in multilevel [161] G. W. Burr et al., “Experimental demonstration and tolerancing of a
phase–change memory,” in IMW 2012, 2012, pp. 143–146. large–scale neural network (165,000 synapses), using phase–change
[139] W. Xu and T. Zhang, “A time–aware fault tolerance scheme to improve memory as the synaptic weight element,” IEEE Trans. Electron De-
reliability of multilevel phase–change memory in the presence of sig- vices, vol. 62, no. 11, pp. 3498–3507, Nov. 2015.
nificant resistance drift,” IEEE Trans. Very Large Scale (VLSI) Syst., [162] G. W. Burr et al., “Large–scale neural networks implemented with non-
vol. 19, no. 8, pp. 1357–1367, Aug. 2011. volatile memory as the synaptic weight element: Comparative perfor-
[140] M. Awasthi et al., “Handling PCM resistance drift with device, circuit, mance analysis (accuracy, speed, and power),” in IEDM Tech. Dig.,
architecture, and system solutions,” in Non–Volatile Memories Work- 2015, p. 4.4.
shop, 2011. [163] C.-Y. Wen et al., “Post–silicon calibration of analog CMOS using
[141] P. Fantini, A. Pirovano, D. Ventrice, and A. Redaelli, “Experimental phase–change memory cells,” in Proc. 41st Eur. Solid–State Circuits
investigation of transport properties in chalcogenide materials through Conf. , 2011, pp. 423–426.
noise measurements,” Appl. Phys. Lett., vol. 88, no. 26, p. 263506, [164] C.-Y. Wen et al., “A non–volatile look–up table design using pcm
2006. (phase–change memory) cells,” in Symp. VLSI Circuits, 2011, p.
[142] G. F. Close et al., “Device, circuit and system–level analysis of noise in C28–4.
multi–bit phase–change memory,” in IEDM Tech. Dig., 2010, p. 29.5. [165] B. Rajendran et al., “Demonstration of CAM and TCAM using phase
[143] C. Longeaud et al., “On the density of states of germanium telluride,” change devices,” in Proc. EEE Int. Memory Workshop, May 2011, pp.
J. Appl. Phys., vol. 112, no. 11, p. 113714, 2012. 139–142.
[144] S. Lavizzari, D. Ielmini, D. Sharma, and A. L. Lacaita, “Reliability [166] H. Wu, F. Lombardi, and J. Han, “A PCM–based TCAM cell using
impact of chalcogenide–structure relaxation in phase–change memory NDR,” in Proc. IEEE/ACM Int. Symp. Nanoscale Architect., 2013, pp.
(PCM) cells–Part II: Physics–based modeling,” IEEE Trans. Electron 89–94.
Devices, vol. 56, no. 5, pp. 1078–1085, May 2009. [167] J. Li, R. K. Montoye, M. Ishii, and L. Chang, “1 Mb 0.41 ,” IEEE
[145] M. Gibbs, J. Evetts, and J. Leake, “Activation energy spectra and re- J. Solid State Circ., vol. 49, no. 4, pp. 896–907, 2014.
laxation in amorphous materials,” J. Mater. Sci., vol. 18, pp. 278–288, [168] P. Hosseini, A. Sebastian, N. Papandreou, C. D. Wright, and H.
1983. Bhaskaran, “Accumulation-based computing using phase-change
[146] W. Chien et al., “Novel self–converging write scheme for 2–bits/cell memories with FET access devices,” IEEE Electron Device Lett., vol.
phase change memory for storage class memory (SCM) application,” 36, no. 9, pp. 975–977, Nov. 2015.
in Symp. VLSI Technol., 2015, p. T7.5.
[147] A. Sebastian, N. Papandreou, A. Pantazi, H. Pozidis, and E. Eleft-
heriou, “Non–resistance–based cell–state metric for phase–change
memory,” J. Appl. Phys., vol. 110, no. 08, p. 084505, 2011.
[148] N. Papandreou et al., “Drift–resilient cell–state metric for multilevel
phase–change memory,” in IEDM Tech. Dig., 2011, p. 3.5.
[149] M. Stanisavljevic, A. Athmanathan, N. Papandreou, H. Pozidis, and E.
Evangelos, “Phase change memory: Feasibility of reliable multi–level
Geoffrey W. Burr (S'87–M'96–SM'13) received
cell storage and retention at elevated temperatures,” in Proc. IEEE Int.
the Ph.D. degree in electrical engineering from
Reliabil. Phys. Symp., 2015.
the California Institute of Technology, Pasadena,
[150] H. Pozidis et al., “Reliable MLC data storage and retention in CA, USA, in 1996, under the supervision of Prof.
phase–change memory after endurance cycling,” in IMW 2013, 2013, Demetri Psaltis.
pp. 100–103. Since that time, he has worked at IBM Re-
[151] H. Pozidis, T. Mittelholzer, N. Papandreou, T. Parnell, and M. search-Almaden, San Jose, CA, USA, where he
Stanisavljevic, “Phase change memory reliability: A signal processing is currently a Principal Research Staff Member.
and coding perspective,” IEEE Trans. Magn., vol. 51, no. 4, p. He has worked in a number of diverse areas, in-
3500107, Apr. 2015. cluding holographic data storage, photon echoes,
[152] D. Kuzum, R. D. Jeyasingh, and H.-S. Wong, “Energy efficient pro- computational electromagnetics, nanophotonics,
gramming of nanoelectronic synaptic devices for large–scale imple- computational lithography, phase-change memory, storage class memory, and
mentation of associative and temporal sequence learning,” in IEDM novel access devices based on mixed-ionic-electronic-conduction (MIEC)
Tech. Dig., 2011, p. 30.3. materials. His current research interests include non-volatile memory and
[153] M. Suri et al., “Phase change memory as synapse for ultra–dense neu- cognitive computing.
romorphic systems: Application to complex visual pattern extraction,” Dr. Burr is a member of MRS, SPIE, OSA, Tau Beta Pi, Eta Kappa Nu, and
in IEDM Tech. Dig., 2011, p. 4.4. the Institute of Physics (IOP).

Authorized licensed use limited to: UNIVERSITE DE SOUSSE. Downloaded on April 15,2022 at 12:40:03 UTC from IEEE Xplore. Restrictions apply.
BURR et al.: RECENT PROGRESS IN PHASE-CHANGE MEMORY TECHNOLOGY 161

Matthew J. Brightsky received the B.S. degree in He is currently a Research Staff Member with the IBM T. J. Watson Research
physics, mathematics, and astrophysics from the Uni- Center. His current research interests are characterization and modeling of phase
versity of Wisconsin at Madison, Madison, WI, USA, change memory devices for various memory applications such as storage-class
in 1994, and the Ph.D. degree in physics from Iowa memory, embedded memory, and brain-inspired neuromorphic computing.
State University, Ames, IA, USA, in 1999.
He is a Research Staff Member at the IBM T. J.
Watson Research Center, Yorktown Heights, NY,
USA. He was with IBM at the IBM Microelectronics Norma Sosa received the B.S. degree in chemistry/
Center, Essex Junction, VT, USA, where he worked materials science and the M.S. degree in materials
on developing low-standby-power SRAM, and on science and engineering from the University of Cal-
dc and RF compact models for CMOSFETs and ifornia, Los Angeles, CA, USA, in 2002 and 2004,
passive devices. In 2005, he joined the exploratory memory group at the T. respectively, and the Ph.D. degree in materials sci-
J. Watson Research Center and has since worked on integration schemes for ence and engineering from Northwestern University,
phase change memory devices. He is an author or coauthor of 14 patents, 31 Chicago, IL, USA, in 2009.
technical papers, and a book chapter. She has been a Research Staff Member with the
IBM Thomas J. Watson Research Center, Yorktown
Heights, NY, USA, since 2009, where she has worked
on layer transfer techniques of III-V and other semi-
Abu Sebastian (M'03–SM'11) received the B. E. conductors for photovoltaic device applications. Her research interests also in-
(Hons.) degree in electrical and electronics engi- clude phase change memory materials and integration.
neering from Birla Institute of Technology and
Science, Pilani, India, in 1998, and the M. S. and
Ph.D. degrees in electrical engineering from Iowa
State University, Ames, IA, USA, in 1999 and 2004, Nikolaos Papandreou (M'03) received the Diploma
respectively. and Ph.D. degree, both in electrical and computer
He is currently a Research Staff Member at IBM engineering, from the University of Patras, Patras,
Research–Zurich, Switzerland. His research has Greece, in 1998 and 2004, respectively.
spanned several topics broadly related to dynamics From 2005 to 2008 he was Research Associate
and control at the nanometer scale. His research at the Electrical and Computer Engineering Depart-
interests include memory and cognitive technologies and enabling tools ment, University of Patras, Greece, where he worked
for nanotechnology such as nanoscale sensing and nanopositioning. He has in various R&D projects in the areas of digital com-
published over 100 articles on these topics. munications. Between 2006 and 2008, he has also
served as Adjunct Faculty Member at the Computer
Engineering and Informatics Department, University
of Patras, Greece. In 2008, he joined IBM Research–Zurich, Switzerland,
where he is working on non-volatile memory technologies with emphasis
Huai-Yu Cheng received the B.S., M.S. and Ph.D.
on phase-change memory and flash. His research interests include device
degrees in materials science and engineering from
characterization and reliability, signal processing and coding for memory
National Tsing Hua University, Taiwan, in 2001,
channels, next generation storage systems and architectures.
2003, and 2007, respectively.
Dr. Papandreou is a member of the Technical Chamber of Greece.
She joined Macronix International Co., in 2007
and is currently a Senior Researcher based in York-
town Heights, NY, USA.

Hsiang-Lan Lung (S'02–M'03) received the B.S.

degree from Feng Chia University, Taichung,
Taiwan, the M.S. degree from National Cheng Kung
University, Tainan, Taiwan, and the Ph.D. degree
from National Tsing Hua University, Hsinchu,
Taiwan, in 1992, 1996, and 2003, respectively, all in
Jau-Yi Wu received the B. S. degree from the materials science and engineering.
Department of Electrical Engineering, Feng Chia He joined Macronix International, Hsinchu,
University, Taichung Taiwan, in 1995, and the M.S. Taiwan, in 1996. Since then, he has engaged in
and Ph.D. degrees from the Department of Electrical research and advanced technology development of
Engineering and Institute of Microelectronic Engi- CMOS logic, embedded SRAM, embedded MROM,
neering, National Cheng Kung University, Tainan, embedded Flash, NROM, FeRAM, and phase-change memory. He is currently
Taiwan, in 1998 and 2002, respectively. the Chief for the Nano-Device R&D department and in charge of the R&D
He joined the Nano-Device R&D Department, work for advanced nonvolatile memory technology. He has published 14
Macronix International, Hsinchu, Taiwan, in 2002. technical papers and has been granted 26 international patents
His current research areas include high-density
memory development, nitride-trapping memory
devices, and advanced nonvolatile memory technologies.
Haralampos Pozidis (SM’10) received the Ph.D. de-
gree in electrical engineering from Drexel University,
Philadelphia, PA, USA, in 1998.
SangBum Kim (S'05–M'11) received the B.S. He is managing the Non-volatile Memory Sys-
degree from Seoul National University, Seoul, South tems group at IBM Research, Zurich, Switzerland.
Korea, in 2001, and the M.S. and Ph.D. degrees from He was with Philips Research, Eindhoven, The
Stanford University, Stanford, CA, USA, in 2005 Netherlands, before joining IBM. He has worked
and 2010, respectively, all in electrical engineering. on read channel design for DVD and Blu-ray Disc
His Ph.D. dissertation focused on the scalability and optical recording formats with technology transfers
reliability of phase change memory (PCM) including to optical drive products in Philips. He has played
scaling rule analysis, germanium nanowire diode a key role in developing the world's first scanning
as a scalable selection device, study of thermal probe-based data storage system, the “Millipede”. His current focus is on
disturbance, drift, and threshold switching using developing Flash memory controllers for all-flash arrays as well as phase
micro thermal stage. change memory technology and system solutions. He holds over 55 U.S. and

Authorized licensed use limited to: UNIVERSITE DE SOUSSE. Downloaded on April 15,2022 at 12:40:03 UTC from IEEE Xplore. Restrictions apply.
162 IEEE JOURNAL ON EMERGING AND SELECTED TOPICS IN CIRCUITS AND SYSTEMS, VOL. 6, NO. 2, JUNE 2016

European patents in the areas of solid-state memory technology, probe-based tions Society Leonard G. Abraham Prize Paper Award. He was also co-recip-
data storage, control systems technology and optical data storage. He is a ient of the 2005 Technology Award of the Eduard Rhein Foundation. In 2005,
Principal Research Scientist, and an IBM Master Inventor. he was appointed an IBM Fellow and inducted into the IBM Academy of Tech-
Dr. Pozidis received the 2009 Control Systems Technology Society Award nology. In 2009, he was co-recipient of the IEEE CSS Control Systems Tech-
and the 2009 IEEE Transactions on Control Systems Technology Best Paper nology Award and of the IEEE Transactions on Control Systems Technology
Award. Outstanding Paper Award.

Evangelos Eleftheriou (S'81–M'86–SM'00–F'02) Chung H. Lam received the B.Sc. degree in elec-
received the B.S. degree in electrical engineering trical engineering at Polytechnic University of New
from the University of Patras, Patras, Greece, in York, in 1978, the M.Sc. and Ph.D. degrees, both in
1979, and the M.Eng. and Ph.D. degrees in electrical electrical engineering, at Rensselaer Polytechnic In-
engineering from Carleton University, Ottawa, stitute, Troy, NY, USA, in 1987 and 1988, respec-
Canada, in 1981 and 1985, respectively. tively.
He joined the IBM Research–Zurich labora-
tory, Rüschlikon, Switzerland, as a Research Staff
Member in 1986. Since 1998, he has held various
management positions and currently heads the Cloud
and Computing Infrastructure department of IBM
Research–Zurich, which focuses on enterprise solid-state storage, storage for
big data, microserver/cloud server and accelerator technologies, high-speed
I/O links, storage security, and memory and cognitive technologies. He holds Since joining IBM, Yorktown Heights, NY, USA, in 1978, he has taken respon-
over 100 patents (granted and pending applications). sibilities in various disciplines of semiconductor research, development, and
Dr. Eleftheriou was Editor of the IEEE Transactions on Communications manufacturing including circuit and device designs as well as process integra-
from 1994 to 1999 in the area of Equalization and Coding. He was Guest Ed- tions for memory and logic applications in IBM's Microelectronic Division. In
itor of the IEEE Journal on Selected Areas in Communications special issues 2003, he transferred to the IBM Research Division at the T. J. Watson Research
“The Turbo Principle: From Theory to Practice” as well as of the IEEE Trans- Center. In 2007, he was named an IBM Distinguished Engineer. Currently, he
actions on Control Systems special issue on “Dynamics and Control of Micro- manages Phase Change Memory Research Joint Projects. He has more than 100
and Nano-scale Systems”. He was co-recipient of the 2003 IEEE Communica- granted U.S. patents and published more than 60 technical papers.

Authorized licensed use limited to: UNIVERSITE DE SOUSSE. Downloaded on April 15,2022 at 12:40:03 UTC from IEEE Xplore. Restrictions apply.