Digital Design:-
● Conversion of one number system into another.
● Question on one's and 2’s complement and XS-3 code,Binary to Gray
converter and vice versa.
● Why NAND and NOR are called as universal gates and implement each one
of them
● A function is given in either pos or sop and you can be asked to impllement
in either NAND or NOR.
● Questions on Full adder and full subtractor and Look ahead carry
adder(Many questions could be asked so it's better to understood the
concepts)
● A Boolean function is given and you could be asked to minimize it using
either K-map or Tabulation method.
● Conceptually understood all the laws and Theorems related to Digital logic
● Implement all the basic gates using 2:1 Mux
● A function in the form like f(a,b,c) = sum(1,3,4,6) is given and can ask you to
implement using 8:1 Mux and 4:1 Mux.(You need to muster the concept of
Mux tree very well as many twisted question can be asked)
● Implement 4:1Mux using 2:1 Mux without using any additional gates.
● Implement a full adder using two 4:1 Mux
● Design a 16:1 Mux using 2:1 Mux
● Implement a 2:1 Mux using Tristate buffers
● Implement the following function using 2:1 Mux
● Design a full adder using 3:8 Decoder(Both active high and low)
● Questions on priority encoder and it's implementation.
● Difference between latch and flip flop
● Conversion of one flip to another like JK to SR,T to D etc
● SISO and PIPO implementation
● Different number of cycles required to implement Johnson Counter,Ring
Counter,Ripple counter.
● Decade counter and up/down counter implementation
● Mod counter with specified duty cycle implementation.
● Sequence Detector like 10101 is given and you are asked to implement this
FSM depending on overlapping and non overlapping method(High Priority)
● Difference between Mealy and Moore.
● Different types of Hazards and their usage.
● Difference between Setup time and Hold time and explain with waveform.
● Propagation delay and contamination delay.
● Questions on Clock skew,Slack and Slew.
● Hold slack calculation
● A given circuit is given and you could be asked to find the frequency of that.
● Divide by 2 counter implementation
● Complete understanding of the ASIC and the FPGA flow.
● What are CLB,IOB and LUT,s in FPGA
● Asynchronous and Synchronous FIFO with special focus on FIFO depth
calculation
● Reset strategies and Reset Recovery time.
● Memory Controller and it's implementation in Verilog.
● Different gates using Mux
● gray code application
● Tri-state buffer
● depth of fifo
● fan-in vs fan-out
● Clock-gating
● What are the different types of skews used in VLSI
● Explain what is Slack?
● Design a clock divider circuit which divides the clock by an odd
number and has 50% duty cycle. (o/p clk = i/p clk/N, where N is
an odd number).
● What is meant by race condition
● What is one hot encoding
● Explain the difference between binary and gray encoding and the benefits
of each?
● universal gates
● Implement 2:1 Mux using Tristate buffers.
● Design 4:16 Decoder using 3:8 Decoder.
● Design Full adder using 3:8 Decoder.
● Implement a counter with Mux
● Design a MOD 10 counter with 50%/33% duty cycle.
● What are synchonisers and when to use them
● Between Binary and G ray C
ounter,which one to use and why?
● For an input clk of f frequency generate an output of 2*f frequency
● Output should be high for only odd +ve edge transition
● No. of 2*4 decoders needed to implement 4*16 Decoder
● what is synchronous and asynchronous counter?
● XOR vs XNOR –special characteristics.
● Edge detection circuitry.
● Noise In digital Cirguits.
● Noise Margin.
Verilog/VHDL:-
● Difference between Blocking and Nonblocking statements.
● Difference between Intra and Inter assignment delay
● Difference between Task and Function.
● Difference between reg and wire
● A code could be given on blocking and Nonblocking and you might be
asked to provide the output.
● Difference between Transport and Inertial delay.
● Different types of wait statements in VHDL and explain each of them.
● Write a verilog code for asynchronous and Synchronous D flip flop
● Why latches are not inferred in RTL Design
● Different Coding guidelines for RTL Design(Refer Sunburst Design Papers)
● Difference between Verilog Full case and Parallel case
● Can a task called a function?If so then how it is possible.
● Verilog code to swap the content of register,with and without using a
temporary variable.
● Difference between $monitor and $strobe.
● Difference between Verilog and VHDL.
● What does if else statements synthesized to and what does c ase
statements synthesized into?
● Difference between Case equality and case inequality.
● Explain the stratified Event Queue in Verilog.
● Difference between signal and variable in VHDL.
● What is Delta Delay in VHDL?
● Different kinds of modelling technique in VHDL and explain each one of
them
● In Verilog code what does “timescale 1 ns/ 1 ps” signifies?
● Explain what is the use of defpararm?
● How Verilog is different to normal programming language?
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