All Optical Design of Hybrid Adder Circuit Using

Terahertz Optical Asymmetric Demultiplexer

Subham Saha*, Arpan Manna†, Chandan Bandyopadhyay*, Hafizur Rahaman*
*Indian Institute of Engineering Science and Technology, Shibpur, Howrah-711103
†
Kalyani Government Engineering College, Kalyani, Nadia-741235
{subhams087, arpan.manna113, chandanb.iiest, rahaman.h}@gmail.com

Abstract - In this work we present the optical domain adder[6,10], BCD adder[9], carry look ahead adder[7], binary
implementation of an n- bit hybrid adder circuit using terahertz sequence generator[8], multiplier were developed using TOAD
optical asymmetric demultiplexer (TOAD). The work is switches. Besides logic functions, reversible circuit [11] were
completed in two phases. In initial phase, we show the naïve also constructed using TOAD as basic building block, for
design of TOAD based circuit for ripple carry and carry look
example Fredkin gate, Toffoli gate, Perez gate.
ahead adder and then in the final phase the design has been
improved by taking optical cost and delay into account. The Our work proposes an efficient implementation of n-bit
presented theoretical model promises both higher processing adder using optical technology. The proposed design
speed and accuracy. From the experimental verification we have drastically reduces the optical cost, if compared with the
seen that the proposed model not only has enhanced the cost of previous designs, as its merit.
the design but also has reduced overall delay of the design. For Rest of the paper is arranged as follows. Section II briefly
fair analysis, we have compared the incurred design cost metrics depicts the working principle and operation of TOAD switch.
with related work results, where a considerable improvement in Proposed technique and optical cost analysis are discussed in
our proposed design model is registered. Section III. At the end Section IV provides conclusion of the
Keywords — TOAD, ripple carry adder, carry lookahead adder,
proposed work.
hybrid adder, full adder II. BACKGROUND
I. INTRODUCTION
A. TOAD Architechture
The recent advancement of optical computing over last few
From Sokoloff et al[1,2] it is evident that TOAD is capable
decades to increase the computational speed, overcome the
of demultiplexing data at a high speed of 50 GBps using
electronic bottleneck and loss of energy of about 30% for
600fJ control pulses and moreover this speed can be further
optoelectronic devices has led to all optical computers and has
accelerated considering two factors- reduction of length of
eliminated the requirement of optical-electrical-optical(OEO)
SOA below 100 µm and incremented in DC bias current. They
inter-conversions providing a greater extent in the field of
combinedly reduce the propagation delay incrementing the
signal transmission and logic computations. In optical
demultiplexing speed to 1Tbps.
multiplexing, Optical Time Division Multiplexing (OTDM)
technology can be exploited, to switching at 100 GB/s.
Basically, optical switches are governed by nonlinear effects Δx
SOA (NLE)
and optical interferometers. Many type of all optical switches
are there- Nonlinear Optical Loop Mirror (NOLM), Terahertz
Optical Asymmetric Demultiplexer (TOAD), Nonlinear
Amplifying Loop Mirror (NALM) are LOOP type optical td
switches. Others are Soliation trap AND Gate, Symmetric
Mach-Zehnder (SMZ)[3] and Ultrafast Nonlinear CP Eccw
Interferometer (UNI). Among the proposed switches, TOAD Ecw
Transmitted
offers significant advantages like high speed data rate, low Ein(t)
Input Port
Output Port 1
power consumption, reduced noise parameter and feasibility in Filter Eout,1
fabrication. Incoming Pulse Optical Circulator
For exploiting faster switching and demultiplexing data at Reflected Filter Eout,2
high rate J.P. Sokoloff proposed Terahertz Optical Output Port 2
Asymmetric Demultiplexer [1] in 1993 followed by subsequent
developments in recent years using TOAD as an all optical Fig. 1(a): Representation of optical switch using
switch. Reconfigurable logic operations like NOT, NOR, X- TOAD
OR[5], logic modules like 4x1multiplexer[5], half adder, full
Not only in data multiplexing, it plays a vital role to exploit Pout ,2 ( t ) = Pin ( t ) ⋅ G ss . When the control signal is injected
strong and slow optical nonlinearities present in into the loop, it changes the index of refraction after it has
semiconductors. It can also distinguish between control and saturated the SOA. As the consequence of this, the counter-
signal pulses with the help of polarizations or by using
propagated data signals face a differential gain saturation
wavelengths.
profiles i.e. G ccw ≠ G cw . So, after the signals recombining at
TOAD-based optical switches consist a loop mirror along
with a 2×2 intraloop coupler. From Fig. 1(a) it is clear that a the input coupler, the data will emit from the output port-1. In
nonlinear element (NLE) and a control pulse (CP) are also this case, the output powers can be expressed as
P ( t − td )
contained in the loop and the NLE is offset by a distance ∆x P = in
out , 1 ⋅ SW ( t ) and Pout , 2 ≈ 0 .
from the midpoint of the loop. 4
The block diagram of TOAD [15] is depicted in Fig. 1(b).
A signal with a field Ein (t ) is splitted in coupler at an
angular frequency w. It traverses in clockwise (cw) and Incoming Signal
T Output Port 1
counter clockwise (ccw) direction throughout the loop. The O (Upper channel)
electrical field at both ports can be expressed as, Control Signal A
[
E out ,1 (t ) = E in (t − t d ) ⋅ e − jwtd ⋅ d 2 ⋅ g cw (t − t d ) − k 2 ⋅ g ccw (t − t d ) ] D Output Port 2
(Lower channel)
[
E out , 2 (t ) = jdk E in (t − t d ) ⋅ e − jwt d ⋅ g cw (t − t d ) + g ccw (t − t d ) ] Fig. 1(b): Block diagram of all optical TOAD switch

td is the pulse round trip time within the loop. The Coupling Case 1: Control pulse is absent and incoming pulse is present
ratios d and k respectively indicate the through and cross  light is observed in output pot-2 but not in output por-1.
coupling. The clockwise signal is amplified by the complex Case 2: Control pulse and incoming pulse both is present
field gain g (t ) and ccw by g (t ) . At port-1 output light is observed in output port-1 but not in output port-2.
cw ccw
Case 3: Incoming pulse is absent light is not observed
power is expressed as, neither at port-1 nor at port-2.
P (t − t d )
Pout ,1 (t ) = in
4
{
Gcw (t ) + Gccw (t ) − 2 Gcw (t ) ⋅ Gccw (t ) ⋅ cos(Δϕ ) } For the purpose of dividing the incoming signal into two
P (t − t d ) optical signals and combining the optical beams beam splitter
= in ⋅ SW (t ) , SW(t) being the transfer function.
4 and beam combiner are used respectively and throughout all
The phase difference between cw pulse and ccw pulse can be the schematic diagrams are symbolized by front slash (/) and
defined as Δ ϕ = (ϕ cw − ϕ ccw ) . The symbols BC.
Gcw (t ), Gccw (t ) denote the respective power gains. The time B. Optical cost of circuit
dependent phase difference between CW and CCW pulses [19] We have considered the TOAD switches count as the
is optical cost of logic realization since the optical cost [9, 10] of
α  G cw ( t )  , where α being the the BC and BS are relatively small.
Δ ϕ = − ⋅ ln  
2  G ccw (t ) 
enhancement factor. C. Design of logic functions with TOAD
Calculation of power at port 2. Using TOAD we can realize any logic operation. For
1 * example, to calculate the x-or or nor value of two numbers or
Pout , 2 (t ) = E out ,2 (t ) ⋅ E (t )
2 out , 2 if we want to implement a multiplexer it can be realized with
2
= d 2 k 2 ⋅ Pin (t − t d ) ⋅ g cw (t − t d ) the help of TOAD switches as described in Gayen et al[5].
Considering an arbitrary logic function f = abc + ab/c/ is
 g 2 (t − t d ) 2
g (t − t d )  realized by TOAD switches as shown in Fig. 2.
⋅ 1 + ccw2 + 2 ⋅ aw ⋅ cos[ϕ cw (t − t d ) − ϕ aw (t − t d )]
 g cw (t − t d ) g cw (t − t d ) 
 G  abc
Gccw a T T
= d 2 k 2 ⋅ Pin (t − t d ) ⋅ Gcw ⋅ 1 + ccw + 2 ⋅ ⋅ cos[Δϕ ] O O
 Gcw Gcw  A A
b
{
= d 2 k 2 ⋅ Pin ⋅ (t − t d ) ⋅ Gcw + Gccw + 2 ⋅ Gccw ⋅ Gcw ⋅ cos[Δϕ ] } D D
T
B
C
abc + ab/c/

When the control signal is absent, the data signal after O

entering the fiber loop, passes through the SOA while counter- c A
propagating around the loop. They also experience the same D ab/c/
unsaturated amplifier gain denoted by Gss , which is
Fig. 2: Schematic diagram of f = abc + ab/c/
recombined at the input coupler i.e. G ccw = G cw leading to
Δ ϕ = 0 . Hence the expressions for Pout ,1 ( t ) = 0 and So, it can be concluded that any arbitrary logic function can be
implemented using TOAD. Hence, in the next section we Each full adder block FAi adds ai and bi bits taking the
present an n-bit adder circuit with the help of TOAD switches. previous carry ci-1 producing the respective sum bit si and
carry ci+1 to be added in the next full adder block. Each full
adder is implemented using TOAD as shown in the Fig. 3(b).
III. PROPOSED TECHNIQUE
a

TOAD
cout =ab+bcin+cina
A. Ripple carry and carry look ahead adder b BC

In this section we have proposed an all optical

TOAD
representation of a hybrid adder using terahertz optical BC

TOAD
asymmetric demultiplexer. First the functionality of ripple S=a⊕b⊕cin
BC
carry adder is explained and next the same is implemented
using TOAD exploiting some properties of both ripple carry

TOAD
cin
and carry look ahead adder to achieve a better result in terms
of both optical cost and optical delay. Fig. 3(b): Full adder circuit
bn-1 an-1 b2 a2 b1 a1 b0 a0 cin

cn-1 c2 c1 For each full adder time delay requires is 2×Δ where Δ=
delay of a single clock pulse. Hence, the total delay for n-bit
FA FA FA FA addition using ripple carry adder is (2n)Δ. For designing of n-
bit ripple carry adder the number of TOAD required =
cout n×(Number of TOAD in Full Adder) = 4n.
sn-1 s2 s1 s0 The delay required for ripple carry adder can be minimized
Fig. 3(a): Block diagram of n-bit ripple carry adder
by using a carry look ahead adder incurring higher amount of
TOAD as a consequence of exponential increment in optical
In ripple carry adder, to add two n-bit numbers, n number of cost. Fig. 3(c) shows the circuit diagram of 4-bit carry look
full adders are required where the carry output from each full
ahead adder with a look ahead block implemented using
adder is fed into the next full adder in the cascade as input
TOAD.
carry. cin a0 b0 a1 b1 a2 b2 a3 b3

TOAD TOAD TOAD TOAD TOAD TOAD TOAD TOAD

BC BC BC BC

TOAD TOAD

BC
BC

TOAD TOAD

BC
BC

TOAD TOAD
TOAD
BC Look ahead block
BC TOAD

TOAD TOAD TOAD TOAD TOAD TOAD

BC
BC
BC

S0 C1 S 1 C2 S 2 C3 S2 Cout P0-3 G0-3

Fig. 3(c): Block diagram of 4-bit CLA with lookahead block
 A 4-bit carry look ahead(CLA)[7] block can be used to addition if compared with the ripple carry adder. Each block
construct a 2n –bit CLA circuit using the same as a building consists of two TOADs where ai bit is inputted as the input
block. In this case the generation and propagation function can signal of one TOAD and control signal for other TOAD and
be expressed as follows: reverse is done in case of bi bit, that is the bi bit is sent to the
G0-3= G3+G2P3+G1P2P3+G0P1P2P3 control port of the first TOAD and incoming signal port of
P0-3 = P0P1P2P3 another TOAD. The output from the output port-II of both the
To illustrate this, a 16-bit CLA can be constructed using switches are combined using beam combiner to produce the Pi
integration of four 4-bit CLA modules and an additional 4-bit i.e. ai⊕ bi bit and outcome from output port-I produces Gi. The
look ahead block. To generalize for computation of 2n bit next following stages displays a stair case approach to
CLA, compute the Si and Ci+1 bits. These rest of the stages can be
No. of 4-bit CLA Blocks = (2n/4 4-bit blocks) + (no. of 4-bit divided in n-1 horizontal levels, each of which consisting
look-ahead blocks to design 2n-2-bit CLA). identical structures where one of the output of the i-1 level is
4i bit CLA= 4i-1(4-bit CLA) + ( 4 − 1 ) look ahead block fed into the control port of a TOAD and the Pi bit of that
i −1

3 respective level is inputted to incoming port of that TOAD and

Thus the n-bit CLA can be constructed recursively using the the reverse is done for another TOAD. The output from the
4-bit CLA block giving an overhead of the look ahead block output port-I of one of the TOAD is combined with the Gi bit
resulting in increased optical cost for presence of group of that level producing Ci+1 and the outcome of the output
generation and propagation functions in the circuit since for port-II of both the TOADs are combined using beam combiner
larger number of bits the optical cost increases exponentially to produce the Si bit of that level where Si and Ci+1 can be
due to presence of the look ahead block as evident from the described as,
equation. Hence the same is removed in the proposed design Si= Pi⊕ (Gi-1 + Pi-1 Gi-2 + Pi-1 . Pi-2 .Gi-3 + …)
avoiding the group generate and group propagate function by Ci+1= Gi + Pi Gi-1 + Pi . Pi-1 .Gi-2 + …
implementing ripple nature of the carry generated in the In other words the equations can be generalized as,
j −1
previous state. i

To cope up with this bottleneck of both the ripple carry S i = Pi ⊕ [G i +  (∏ Pi − k ).G i − j ]

j=2 k =1
adder and carry look ahead adder a hybrid adder is proposed i j −1
that works like a ripple carry adder exploiting the functional
properties of the carry look ahead adder.
C i +1 = G i +  (∏
j =1 k =0
Pi − k ). G i − j

In the hybrid adder the carry output ci+1 is related to the The equations reveal the generation of sum and carry bits in
carry input ci as follows: ci+1=aibi+ (ai⊕bi)ci . The equation the proposed design. After n-1 hierarchical levels we get the
can be rewritten as: ci+1= Gi + Pi .ci , where Gi=ai.bi and final result of the addition and the carry out bit.
Pi=ai⊕bi and the sum bit si is calculated as si=ai⊕bi⊕ci . B.1. Calculation of Optical Cost:
For example in order to add two 4-bit numbers the equations
revealing the dependencies of the carry bits on the previous For adding two n-bit numbers, the first level of the hybrid
one can be written as , design is divided in n- identical block each of which
c1 = G0 , since the initial carry is not considered consisting of two TOADs and one beam combiner that
c2 = G1 + P1 .c1 = G1 + P1 . G0 requires total 2n TOADs and n beam combiner for that level.
c3 = G2 + P2 .c2 = G2 + P2 (G1 + P1 . G0) For the rest of the (n-1) level, each level consists two TOADs
c4 = G3 + P3 .c3 = G3 + P3 (G2 + P2 (G1 + P1 . G0)) and two beam combiner. Hence, in total for these (n-1) levels
Hence, the sum bits can be computed as, 2(n-1) numbers of TOAD switches and 2(n-1) beam combiner
S 0 = P 0⊕ 0 = P 0 is required. So, the optical cost for this hybrid design can be
S 1 = P 1⊕ G 0 stated as,
S2 = P2⊕ (G1 + P1 . G0) The number of TOAD switch = 2n + 2x(n - 1) = 4n-2
S3 = P3⊕ (G2 + P2 (G1 + P1 . G0)) The number of beam combiner = n + (2n - 2) = 3n - 2
i.e. in each step Pi and Gi bits are rippled to the next step for C. Calculation of Optical delay
computation of the sum bit . The first horizontal level computes the x-or value of ai and
B. Hybrid design for n-bit adder bi bits in unit time making optical delay= Δ, where Δ being the
The proposed design can be viewed as cascade of n blocks delay for a single clock pulse. For subsequent levels in the
in the first level followed by a hierarchical staircase approach staircase design each level requires a delay of Δ to give (n-1)
for rest of the block in the subsequent levels for the two n-bit Δ delay for (n-1) levels making overall optical delay of the
numbers being added. The proposed design is implemented in adder circuit = Δ+(n-1)Δ=nΔ, also shown in the Fig. 3(d).
the Fig. 3(d) where two n-bit numbers an-1an-2…a1a0 and bn-1bn- Table-I depicts the comparison result of our proposed
design with the related works considering various design
2…b1b0 are added producing sum sn-1sn-2…s1s0 and carry out
bit cn. In the first level of the hybrid design n numbers of metrics. From the experimental result it is evident that the
identical blocks in parallel compute the propagation and presented design is more efficient than the previous works
generator bit to significantly minimize the delay of the
since it takes less delay and uses reduced no. of TOADs for
computation of the same.

Optical an-1 bn-1 an-2 bn-2 a2 b2 a1 b1 a0 b0

Delay Number of
TOAD

1Δ TOAD TOAD TOAD TOAD TOAD TOAD TOAD TOAD TOAD TOAD (2×n)

BC BC BC BC BC

Pn-1 Gn-1 Pn-2 Gn-2 P2 G2 P1 G1 P0 G0

1Δ
TOAD TOAD 2

BC
BC

1Δ
TOAD TOAD 2

BC
BC
(n-1)
terms
1Δ
TOAD TOAD

2
BC
BC

TOAD TOAD 2
1Δ

BC
BC

Total Optical Total Number

Delay of TOAD
1Δ + (n-1)Δ = nΔ Sn-1 Cn Sn-2 Cn-1 S 2 C3 S 1 C2 S 0 C1
2n + 2(n-1)
= 4n-2
Fig. 3(d): Proposed adder circuit

Table-I: Design cost metrics comparison

Work-I Work-II Work-III Work-IV Work-I Proposed design

(design-1) [15] [13] [9] (design-2)
[4] [4]
No. of Ancilla 0 0 0 0 0 0
input
No. of Garbage 0 0 0 0 0 0
output
Total Optical cost 18n-19 8n-8 6n+2 19n-5 18n-8 4n-2

Total Delay (Δ) 4n+5 3n+2 3n+1 4n+4 4n+1 n

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