MOS DEVICE FUNDAMENTALS

Professor A. K. Majumdar

Computer Science and Engineering Department Indian Institute of Technology, Kharagpur

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Metal-Oxide Semiconductor (MOS) Field Effect Transistors

NMOS enhancement mode transistor

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Induced Channel in NMOS Transistor

Enhancement mode NMOS transistor with VGS>0 showing induced channel

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Current Voltage characteristics of NMOS transistors

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NMOS Transistor Analysis

Induced Channel Charge / Unit Area Q(x) = - COX [ VGS V(x) Vth] Where COX = OX/ tOX capacitance per unit area due to gate oxide Drain current IDS = vn(x) Q(x)W vn(x) = drift velocity of electron

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NMOS Transistor Analysis Contd

vn(x) = - n E(x) = n dV/dx n = Mobility of electrons Hence IDS = - n Q(x)W dV/dx Substituting for Q(x), IDS dx = n COX W[VGS V(x) Vth] dV Integrating IDS= n COX W/L[(VGS - Vth ) - VDS /2 ] VDS IDS = n [(VGS - Vth ) - VDS /2 ] VDS
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NMOS Transistor Analysis in Linear Region

kn =n COX = n OX/ tOX is called process transconductance parameter n = kn(W/L) is called gain factor For small VDS , VDS2 /2 can be ignored and IDS depends linearly on VDS Rlinear = 1/ (n (VGS - Vth))

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NMOS Transistor Analysis in Linear Region

Transconductance of NMOS transistor gm = (dIDS/ dVGS) VDS = constant In linear region gm = n VDS

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NMOS Transistor Analysis Saturation Region

VDS VGS Vth Channel is pinched off Assuming voltage difference over induced channel from source to pinch off point fixed at VGS Vth IDS = n /2 (VGS Vth)2 In saturation region, MOS transistor acts as a constant current source. Transconductance in saturation region gm = n (VGS Vth)
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Current Voltage Relationship of NMOS Transistor

The drain-to-source current-voltage dependence for a NMOS transistor is given by the following equations
IDS = 0 IDS = n/2.(VGS Vth)2 for VDS < Vth (off) for 0 < VDS Vth < VDS (saturation)

IDS = n(VGS Vth VDS/2)VDS for VGS > Vth and VGS Vth VDS (linear) n = (nox/tox).W/L

where n is the mobility of electron, ox is the permittivity of the oxide material, and tox is the thickness of the oxide.
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Channel Length Modulation

In saturation region, the transistor does not operate as a perfect current source, i.e. IDS is not independent of VDS As VDS is increased beyond (VGS Vth) effective channel length decreases. Since IDS 1/L, reduction in effective channel length increases IDS More accurate representation IDS = n/2.(Vgs Vth)2 ( 1 + VDS)
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Current Voltage Relationship of PMOS Transistor

Cut off VGS > Vth IDS = 0 Linear Region: VGS Vth and VDS > VGS Vth IDS = p(VGS Vth VDS/2)VDS Saturation region VGS Vth, and VDS < VGSVth IDS = p/2.(VGSVth)2 where the gain factor p = (pox/tox).W/L and p is mobility of holes
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Velocity Saturation
Electron mobility cannot be considered to be constant with increasing electric field For short channel devices velocity saturates

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Velocity saturation effect

Let VDSAT : drain-source voltage at which the critical field for velocity saturation is reached First order approximation: For VDS < VDSAT, IDS expression is similar to long channel model For VDS VDSAT IDS =IDSAT = SAT Cox W [ VGS Vth VDSAT/2 ] Where SAT = VDSAT / L is the saturation velocity
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MOS Transistor Threshold Voltage

Depletion region charge density - due to fixed acceptor ions in the p-type substrate:
Qdep = 2q si N AVdep

where, Vdep is the voltage across the depletion layer at the oxide silicon boundary Channel inversion occurs when Vdep = 2F where the Fermi potential F = kT/q ln( NA/ ni) F -0.3 V for nMOS
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Threshold Voltage
At strong inversion depletion layer charge density:

Qdep = 2qsi NA (| 2F +VSB |)

Where VSB is the substrate bias With zero substrate bias, threshold voltage Vth0 = GC -2 F - Qdep / Cox - Qi / Cox where is GC the work function difference between the gate and substrate (flat band voltage) and Qi is due to impurities at the interface between the gate oxide and silicon substrate

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Threshold Voltage
Threshold voltage with non-zero substrate bias
V =V 0 + | 2F +V | | 2F | th th SB

where the parameter is called bodyeffect (substrate bias) coefficient.

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Threshold Variations in Short Channel Devices

Threshold depends on L, W and VDS Due to depletion regions of the source and reversebiased drain junction. Drain-induced barrier lowering (DIBL) : Vth0 decreases with increasing VDS . Very high drain voltage source and drain depletion regions may get shorted (punch-through) Narrow channel effects: Vth0 increases since depletion regions does not abruptly stops at the edges of the transistors but extends to isolating field oxide regions. Gate voltage must support the extra depletion charge to establish conducting channel.
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Sub-threshold / Weak-Inversion Current

Channel current when VGS < Vth IDS (sub-threshold) has exponential dependence on both gate and drain voltages and can be expressed as

ISe

q / kT ( AVGS + BVDS )

Slope factor: S - rate of decline of the current with respect to VGS below Vth in mv/ decade( 2.3 kT/Aq). With A =1, S evaluates to 60mV/decade (i.e. current drops by a factor of ten for a reduction of VGS by 60mv) usually A<1 and current falls at a reduced rate e.g 90mV/decade
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Reverse-Biased Diode Leakage

GATE

p+

p+

Reverse Leakage Current +

V - dd

IDL = JS A

Reverse leakage Current of a p-n junction Ireverse=

Reverse saturation current Density JS = 10-100 pA/m2
JS doubles for every 9 deg C!

A JS(e

qVbias/kT

1)

at 25 deg C for 0.25m CMOS,

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Lateral diffusion of source and drain regions

Lateral diffusion = Ld Effective channel length Leff = L -2 Ld

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MOSFET Capacitances
Oxide related (Gate ) capacitances: CGS, CGD, CGB Junction capacitances : CSB, CDB - due to source / drain diffusion regions in the substrate

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MOS transistor gate capacitances for three operating regions

Capacitance CGB CGS CGD

Cutoff Linear Saturation CoxW Leff 0 0 Cox W Ld CoxW Ld + CoxW Leff CoxW Ld + 2/3 CoxW Leff Cox W Ld CoxW Ld + CoxW Leff CoxW Ld

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NMOS Inverter

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Pull Up and Pull Down transistors

The depletion mode transistor is a pull up device. It is always on (Vgs = 0) The enhancement mode transistor is the pull down device. With no current drawn from output, current in both pull up and pull down transistors must be same.

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Current Voltage Characteristics of NMOS Inverter

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NMOS Inverter
The points of intersection of the pull up (for Vgs =0 ) and pull down curves give points on the transfer characteristics for the inverter As Vin exceeds VTpd (pull down transistor threshold) current will flow and Vout falls. Further increase in Vin will cause pull down transistor to be out of saturation and will behave as resistor Pull up device is initially resistive when pull down is turned on The point at which Vin = Vout is called Vinv Vinv can be shifted by variation of ratios of pull up and down resistances determined by the length to width ratio of the transistor.
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NMOS Inverter
With NMOS Depletion Mode transistor High Dissipation: When VIN is high current flows through both the devices. Output switching: occurs when Vin exceeds Vthpd During fall 1 0 transition, pull up offers lower resistance to charge capacitive load. Degrades 0 value : Low output value is determined by pull down resistance.
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CMOS INVERTER

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CMOS Inverter
N Well VDD 2

VDD PMOS In Out

PMOS

Contacts

In

Out Metal 1

NMOS

Polysilicon

NMOS GND

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CMOS Fabrication

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CMOS Fabrication

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Current Voltage Characteristics

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CMOS INVERTER VOLTAGE TRANSFER CHARACTERISTICS

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CMOS INVERTER - CONTD

Region R1: 0 < Vin < Vthn, NMOS transistor is off, PMOS device operates in the linear region. Region R2: Vthn< Vin< VDD - |Vthp| and Vin + |Vthp| < Vout VDD, NMOS transistor in saturation, and PMOS transistor still in the linear region. Region R3: Vthn<Vin<VDD - |Vthp| and Vin - Vthn Vout Vin + |Vthp|, both the transistors are in saturation. Region R4: Vthn < Vin< VDD |Vthp| and Vout < Vin - Vthn, NMOS transistor is in the linear region and PMOS remains in saturation. Region R5: VDD |Vthp| < Vin < VDD, PMOS transistor in cut-off, NMOS in the linear region.

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CMOS Inverter Characteristics

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Static Analysis of CMOS Inverter

Current Voltage Relationship of NMOS transistor : VGSn = Vin , VDSn = Vout n = (n /tox) (W/L)n Cut-off (Vin Vthn) : IDS = 0

Linear (Vin Vthn Vout) : IDS = n(VGSn Vthn VDSn/2)VDSn Saturation ( Vthn Vin, Vout > Vin Vthn): IDS = n/2(VGSn Vthn)2
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Current Voltage Relationship of PMOS transistor

VGSp = - (VDD Vin), VDSp = - (VDD Vout) p = (p /tox) (W/L)n Cut-off (Vin > VDD - |Vthp|) : IDS = 0

Linear (Vin VDD - |Vthp|) and (Vout >Vin +|Vthn|) : IDS = n(VGSp |Vthp| VDSp/2)VDSp Saturation (Vin VDD - |Vthp|) and (Vout Vin +|Vthp|) :IDS = p/2(VGSn |Vthp|)2

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Static Analysis of CMOS InverterContd

VOH = VDD VOL = 0 Vinv = [ Vthn + (1/)(VDD + Vthp)] / (1 + 1/) = n/p =[n(ox/tox)n (W/L)n ]/ [p(ox/tox)p(W/L)p] for = 1, (W/L)n / (W/L)p = p/n 1/2.5 (W/L)p 2.5 (W/L)n
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Static Analysis of CMOS InverterContd

VIL = (2Vout + Vthp VDD + Vthn) / (1 + ) = 1, and Vthn = Vthp VIL = 1/8 (3VDD +2 Vthn) VIH = [VDD + Vthp + (2 Vout + Vthn)] / (1 + ) with = 1, and Vthn = Vthp, VIH = (5VDD 2Vthn) /8

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NOISE MARGINS

NML = VIL VOL = VIL NMH = VOH VIH = VDD VIH

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Switching Characteristics of a CMOS Inverter

Parasitic capacitances in a cascaded CMOS inverter

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Switch model of a static CMOS inverter

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Propagation delay times and rise and fall times of an inverter

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CMOS inverter equivalent circuit during high-to-low and low-to-high output transitions

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Propagation Delay Estimation

High to Low Transition pHL = pHL1 + pHL2 pHL1 = the period during which Vout drops from VDD to VDD Vthn. pHL1 = 2 CLVthn / n (VDD Vthn)2 pHL2 = the period during which Vout drops from VDD Vthn to VDD /2. pHL2 =
4V thn CL ln 3 n (V DD V thn ) V DD
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Propagation Delay Estimation Contd.

Low to High Transition pLH =
2|Vthp | 4|Vthp | CL + ln3 p(VDD|Vthp |)(VDD|Vthp |) VDD

For pHL = pLH , (W/L)p 2.5 (W/L)n

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Typical input - output and load capacitor current waveforms in a CMOS inverter

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Power Dissipation in CMOS Inverter

Dynamic Power Consumption
Charging and Discharging Capacitors

Short Circuit Currents

Short Circuit Path between Supply Rails during Switching

Leakage
Leaking diodes and transistors

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Dynamic Power Consumption

E-charge = CL VDD2 E-discharge = CL VDD2 Average Power dissipation PAvg= 1/T CL VDD2 = CL VDD2 f
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Switching Power Dissipation in CMOS Inverter

fmax = 1/2p Power Delay Product, PDP = Pavg p For f = fmax, PDP = CL VDD2 fmax p = CL VDD2 Note: average switching power dissipation of a CMOS inverter is independent of transistor sizes and characteristics provided there is full voltage swing Analysis is valid when output node of the gate undergoes one transition (0 to VDD) in a clock cycle.
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Switching Power Dissipation - Contd

When node transition rate is slower than clock rate PAvg = T CL VDD2 f where T is the node transition factor (effective number of power consuming transition per cycle) Energy Delay Product EDP = PDP p = CL VDD2 p

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Short Circuit Current in CMOS Inverter

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Short Circuit Current

Short circuit current is large if output load capacitance is low and input rise/fall time is large. To reduce short circuit power dissipation input/output rise and fall times should be of same order = PAvg(short-circuit) = 1/12[k f (VDD- Vthn -|Vthp|)3]

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Sub Threshold Leakage

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Advantages of CMOS Inverter

The high and low output voltages are equal to Vdd and ground respectively so that the voltage swing is the same as the supply voltage.. The logic levels are not dependent on the relative device sizes and hence the size of the transistors can be minimized. There is always a finite resistance between the output and either Vdd or ground in the steady state. The inverter can, therefore, be designed to have a low input impedance, making it less sensitive to noise. The CMOS inverter has a very high input resistance and draws no dc input current as the gate of a MOS transistor is virtually a perfect insulator.
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Technology Scaling
Full Scaling (Constant Field Scaling) Constant Voltage Scaling
Parameter Channel Length (L) Channel Width (W) Gate oxide thickness (tox) Supply voltage VDD Junction depth (Xj) Threshold voltage (Vth) Doping densities ND (NA) Full Scaling Constant-Voltage Scaling L/ L/ W/ W/ tox / tox / VDD / Xj / Vth/ ND (NA) VDD Xj / Vth ND (NA )
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2 2

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Effects of scaling on MOS transistor characteristics

Parameter Gate Area (A = WL) Oxide capacitance (Cox) Gate capacitance Cg (= CoxWL) Transconductance/Gain factor () Electric field (E) Drain current (IDS) Power dissipation (P) Power density ( PD = P/area) Gate delay () Full Scaling 2 A/ Constant-Voltage Scaling 2 A/

Cox Cg/
E IDS/ 2 P/ PD /

Cox Cg/ E IDS P 3 PD 2 /

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Inter-dependence of leakage currents in short channel devices

Device Geometry (channel length, oxide thickness) and doping profile affects Sub-threshold leakage Gate leakage Reverse biased diode (drain/ source substrate) leakage

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Factors affecting scaling

Constant field scaling requires threshold voltage reduction to improve propagation delay. Low threshold affects: noise margins and sub-threshold conduction. Gate oxide thickness reduction: Increases gate leakage due to electron tunneling and hot carrier injection from substrate to gate
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Threshold Reduction
By well engineering : changing doping profile in the channel (e.g halo doping). Aims to minimize leakage currents while maximizing linear and saturated currents. Multiple threshold CMOC circuits Variable threshold circuits

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SPICE SIMULATION
Active/ passive devices used in the circuit under simulation are represented by suitable models. Uses Kirchoff laws for analysis of circuit behavior Circuit voltage and current signals are represented as continuous waveforms. During simulation continuous variables are approximated by floating point numbers with suitable increment steps specified. SPICE supports different modes of analysis of active circuits : DC analysis, transient analysis, small signal analysis, etc. Different versions of SPICE: PSPICE, HSPICE, T-SPICE
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MOSFET MODEL
SPICE syntax for MOSFET device is .model <name> nmos | pmos level = 1| 2| 3 (parameters) Some of the parameters are gate oxide thickness (TOX), channel length (L), channel width (W), drain area (AD), source area (AS), drain resistance (RD), source resistance (RS), etc.
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MODEL FILE
.model nmos nmos Level=1 + Vto=2.0 Kp=3.0E-5 Gamma=0.35 + Phi=0.65 Lambda=0.002 Tox=0.1u + Nsub=1.0E+15 Nss=1.0E+10 Ld=0.8u + Tpg=1.00 Uo=700.0 Af=1.2 + Kf=1.0E-26 Is=1.0E-15 Js=1.0E-8 + Pb=0.75 Cj=2.0E-4 Mj=0.5 + Cjsw=1.00E-9 Mjsw=0.33 Fc=0.5 + Cgbo=2.0E-10 Cgdo=4.00E-11 Cgso=4.00E-11 + Rd=10.0 Rs=10.0 Rsh=30.0 .model pmos pmos Level=1 + Vto=-2.0 Kp=3.0E-5 Gamma=0.35 + Phi=0.65 Lambda=0.002 Tox=0.1u + Nsub=1.0E+15 Nss=1.0E+10 Ld=0.8u + Tpg=1.00 Uo=700.0 Af=1.2 + Kf=1.0E-26 Is=1.0E-15 Js=1.0E-8 + Pb=0.75 Cj=2.0E-4 Mj=0.5 + Cjsw=1.00E-9 Mjsw=0.33 Fc=0.5 + Cgbo=2.0E-10 Cgdo=4.00E-11 Cgso=4.00E-11 + Rd=10.0 Rs=10.0 Rsh=30.0

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FORMAT FOR WRITING SPICE NETLIST

* Waveform probing commands .probe .options probefilename="INV.dat" + probesdbfile="C:\Documents and Settings\smdp\Desktop\inv\INV.sdb" + probetopmodule="Module0 .include ml1_1_typ.md (model file included) vdd vdd 0 5 0 vin vin gnd PULSE (0 5 0 1n 1n 1u 2u) ROUND=0 (input pulse) .tran .1u 10u start=0 (type of analysis) .print tran v(vin) v(vout) (probing for the output) * Main circuit: Module0 M1 vout vin Gnd Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u M2 vout vin Vdd Vdd PMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u * End of main circuit: Module0
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DC ANALYSIS RESULT

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AC ANALYSIS RESULT

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EFFECT OF CHANGE IN THE MODEL FILE PARAMETER

Declaration of model file 1 .model nmos nmos Level=1 + Vto=2.0 Kp=3.0E-5 .model pmos pmos Level=1 + Vto=-2.0 Kp=3.0E-5 Gamma=0.35 Gamma=0.35

Declaration of model file 2 .model nmos nmos Level=1 + Vto=1.0 Kp=3.0E-5 .model pmos pmos Level=1 + Vto=-1.0 Kp=3.0E-5 Gamma=0.35 Gamma=0.35

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RESULT COMPARISON

REFERENCES
1. 2. 3. Rabaey J. M.,Chandrakasan A., and Nikolic B., Digital Integrated Circuits, Prentice- Hall of India, 2003. Kang, Sung-Mo and Leblebici, Y.: CMOS Digital Integrated Circuits, McGraw Hill Pub., 2003 Weste N.H.E and Eshraghlan, K: Principles of CMOS VLSI Design, Pearson Education, 2004.

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