Analog CMOS Circuit Deisgn

Page 9.0-1

CHAPTER 9 -SWITCHED CAPACITOR CIRCUITS

Outline Section 9.1 - Switched Capacitor Circuits Section 9.2 - Switched Capacitor Amplifiers Section 9.3 - Switched Capacitor Integrators Section 9.4 - z-domain Models of Two-Phase, Switched Capacitor Circuits, Simulation Section 9.5 - First-order, Switched Capacitor Circuits Section 9.6 - Second-order, Switched Capacitor Circuits Section 9.7 - Switched Capacitor Filters Section 9.8 - Summary

Chapter 9 - Switched Capacitor Circuits (6/4/01) Analog CMOS Circuit Deisgn

P.E. Allen, 2001 Page 9.1-1

9.1 - SWITCHED CAPACITOR CIRCUITS

RESISTOR EMULATION Switched capacitor circuits are not new. James Clerk Maxwell used switches and a capacitor to measure the equivalent resistance of a galvanometer in the 1860s. Parallel Switched Capacitor Equivalent Resistor:
i1(t) v1(t)
1 2

i2 (t) v2 (t) v1(t)

i1(t)

i2 (t) v2 (t)

vC (t)

C
(a.)

(b.)

Figure 9.1-1 (a.) Parallel switched capacitor equivalent resistor. (b.) Continuous time resistor of value R.

Two-Phase, Nonoverlapping Clock:

1

1 0
2

1 t 0 0 T/2 T 3T/2 2T Figure 9.1-2 - Waveforms of a typical two-phase, nonoverlapping clock scheme.

Chapter 9 - Switched Capacitor Circuits (6/4/01)

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Analog CMOS Circuit Deisgn

Page 9.1-2

EQUIVALENT RESISTANCE OF A SWITCHED CAPACITOR CIRCUIT Assume that v1(t) and v2(t) are changing slowly with respect to the clock period. The average current is, T T/2 i1(t) i2 (t) 1 1 1 2 i1(average) = T i1(t)dt = T i1(t)dt
v1(t) vC (t) Charge and current are related as, dq1(t) i1(t) = dt Substituting this in the above gives, T/2 1 q1(T/2)-q1(0) CvC(T/2)-CvC(0) = i1(average) = T dq1(t) = T T
0 0 0

v2 (t)

However, vC(T/2) = v1(T/2) and vC(0) = v2(0). Therefore, C [v1(T/2)-v2(0)] C [V1-V2] i1(average) = T T For the continuous time circuit: i1(t) i2 (t) R V -V T i1(average) = 1R 2 R C v (t) v (t)
1 2

For v1(t) V1 and v2(t) V2, the signal frequency must be much less than fc.

Chapter 9 - Switched Capacitor Circuits (6/4/01) Analog CMOS Circuit Deisgn

P.E. Allen, 2001 Page 9.1-3

EXAMPLE 9.1 - Design of a Parallel Switched Capacitor Resistor Emulation If the clock frequency of parallel switched capacitor equivalent resistor is 100kHz, find the value of the capacitor C that will emulate a 1M resistor. Solution The period of a 100kHz clock waveform is 10sec. Therefore, using the previous relationship, we get that T 10-5 C = R = 106 = 10pF We know from previous considerations that the area required for 10pF capacitor is much less than for a 1M resistor when implemented in CMOS technology.

Chapter 9 - Switched Capacitor Circuits (6/4/01)

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Analog CMOS Circuit Deisgn

Page 9.1-4

POWER DISSIPATION IN THE RESISTANCE EMULATION

If the switched capacitor circuit is an equivalent resistance, how is the power dissipated?
i1(t) v1(t)
1 2

i2 (t) v2 (t) v1(t)

i1(t)

i2 (t) v2 (t)

vC (t)

C
(a.)

(b.)

Figure 9.1-1 (a.) Parallel switched capacitor equivalent resistor. (b.) Continuous time resistor of value R.

Continuous Time Resistor: (V1 - V2)2 R Discrete Time Resistor Emulation: Assume the switches have an ON resistance of Ron. The power dissipated per clock cycle is, Power = (V1 -V2) T Power = i1(aver.)(V1-V2) where i1 (aver.) = R T e -t/(RonC)dt on
0

(V1-V2)2 T (V1-V2)2 (V1-V2)2 e -t/(RonC)dt = (T/C) [ -e -T /(R onC) + 1] (T/C) Power = TR if T >> RonC on 0 Thus, if R = T/C, then the power dissipation is identical in the continuous time and discrete time realizations.

Chapter 9 - Switched Capacitor Circuits (6/4/01) Analog CMOS Circuit Deisgn

P.E. Allen, 2001 Page 9.1-5

OTHER SWITCHED CAPACITOR EQUIVALENT RESISTANCE CIRCUITS

i1(t) v1(t)
1 2

i2 (t) v1(t)

i1(t)

i2 (t)

i1(t)

S1

S2 v2 (t)

C
vC (t)

C1

S1

S2 v2 (t) vC2(t) v1(t)

S1 C S2 i2 (t) vC (t)
2

S1

vC1 (t)

S2 v2 (t)

Series Series-Parallel: The current, i1(t), that flows during both the 1 and 2 clocks is:
T 0 T/2 T

C2 Series-Parallel

Bilinear

q (T/2)-q (0) q (T)-q (T/2) 1 1 i1(average) = T i1(t)dt = T i1(t)dt + i1(t)dt = 1 T 1 + 1 T1 0

T/2

Therefore, i1(average) can be written as, C2 [vC2(T/2)-vC2(0)] C1 [vC1(T)-vC1(T/2)] + i1(average) = T T The sequence of switches cause,vC2(0) = V2, vC2(T/2) = V1, vC1(T/2) = 0, and vC1(T) = V1 - V2. Applying these results gives C2[V1-V2] C1[V1-V2- 0] (C1+C2)(V1-V2) + = i1(average) = T T T T Equating the average current to the continuous time circuit gives: R =C +C 1 2

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Analog CMOS Circuit Deisgn

Page 9.1-6

EXAMPLE 9.1-2 - Design of a Series-Parallel Switched Capacitor Resistor Emulation If C1 = C2 = C, find the value of C that will emulate a 1M resistor if the clock frequency is 250kHz. Solution The period of the clock waveform is 4sec. Using above relationship we find that C is given as, T 4x10-6 2C = R = = 4pF 106 Therefore, C1 = C2 = C = 2pF.

Chapter 9 - Switched Capacitor Circuits (6/4/01) Analog CMOS Circuit Deisgn

P.E. Allen, 2001 Page 9.1-7

SUMMARY OF THE FOUR SWITCHED CAPACITOR RESISTANCE CIRCUITS

Switched Capacitor Resistor Emulation Circuit
1

Schematic
2

Equivalent Resistance

Parallel

v1(t) C

v2 (t)

T C

Series

v1(t)

C
1 2

v2 (t)

T C

Series-Parallel

v1(t)

C1
1

C2
2

v2 (t)

T C1+C2

Bilinear

C
v1(t)
2 1

v2 (t)

T 4C

Chapter 9 - Switched Capacitor Circuits (6/4/01)

P.E. Allen, 2001

Analog CMOS Circuit Deisgn

Page 9.1-8

ACCURACY OF SWITCHED CAPACITOR CIRCUITS Consider the following continuous time, first-order, low pass circuit:
R1 v1 C2 v2

The transfer function of this simple circuit is, V2(j) 1 1 H(j) = V (j) = j R C + 1 = j + 1 1 1 2 1 where 1 = R1C2 is the time constant of the circuit and determines the accuracy. Continuous Time Accuracy Let 1 = C. The accuracy of C can be expressed as, dC dR1 dC2 C = R1 + C2 5% to 20% depending on the size of the components Discrete Time Accuracy T 1 Let 1 = D = C C2 = f C C2. The accuracy of D can be expressed as, 1 c 1 dD dC2 dC1 dfc 0.1% to 1% depending on the size of components D = C2 - C1 - fc The above is the primary reason for the success of switched capacitor circuits in CMOS technology.

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P.E. Allen, 2001 Page 9.1-9

ANALYSIS METHODS FOR TWO-PHASE, NONOVERLAPPING CLOCKS Sampled Data Voltage Waveforms for a Two-phase Clock:
v*(t)

A sampled-data voltage waveform for a two-phase clock.

1 2

v(t)

0 1/2 1 3/2 2 5/2 3 7/2 4 9/2 5 vO(t)

t/T

A sampled-data voltage waveform for the odd-phase clock.

1

v(t)

0 1/2 1 3/2 2 5/2 3 7/2 4 9/2 5

t/T

A sampled-data v (t) voltage waveform for the even-phase clock.

e

v(t)

0 1/2 1 3/2 2 5/2 3 7/2 4 9/2 5

t/T

Chapter 9 - Switched Capacitor Circuits (6/4/01)

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Analog CMOS Circuit Deisgn

Page 9.1-10

ANALYSIS METHODS FOR TWO-PHASE, NONOVERLAPPING CLOCKS - CONTD Time-domain Relationships: The previous figure showed that, v*(t) = vo(t) + ve(t) (2). where the superscript o denotes the odd phase (1) and the superscript e denotes the even phase For any given sample point, t = nT/2, the above may be expressed as nT nT nT = v o 2 n=1,3,5, + v e 2 n=2,4,5, v* 2 n=1,2,3,4,5,6, z-domain Relationships: Consider the one-sided z-transform of a sequence, v(nT), defined as V(z) = v(nT)z - n = v(0) + v(T)z- 1 + v(2T)z- 2 +
n=0

for all z for which the series V(z) converges. Now, this equation can be expressed in the z-domain as V*(z) = V o(z) + V e(z) . The z-domain format for switched capacitor circuits will allow us to analyze transfer functions.

Chapter 9 - Switched Capacitor Circuits (6/4/01) Analog CMOS Circuit Deisgn

P.E. Allen, 2001 Page 9.1-11

TRANSFER FUNCTION VIEWPOINT OF SWITCHED CAPACITOR CIRCUITS Input-output voltages of a general switched capacitor circuit in the z-domain.
Switched Capacitor Circuit
1 2

Vi (z) = Vi (z) + Vi (z)

Vo (z) = V (z) + Vo (z) o

z-domain transfer functions: j V o (z) ij H (z) = i V i(z) where i and j can be either e or o. For example, Hoe(z) represents Vo (z)/ V i (z) . Also, a transfer function, H(z) can be defined as Vo(z) V o(z) + Vo (z) . H(z) = V (z) = e o i V i (z) + V i (z)
e o
e o

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Analog CMOS Circuit Deisgn

Page 9.1-12

APPROACH FOR ANALYZING SWITCHED CAPACITOR CIRCUITS 1.) 2.) 3.) 4.) 5.) 6.) Analyze the circuit in the time-domain during a selected phase period. The resulting equations are based on q = Cv. Analyze the following phase period carrying over the initial conditions from the previous analysis. Identify the time-domain equation that relates the desired voltage variables. Convert this equation to the z-domain. Solve for the desired z-domain transfer function.

7.) Replace z by ejT and examine the frequency response.

Chapter 9 - Switched Capacitor Circuits (6/4/01) Analog CMOS Circuit Deisgn

P.E. Allen, 2001 Page 9.1-13

EXAMPLE 9.1-3 - Analysis of a Switched Capacitor, First-order, Low pass Filter Use the above approach to find the z-domain transfer function of the first-order, low pass switched capacitor circuit shown below. This circuit was developed by replacing the resistor, R1, of the previous circuit with the parallel switched capacitor resistor circuit. The timing of the clocks is also shown. This timing is arbitrary and is used to assist the analysis and does not change the result.
1 2

v1

C1

C2

v2

Switched capacitor, low pass filter.

1 1 2 2 2 t 1 3 1 n- 2 n-1 n- 2 n n+ 2 n+1 T Clock phasing for this example.

Solution 1: (n-1)T< t < (n-0.5)T Equivalent circuit:

C2 v1o(n-1)T C1 C2
e o 3 v2(n- 2 )T v2(n-1)T

v1o(n-1)T C1

e o 3 v2(n- 2 )T v2(n-1)T

Equivalent circuit.

Simplified equivalent circuit.

o v2(n-1)T

The voltage at the output (across C2) is

e v2

(n-3/2)T

(1)

Chapter 9 - Switched Capacitor Circuits (6/4/01)

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Analog CMOS Circuit Deisgn

Page 9.1-14

EXAMPLE 9.1-3 - Continued

2: (n-0.5)T< t < nT Equivalent circuit:

C1 e v1(n-1/2)T C2 C1 vo(n-1)T 1
1 v e(n- 2 )T 2 o v2 (n-1)T

The output of this circuit can be expressed as the superposition of two voltage sources, o o v1 (n-1)T and v2 (n-1)T given as C1 C2 e o o v2 (n-1/2)T = C +C v1 (n-1)T + C +C v2 (n-1)T. 1 1 2 2 If we advance Eq. (1) by one full period, T, it can be rewritten as o e v2(n)T = v2 (n-1/2)T. Substituting, Eq. (3) into Eq. (2) yields the desired result given as C1 C2 o o o v2 (nT) = C +C v1 (n-1)T + C +C v2 (n-1)T. 1 1 2 2

(2) (3) (4)

Chapter 9 - Switched Capacitor Circuits (6/4/01) Analog CMOS Circuit Deisgn

P.E. Allen, 2001 Page 9.1-15

EXAMPLE 9.1-3 - Continued z-domain Analysis The next step is to write the z-domain equivalent expression for Eq. (4). This can be done term by term using the sequence shifting property given as The result is v(n-n1)T z-n1V(z) .
o C1 -1 o C2 -1 o V 2 (z) = C +C z V 1 (z) + C +C z V 2 (z). 1 2 1 2

(5) (6)

Finally, solving for capacitor circuit of this example as H (z) =

oo

o o V 2 (z)/V 1 (z)

gives the desired z-domain transfer function for the switched C1 z-1C +C
1

V 2 (z)
o V 1 (z)

z-1 C2 2 C2 = 1 + - z-1 , where = C1 . -1 1 - z C +C 1 2

(7)

Chapter 9 - Switched Capacitor Circuits (6/4/01)

P.E. Allen, 2001

Analog CMOS Circuit Deisgn

Page 9.1-16

DISCRETE-FREQUENCY DOMAIN ANALYSIS Relationship between the continuous and discrete frequency domains: z = e j T Illustration:
j Continuous time frequency response = =0 -1 Discrete time frequency response Imaginary Axis +j1 r=1 = = - = - Continuous Frequency Domain -j1 Discrete Frequency Domain =0 +1 Real Axis

Chapter 9 - Switched Capacitor Circuits (6/4/01) Analog CMOS Circuit Deisgn

P.E. Allen, 2001 Page 9.1-17

EXAMPLE 9.1-4 - Frequency Response of Example 9.1-3 Use the results of the previous example to find the magnitude and phase of the discrete time frequency response for the switched capacitor circuit of Fig. 9.1-7a. Solution The first step is to replace z in Eq. (9) of Ex. 9.1-3 by e jT. The result is given below as e-jT 1 1 = = (1) Hoo( ej) = 1+- e-jT (1+)ejT- (1+)cos(T)- + j(1+)sin(T) where we have used Eulers formula to replace e jT by cos(T)+jsin(T). The magnitude of Eq. (1) is found by taking the square root of the square of the real and imaginary components of the denominator to give 1 oo |H | = (1+)2cos2(T) - 2(1+)cos(T) + 2 + (1+)2sin2(T) 1 = (1+)2[cos2(T)+sin2(T)]+2-2(1+)cos(T) 1 1 = . (2) = 1+2+2 -2(1+)cos(T) 1+2(1+)(1-cos(T)) The phase shift of Eq. (1) is expressed as (1+)sin(T) sin(T) (3) Arg[ H oo] = - tan-1(1+)cos(T)- = - tan-1 cos(T) 1+

Chapter 9 - Switched Capacitor Circuits (6/4/01)

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Analog CMOS Circuit Deisgn

Page 9.1-18

THE OVERSAMPLING ASSUMPTION The oversampling assumption is simply to assume that fsignal << fclock = fc. This means that, 1 2 fsignal = f << T 2 f = << T T << 2. The importance of the oversampling assumption is that is permits the design of switched capacitor circuits that approximates the continuous time circuit until the signal frequency begins to approach the clock frequency.

Chapter 9 - Switched Capacitor Circuits (6/4/01) Analog CMOS Circuit Deisgn

P.E. Allen, 2001 Page 9.1-19

EXAMPLE 9.1-5 - Design of Switched Capacitor Circuit and Resulting Frequency Response Design the first-order, low pass, switched capacitor circuit of Ex. 9.1-3 to have a -3dB frequency at 1kHz. Assume that the clock frequency is 20kHz Plot the frequency response for the resulting discrete time circuit and compare with a first-order, low pass, continuous time filter. Solution If we assume that T is less than unity, then cos(T) approaches 1 and sin(T) approaches T. Substituting these approximations into the magnitude response of Eq. (2) of Ex. 9.1-4 results in 1 1 (1) Hoo(ejT) (1+) - + j(1+) = 1 + j(1+)T . Comparing this equation to the simple, first-order, low pass continuous time circuit results in the following relationship which permits the design of the circuit parameter . 1 = (1+)T (2) Solving for gives 1 f = T - 1 = fc1 - 1 = c - 1 = 2c - 1 . (3) -3dB -3dB Using the values given, we see that = (20/6.28)-1 =2.1831. Therefore, C2 = 2.1831C1.

Chapter 9 - Switched Capacitor Circuits (6/4/01)

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Analog CMOS Circuit Deisgn

Page 9.1-20

EXAMPLE 9.1-5 - Continued Frequency Response of the First-order, Switched Capacitor, Low Pass Circuit:
1 0.8 0.707 0.6 |H (e 0.4 0.2 = 1/ 0 0
1 oo j T

100

50 Arg[H oo(e j)] )| 0 = 1/

|H(j)|

-50

Arg[H(j)]

0.2

0.4

0.6 / c Magnitude

0.8

-100 0 0.2 0.6 / c Phase Shift (Degrees) 0.4 0.8 1

Better results would be obtained if fc > 20kHz.

Chapter 9 - Switched Capacitor Circuits (6/4/01) CMOS Analog Circuit Design

P.E. Allen, 2001 Page 9.2-1

9.2- SWITCHED CAPACITOR AMPLIFIERS

CONTINUOUS TIME AMPLIFIERS
R1 R2 vOUT vIN R1 Inverting Amplifier R2 vOUT

Gain and GB = : Gain , GB = : Vout Vin =

Noninverting Amplifier

Vout R1+R2 Vin = R1 Vout Vin =

Vout R2 Vin = - R1 -R2Avd(0) R1Avd(0) R1+R2 R1+R2 R 2 Avd(0)R1 = - R1 Avd(0)R1 1 + R1+R2 1 + R1+R2 GBR1 R1+R2 R 2 H GBR1 = - R1 s+ H s + R1+R2

Avd(0) R1 Avd(0) R1+R2 R1+R2 Avd(0)R1 = R1 Avd(0)R1 1 + R +R 1 + R1+R2 1 2 GBR1 R1+R2 R1+R2 H GBR1= R1 s+ H s + R1+R2

Gain , GB : Vout(s) R1+R2 Vin(s) = R1

Vout(s) R2 Vin(s) = - R1

Chapter 9 - Switched Capacitor Circuits (6/4/01)

+ P.E. Allen, 2001

vIN

CMOS Analog Circuit Design

Page 9.2-2

EXAMPLE 9.2-1- Accuracy Limitation of Voltage Amplifiers due to a Finite Voltage Gain Assume that the noninverting and inverting voltage amplifiers have been designed for a voltage gain of +10 and -10. If Avd(0) is 1000, find the actual voltage gains for each amplifier. Solution For the noninverting amplifier, the ratio of R2/R1 is 9. 1000 Avd(0)R1/(R1+R2) = 1+9 = 100. Vout 100 Vin = 10 101 = 9.901 rather than 10. For the inverting amplifier, the ratio of R2/R1 is 10. Avd(0)R1 1000 R1+R2 = 1+10 = 90.909 Vout 90.909 Vin = -(10)1+90.909 = - 9.891 rather than -10.

Chapter 9 - Switched Capacitor Circuits (6/4/01) CMOS Analog Circuit Design

P.E. Allen, 2001 Page 9.2-3

EXAMPLE 9.2-2 - -3dB Frequency of Voltage Amplifiers due to Finite Unity-Gainbandwidth Assume that the noninverting and inverting voltage amplifiers have been designed for a voltage gain of +1 and -1. If the unity-gainbandwidth, GB, of the op amps are 2Mrads/sec, find the upper 3dB frequency for each amplifier. Solution In both cases, the upper -3dB frequency is given by GBR1 H = R +R 1 2 For the noninverting amplifier with an ideal gain of +1, the value of R2/R1 is zero. H = GB = 2 Mrads/sec (1MHz) For the inverting amplifier with an ideal gain of -1, the value of R2/R1 is one. GB1 GB H = 1+1 = 2 = Mrads/sec (500kHz)

Chapter 9 - Switched Capacitor Circuits (6/4/01)

P.E. Allen, 2001

CMOS Analog Circuit Design

Page 9.2-4

CHARGE AMPLIFIERS
C1 C2 vOUT vIN C1 Inverting Charge Amplifier C2 vOUT

Gain and GB = :

Noninverting Charge Amplifier

Gain , GB = :

Vout C1+C2 Vin = C2 Avd(0)C2 Vout C1+C2 C1+C2 Avd(0)C2 Vin = C2 1 + C +C 1 2 GBC2 Vout C1+C2 C1+C2 GBC2 Vin = C2 s + C +C 1 2

C1 Vout Vin = - C2 Avd(0)C2 Vout C1 C1+C2 Avd(0)C2 Vin = -C2 1 + C +C 1 2 GBC2 Vout C1 C1+C2 GBC2 Vin = -C2 s + C +C 1 2

Gain , GB :

Chapter 9 - Switched Capacitor Circuits (6/4/01) CMOS Analog Circuit Design

SWITCHED CAPACITOR AMPLIFIERS Parallel Switched Capacitor Amplifier:

1 2 1

vin

C2 +

+ vC2 -

vout

vin

+ C1 -

vC1

C1

+ -

vC1

Inverting Switched Capacitor Amplifier

Modification to prevent open-loop operation

Analysis: Find the even-odd and the even-even z-domain transfer function for the above switched capacitor inverting amplifier.
1 1 2 2 2 t 1 3 1 n- 2 n-1 n- 2 n n+ 2 n+1 T Clock phasing for this example.

1: (n -1)T < t < (n -0.5)T

and vC1(n -1)T = vin (n -1)T vC2(n -1)T = 0
o o
o

Chapter 9 - Switched Capacitor Circuits (6/4/01)

+ P.E. Allen, 2001 Page 9.2-5 + vC2 + C2 vout P.E. Allen, 2001

vIN

CMOS Analog Circuit Design

Page 9.2-6

SWITCHED CAPACITOR AMPLIFIERS - Continued

2: (n -0.5)T < t < nT Equivalent circuit:

t=0 2

vC2 = 0 v e - + out (n-1/2)T + +

o vin (n-1)T

vC1 = 0 - + C1 -

vC2 = 0 e - + vout (n-1/2)T C2

C1

From the simplified equivalent circuit we write,

+ o vin (n-1)T -

+ Simplified equivalent circuit.

Equivalent circuit at the moment 2 closes.

e vout (n-1/2)T

C o = - C1 vin (n-1)T 2

Converting to the z-domain gives, e o C1 z -1/2 Vout(z) = -C z -1 Vin(z) 2 Multiplying by z-1/2 gives, e o C1 V out(z) = -C z -1/ 2 V in(z) 2 Solving for the even-odd transfer function, Hoe (z), gives, H oe (z) = V out(z) Vin(z)
o e

C = -C1 z -1/ 2
2

Chapter 9 - Switched Capacitor Circuits (6/4/01) CMOS Analog Circuit Design

P.E. Allen, 2001 Page 9.2-7

SWITCHED CAPACITOR AMPLIFIERS - Continued Solving for the even-even transfer function, Hee (z). o Assume that the applied input signal, vin (n-1)T, was uncharged during the previous 2 phase period(from t = (n-3/2)T to t = (n-1)T), then o e vin (n-1)T = vin (n-3/2)T which gives o e V in(z) = z -1/2 Vin(z) . Substituting this relationship into Hoe(z) gives e e C1 V out(z) = -C z -1 Vin(z) 2 or H (z) =
ee

V out(z)
e Vin(z)

C = -C1 z -1
2

Chapter 9 - Switched Capacitor Circuits (6/4/01)

P.E. Allen, 2001

CMOS Analog Circuit Design

Page 9.2-8

FREQUENCY RESPONSE OF SWITCHED CAPACITOR AMPLIFIERS Replace z by e jT. H and Hee (e jT) = V out( e jT)
e Vin( e oe

(e jT)

V out( e jT)
o Vin(

e j T )

C = -C1 e -jT/2
2

e j T )

C = -C1 e -jT
2

If C1/C2 is equal to R2/R1, then the magnitude response is identical to inverting unity gain amplifier. However, the phase shift of Hoe(e jT) is Arg[Hoe(e jT)] = 180 - T/2 and the phase shift of Hoe(e jT) is Arg[Hee(e jT)] = 180 - T. Comments: The phase shift of the switched capacitor inverting amplifier has an excess linear phase delay. When the frequency is equal to 0.5fc, this delay is 90. One must be careful when using switched capacitor circuits in a feedback loop because of the excess phase delay.

Chapter 9 - Switched Capacitor Circuits (6/4/01) CMOS Analog Circuit Design

P.E. Allen, 2001 Page 9.2-9

POSITIVE AND NEGATIVE TRANSRESISTANCE EQUIVALENT CIRCUITS Transresistance circuits are two-port networks where the voltage across one port controls the current flowing between the ports. Typically, one of the ports is at zero potential (virtual ground). Circuits:
i1(t) v1(t)
2

vC(t) C
1 1

i2(t) v1(t)

i1(t)

vC(t) C
2 1

i2(t)

CP

CP

CP

CP

Positive Transresistance Realization.

Negative Transresistance Realization.

Analysis (Negative transresistance realization): v1(t) v1 RT = i (t) = i (average) 2 2 If we assumev1(t) is approximately constant over one period of the clock, then we can 1 q (T) - q2(T/2) CvC(T) - CvC(T/2) -Cv1 i2(average) = T i2(t)dt = 2 = = T T T
T/2 T

write

Substituting this expression into the one above shows that RT = -T/C Similarly, it can be shown that the positive transresistance is T/C. Comments: These results are only valid when fc >> f. These circuits are insensitive to the parasitic capacitances shown as dotted capacitors.

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CMOS Analog Circuit Design

Page 9.2-10

NONINVERTING STRAY INSENSITIVE SWITCHED CAPACITOR AMPLIFIER Analysis: 1 1 2 2 2 t 1 3 1 n- 2 n-1 n- 2 n n+ 2 n+1 T 1: (n -1)T < t < (n -0.5)T
Clock phasing for this example.

The voltages across each capacitor can be written as o o vC1(n -1)T = vin(n -1)T and o o vC2(n -1)T = vout(n -1)T = 0 . 2: (n -0.5)T < t < nT The voltage across C2 is e C1 o vout(n -1/2)T = C vin(n -1)T 2
o e C1 V out(z) = C z -1/2 Vin(z)
2

vin

vC1(t) C1
1

vC2

+ C2

vout

Noninverting Switched Capacitor Voltage Amplifier.

C1 Hoe(z) = C z-1/2 2

If the applied input signal, vin(n -1)T, was unchanged during the previous 2 phase period above becomes C1 e e C1 V out(z) = C z-1 Vin(z) Hee(z) = C z-1 2 2 Comments: Excess phase of H oe(e jT) is -T/2 and for H ee(e jT) is -T

Chapter 9 - Switched Capacitor Circuits (6/4/01) CMOS Analog Circuit Design

P.E. Allen, 2001 Page 9.2-11

INVERTING STRAY INSENSITIVE SWITCHED CAPACITOR AMPLIFIER Analysis: 1: (n -1)T < t < (n -0.5)T 1 The voltages across each capacitor can be written as vC2 vC1(t) o vin 2 2 - + vC1(n -1)T = 0 and C2 C1 o o 1 1 vC2(n -1)T = vout(n -1)T = 0 .

vout

2: (n -0.5)T < t < nT The voltage across C2 is e C1 e vout(n -1/2)T = - C vin(n -1/2)T 2
e C1 o V out(z) = - C V in(z)
2

vC1(t)

Inverting Switched Capacitor Voltage Amplifier.

C1 Hoe(z) = - C 2

Comments: The inverting switched capacitor amplifier has no excess phase delay. There is no transfer of charge during 1.

Chapter 9 - Switched Capacitor Circuits (6/4/01)

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CMOS Analog Circuit Design

Page 9.2-12

EXAMPLE 9.2-3 - DESIGN OF A SWITCHED CAPACITOR SUMMING AMPLIFIER Design a switched capacitor summing amplifier using the circuits in stray insensitive transresistance circuits which gives the output voltage during the 2 phase period that is equal to 10v1 5v2, where v1 and v2 are held constant during a 2-1 period and then resampled for the next period. Solution 10C 2 1 1 A possible solution is shown. Considering v1 C each of the inputs separately, we can write that vo
2

vo1(n-1/2)T = 10v1(n-1)T (1) and vo2(n-1/2)T = -5v2(n-1/2)T . Because v1(n-1)T = v1(n-3/2)T, Eq. (1) can be rewritten as vo1(n-1/2)T = 10v1(n-3/2)T . Combining Eqs. (2) and (3) gives
e e o e e e

v2

2 1

5C
1

(2)

(3)
e e e

vo(n-1/2)T = vo1(n-1/2)T + vo2(n-1/2)T = 10v1(n-3/2)T - 5v2(n-1/2)T . or V o(z) = 10z-1V1(z) - 5V2(z) . Eqs. (4) and (5) verifies that proposed solution satisfies the specifications of the example.
e e e

(4)

(5)

Chapter 9 - Switched Capacitor Circuits (6/4/01) CMOS Analog Circuit Design

P.E. Allen, 2001 Page 9.2-13

NONIDEALITIES OF SWITCHED CAPACITOR CIRCUITS - CAPACITORS See Chapter 2

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P.E. Allen, 2001

CMOS Analog Circuit Design

Page 9.2-14

NONIDEAL OP AMPS - FINITE GAIN Finite Amplifier Gain Consider the noninverting switched capacitor amplifier during 2:
C1 o vin (n-1)T e vout (n-1/2)T Avd(0) +

C2 +

e vout (n-1/2)T

Op amp with finite value of Avd(0)

Fig. 9.2-11

The output during 2 can be written as,

e vout(n

C o C +C vout(n -1/2)T -1/2)T = C1 vin(n -1)T + 1 2 2 C2 Avd(0)

Converting this to the z-domain and solving for the Hoe(z) transfer function gives e Vout(z) C1 -1/2 1 oe H (z) = o = C z C1 + C2 . 2 1 V in(z) Avd(0)C2 Comments: The phase response is unaffected by the finite gain A gain of 1000 gives a magnitude of 0.998 rather than 1.0.

Chapter 9 - Switched Capacitor Circuits (6/4/01) CMOS Analog Circuit Design

P.E. Allen, 2001 Page 9.2-15

NONIDEAL OP AMPS - FINITE BANDWIDTH AND SLEW RATE Finite GB: In general the analysis is complicated. (We will provide more detail for integrators.) The clock period, T, should be equal to or less that 10/GB. The settling time of the op amp must be less that T/2. Slew Rate: The slew rate of the op amp should be large enough so that the op amp can make a full swing within T/2.

Chapter 9 - Switched Capacitor Circuits (6/4/01)

P.E. Allen, 2001

CMOS Analog Circuit Design

Page 9.3-1

9.3 - SWITCHED CAPACITOR INTEGRATORS

CONTINUOUS TIME INTEGRATORS
+ (a.) Vin R1 C2 R I I I 100 10 10I 100I 0 log10 (a.) Eq. (3) x2 = GB log10 Eq. (2) + Inverter Arg[Vout(j)/Vin(j)] 90 I log10 (b.) Arg[Vout(j)/Vin(j)] I 180 10Avd(0) 10I 135 Avd(0) 90 45 0 I Avd(0) R Vout Vin R1 C2 Vout

(a.) Noninverting and (b.) inverting continuous time integrators. Ideal Performance: Noninverting1 I -j I Vout(j) Vin(j) = j R 1C2 = j = Frequency Response:
|Vout(j)/Vin(j)| 40 dB 20 dB 0 dB -20 dB -40 dB

InvertingVout(j) -1 - I j I Vin(j) = j R 1C2 = j =

Chapter 9 - Switched Capacitor Circuits (6/4/01) CMOS Analog Circuit Design

CONTINUOUS TIME INTEGRATORS - NONIDEAL PERFORMANCE Finite Gain: Avd(s) (s/ ) Avd(s) sR1C2 (s/ ) + 1 Vout 1 sR1C2 + 1 I Vin = -sR1C2 Avd(s) sR1C2 = - s Avd(s) (s/ ) 1 + sR1C2+1 1 + (s/ ) + 1 Avd(0) GB GB where Avd(s) = s+ a = s+ s a a Vout V - Avd(0) Case 1: s 0 Avd(s) = Avd(0) in GB V out GB V - s s I Case 2: s Avd(s) = s in V out I V - s Case 3: 0 < s < Avd(s) = in
|Vout(j)/Vin(j)| Avd(0) dB Eq. (1) 0 dB

I x1 = I Avd(0)

GB 10 10GB

GB

Chapter 9 - Switched Capacitor Circuits (6/4/01)

+ (b.) P.E. Allen, 2001 Page 9.3-2

(1) (2) (3)

log10

P.E. Allen, 2001

CMOS Analog Circuit Design

Page 9.3-3

EXAMPLE 9.3-1 - Frequency Range over which the Continuous Time Integrator is Ideal Find the range of frequencies over which the continuous time integrator approximates ideal behavior if Avd(0) and GB of the op amp are 1000 and 1MHz, respectively. Assume that I is 2000 radians/sec. Solution The idealness of an integrator is determined by how close the phase shift is to 90 (+90 for an inverting integrator and -90 for a noninverting integrator). The actual phase shift in the asymptotic plot of the integrator is approximately 6 above 90 at the frequency 10I/Avd(0) and approximately 6 below 90 at GB /10. Assume for this example that a 6 tolerance is satisfactory. The frequency range can be found by evaluating 10I/Avd(0) and GB/10. Therefore the range over which the integrator approximates ideal behavior is from 10Hz to 100kHz. This range will decrease as the phase tolerance is decreased.

Chapter 9 - Switched Capacitor Circuits (6/4/01) CMOS Analog Circuit Design

P.E. Allen, 2001 Page 9.3-4

NONINVERTING SWITCHED CAPACITOR INTEGRATOR Analysis: 1: (n -1)T < t < (n -0.5)T v (t) The voltage across each capacitor is o o vc1(n-1)T = vin(n-1)T and vc2(n-1)T = vout(n-1)T .
o o

vin

S1
2

C1

+ + -

vC2

C1 S2

S4
1

+ C2

vout

S3

2: (n -0.5)T < t < n T

Equivalent circuit:
o vC2 = vout (n-1)T e vout (n-1/2)T - + C2 - o2 vin (n-1)T + t=0 2

Noninverting, stray insensitive integrator.

vC1 = 0 + o vin(n-1)T

C1

C1

o vout (n-1)T C e 2 vout (n-1/2)T + - + vC2 = 0

Equivalent circuit at the moment the 2 switches close.

We can write that,

e vout(n

Chapter 9 - Switched Capacitor Circuits (6/4/01)

t=0

Simplified equivalent circuit.

C o o -1/2)T = C1 vin(n -1)T + vout(n -1)T 2

P.E. Allen, 2001

CMOS Analog Circuit Design

Page 9.3-5

NONINVERTING SWITCHED CAPACITOR INTEGRATOR - Continued

1: nT < t < (n + 0.5)T

If we advance one more phase period, i.e. t = (n)T to t = (n-1/2)T, we see that the voltage at the output is unchanged. Thus, we may write vout(n)T = vout(n-1/2)T . Substituting this relationship into the previous gives the desired time relationship expressed as o o C1 o vout(n)T = C vin(n -1)T + vout(n -1)T . 2 Transferring this equation to the z-domain gives, Vout(z) C z-1 C C 1 o o o V out(z) = C1 z-1Vin(z) + z-1Vout(z) Hoo(z) = o = C1 1-z-1 = C1 z-1 2 2 V (z) 2
in o o e

Replacing z by ej gives, H (e
oo
j

)=

Vout( e j )
o Vin(

1 e-j/2 C1 C1 = C e j -1 = C e j/2 - e-j/2 2 ej ) 2

Replacing ej/2 - e-j/2 by its equivalent trigonometric identity, the above becomes Hoo(e j ) = V out(e j )
in

e-j/2 C T C1 = C1 j2 sin(T/2) T = jTC o 2 j 2 V (e )

T/2 -j/2 e ) sin(T/2) (

I C1 Hoo(ejT) = (Ideal)x(Magnitude error)x(Phase error) where I = TC Ideal = j

2

Chapter 9 - Switched Capacitor Circuits (6/4/01) CMOS Analog Circuit Design

P.E. Allen, 2001 Page 9.3-6

EXAMPLE 9.3-2 - Comparison of a Continuous Time and Switched Capacitor Integrator Assume that I is equal to 0.1c and plot the magnitude and phase response of the noninverting continuous time and switched capacitor integrator from 0 to I. Solution Letting I be 0.1c gives 1 1 / c H(j) = 10j / and Hoo(e j ) = 10j / sin(/ ) ( e-j / c) c c c Plots:
5 Magnitude 4 3 |H (e 2 1 0 0 0.2 0.4 / c 0.6 0.8 1 I |H(j)|
oo j T

0 -50 -100 )| -150 -200 -250 -300 0 I Arg[H (e

oo j T

Phase Shift (Degrees)

Arg[H(j )]

)]

0.2

0.4

0.6 / c

0.8

Chapter 9 - Switched Capacitor Circuits (6/4/01)

P.E. Allen, 2001

CMOS Analog Circuit Design

Page 9.3-7

INVERTING SWITCHED CAPACITOR INTEGRATOR Analysis: 1: (n -1)T < t < (n -0.5)T vin The voltage across each capacitor is o vc1(n -1)T = 0 and 3 o o e vc2(n -1)T = vout(n -1)T = vout(n -2)T.

vC1(t) C1 S2

S1
1

vC2

S4
1

+ C2

vout

S3

Inverting, stray insensitive integrator.

2: (n -0.5)T < t < n T

Equivalent circuit:
t=0

C1 -

t=0

e vin (n-1/2)T

Equivalent circuit at the moment the 2 switches close.

Simplified equivalent circuit.

Now we can write that,

e e C1 e vout(n-1/2)T = vout(n-3/2)T - C vin(n-1/2)T . (22)
2

Chapter 9 - Switched Capacitor Circuits (6/4/01) CMOS Analog Circuit Design

INVERTING SWITCHED CAPACITOR INTEGRATOR - Continued Expressing the previous equation in terms of the z-domain equivalent gives, e Vout(z) C 1 C z e e C1 e -1 ee V out(z) = z Vout(z) - C V in(z) H (z) = e = - C1 1-z-1 = - C1 z-1 2 2 2 Vin(z) To get the frequency response, we replace z by ej giving, e Vout( e j ) e j/2 C e j C Hee(e j ) = e j = - C1 e j -1 = - C1 e j/2 - e-j/2 2 2 V (e )
in

Replacing ej/2 - e-j/2 by 2j sin(T/2) and simplifying gives, H (e

ee
j

e Same as noninverting integrator except for phase error.

)=

V out(e j )
e Vin(
j

C1 T/2 = - jTC sin(T/2) ( e j/2) 2 )

Consequently, the magnitude response is identical but the phase response is given as Arg[Hee(e j )] = 2 + 2 . Comments: Note that the phase error is positive for the inverting integrator and negative for the noninverting integrator. The cascade of an inverting and noninverting switched capacitor integrator has no phase error.

Chapter 9 - Switched Capacitor Circuits (6/4/01)

2 v =0 2 C1 e vin(n-1/2)T

vC2 = e vout (n-3/2)T e - + vout (n-1/2)T C2

e vC1 = 0 vout (n-3/2)T C2 e vout (n-1/2)T + - + - + vC2 = 0 C1 +

P.E. Allen, 2001 Page 9.3-8

P.E. Allen, 2001

CMOS Analog Circuit Design

Page 9.3-9

A SIGN MULTIPLEXER A circuit that changes the 1 and 2 of the leftmost switches of the stray insensitive, switched capacitor integrator.
1 2 x

To switch connected to the input signal (S1). VC

x 2 1 y 1 2

VC

0 1
y

To the left most switch connected to ground (S2).

Fig. 9.3-8

This circuit steers the 1 and 2 clocks to the input switch (S1) and the leftmost switch connected to ground (S2) as a function of whether Vc is high or low.

Chapter 9 - Switched Capacitor Circuits (6/4/01) CMOS Analog Circuit Design

P.E. Allen, 2001 Page 9.3-10

SWITCHED CAPACITOR INTEGRATORS - FINITE OP AMP GAIN Consider the following circuit which is vo o vout (n-1)T - out (n-1)T equivalent of the noninverting integrator at the Avd(0) vC1 = 0 e beginning of the 2 phase period. C2 vout (n-1/2)T + - + The expression for vout (n-1/2)T can be written as
e o vin (n-1)T

vout(n-1)T vout(n-1/2)T C +C C o e o vout(n-1/2)T = C1 vin(n-1)T + vout(n-1)T - A (0) + A (0) 1 2 2 C2 vd vd Substituting vout(n)T = vout(n -0.5)T into this equation gives vout(n-1)T vout(n)T C1+C2 o o C1 o vout(n)T = C vin(n-1)T + vout(n-1)T - A (0) + A (0) C 2 vd vd 2 Using the previous procedures to solve for the z-domain transfer function results in, C1 -1 o Vout(z) C2 z Hoo(z) = o = -1 1 z-1 z-1 Vin(z) 1 - z-1 + z - C1 Avd(0) Avd(0)C2 z-1 + Avd(0) z-1 or o 1 Vout(z) (C1/C2) z-1 HI(z) oo H (z) = o = 1 - z-1 = 1 C1 C1 1 Vin(z) 1 -1 Avd(0) Avd(0)C2(1-z-1) 1 - Avd(0) - Avd(0)C2(1-z )
o o

Chapter 9 - Switched Capacitor Circuits (6/4/01)

e C1 vout (n-1/2)T Avd(0) + -

- + vC2 = 0

Fig. 9.3-10

P.E. Allen, 2001

CMOS Analog Circuit Design

Page 9.3-11

FINITE OP AMP GAIN - Continued Substitute the z-domain variable, z, with ejwT to get Hoo(e jT) = HI(e jT) 1 C1 C1/C2 1 - A (0) 1 + 2C - j vd 2 T 2Avd(0) tan 2 (1)

where now HI(e jT) is the integrator transfer function for Avd(0) = . The error of an integrator can be expressed as HI(j) H(j) = [1-m()] e-j() where m() = the magnitude error due to Avd(0)

() = the phase error due to Avd(0)

If () is much less than unity, then this expression can be approximated by HI(j) (2) H(j) 1 - m() - j() Comparing Eq. (1) with Eq. (2) gives the magnitude and phase error due to a finite value of Avd(0) as 1 C1/C2 C1 and (j) = m(j) = - A (0) 1 + 2C vd 2 T 2Avd(0) tan 2

Chapter 9 - Switched Capacitor Circuits (6/4/01) CMOS Analog Circuit Design

P.E. Allen, 2001 Page 9.3-12

EXAMPLE 9.3-3 - Evaluation of the Integrator Errors due to a finite value of Avd(0) Assume that the clock frequency and integrator frequency of a switch capacitor integrator is 100kHz and 10kHz, respectively. If the value of Avd(0) is 100, find the value of m(j) and (j) at 10kHz. Solution The ratio of C1 to C2 is found as 210,000 C1 C2 = IT = 100,000 = 0.6283 . Substituting this value along with that for Avd(0) into m(j) and (j) gives 0.6283 m(j) = - 1 + 2 = -0.0131 and 0.6283 (j) = 2100tan(18) = 0.554 . The ideal switched capacitor transfer function, HI(j), will be multiplied by a value of approximately 1/1.0131 = 0.987 and will have an additional phase lag of approximately 0.554. In general, the phase shift error is more serious than the magnitude error.

Chapter 9 - Switched Capacitor Circuits (6/4/01)

P.E. Allen, 2001

CMOS Analog Circuit Design

Page 9.3-13

SWITCHED CAPACITOR INTEGRATORS - FINITE OP AMP GB The precise analysis of the influence of GB can be found elsewhere . The results of such an analysis can be summarized in the following table. Noninverting Integrator C2 m() -e-k C +C 1 2 ( ) 0
1

Inverting Integrator C2 m() -e-k 1 - C +C cos(T) 1 2 -k C2 () -e C +C cos(T) 1 2 C2 GB k1 C +C f 1 2 c

1 1

If T is much less than unity, the expressions in table reduce to f m() -2 f e-(GB/f ) c
c

K. Martin and A.S. Sedra, Effects of the Op Amp Finite Gain and Bandwidth on the Performance of Switched-Capacitor Filters, IEEE Trans. on Circuits and Systems, vol. CAS-28, no. 8, August 1981, pp. 822-829.

Chapter 9 - Switched Capacitor Circuits (6/4/01) CMOS Analog Circuit Design

P.E. Allen, 2001 Page 9.3-14

SWITCHED CAPACITOR CIRCUITS - kT/C NOISE Switched capacitors generate an inherent thermal noise given by kT/C. This noise is verified as follows. An equivalent circuit for a switched capacitor:
Ron + vin C

+ vout

+ vin

+ vout

(a.) (b.) Figure 9.3-11 - (a.) Simple switched capacitor circuit. (b.) Approximation of (a.).

The noise voltage spectral density of Fig. 9.3-11b is given as 2kTRon 2 Volt2/Rad./sec. eRon = 4kTRon Volts2/Hz = The rms noise voltage is found by integrating this spectral density from 0 to to give
2 vRon

(1)

2kTRon 12d 2kTRon 1 kT = 2 2 = 2 = C Volts(rms)2 1 +

0

(2)

where 1 = 1/(RonC). Note that the switch has an effective noise bandwidth of 1 fsw = 4R C Hz on which is found by dividing Eq. (2) by Eq. (1). (3)

Chapter 9 - Switched Capacitor Circuits (6/4/01)

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CMOS Analog Circuit Design

Page 9.4-1

9.4 Z-DOMAIN MODELS OF TWO-PHASE, SWITCHED CAPACITOR CIRCUITS

Objective: Allow easy analysis of complex switched capacitor circuits Develop methods suitable for simulation by computer Will constrain our focus to two-phase, nonoverlapping clocks General Two-Port Characterization of Switched Capacitor Circuits:

Dependent Switched Independent Unswitched Voltage Capacitor Voltage Capacitor Source Circuit Source Figure 9.4-1 - Two-port characterization of a general switched capacitor circuit.

Approach: Four port - allows both phases to be examined Two-port - simplifies the models but not as general

Chapter 9 - Switched Capacitor Circuits (6/4/01) CMOS Analog Circuit Design

INDEPENDENT VOLTAGE SOURCES

v*(t) v(t) Ve(z)

Phase Dependent Voltage Source

Vo(z)
1 2 1 2 1 2 1 2 1 2

0 1/2 1 3/2 2 5/2 3 7/2 4 9/2 5 v (t)

O

t/T

v(t)

Phase Independent Voltage Source for the Odd Phase

1 2 1 2 1 2 1 2 1 2

0 1/2 1 3/2 2 5/2 3 7/2 4 9/2 5 v (t)

e

t/T

v(t)

Phase Independent Voltage Source for the Even Phase

2 1 2 1 2 1 2 1 2 1

0 1/2 1 3/2 2 5/2 3 7/2 4 9/2 5

t/T

Chapter 9 - Switched Capacitor Circuits (6/4/01)

vin(t)

vout(t)

P.E. Allen, 2001 Page 9.4-2

z-1/2Vo(z)

Vo(z)

Ve(z)

z-1/2Ve(z)

P.E. Allen, 2001

CMOS Analog Circuit Design

Page 9.4-3

SWITCHED CAPACITOR FOUR-PORT CIRCUITS AND Z-DOMAIN MODELS

Switched Capacitor, Two-Port Circuit Four-Port, z-domain Equivalent Model Simplified, Two-Port z-domain Model -Cz-1/2 1 + v1(t) 2 C + v2(t) + o V1 e V1 + + o V1 e V1 + + o V1 -e V1 + + o V1 -e V1 + + o V2 e V2 + + o V2 e V2 + + o V2 -e V2 + + o V2 -e V2 + + o V1 Cz-1/2 + e V2 C

Cz-1/2

-Cz-1/2

Parallel Switched Capacitor 1 + v1(t) 2 C 2 1 + v2(t) -

(Circuit connected between defined voltages)

+ o V1 -Cz-1/2 + e V2 -

Cz-1/2

-Cz-1/2

Cz-1/2

Negative SC Transresistance + 2 v1(t) 1 C 2 + 1 v2(t) -

(Circuit connected between defined voltages)

C + + e e V1 V2 (Circuit connected between defined voltages) C(1-z-1) + + e e V1 V2 (Circuit connected between defined voltages) Fig. 9.4-3

Positive SC Transresistance C + v1(t) 2 + v2(t) -

Capacitor and Series Switch

C(1-z-1)

K.R. Laker, Equivalent Circuits for Analysis and Synthesis of Switched Capacitor Networks, Bell System Technical Journal, vol. 58, no. 3, March 1979, pp. 729-769.

Chapter 9 - Switched Capacitor Circuits (6/4/01) CMOS Analog Circuit Design

P.E. Allen, 2001 Page 9.4-4

Z-DOMAIN MODELS FOR CIRCUITS THAT MUST BE FOUR-PORT

Switched Capacitor Circuit C + + v2(t) v1(t) Unswitched Capacitor C + + v2(t) v1(t) 1 Capacitor and Shunt Switch + o V1 -e V1 + + o V1 V1 +
e

Four-port z-domain Model C -Cz-1/2 -Cz-1/2 Cz-1/2 Cz-1/2 + o V2 e V2 +

Simplified Four-port z-domain Model + o V1 e V1 + + o V1 -e V1 + C -Cz-1/2 -Cz-1/2 C C + o V2 e V2 +

C C

+ o V2 -e V2 +

+ o V2 -e V2 +
Fig. 9.4-4

Chapter 9 - Switched Capacitor Circuits (6/4/01)

P.E. Allen, 2001

CMOS Analog Circuit Design

Page 9.4-5

Z-DOMAIN MODEL FOR THE IDEAL OP AMP

+ + vi(t) + vo(t) = Avvi(t) Vio(z) Vie(z) + +
e o

+ Voo(z) = AvVio(z) Voe(z) = AvVie(z) +

Figure 9.4-5

Time domain op amp model.

z-domain op amp model

Chapter 9 - Switched Capacitor Circuits (6/4/01) CMOS Analog Circuit Design

P.E. Allen, 2001 Page 9.4-6

EXAMPLE 9.4-1- Illustration of the Validity of the z-domain Models Show that the z-domain four-port model for the negative switched capacitor transresistance circuit of Fig. 9.4-3 is equivalent to the two-port switched capacitor circuit. Solution + + For the two-port switched capacitor circuit, we observe that o o V1 V2 during the 1 phase, the capacitor C is charged to v1(t). Let us assume that the time reference for this phase is t - T/2 so that the e e capacitor voltage is V2 V1 + + vC = v1(t - T/2).
Cz-1/2 C -Cz-1/2 Cz-1/2

During the next phase, 2, the capacitor is inverted and v2 can be expressed as v2(t) = -vC = -v1(t - T/2).
e

Negative SC Transresistance Model

Next, let us sum the currents flowing away from the positive V 2 node of the four-port z-domain model in Fig. 9.4-3. This equation is, -Cz-1/2(V 2 - V 1 ) + Cz-1/2V 2 + CV 2 = 0. This equation can be simplified as V 2 = -z-1/2V 1
e o e e

which when translated to the time domain gives v2(t) = -vC = -v1(t - T/2). Thus, we have shown that the four-port z-domain model is equivalent to the time domain circuit for the above consideration.

Chapter 9 - Switched Capacitor Circuits (6/4/01)

P.E. Allen, 2001

CMOS Analog Circuit Design

Page 9.4-7

Z-DOMAIN, HAND-ANALYSIS OF SWITCHED CAPACITOR CIRCUITS General, time-variant, switched capacitor circuit.
v1
v1 v2 o e

1 2

2 1

v3

2 1

2 1

v4 -

vo

1 2

2 1 + e

2 1

2 1
e

V1(z) V2(z)

V3(z)

V4(z)

+ Vo(z)
Fig9.4-6b

Simplification of the above circuit to a two-port, timeinvariant model.

V1(z)
o

V2(z) 1 2 2 + 1

V3(z) 2 1

V4(z) 2 + 1 Vo(z)
e

Chapter 9 - Switched Capacitor Circuits (6/4/01) CMOS Analog Circuit Design

P.E. Allen, 2001 Page 9.4-8

EXAMPLE 9.4-2 - z-domain Analysis of the Noninverting Switched Capacitor Integrator Find the z-domain transfer function V o (z)/V i (z) and
o o V o (z)/V i (z) e o

vi(t)

-C1z-1/2
o

(a.) C2(1-z-1) V e(z) o -

Vi(z)

z-1/2Vo(z)

-C1z-1/2V i (z) + C2(1-z-1)Vo (z) = 0 Hoe(z) = V o (z) V i (z)

o e

(b.) Figure 9.4-8 - (a.) Modified equivalent circuit of Fig. 9.3-4a. (b.) Two-port, z-domain model for Fig. 9.4-8a.

C1z-1/2 . C2(1-z-1)
o e

Hoo(z) is found by using the relationship that V o (z) = z-1/2V o (z) to get
-1 o V i (z) C2(1-z ) which is equal to z-domain transfer function of the noninverting switched capacitor integrator.

Hoo(z)

V o (z)

C1z-1

Chapter 9 - Switched Capacitor Circuits (6/4/01)

P.E. Allen, 2001

of the noninverting switched capacitor integrator using the above methods. Solution First redraw Fig. 9.3-4a as shown in Fig. 9.4-8a. We have added an additional 2 switch to help in using Fig. 9.4-3. Because this circuit is time-invariant, we may use the two-port modeling approach of Fig. 9.4-7. Note that C2 and the indicated 2 switch are modeled by the bottom row, right column of Fig 9.4-3. The resulting z-domain model for Fig. 9.4-8a is shown in Fig. 9.4-8b. Recalling that the z-domain models are of admittance form, it is easy to write

1 2

C1 2 1 2

C2

Four-port, model of the o above circuit. V1(z)

V2(z)

V3(z)

V4(z)

+
Fig. 9.6-4a

Vo(z)
o

+ -

Vo(z)

Fig. 9.4-7

vo

CMOS Analog Circuit Design

Page 9.4-9

EXAMPLE 9.4-3 - z-domain Analysis of the Inverting Switched Capacitor Integrator Find the z-domain transfer function V o (z)/V i (z) and V o (z)/V i (z) of Fig. 9.3-4a using the above methods. Solution Fig. 9.4-9a shows the modified equivalent circuit of Fig. 9.3-4b. The two-port, z-domain model for Fig. 9.4-9a is shown in Fig. 9.4-9b. Summing the currents flowing to the inverting node of the op amp gives C1V i (z) + C2(1-z-1)Vo (z) = 0 which can be rearranged to give Hee(z) = V o (z)
e V i (z) e e e o e e e

2 vi(t) 1

C1 2 1 2

C2 z-1/2Vo(z)
e

vo

C1
e

(a.) C2(1-z-1) V e(z) o -

Vi(z)

-C1 C2(1-z-1)

which is equal to inverting, switched capacitor integrator z-domain transfer function.

o

(b.) Figure 9.4-9 - (a.) Modified equivalent circuit of inverting SC integrator. (b.) Two-port, z-domain model for Fig. 9.4-9a
e

Heo(z) is found by using the relationship that V o (z) = z-1/2V o (z) to get Heo(z) = V o (z) V i (z)
e o

C1z-1/2 C2(1-z-1)

Chapter 9 - Switched Capacitor Circuits (6/4/01) CMOS Analog Circuit Design

P.E. Allen, 2001 Page 9.4-10

EXAMPLE 9.4-4 - z-domain Analysis a Time-Variant Switched Capacitor Circuit Find V o (z) and V o (z) as function of V 1 (z) and for the summing, switched capacitor integrator of v1(t) Fig. 9.4-10a. Solution This circuit is time-variant because C3 is charged from a different circuit for each phase. Therefore, we must use a four-port model. The resulting z-domain model for Fig. 9.4-10a is shown in Fig. 9.4-10b. v2(t)
o V 2 (z) o e o

1 2

C1 2 + 1

1 2

C1 1 2

Fig. 9.4-10a - Summing Integrator.

Chapter 9 - Switched Capacitor Circuits (6/4/01)

P.E. Allen, 2001

+ Vo(z)
o

C3

vo

CMOS Analog Circuit Design

Page 9.4-11

EXAMPLE 9.4-4 - Continued Summing the currents flowing away from the V i (z) node gives
o C2V 2 (z) o

-C3z-1/2 -C1z-1/2 Vi(z) C3 o

+
o

o C3V o (z)

e C3z-1/2V o (z)

Vo(z)

=0
e

(1)
e V i (z)

-C1z-1/2V 1 (z) - C3z-1/2V o (z) + C3V o (z) = 0 Multiplying (2) by z-1/2 and adding it to (1) gives C2V 2 (z) + C3V o (z) - C1z-1V 1 (z) - C3z-1V o (z) = 0
o Solving for V o (z) gives, o C1z-1V 1 (z) o V o (z) = C3(1-z-1) o o o o

(2)
V2(z)
o

(3)

C2
e Vi(z)

C2V 2 (z) C3(1-z-1)

-C3z-1/2 Fig. 9.4-10b - Four-port, z-domain model for Fig. 9.4-10a.

Multiplying Eq. (1) by z-1/2 and adding it to Eq. (2) gives C2z-1/2V 2 (z) - C1z-1V 1 (z) - C3z-1V o (z) + C3V o (z) = 0 Solving for V o (z) gives,
e V o (z) e o o e e

C1z-1/2V 1 (z) C2z-1/2V 2 (z) = . C3(1-z-1) C3(1-z-1)

Chapter 9 - Switched Capacitor Circuits (6/4/01) CMOS Analog Circuit Design

P.E. Allen, 2001 Page 9.4-12

FREQUENCY DOMAIN SIMULATION OF SWITCHED CAPACITOR CIRCUITS USING SPICE Storistors A storistor is a two-terminal element that has a current flow that occurs at some time after the voltage is applied across the storistor. I(z) I(z) z-domain: I(z) = Cz-1/2 [V1(z) - V2(z)] Time-domain:
T T i(t) = Cv1t - 2 - v2t - 2 V1(z) Cz-1/2 V2(z)
Fig. 9.4-11a

i(t) + v1(t) -

Cv3(t)

Delay of T/2
Rin =

SPICE Primitives:
1 3 V1-V2 CV4 LosslessTransmission Line TD = T/2, Z0 = R
Fig. 9.4-11c

T +2

2 4 R

B.D. Nelin, Analysis of Switched-Capacitor Networks Using General-Purpose Circuit Simulation Programs, IEEE Trans. on Circuits and Systems, pp. 43-48, vol. CAS-30, No. 1, Jan. 1983.

Chapter 9 - Switched Capacitor Circuits (6/4/01)

P.E. Allen, 2001

+ + C3
e Vo(z)

Summing the currents flowing away from the

nodes gives

V1(z)

i(t) + v2(t) +v3(t) -

Fig. 9.4-11b

CMOS Analog Circuit Design

Page 9.4-13

EXAMPLE 9.4-5 - SPICE Simulation of Example 9.4-2 Use SPICE to obtain a frequency domain simulation of the noninverting, switched capacitor integrator. Assume that the clock frequency is 100kHz and design the ratio of C1 and C2 to give an integration frequency of 10kHz. Solution The design of C1/C2 is accomplished from the ideal integrator transfer function. 2fI C1 C2 = IT = fc = 0.6283 AssumeC2 = 1F C1 = 0.6283F. Next we replace the switched capacitor C1 and the unswitched capacitor of integrator by the z-domain model of the second row of Fig. 9.4-3 and the first row of Fig. 9.4-4 to obtain Fig. 9.4-12. Note that in addition we used Fig. 9.4-5 for the op amp and assumed that the op amp had a differential voltage gain of 106. Also, the unswitched Cs are conductances.
C1z-1/2

-C1z-1/2

-C2z-1/2

-C2z-1/2

C2z-1/2

C1z-1/2

-e Vi +
2

C1

C2

C2z-1/2

+o Vi -

C2

C1

106V3

106V4

+ o Vo 0 -e Vo +
6

Figure 9.4-12 - z-domain model for noninverting switched capacitor integrator.

As the op amp gain becomes large, the important components are indicated by the darker shading.

Chapter 9 - Switched Capacitor Circuits (6/4/01) CMOS Analog Circuit Design

P.E. Allen, 2001 Page 9.4-14

EXAMPLE 9.4-5 - Continued The SPICE input file to perform a frequency domain simulation of Fig. 9.4-12 is shown below.
VIN 1 0 DC 0 AC 1 R10C1 1 0 1.592 X10PC1 1 0 10 DELAY G10 1 0 10 0 0.6283 X14NC1 1 4 14 DELAY G14 4 1 14 0 0.6283 R40C1 4 0 1.592 X40PC1 4 0 40 DELAY G40 4 0 40 0 0.6283 X43PC2 4 3 43 DELAY G43 4 3 43 0 1 R35 3 5 1.0 X56PC2 5 6 56 DELAY G56 5 6 56 0 1 R46 4 6 1.0 X36NC2 3 6 36 DELAY G36 6 3 36 0 1 X45NC2 4 5 45 DELAY G45 5 4 45 0 1 EODD 6 0 4 0 -1E6 EVEN 5 0 3 0 -1E6 ******************** .SUBCKT DELAY 1 2 3 ED 4 0 1 2 1 TD 4 0 3 0 ZO=1K TD=5U RDO 3 0 1K .ENDS DELAY ******************** .AC LIN 99 1K 99K .PRINT AC V(6) VP(6) V(5) VP(5) .PROBE .END

Chapter 9 - Switched Capacitor Circuits (6/4/01)

P.E. Allen, 2001

CMOS Analog Circuit Design

Page 9.4-15

EXAMPLE 9.4-5 - Continued Simulation Results:

5 4 Magnitude 3 Both H 2 1 0
oe

200 150 Phase Shift (Degrees) 100 50 0 -50 Phase of H

oo

and H

oo

(jw)

Phase of H (jw)

oe

-100 -150

20

40 60 Frequency (kHz) (a.)

80

100

-200

20

40 60 Frequency (kHz) (b.)

80

100

Comments: This approach is applicable to all switched capacitor circuits that use two-phase, nonoverlapping clocks. If the op amp gain is large, some simplification is possible in the four-port z-domain models. The primary advantage of this approach is that it is not necessary to learn a new simulator.

Chapter 9 - Switched Capacitor Circuits (6/4/01) CMOS Analog Circuit Design

P.E. Allen, 2001 Page 9.4-16

SIMULATION OF SWITCHED CAPACITOR CIRCUITS USING SWITCAP Introduction SWITCAP is a general simulation program for analyzing linear switched capacitor networks (SCNs) and mixed switched capacitor/digital (SC/D) networks.
Signal Generators SCN's or Mixed SC/D Networks Outputs

Clocks General Setup of SWITCAP

Major Features 1.) Switching Intervals - An arbitrary number of switching intervals per switching period is allowed. The durations of the switching intervals may be unequal and arbitrary. 2.) Network Elements ON-OFF switches, linear capacitors, linear VCVSs, and independent voltage sources. The waveforms of the independent voltage sources may be continuous or piecewise-constant. The switches in the linear SCNs are controlled by periodic clock waveforms only. A mixed SC/D network may contain comparators, logic gates such as AND, OR, NOT, NAND, NOR, XOR, and XNOR. The ON-OFF switches in the SC/D network may be controlled not only by periodic waveforms but also by nonperiodic waveforms from the output of comparators and logic gates.

K. Suyama, Users Manual for SWITCAP2, Version 1.1, Dept. of Elect. Engr., Columbia University, New York, NY 10027, Feb. 1992.

Chapter 9 - Switched Capacitor Circuits (6/4/01)

P.E. Allen, 2001

CMOS Analog Circuit Design

Page 9.4-17

SWITCAP - Major Features, Continued 3.) Time-Domain Analyses of Linear SCNs and Mixed SC/D Networks a.) Linear SCNs only: The transient response to any prescribed input waveform for t 0 after computing the steady-state values for a set of dc inputs for t < 0. b.) Both types of networks: Transient response without computing the steady-state values as initial conditions. A set of the initial condition of analog and digital nodes at t = 0- may be specified by the user. 4.) Various Waveforms for Time Domain Analyses - Pulse, pulse train, cosine, exponential, exponential cosine, piecewise linear, and dc sources. 5.) Frequency Domain Analyses of Linear SCNs - A single-frequency sinusoidal input can produce a steady-state output containing many frequency components. SWITCAP can determine all of these output frequency components for both continuous and piecewise-constant input waveforms. z-domain quantities can also be computed. Frequency-domain group delay and sensitivity analyses are also provided. 6.) Built-In Sampling Functions - Both the input and output waveforms may be sampled and held at arbitrary instants to produce the desired waveforms for time- and frequency-domain analyses of linear SCNs except for sensitivity analysis. The output waveforms may also be sampled with a train of impulse functions for z-domain analyses. 7.) Subcircuits - Subcircuits, including analog and/or digital elements, may be defined with symbolic values for capacitances, VCVS gains, clocks, and other parameters. Hierarchical use of subcircuits is allowed. 8.) Finite Resistances, Op Amp Poles, and Switch Parasitics - Finite resistance is modeled with SCNs operating at clock frequencies higher than the normal clock. These resistors permit the modeling of op amp poles. Capacitors are added to the switch model to represent clock feedthrough.

Chapter 9 - Switched Capacitor Circuits (6/4/01) CMOS Analog Circuit Design

P.E. Allen, 2001 Page 9.4-18

SWITCAP - MIXED SC/D NETWORKS Structure of mixed SC/D networks as defined in SWITCAP2.
Timing

Threshold + + + -

Logic

. . . . . .

+ v -

Av

SCN - Function Generation

Chapter 9 - Switched Capacitor Circuits (6/4/01)

P.E. Allen, 2001

CMOS Analog Circuit Design

Page 9.4-19

SWITCAP - RESISTORS
RQ RQ

Ceq R= T 4Ceq RQ RQ RQ

t RQ

The clock, RQ, for the resistor is run at a frequency, much higher than the system clock in order to make the resistor model still approximate a resistor at frequencies near the system clock.

Chapter 9 - Switched Capacitor Circuits (6/4/01) CMOS Analog Circuit Design

P.E. Allen, 2001 Page 9.4-20

SWITCAP - MOS SWITCHES MOS Transistor Switch Model:

High Clock Voltage G MQ MQ MQ MQ MQ G S D Cgs S Cbs Frequency Higher than MQ clock RON MQ Cgd D Cbd

More information: SWITCAP Distribution Center Columbia University 411 Low Memorial Library New York, NY 10027 suyama@elab.columbia.edu

Chapter 9 - Switched Capacitor Circuits (6/4/01)

P.E. Allen, 2001

CMOS Analog Circuit Design

Page 9.4-21

INFO ON SWITCAP3
Dear Prof. Allen: Let me explain the latest regarding the development of SWITCAP3. The current version of SWITCAP is SWITCAP2 version 1.2. It has time-domain and frequencydomain (sinusoidal stead-state, spectrum, frequency-component analyses) analyses, sensitivity analysis, group delay analysis for SCF's. It has also time-domain analysis of mixed switched-capacitor and digital networks so that you can simulate data converters including sigma-delta converters. We only have Sun and HP versions. We don't have a PC version for SWITCAP2. We are distributing a graphic interface package for SWITCAP2 called XCAP. It has input schematic caption and postprocessing graphics. The package was developed by an outside company. We have finished 95 percent of SWITCAP3 coding. It will include all the analyses in SWITCAP2 plus noise analysis of SCF's and time- and frequency-domain analyses of switched-current circuits that are modelled using actual MOSFET models (currently, we have BSIM3 and Level 3) and usual SCN ideal components. Although we are already running some examples, it will take a few more months to make a beta-site version available. I hope the above information is sufficient for your purpose. If you or your students have further questions, please don't hesitate to contact me. Regards, Ken Suyama ----------------------------------------------------------------------Microelectronic Circuits & Systems Laboratory Department of Electrical Engineering, Columbia University 1312 S. W. Mudd Building, 500 West 120th Street, New York, NY 10027, USA TEL:212-854-6895 FAX:212-663-7203 EMAIL:suyama@elab.columbia.edu

Chapter 9 - Switched Capacitor Circuits (6/4/01) CMOS Analog Circuit Design

P.E. Allen, 2001 Page 9.5-1

9.5 - FIRST-ORDER, SWITCHED CAPACITOR CIRCUITS

GENERAL, FIRST-ORDER TRANSFER FUNCTIONS A general first-order transfer function in the s-domain: sa1 a0 H(s) = s + b 0 a1 = 0 Low pass, a0 = 0 High Pass, a0 0 and a1 0 All pass Note that the zero can be in the RHP or LHP. A general first-order transfer function in the z-domain: zA1 A0 A1 A0z-1 H(z) = z - B = 1 - B z-1 0 0

Chapter 9 - Switched Capacitor Circuits (6/4/01)

P.E. Allen, 2001

CMOS Analog Circuit Design

Page 9.5-2

NONINVERTING, FIRST-ORDER, LOW PASS CIRCUIT

2C1
2 1 1 2 vo(t) 1 2 2 C1 vi(t) vo(t) 1 2 2 2C1 1 1 2 1C1 2 1 P.E. Allen, 2001 Page 9.5-3 P.E. Allen, 2001 + + Vo(z)
o

C1

vo(t)

1C1
1 vi(t)

(a.) (b.) Figure 9.5-1 - (a.) Noninverting, first-order low pass circuit. (b.) Equivalent circuit of Fig. 9.5-1a.

Transfer function: Summing currents flowing toward the inverting op amp terminal gives
e o e e 2C1V o (z) - 1C1z-1/2V i (z) + C1(1-z-1)Vo (z) = 0 Vo(z) o o

Vi(z) 1z-1 e z-1/2Vo(z) 1z-1 1+2 = -1 = z-1 V (z) 1 + 2 - z Figure 9.5-2 - z-domain model of Fig. 9.5-1b. 1 - 1+ i 2 Equating the above to the H(z) of the previous page gives the design equations for Fig. 9.5-2 as A0 1-B0 1 = B and 2 = B 0 0 +
o V o (z) o

Chapter 9 - Switched Capacitor Circuits (6/4/01) CMOS Analog Circuit Design

INVERTING, FIRST-ORDER, LOW PASS CIRCUIT An inverting low pass circuit can be obtained by reversing the phases of the leftmost two switches in Fig. 9.5-1a.
2C1
2 1 1 2 vo(t) 1 2 1 C1 vi(t) vo(t) 2 2 2 C 1 2 1 1 2 1C1 1 1

1C1
2 vi(t)

Inverting, first-order low pass circuit.

Equivalent circuit.

It can be shown that, -1 = 1 + - z-1 = e 2 V (z) V o (z)

i e

-1 1+2 z-1 1 - 1+ 2

Equating to H(z) gives the design equations for the inverting low pass circuit as -A1 1-B0 1 = B and 2 = B 0 0

Chapter 9 - Switched Capacitor Circuits (6/4/01)

Solving for V o (z)/V i (z) gives

+ C 1 2 -C11z-1/2 C1(1-z-1) V e(z) o

o

C1

vo(t)

CMOS Analog Circuit Design

Page 9.5-4

EXAMPLE 9.5-1 - Design of a Switched Capacitor First-Order Circuit Design a switched capacitor first-order circuit that has a low frequency gain of +10 and a -3dB frequency of 1kHz. Give the value of the capacitor ratios 1 and 2. Use a clock frequency of 100kHz. Solution Assume that the clock frequency, fc, is much larger than the -3dB frequency. In this example, the clock frequency is 100 times larger so this assumption should be valid. Based on this assumption, we approximate z-1 as z-1 = e-sT 1- sT + Rewrite the z-domain transfer function as V o (z) V (z)
i o o

(1)

1z-1 2 + 1- z-1

(2)

Next, we note from Eq. (1) that 1-z-1 sT. Furthermore, if sT<<1, then z-1 1. (Note that sT<<1 is equivalent to << fc which is valid.) Making these substitutions in Eq. (2), we get V o (z) V
o i o

1 1/2 + sT = 1 + s(T/ ) 2 2 (z)

(3)

-3dB Equating Eq. (3) to the specifications gives 1 = 102 and 2 = f c

2 = 6283/100,000 = 0.0628 and 1 = 0.6283

Chapter 9 - Switched Capacitor Circuits (6/4/01) CMOS Analog Circuit Design

P.E. Allen, 2001 Page 9.5-5

FIRST-ORDER, HIGH PASS CIRCUIT

2C 2 1 1 1C C vi(t) vi(t) 2 vo(t) 1C 2 C 2C 2 1 1 2 vo(t)

(b.) (a.) Figure 9.5-3 - (a.) Switched-capacitor, high pass circuit. (b.) Version of Fig. 9.5-3a that constrains the charging of C1 to the 2 phase.

Transfer function: Summing currents at the inverting input node of the op amp gives

1(1-z-1)Vo (z) + 2V o (z) + (1-z-1)V i (z) = 0

Solving for the Hee(z) transfer function gives 1 -1 e V (z) -1(1-z-1) 2+1 (1-z ) ee(z) = o H = +1-z-1 = e 1 2 V i (z) 1 - +1 z-1 2 Equating Eq. (2) to H(z) gives, -A1 1 = B and 0

(1)
Vi(z)
e

1(1-z-1)

(2)

Figure 9.5-4 - z-domain model for Fig. 9.5-3.

1 2 = 1 - B 0

Chapter 9 - Switched Capacitor Circuits (6/4/01)

+ 2
(1-z-1) e Vo(z)

Vo(z)

z-1/2Vo(z)

P.E. Allen, 2001

CMOS Analog Circuit Design

Page 9.5-6

FIRST-ORDER, ALLPASS CIRCUIT

3C 2 2C 1 1 2 vo(t) 1C 2 1 2 C vi(t) 1 3C 2 2 2C 1 1 2 vo(t) 2
(1-z-1) e Vo(z)

1 vi(t)

(a.) (b.) Figure 9.5-5 - (a.) High or low frequency boost circuit. (b.) Modification of (a.) to simplify the z-domain modeling

Transfer function: Summing the currents flowing into the inverting input of the op amp gives -1z-1/2Vo (z)+3z-1/2Ve (z)+2Ve(z)+(1-z-1)Ve (z) i i o o =0

3(1-z-1) Vi(z)
o e

-1z-1/2

V e (z) 2+1-z-1 = 1z-1Ve(z) - 3(1-z-1)Ve(z) o i i Solving for Hee(z) gives

Figure 9.5-6 - z-domain model for Fig. 9.5-5b.

1+ 3 -1 1z-1 - 3(1-z-1) -3 1 - 3 z Hee(z) = z-1 2 +(1-z-1) = 2+1 1 - +1 2

1 =

A 1+A 0 - A0 1 B0 , 2 = 1 - B0 and 3 = B0

Chapter 9 - Switched Capacitor Circuits (6/4/01) CMOS Analog Circuit Design

EXAMPLE 9.5-2 - Design of a Switched Capacitor Bass Boost Circuit Find the values of the capacitor ratios1, 2, and 3 using a 100kHz clock for Fig. 9.5-5 that will realize the asymptotic frequency response shown in Fig. 9.5-7.
20 dB 0 10Hz 100Hz 1kHz 10kHz Frequency Figure 9.5-7 - Bass boost response for Ex. 9.5-2.

Solution Since the specification for the example is given in the continuous time frequency domain, let us use the approximation that z-1 1 and 1-z-1 sT, where T is the period of the clock frequency. Therefore, the allpass transfer function can be written as -sT3 + 1 1 sT3/1 - 1 Hee(s) sT + = - sT/ + 1 2 2 2 From Fig. 9.5-7, we see that the desired response has a dc gain of 10, a right-half plane zero at 2 kHz and a pole at -200 Hz. Thus, we see that the following relationships must hold. 1 1 2 T = 200 2 = 10 , T3 = 2000 , and From these relationships we get the desired values as 2000 fc , 200 fc , and 3 = 1

1 =

2 =

Chapter 9 - Switched Capacitor Circuits (6/4/01)

Since Vo(z) = z-1/2Ve(z), then the above becomes i i

Vi(z)

P.E. Allen, 2001 Page 9.5-7

P.E. Allen, 2001

+ Vo(z)
o

C 2 1 1

z-1/2Vo(z)

CMOS Analog Circuit Design

Page 9.5-8

PRACTICAL IMPLEMENTATIONS OF THE FIRST-ORDER CIRCUITS

1 1C 1 vi(t) 1 2 C1 2 1 2 2 1 -+ +1 2 + 1C 2 -+ +vo(t) vi(t) C 2C 2 vo(t) 1C 2 2 1 1 1 2 1 + 1 2 C -+ +vo(t) vi(t) C 2C 2 vo(t) 1 1 3C 2 1 + vo(t) C 2 2C 2 1 vo(t) 2 1C 2 1 1C 2 1 2

C 2 2 C

C 2 2 C

3C

2 2C

1C

(c.) (a.) (b.) Figure 9.5-8 - Differential implementations of (a.) Fig. 9.5-1, (b.) Fig. 9.5-3, and (c.) Fig. 9.5-5.

Comments: Differential operation reduces clock feedthrough, common mode noise sources and enhances the signal swing. Differential operation requires op amps or OTAs with differential outputs which in turn requires a means of stabilizing the output common mode voltage.

Chapter 9 - Switched Capacitor Circuits (6/4/01) CMOS Analog Circuit Design

P.E. Allen, 2001 Page 9.6-1

9.6 - SECOND-ORDER SWITCHED CAPACITOR CIRCUITS

WHY SECOND-ORDER CIRCUITS? They are fundamental blocks in switched capacitor filters. Switched Capacitor Filter Design Approaches Cascade design
Vin SecondOrder Circuit Stage 1 FirstOrder Circuit Stage 1 SecondOrder Circuit Stage 2 (a.) SecondOrder Circuit Stage n Vout

SecondSecondVout Order Order Circuit Circuit Stage 2 Stage n (b.) Figure 9.6-1 - (a.) Cascade design when n is even. (b.) Cascade designwhen n is odd. Vin

Ladder design Also uses first- and second-order circuits There are also other applications of first- and second-order circuits: Oscillators Converters

Chapter 9 - Switched Capacitor Circuits (6/4/01)

P.E. Allen, 2001

CMOS Analog Circuit Design

Page 9.6-2

BIQUAD TRANSFER FUNCTION A biquad has two poles and two zeros. Poles are complex and always in the LHP. The zeros may or may not be complex and may be in the LHP or the RHP. Transfer function: Vout(s) -(K2s2+ K1s + K0) (s-z1)(s-z2) = K (s-p )(s-p ) Ha(s) = V (s) = o in 1 2 s2 + Q s+ o2
j

o 2Q

Low pass: zeros at High pass: zeros at 0 Bandpass: One zero at 0 and the other at

Bandstop: zeros at jo Allpass: Poles and zeros are complex conjugates

Chapter 9 - Switched Capacitor Circuits (6/4/01) CMOS Analog Circuit Design

P.E. Allen, 2001 Page 9.6-3

LOW-Q, SWITCHED CAPACITOR BIQUAD Development of the Biquad: Rewrite Ha(s) as: os s2Vout(s) + Q Vout(s) + o2Vout(s) = -(K2s2 + K1s + K0)Vin(s) Dividing through by s 2 and solving for Vout(s), gives o -1 1 Vout(s) = s (K1 + K2s)Vin(s) + Q Vout(s) + s (K0Vin(s) +o2Vout(s)) If we define the voltage V1(s) as -1 K0 V1(s) = s Vin(s) + oVout(s) o then Vout(s) can be expressed as o -1 Vout(s) = s (K1 + K2s) Vin(s) + Q Vout(s) - oV1(s) Synthesizing the voltages V1(s) and Vout(s), gives
Vout(s) 1/o Vin(s) o/K0 CA=1 V1(s) Vin(s) K2 Vin(s) 1/K1 Vout(s) Q/o + CB=1 + P.E. Allen, 2001 Vout(s)

V1(s) -1/o (a.) (b.) Figure 9.6-2 - (a.) Realization of V1(s). (b.) Realization of Vout(s).

Chapter 9 - Switched Capacitor Circuits (6/4/01)

CMOS Analog Circuit Design

Page 9.6-4

LOW-Q, SWITCHED CAPACITOR BIQUAD - Continued Replace the continuous time integrators with switched capacitor integrators to get:
2 C 1
2 1 2

Vin(z) C1 V1(z)
e

3 C 2 4 C2 2 1 2

Vout(z)
e

Vin(z)
o

C2 V e (z) out

2 1

V1(s)
e

1 2

6 C 2
2 1 1

Vout(z)

(a.)

(b.) Figure 9.6-3 - (a.) Switched capacitor realization of Fig. 9.6-2a. (b.) Switched capacitor realization of Fig. 9.6-2b.

From these circuits we can write that: 1 e 2 e e V 1 (z) = - 1-z-1 V in(z) - 1-z-1 V out(z) and 4 e 5z-1 e 6 e e e V out(z) = -3 Vin(z) - -1 V in(z) + -1 V 1(z) - -1 V out(z) . 1-z 1-z 1-z Note that we multiplied the V 1 (z) input of Fig. 9.6-3b by z-1/2 to convert it to V 1 (z).
o e

Chapter 9 - Switched Capacitor Circuits (6/4/01) CMOS Analog Circuit Design

LOW-Q, SWITCHED CAPACITOR BIQUAD - Continued Connecting the two circuits of Fig. 9.6-3 together gives the desired, low-Q, biquad realization.
2 C1
e Vin(z) 1

1 C1
2

C1
2

e V1(z)

5 C 2
1 2

6 C2
2

C2 -

4 C2 3 C2
1

Figure 9.6-4 - Low Q, switched capacitor, biquad realization.

If we assume that T<<1, then 1-z-1 sT and V 1(z) andVout(z) can be approximated as 1 e 2 e 2 e -1 1 e e V 1 (s) - sT V in(s) - sT V out(s) = s T V in(s) + T V out(s) and 5 e 6 e -1 4 e e V out(s) s ( T + s3)Vin(s) + T V 1(s) + sT V out(s) . These equations can be combined to give the transfer function, Hee(s) as follows. s 4 1 5 -3s2 + T + T2 Hee(s) s 6 2 5 s2 + T + T 2

Chapter 9 - Switched Capacitor Circuits (6/4/01)

+ P.E. Allen, 2001 Page 9.6-5

2

Vin(z)

1 C1

5 C 2

Vout(z)

P.E. Allen, 2001

CMOS Analog Circuit Design

Page 9.6-6

LOW-Q, SWITCHED CAPACITOR BIQUAD - Continued Equating Hee(s) to Ha(s) gives s 4 1 5 -3s2 + T + T2 -(K s2+ K s + K ) 2 1 0 s 6 2 5 = o s2 + Q s+ o2 s2 + T + T 2 which gives, K 0T oT 1 = , 2 = |5| = oT, 3 = K2, 4 = K1T, and 6 = Q . o Largest capacitor ratio: If Q > 1 and oT << 1, the largest capacitor ratio is 6. For this reason, the low-Q, switched capacitor biquad is restricted to Q <5. Sum of capacitance: To find this value, normalize all of the capacitors connected or switched into the inverting terminal of each op amp by the smallest capacitor, minC. The sum of the normalized capacitors associated with each op amp will be the sum of the capacitance connected to that op amp. Thus, n 1 C = i min
i =1

where there are n capacitors connected to the op amp inverting terminal, including the integrating capacitor.

Chapter 9 - Switched Capacitor Circuits (6/4/01) CMOS Analog Circuit Design

P.E. Allen, 2001 Page 9.6-7

EXAMPLE 9.6-1- Design of a Switched Capacitor, Low-Q, Biquad Assume that the specifications of a biquad arefo = 1kHz, Q = 2, K0 = K2 = 0, and K1 = 2fo/Q (a bandpass filter). The clock frequency is 100kHz. Design the capacitor ratios of Fig. 9.6-4 and determine the maximum capacitor ratio and the total capacitance assuming that C1 and C2 have unit values. Solution From the previous slide we have K 0T oT 1 = , 2 = |5| = oT, 3 = K2, 4 = K1T, and 6 = Q . o Setting K0 = K2 = 0, and K1 = 2fo/Q and letting fo = 1kHz, Q = 2 gives

1 = 3 = 0, 2 = 5 = 0.0628, and 4 = 6 = 0.0314.

The largest capacitor ratio is 4 or 6 and is 1/31.83. capacitors connected to the input op amp = 1/0.0628 + 1 = 16.916. capacitors connected to the second op amp = 0.0628/0.0314 + 1/0.0314 + 2 = 35.85. Therefore, the total biquad capacitance is 52.76 units of capacitance. (Note that this number will decrease as the clock frequency becomes closer to the signal frequencies.)

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CMOS Analog Circuit Design

Page 9.6-8

Z-DOMAIN CHARACTERIZATION OF THE LOW-Q, BIQUAD Combining the following two equations, 1 e 2 e e V 1 (z) = - 1-z-1 V in(z) - 1-z-1 V out(z) and 5z-1 e 4 e 6 e e e V out(z) = -3 Vin(z) - -1 V in(z) + -1 V 1(z) - -1 V out(z) . 1-z 1-z 1-z gives, V out(z) V in(z)
e e

= Hee(z) = -

(3 + 4)z2 + (15 - 4 - 23)z + 3 (1 + 6)z2 + (25 - 6 - 2)z + 1

A general z-domain specification for a biquad can be written as a2z2 + a1z + a0 H(z) = - b z2 + b z + 1
2 1

Equating coefficients gives

3 = a0, 4 = a2-a0, 15 = a2+a1+a0, 6 = b2-1, and 25 = b2+b1+1

Because there are 5 equations and 6 unknowns, an additional relationship can be introduced. One approach would be to select 5 = 1 and solve for the remaining capacitor ratios. Alternately, one could let 2 = 5 which makes the integrator frequency of both integrators in the feedback loop equal.

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P.E. Allen, 2001 Page 9.6-9

VOLTAGE SCALING It is desirable to keep the amplitudes of the output voltages of the two op amps approximately equal over the frequency range of interest. This can be done by voltage scaling. If the voltage at the output node of an op amp in a switched capacitor circuit is to be scaled by a factor of k, then all switched and unswitched capacitors connected to that output node must be scaled by a factor of 1/k. For example,
1C1
-

C1

v1

2C2
+

C2

The charge associated with v1 is: Q(v1) = C1v1 + 2C2v1 Suppose we wish to scale the value of v1 by k1 so that v1 = k1v1. Therefore, Q(v1) = C1v1 + 2C2v1 = C1k1v1 + 2C2k1v1 But, Q(v1) = Q(v1) so that C1 = C1/k1 and C2 = C2/k1. This scaling is based on keeping the total charge associated with a node constant. The choice above of 2 = 5 results in a near-optimally scaled dynamic range realization.

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CMOS Analog Circuit Design

Page 9.6-10

HIGH-Q, SWITCHED CAPACITOR BIQUAD Desired: A biquad capable of realizing higher values of Q without suffering large element spreads. Development of such a biquad: Reformulate the equations for V1(s) and Vout(s) as follows, 1 Vout(s) = - s [ K2sVin - oV1(s)] and 1 K0 K1 s V1(s) = - s + s Vin(s) + o + Q Vout(s) o o Synthesizing these equations:
Vout(s) 1/o Vout(s) 1/Q Vin(s) K1/o Vin(s) o/K0 CA=1 Vin(s) K2 V1(s) 1
o

CB=1 1

V1(s) -1/o

Vout(s)

Realization of V1(s).

Realization of Vout(s).

Chapter 9 - Switched Capacitor Circuits (6/4/01) CMOS Analog Circuit Design

HIGH-Q, SWITCHED CAPACITOR BIQUAD - Continued Replace the continuous time integrators with switched capacitor integrators to get:
e Vout(z)

4 C 1 3 C1 2 C1 +
2 1 2

Vin(z) Vout(z)
e e

C1 -

V1(z) Vin(z) V1(s)

o e

6 C2 5 C2 2 1 2

2 1

(a.) (b.) Figure 9.6-6 - (a.) Switched capacitor realization of Fig. 9.6-5a. (b.) Switched capacitor realization of Fig. 9.6-5b.

From these circuits we can write that: 1 e 2 e e e e V 1 (z) = - 1-z-1 V in(z) - 1-z-1 V out(z) - 3Vin(z) - 4Vout(z) and 5z-1 e e e V out(z) = -6 Vin(z) + -1 V 1(z) . 1-z Note that we multiplied the V 1 (z) input of Fig. 9.6-6b by z-1/2 to convert it to V 1 (z).
e

Chapter 9 - Switched Capacitor Circuits (6/4/01)

Vin(z)

1 C1

P.E. Allen, 2001 Page 9.6-11

C2 V e (z) out

P.E. Allen, 2001

CMOS Analog Circuit Design

Page 9.6-12

HIGH-Q, SWITCHED CAPACITOR BIQUAD - Continued Connecting the two circuits of Fig. 9.6-6 together gives the desired, high-Q biquad realization.
2 C 1 3 C 1 Vin(z)
e 1

4 C1 C1 Ve (z) 1 5 C 2 1 2 1 2

1 C 1
2 1 1 2

C2

Vout(z)

6 C 2

Figure 9.6-7 - High Q, switched capacitor, biquad realization.

If we assume that T<<1, then 1-z-1 sT and V 1(z) andVout(z) can be approximated as e e 1 1 1 2 e V 1 (s) - s T + s3V in(s) - s T + s4V out(s) and 5 e -1 e e V out(s) s (s6)Vin(s) - T V 1(s) . These equations can be combined to give the transfer function, Hee(s) as follows. s35 15 -6s2 + T + T2 Hee(s) s45 25 s2 + T + 2 T
Chapter 9 - Switched Capacitor Circuits (6/4/01) CMOS Analog Circuit Design

HIGH-Q, SWITCHED CAPACITOR BIQUAD - Continued Equating Hee(s) to Ha(s) gives s35 15 T + T2 -(K2s2+ K1s + K0) s45 25 = o s2 + Q s+ o2 s2 + T + T 2 which gives, -6s2 +

K 0T K1 1 1 = , 2 = | 5| = oT, 3 = , 4 =Q, and 6 = K2 . o o Largest capacitor ratio: If Q > 1 and oT << 1, the largest capacitor ratio is 2 (5) or 4 depending on the values of Q and oT.

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CMOS Analog Circuit Design

Page 9.6-14

EXAMPLE 9.6-2 - Design of a Switched Capacitor, High-Q, Biquad Assume that the specifications of a biquad arefo = 1kHz, Q = 10, K0 = K2 = 0, and K1 = 2fo/Q (a bandpass filter). The clock frequency is 100kHz. Design the capacitor ratios of the high-Q biquad of Fig. 9.6-4 and determine the maximum capacitor ratio and the total capacitance assuming that C1 and C2 have unit values. Solution From the previous slide we have, K 0T K1 1 1 = , 2 = | 5| = oT, 3 = , 4 =Q, and 6 = K2 . o o Using fo = 1kHz, Q = 10 and setting K0 = K2 = 0, and K1 = 2fo/Q (a bandpass filter) gives

1 = 6 = 0, 2 = 5 = 0.0628, and 3 =4 = 0.1.

The largest capacitor ratio is 2 or 5 and is 1/15.92. capacitors connected to the input op amp = 1/0.0628 + 2(0.1/0.0628) + 1 = 20.103. capacitors connected to the second op amp = 1/0.0628 + 1 = 16.916. Therefore, the total biquad capacitance is 36.02 units of capacitance.

Chapter 9 - Switched Capacitor Circuits (6/4/01) CMOS Analog Circuit Design

P.E. Allen, 2001 Page 9.6-15

Z-DOMAIN CHARACTERIZATION OF THE HIGH-Q, BIQUAD Combining the following two equations, 1 e 2 e e e e V 1 (z) = - 1-z-1 V in(z) - 1-z-1 V out(z) - 3Vin(z) - 4Vout(z) and 5z-1 e e e V out(z) = -6 Vin(z) + -1 V 1(z) 1-z gives, V out(z) V in(z)
e e

= H ee(z) = -

6z2 + (35 - 15 - 26)z + (6 - 35) z2 + (45 + 25 - 2)z + (1 - 45)

A general z-domain specification for a biquad can be written as (a2/b2)z2 + (a1/b2)z + (a0/b2) a2z2 + a1z + a0 H(z) = - b z2 + b z + 1 = - z2 + (b /b )z + (b /b )
2 1 1 2 0 2

Equating coefficients gives a2 a2-a0 a2+a1+a0 b1+1 1 6 = b , 3 5 = b , 1 5 = , 45 = 1- b and 25 = 1 + 2 b2 2 2 2 Because there are 5 equations and 6 unknowns, an additional relationship can be introduced. One approach would be to select 5 = 1 and solve for the remaining capacitor ratios. Alternately, one could let 2 = 5 which makes the integrator frequency of both integrators in the feedback loop equal.

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CMOS Analog Circuit Design

Page 9.6-16

FLEISCHER-LAKER, SWITCHED CAPACITOR BIQUAD

E K
2

C F
2 1 2

Vin(z)

G
2 1 2

D -

V1(s)

A
1 2

B -

Vout(z)

H
1

I J
1

L
2

Figure 9.6-8 - Fleischer-Laker, switched capacitor biquad.

V out(z) V in(z) = e V in(z) V 1(z)
e e e

^ ^ ^ ^ ^ ^ (D J - AH )z -2 - [D ( I + J ) - A G ]z - D I (D B - AE)z -2 - [2D B - A(C + E) + D F ]z -1 + D (B +F)

^ ^ ^ ^ ^ ^ ^ I ^ I (E J - B H)z -2 +[B( G + H ) + F H - E ( ^ + J ) - C J ]z -1 - [ ^ (C + E ) - G(F+B)] -2 - [2D B - A(C + E) + D F ]z -1 + D (B +F) (D B - AE)z

where

^ G = G+L,

^ H = H+L ,

^ I = I+K

and

P.E. Fleischer and K.R. Laker, A Family of Active Switched Capacitor Biquad Building Blocks, Bell System Technical Journal, vol. 58, no. 10, Dec. 1979, pp. 2235-2269.

Chapter 9 - Switched Capacitor Circuits (6/4/01) CMOS Analog Circuit Design

Z-DOMAIN MODEL OF THE FLEISCHER-LAKER BIQUAD

E(1-z-1) C K(1-z-1) D(1-z-1) V e(z) -Az-1 1 F B(1-z-1) e Vout(z)

G
e

Vin(z)

-Hz-1

-Jz-1 L(1-z-1)

Figure 9.6-9 - z-domain equivalent circuit for the Fleischer-Laker biquad of Fig. 9.6-8.

Type 1E Biquad (F = 0) V out V in and V1 V in

e e e e

z-2(DB

z-2(JD - HA) + z-1(AG - DJ - DI) + DI - AE) + z-1(AC + AE - 2BD) + BD

z-2(EJ - HB) + z-1(GB + HB - IE - CJ - EJ) + (IC + IE - GB) z-2(DB - AE) + z-1(AC + AE - 2BD) + BD

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^ J = J+L

P.E. Allen, 2001 Page 9.6-17

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CMOS Analog Circuit Design

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Z-DOMAIN MODEL OF THE FLEISCHER-LAKER BIQUAD - Continued

E(1-z-1) C K(1-z-1) D(1-z-1) V e(z) -Az-1 1 F B(1-z-1) I -Jz-1 L(1-z-1) +
e Vout(z)

G
e

Vin(z)

-Hz-1

Figure 9.6-9 - z-domain equivalent circuit for the Fleischer-Laker biquad of Fig. 9.6-8.

Type 1F Biquad (E = 0) V out

e V in e

z-2DB

z-2(JD - HA) + z-1(AG - DJ - DI) + DI + z-1(AC - 2BD - DF) + (BD + DF)

and V1 V in
e e

-z-2HB + z-1(GB + HB + HF - CJ) + (IC + GF - GB) z-2DB + z-1(AC - 2BD - DF) + (BD + DF)

Chapter 9 - Switched Capacitor Circuits (6/4/01) CMOS Analog Circuit Design

EXAMPLE 9.6-3 - Design of a Switched Capacitor, Fleischer-Laker Biquad Use the Fleischer-Laker biquad to implement the following z-domain transfer function which has poles in the z-domain at r = 0.98 and = 6.2. H(z) = 0.003z-2 + 0.006z-1 + 0.003 0.9604z-2 - 1.9485z-1 + 1

Solution Let us begin by selecting a Type 1E Fleischer-Laker biquad. Equating the numerator of Eq. (1) with the numerator of H(z) gives DI = 0.003 AG-DJ-DI = 0.006 AG-DJ = 0.009 DJ-HA = 0.003 If we arbitrarily choose H = 0, we get DI = 0.003 JD = 0.003 AG = 0.012 Picking D = A = 1 gives I = 0.003, J = 0.003 and G = 0.012. Equating the denominator terms of Eq. (1) with the denominator of H(z), gives BD = 1 BD-AE = 0.9604 AE = 0.0396 AC+AE-2BD = -1.9485 AC+AE = 0.0515 AC = 0.0119 Because we have selected D = A = 1, we get B = 1, E = 0.0396, and C = 0.0119. If any capacitor value was negative, the procedure would have to be changed by making different choices or choosing a different realization such as Type 1F. Since each of the alphabetic symbols is a capacitor, the largest capacitor ratio will be D or A divided by I or J which gives 333. The large capacitor ratio is being caused by the term BD = 1. If we switch to the Type 1F, the term BD = 0.9604 will cause large capacitor ratios. This example is a case where both the E and F capacitors are needed to maintain a smaller capacitor ratio.

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CMOS Analog Circuit Design

Page 9.7-1

9.7 - SWITCHED CAPACITOR FILTERS

APPROACH Todays switched capacitor filters are based on continuous time filters. Consequently, it is expedient to briefly review the subject of continuous time filters. Filter Specifications Ideal Filter:
Magnitude 1.0 Passband 0.0 0 Stopband Frequency Phase 0 0 Slope = -Time delay

Continuous Time Filter

Switched Capacitor Filter

fcutoff = fPassband

Frequency

This specification cannot be achieve by realizable filters because: An instantaneous transition from a gain of 1 to 0 is not possible. A band of zero gain is not possible. Therefore, we develop filter approximations which closely approximate the ideal filter but are realizable.

Chapter 9 - Switched Capacitor Circuits (6/4/01) CMOS Analog Circuit Design

P.E. Allen, 2001 Page 9.7-2

CHARACTERIZATION OF FILTERS A low pass filter magnitude response.

T(j) T(j0) T(jPB) T(jSB) 0 0 Tn(jn) 1 T(jPB)/T(j0) T(jSB)/T(j0) 0 0 PB SB 1 SB/PB=n (b.) (a.) Figure 9.7-1 - (a.) Low pass filter. (b.) Normalized, low pass filter. n

Three basic properties of filters. 1.) Passband ripple = |T(j0) - T(jPB)|. 2.) Stopband frequency = SB. 3.) Stopband gain/attenuation = T(jSB). For a normalized filter the basic properties are: 1.) Passband ripple = T(jPB)/T(j0) = T(jPB) if T(j0) = 1. 2.) Stopband frequency (called the transition frequency) = n = SB/PB. 3.) Stopband gain = T(jSB)/T(j0) = T(jSB) if T(j0) = 1.

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CMOS Analog Circuit Design

Page 9.7-3

FILTER SPECIFICATIONS IN TERMS OF BODE PLOTS (dB)

Tn(jn) dB 0 T(jPB) T(jSB) 1 An(jn) dB

log10(n) A(jSB) A(jPB) 0 0

log10(n) 1 n (b.) (a.) Figure 9.7-2 - (a.) Low pass filter of Fig. 9.7-1 as a Bode plot. (b.) Low pass filter of Fig. 9.7-2a shown in terms of attenuation (A(j) = 1/T(j)).

Therefore, Passband ripple = T(jPB) dB Stopband gain = T(jSB) dB or Stopband attenuation = A(jPB) Transition frequency is still = n = SB/PB

Chapter 9 - Switched Capacitor Circuits (6/4/01) CMOS Analog Circuit Design

P.E. Allen, 2001 Page 9.7-4

BUTTERWORTH FILTER APPROXIMATION This approximation is maximally flat in the passband.

1 0.8 0.6 |T LPn (j n)| 0.4 0.2 0 0 0.5 A 1 1+
N=5 N=4 N=6 N=8 N=10 N=3 N=2

1 1.5 2 Normalized Frequency, n

2.5

Butterworth Magnitude Approximation: 1 T LPn(j n) = 2N 1 + 2 n where N is the order of the approximation and is defined in the above plot. The magnitude of the Butterworth filter approximation at SB is given as
j S B TLPn = |TLPn(j n)| = TSB = PB

1 1 + 2
2N n

This equation in terms of dB is useful for finding N given the filter specifications.
2N 20 log10(TSB) = TSB (dB) = -10 log101 + 2 n

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CMOS Analog Circuit Design

Page 9.7-5

EXAMPLE 9.7-1 - Determining the Order of A Butterworth Filter Approximation Assume that a normalized, low-pass filter is specified as TPB = -3dB, TSB = -20 dB, and n = 1.5. Find the smallest integer value of N of the Butterworth filter approximation which will satisfy this specification. Solution TPB = -3dB corresponds to TPB = 0.707 which implies that = 1. Thus, substituting = 1 and n = 1.5 into the equation at the bottom of the previous slide gives TSB (dB) = - 10 log10( 1 + 1.52N) Substituting values of N into this equation gives, TSB = -7.83 dB for N = 2 -10.93 dB for N = 3 -14.25 dB for N = 4 -17.68 dB for N = 5 -21.16 dB for N = 6. Thus, N must be 6 or greater to meet the filter specification.

Chapter 9 - Switched Capacitor Circuits (6/4/01) CMOS Analog Circuit Design

P.E. Allen, 2001 Page 9.7-6

POLES AND QUADRATIC FACTORS OF BUTTERWORTH FUNCTIONS Table 9.7-1 - Pole locations and quadratic factors (sn2 + a1sn + 1) of normalized, low pass Butterworth functions for = 1. Odd orders have a product (sn+1). N 2 3 4 5 6 7 8 9 10 Poles -0.70711 j0.70711 -0.50000 j0.86603 -0.38268 j0.92388 -0.92388 j0.38268 -0.30902 j0.95106 -0.80902 j0.58779 -0.25882 j0.96593 -0.70711 j0.70711 -0.22252 j0.97493 -0.62349 j0.78183 -0.19509 j0.98079 -0.55557 j0.83147 -0.17365 j0.98481 -0.50000 j0.86603 -0.15643 j0.98769 -0.45399 j0.89101 -0.70711 j0.70711 a1 coefficient 1.41421 1.00000 0.76536 1.84776 0.61804 1.61804 0.51764 1.93186 1.41421 0.44505 1.80194 1.24698 0.39018 1.66294 1.11114 1.96158 0.34730 1.53208 1.00000 1.87938 0.31286 1.78202 0.90798 1.97538 1.41421

-0.96593 j0.25882 -0.90097 j0.43388 -0.83147 j0.55557 -0.98079 j0.19509 -0.76604 j0.64279 -0.93969 j0.34202 -0.89101 j0.45399 -0.98769 j0.15643

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CMOS Analog Circuit Design

Page 9.7-7

Example 9.7-2 - Finding the Butterworth Roots and Polynomial for a given N Find the roots for a Butterworth approximation with =1 for N = 5. Solution For N = 5, the following first- and second-order products are obtained from Table 9.7-1 1 1 1 TLPn(sn) = T1(sn)T2(sn)T3(sn) = sn+1 2 2 sn+0.6180sn+1 sn+1.6180sn+1 Illustration of the individual magnitude contributions of each product of TLPn(sn).
2 T 2 (jn) 1.5 Magnitude TLPn(jn ) 1 T1 (jn ) 0.5 T3 (jn ) 0 0 0.5 1 1.5 2 Normalized Frequency, n 2.5 3

Chapter 9 - Switched Capacitor Circuits (6/4/01) CMOS Analog Circuit Design

P.E. Allen, 2001 Page 9.7-8

CHEBYSHEV FILTER APPROXIMATION The magnitude response of the Chebyshev filter approximation for = 0.5088.
1 0.8 0.6 TLPn(jn ) 0.4 0.2 0 0 0.5 A 1 1+2
N=2 N=3

N=4 N=5

1 1.5 2 Normalized Frequency, n

2.5

The magnitude of the normalized, Chebyshev, low-pass, filter approximation can be expressed as 1 , n 1 | TLPn(jn)| = 1 + 2 cos2[Ncos-1(n)] and 1 , n > 1 | TLPn(jn)| = 1 + 2 cosh2[Ncosh-1(n)] where N is the order of the filter approximation and is defined as 1 . |TLPn(PB)| = |TLPn(1)| = TPB = 1+2 N is determined from 20 log10(TSB) = TSB (dB) = -10log10{1 + 2cosh2[Ncosh-1(n)]}

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CMOS Analog Circuit Design

Page 9.7-9

EXAMPLE 9.7-3 - Determining the Order of A Chebyshev Filter Approximation Repeat Ex. 9.7-1 for the Chebyshev filter approximation. Solution In Ex. 9.7-2, = 1 which means the ripple width is 3 dB or TPB = 0.707. Now we substitute = 1 into 20 log10(TSB) = TSB (dB) = -10log10{1 + 2cosh2[Ncosh-1(n)]} and find the value of N which satisfies TSB = - 20dB. For N = 2, TSB = - 11.22 dB. For N =3, TSB = -19.14 dB. For N = 4, TSB = -27.43 dB. Thus N = 4 must be used although N = 3 almost satisfies the specifications. This result compares with N = 6 for the Butterworth approximation.

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P.E. Allen, 2001 Page 9.7-10

POLES AND QUADRATIC FACTORS OF CHEBYSHEV FUNCTIONS Table 9.7-2 - Pole locations and quadratic factors (a0 + a1sn + sn2) of normalized, low pass Chebyshev functions for = 0.5088 (1dB). N 2 3 4 5 6 7 Normalized Pole Locations -0.54887 j0.89513 -0.24709 j0.96600 -0.49417 -0.13954 j0.98338 -0.33687 j0.40733 -0.08946 j0.99011 -0.23421 j0.61192 -0.28949 -0.06218 j0.99341 -0.16988 j0.72723 -0.23206 j0.26618 -0.04571 j0.99528 -0.12807 j0.79816 -0.18507 j0.44294 -0.20541 a0 1.10251 0.99420 0.98650 0.27940 0.98831 0.42930 0.99073 0.55772 0.12471 0.99268 0.65346 0.23045 a1 1.09773 0.49417 0.27907 0.67374 0.17892 0.46841 0.12436 0.33976 0.46413 0.09142 0.25615 0.37014

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CMOS Analog Circuit Design

Page 9.7-11

EXAMPLE 9.7-4 - Finding the Chebyshev Roots for a given N Find the roots for the Chebyshev approximation with =1 for N = 5. Solution For N = 5, we get the following quadratic factors which give the transfer function as 0.2895 TLPn(sn) = T1(sn)T2(sn)T3(sn) = s +0.2895 n
2 2 sn+0.1789sn+0.9883 sn+0.4684sn+0.4293

0.9883

0.4293

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P.E. Allen, 2001 Page 9.7-12

OTHER APPROXIMATIONS Thomson Filters - Maximally flat magnitude and linear phase1 Elliptic Filters - Ripple both in the passband and stopband, the smallest transition region of all filters.2 An excellent collection of filter approximations and data is found in A.I. Zverev, Handbook of Filter Synthesis, John Wiley & Sons, Inc., New York, 1967.

1 2

W.E. Thomson, Delay Networks Having Maximally Flat Frequency Characteristics, Proc. IEEE, part 3, vol. 96, Nov. 1949, pp. 487-490. W. Cauer, Synthesis of Linear Communication Networks, McGraw-Hill Book Co., New York, NY, 1958.

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CMOS Analog Circuit Design

Page 9.7-13

GENERAL APPROACH FOR CONTINUOUS AND SC FILTER DESIGN

Normalized LP Filter Root Locations Normalized Low-Pass RLC Ladder Realization Frequency Transform the Roots to HP, BP, or BS Frequency Transform the L's and C's to HP, BP, or BS Cascade of First- and/or Second-Order Stages First-Order Replacement of Ladder Components

Low-Pass, Normalized Filter with a passband of 1 rps and an impedance of 1 ohm.

Denormalize the Filter Realization

All designs start with a normalized, low pass filter with a passband of 1 radian/second and an impedance of 1 that will satisfy the filter specification. 1.) Cascade approach - starts with the normalized, low pass filter root locations. 2.) Ladder approach - starts with the normalized, low pass, RLC ladder realizations.

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P.E. Allen, 2001 Page 9.7-14

A DESIGN PROCEDURE FOR THE LOW PASS, SC FILTERS USING THE CASCADE APPROACH 1.) From TPB, TSB, and n (or APB, ASB, and n) determine the required order of the filter approximation, N. 2.) From tables similar to Table 9.7-1 and 9.7-2 find the normalized poles of the approximation. 3.) Group the complex-conjugate poles into second-order realizations. For odd-order realizations there will be one first-order term. 4.) Realize each of the terms using the first- and second-order blocks of Secs. 9.5 and 9.6. 5.) Cascade the realizations in the order from input to output of the lowest-Q stage first (first-order stages generally should be first). More information can be found elsewhere1,2,3,4.

1 2 3 4

K.R. Laker and W.M.C. Sansen, Design of Analog Integrated Circuits and Systems, McGraw Hill, New York, 1994. P.E. Allen and E. Sanchez-Sinencio, Switched Capacitor Circuits, Van Nostrand Reinhold, New York, 1984. R. Gregorian and G.C. Temes, Analog MOS Integrated Circuits for Signal Processing, John Wiley & Sons, New York, 1987. L.P. Huelsman and P.E. Allen, Introduction to the Theory and Design of Active Filters, McGraw Hill Book Company, New York, 1980.

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CMOS Analog Circuit Design

Page 9.7-15

EXAMPLE 9.7-5 - Fifth-order, Low Pass, Switched Capacitor Filter using the Cascade Approach Design a cascade, switched capacitor realization for a Chebyshev filter approximation to the filter specifications of TPB = -1dB, TSB = -25dB, fPB = 1kHz and fSB = 1.5kHz. Give a schematic and component value for the realization. Also simulate the realization and compare to an ideal realization. Use a clock frequency of 20kHz. Solution First we see that n = 1.5. Next, recall that when TPB = -1dB that this corresponds to = 0.5088. We find that N = 5 satisfies the specifications (TSB = -29.9dB). Using the results of Ex. 9.7-4, we may write TLPn(sn) as 0.2895 TLPn(sn) = sn+0.2895
2 2 sn+0.1789sn+0.9883 sn+0.4684sn+0.4293

0.9883

0.4293

(1)

Next, we design each of the three stages individually.

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P.E. Allen, 2001 Page 9.7-16

EXAMPLE 9.7-5 - Continued Stage 1 - First-order Stage 1 21C11 Let us select Fig. 9.5-1 to realize the first-order stage. 2 Vin(ej) 11C11 V2(ej) We will assume that fc is much greater than fBP (i.e. 100) and 1 2 C11 use Eq. (10) of Sec. 9.5 repeated below to accomplish the 2 1 design. 11/21 (2) T1(s) 1 + s(T/ ) Stage 1 21 Note that we have used the second subscript 1 to denote the first stage. Before we can use this equation we must normalize the sT factor. This normalization is accomplished by
s sT = (PBT) = snTn . PB + -

(3)

Therefore, Eq. (2) can be written as 11/21 11/Tn T1(sn) 1 + s (T / ) = s + /T n n 21 n 21 n where 11 = C11/C and 21 = C21/C. Fig. 9.5-1 as

(4)

Equating Eq. (4) to the first term in TLPn(sn) gives the design of 0.2895PB 0.28952000 = = 0.0909 fc 20,000

21 = 11 = 0.2895Tn =

The sum of capacitances for the first stage is 1 First-stage capacitance = 2 + 0.0909 = 13 units of capacitance

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CMOS Analog Circuit Design

Page 9.7-17

EXAMPLE 9.7-5 - Continued Stage 2 - Second-order, High-Q Stage The next product of TLPn(sn) is 0.9883
2 sn

22C12 12C12 1 1
-

1 42C12 2 V3(ej) 1
-

V2(ej)

52C22 2 C12 1 2 2 C22

+ 0.1789sn + 0.9883 =
2 T(0)n

(5) n 2 2 Stage 2 sn + Q sn + n where T(0) = 1, n = 0.9941 and Q = (0.9941/0.1789) = 5.56. Therefore, select the low pass version of the high-Q biquad of Fig. 9.6-7. First, apply the normalization of Eq. (3) to get sn3252 1252 + 2 Tn Tn . T2(sn) sn4252 2252 2 sn + + 2 Tn Tn To get a low pass realization, select 32 = 62 = 0 to get -62sn +

1252
2

Tn T2(sn) 2252 . 2 sn4252 sn + + 2 Tn Tn

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P.E. Allen, 2001 Page 9.7-18

EXAMPLE 9.7-5 - Continued Equating Eq. (7) to the middle term of TLPn(sn) gives 0.9883PB2 0.988342 2 1252 = 2252 = 0.9883Tn = = = 0.09754 400 fc2 and 0.1789PB 0.17892 4252 = 0.1789Tn = = = 0.05620 fc 20 Choose a12 = a22 = 52 to get optimum voltage scaling. Thus we get, 12 = 22 = 52 = 0.3123 and 42 = 0.05620/0.3123 = 0.1800. The second-stage capacitance is 3(0.3123) 2 Second-stage capacitance = 1 + 0.1800 + 0.1800 = 17.316 units of capacitance Stage 3 - Second-order, Low-Q Stage The last product of TLPn(sn) is 0.4293 sn + 0.4684sn + 0.4293 T(0)n = n 2 2 sn + Q sn + n
2 2

(8)

Stage 3

where we see that T(0) = 1, n = 0.6552 and Q = (0.6552/0.4684) = 1.3988. Therefore, select the low pass version of the low-Q biquad. First, apply the normalization of Eq. (3) to get

Chapter 9 - Switched Capacitor Circuits (6/4/01)

P.E. Allen, 2001

V3(ej) 13C13 2

21C13 2 C13 1

53C23

63C23 2 C23

(6)

(7)

Vout(ej)

CMOS Analog Circuit Design

Page 9.7-19

EXAMPLE 9.7-5 - Continued sn43 1353 2 -33sn + T + 2 n Tn T3(sn) . sn63 2353 2 sn + Tn + 2 Tn To get a low pass realization, select 33 = 43 = 0 to get 1353 - 2 Tn T3(sn) sn63 2353 . 2 sn + Tn + 2 Tn Equating Eq. (10) to the last term of TLPn(sn) gives 0.4293PB2 0.429342 2 1353 = 2353 = 0.4293Tn = = = 0.04237 400 fc2 and 0.4684PB 0.46842 63 = 0.4684Tn = = = 0.1472 fc 20

(9)

(10)

Choose a13 = a23 = 53 to get optimum voltage scaling. Thus , 13 = 23 = 53 = 0.2058 and 63 = 0.1472. The third-stage capacitance is 3(0.2058) 2 Third-stage capacitance = 1 + 0.1472 + 0.1472 = 18.78 units of capacitance The total capacitance of this design is 13 + 17.32 + 18.78 = 49.10 units of capacitance.

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P.E. Allen, 2001 Page 9.7-20

EXAMPLE 9.7-5 - Continued Final design with stage 3 second to maximize the dynamic range.
Stage 1 11C11 Vin(ej) 1 2 1 2 21C11 C11
-

1 2

Stage 3 13C13 1 1
-

23C13 2 C13 1

53C23 2

Stage 2 22C12 12C12 1 1

-

42C12

52C22 2 1
-

C12

Figure 9.7-7 - Fifth-order, Chebyshev, low pass, switched capacitor filter of Example 9.7-5.

Chapter 9 - Switched Capacitor Circuits (6/4/01)

63C23 2 C23

1 2

1 2 Vout(ej) C22

P.E. Allen, 2001

CMOS Analog Circuit Design

Page 9.7-21

EXAMPLE 9.7-5 - Continued Simulated Frequency Response:

0 -10 -20 Stage 1 Output 200 150 Stage 2 Phase Shift (Filter Output) Stage 3 Phase Shift

Magnitude (dB)

Phase (Degrees)

100 50 0 -50 -100 -150

-30 -40 -50 -60 -70 Stage 2 Output (Filter Output)

Stage 3 Output

Stage 1 Phase Shift 0 1500 2000 2500 3000 3500 Frequency (Hz) Figure 9.7-8b - Simulated phase response of Ex. 9.7-5 500 1000

1500 2000 2500 3000 3500 Frequency (Hz) Figure 9.7-8a - Simulated magnitude response of Ex. 9.7-5

500

1000

-200

Comments: There appears to be a sinx/x effect on the magnitude which causes the passband specification to not be satisfied. This can be avoided by prewarping the specifications before designing the filter. Stopband specifications met None of the outputs of the biquads exceeds 0 dB (Need to check internal biquad nodes)

Chapter 9 - Switched Capacitor Circuits (6/4/01) CMOS Analog Circuit Design

P.E. Allen, 2001 Page 9.7-22

EXAMPLE 9.7-5 - Continued SPICE Input File:

******** 08/29/97 13:17:44 ********* *******PSpice 5.2 (Jul 1992) ******** *SPICE FILE FOR EXAMPLE 9.7-5 *EXAMPLE 9-7-5: nodes 5 is the output *of 1st stage, node 13 : second stage (in *the figure it is second while in design it *is third, low Q stage), and node 21 is the *final output of the *filter. **** CIRCUIT DESCRIPTION **** VIN 1 0 DC 0 AC 1 *.PARAM CNC=1 CNC_1=1 CPC_1=1 XNC1 1 2 3 4 NC1 XUSCP1 3 4 5 6 USCP XPC1 5 6 3 4 PC1 XAMP1 3 4 5 6 AMP XPC2 5 6 7 8 PC2 XUSCP2 7 8 9 10 USCP XAMP2 7 8 9 10 AMP XNC3 9 10 11 12 NC3 XAMP3 11 12 13 14 AMP XUSCP3 11 12 13 14 USCP XPC4 13 14 11 12 PC4 XPC5 13 14 7 8 PC2 XPC6 13 14 15 16 PC6 XAMP4 15 16 17 18 AMP XUSCP4 15 16 17 18 USCP XNC7 17 18 19 20 NC7 XAMP5 19 20 21 22 AMP XUSCP5 19 20 21 22 USCP XUSCP6 21 22 15 16 USCP1 XPC8 21 22 15 16 PC6 .SUBCKT DELAY 1 2 3 ED 4 0 1 2 1 TD 4 0 3 0 ZO=1K TD=25US RDO 3 0 1K .ENDS DELAY .SUBCKT NC1 1 2 3 4 RNC1 1 0 11.0011 XNC1 1 0 10 DELAY GNC1 1 0 10 0 0.0909 XNC2 1 4 14 DELAY GNC2 4 1 14 0 0.0909 XNC3 4 0 40 DELAY GNC3 4 0 40 0 0.0909 RNC2 4 0 11.0011 .ENDS NC1 .SUBCKT NC3 1 2 3 4 RNC1 1 0 4.8581 XNC1 1 0 10 DELAY GNC1 1 0 10 0 0.2058 XNC2 1 4 14 DELAY GNC2 4 1 14 0 0.2058 XNC3 4 0 40 DELAY GNC3 4 0 40 0 0.2058 RNC2 4 0 4.8581

Ends NC3
P.E. Allen, 2001

Chapter 9 - Switched Capacitor Circuits (6/4/01)

CMOS Analog Circuit Design

Page 9.7-23

EXAMPLE 9.7-5 - Continued Spice Input File - Continued

.SUBCKT NC7 1 2 3 4 RNC1 1 0 3.2018 XNC1 1 0 10 DELAY GNC1 1 0 10 0 0.3123 XNC2 1 4 14 DELAY GNC2 4 1 14 0 0.3123 XNC3 4 0 40 DELAY GNC3 4 0 40 0 0.3123 RNC2 4 0 3.2018 .ENDS NC7 .SUBCKT PC1 1 2 3 4 RPC1 2 4 11.0011 .ENDS PC1 .SUBCKT PC2 1 2 3 4 RPC1 2 4 4.8581 .ENDS PC2 .SUBCKT PC4 1 2 3 4 RPC1 2 4 6.7980 .ENDS PC4 .SUBCKT PC6 1 2 3 4 RPC1 2 4 3.2018 .ENDS PC6 .SUBCKT USCP 1 2 3 4 R1 1 3 1 R2 2 4 1 XUSC1 1 2 12 DELAY GUSC1 1 2 12 0 1 XUSC2 1 4 14 DELAY GUSC2 4 1 14 0 1 XUSC3 3 2 32 DELAY GUSC3 2 3 32 0 1 XUSC4 3 4 34 DELAY GUSC4 3 4 34 0 1 .ENDS USCP .SUBCKT USCP1 1 2 3 4 R1 1 3 5.5586 R2 2 4 5.5586 XUSC1 1 2 12 DELAY GUSC1 1 2 12 0 0.1799 XUSC2 1 4 14 DELAY GUSC2 4 1 14 0 .1799 XUSC3 3 2 32 DELAY GUSC3 2 3 32 0 .1799 XUSC4 3 4 34 DELAY GUSC4 3 4 34 0 .1799 .ENDS USCP1 .SUBCKT AMP 1 2 3 4 EODD 3 0 1 0 1E6 EVEN 4 0 2 0 1E6 .ENDS AMP .AC LIN 100 10 3K .PRINT AC V(5) VP(5) V(13) VP(13) V(21) VP(21) .PROBE .END

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P.E. Allen, 2001 Page 9.7-24

EXAMPLE 9.7-5 - Continued Switcap2 Input File (The exact same results were obtained as for SPICE)
TITLE: EXAMPLE 9-7-5 OPTIONS; NOLIST; GRID; END; TIMING; PERIOD 50E-6; CLOCK CLK 1 (0 25/50); END; SUBCKT (1 100) STG1; S1 (1 2) CLK; S2 (2 0) #CLK; S3 (3 4) #CLK; S4 (3 0) CLK; S5 (5 100) #CLK; S6 (5 0) CLK; CL11 (2 3) 0.0909; CL21 (3 5) 0.0909; E1 (100 0 0 4) 1E6; END; SUBCKT (200 300) STG2; S1 (200 2) #CLK; S2 (2 0) CLK; S3 (3 0) CLK; S4 (3 4) #CLK; S5 (6 5) CLK; S6 S7 S8 S9 S10 CL12 CL22 CL42 C12 CL52 C22 E1 E2 END; (6 0) (7 0) (7 8) (300 9) (9 0) (2 3) (3 9) (4 300) (4 5) (6 7) (8 300) (5 0 0 4) (300 0 0 8) #CLK; CLK; #CLK; #CLK; #CLK; 0.3123; 0.3123; 0.1799; 1; 0.3123; 1; 1E6; 1E6 CL53 C23 E1 E2 END; (6 7) (8 200) (5 0 0 4) (200 0 0 8) 0.2058; 1; 1E6; 1E6

CIRCUIT; X1 (1 100) X2 (100 200) X3 (200 300) V1 (2 0); END;

STG1; STG3; STG2;

SUBCKT (100 200) STG3; S1 (100 2) #CLK; S2 (2 0) CLK; S3 (3 0) CLK; S4 (3 4) #CLK; S5 (6 5) CLK; S6 (6 0) #CLK; S7 (7 0) CLK; S8 (7 8) #CLK; S9 (200 9) #CLK; S10 (9 0) #CLK; CL13 (2 3) 0.2058; CL23 (3 9) 0.2058; CL63 (9 7) 0.1471; C13 (4 5) 1;

ANALYZE SSS; INFREQ 1 3000 LIN 150; SET V1 AC 1.0 0.0; PRINT vdb(100) vp(100); PRINT vdb(200) vp(200); PRINT vdb(300) vp(300); PLOT vdb(300); END; END;

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CMOS Analog Circuit Design

Page 9.7-25

USING THE CASCADE APPROACH FOR OTHER TYPES OF FILTERS Other types of filters are developed based on the low pass approach.
TLP(j) 1 TPB TSB 0 0 TBP(j) 1 TPB
Transition Region One possible filter realization B

THP(j) 1 TPB

One possible filter realization A

PB SB (a.)
One possible filter realization

TSB (rps) 0 0

Transition Region

SB PB TBS(j) (b.)

(rps)

Lower Transition Region B C

Upper Transition Region

1 TPB (rps)

One possible Lower filter realization Transition Region A C

TSB A D 0 0 SB1 PB1 PB2 SB2 (c.)

Upper TransiTSB B D tion Region 0 (rps) 0 PB1 SB1 SB2 PB2 (d.)

Practical magnitude responses of (a.) low pass, (b.) high pass, (c.) bandpass, and (d.) bandstop filter. We will use transformations from the normalized, low pass filter to the normalized high pass, bandpass or bandstop to achieve other types of filters.

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P.E. Allen, 2001 Page 9.7-26

HIGH PASS, SC FILTERS USING THE CASCADE APPROACH Normalized, low pass to normalized high pass transformation: 1 sln = shn where shn is the normalized, high-pass frequency variable. A general form of the normalized, low-pass transfer function is p1lnp2lnp3lnpNln TLPn(sln) = (sln+p1ln)(sln+p2ln)(sln+p3ln)(sln+pNln) where pkln is the kth normalized, low-pass pole. Applying the normalized, low-pass to high-pass transformation toTLPn(sln) gives shn p1lnp2lnp3lnpNln = THPn(shn) = 1 1 1 1 1 1 1 1 shn+p1ln shn+p2ln shn+p3ln shn+pNln shn+p1ln shn+p2ln shn+p3ln shn+pNln = shn ( shn+p1hn) ( shn+p2hn) ( shn+p3hn) ( shn+pNhn)
N N

where pkhn is the kth normalized high-pass pole. Use the high pass switched capacitor circuits of Secs. 9.5 and 9.6 to achieve the implementation.

n is defined for the high pass normalized filter as:

PB 1 n = = hn SB

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CMOS Analog Circuit Design

Page 9.7-27

EXAMPLE 9.7-7 - Design of a Butterworth, High-Pass Filter Design a high-pass filter having a -3dB ripple bandwidth above 1 kHz and a gain of less than -35 dB below 500 Hz using the Butterworth approximation. Use a clock frequency of 100kHz. Solution From the specification, we know that TPB = -3 dB and TSB = -35 dB. Also, n = 2 (hn = 0.5). = 1 because TPB = -3 dB. Therefore, find that N = 6 will give TSB = -36.12 dB which is the lowest, integer value of N which meets the specifications. Next, the normalized, low-pass poles are found from Table 9.7-1 as p1ln, p6ln = -0.2588 j 0.9659 p2ln, p5ln = -0.7071 j 0.7071 and p3ln, p4ln = -0.9659 j 0.2588 Inverting the normalized, low-pass poles gives the normalized, high-pass poles which are p1hn, p6hn = -0.2588 + j 0.9659 p2hn, p5hn = -0.7071 + j 0.7071 and p3hn, p4hn = -0.9659 + j 0.2588 . We note the inversion of the Butterworth poles simply changes the sign of the imaginary part of the pole.

Chapter 9 - Switched Capacitor Circuits (6/4/01) CMOS Analog Circuit Design

P.E. Allen, 2001 Page 9.7-28

EXAMPLE 9.7-7 - Continued The next step is to group the poles in second-order products, since there are no first-order products. This result gives the following normalized, high-pass transfer function.
shn shn shn THPn(shn) = T1(shn)T2(shn)T3(shn) = (shn+p1hn)(shn+p6hn)(shn+p2hn)(shn+p5hn)(shn+p3hn)(shn+p4hn)
2 2 2

2 2 2 shn shn shn 2 2 2 shn+0.5176shn+1shn+1.4141shn+1shn+1.9318shn+1

Now we are in a position to do the stage-by-stage design. We see that the Qs of each stage are Q1 = 1/0.5176 = 1.932, Q2 = 1/1.414 = 0.707, and Q3 = 1/1.9318 = 0.5176. Therefore, we will choose the low-Q biquad to implement the realization of this example. The low-Q biquad design equations are: K 0T n onTn 1 = , 2 = |5| = onTn, 3 = K2, 4 = K1Tn, and 6 = Q . on For the high pass, K0 = K1 = 0 and K2 = 1, so that 1 = 4 = 0 and 2 = |5| = onTn, 3 = K2 and 6 = Stage 1

onTn Q .

PB 2103 PB 0.06283 21 = 51 = f = 105 = 0.06283, 31 = 1, and 61 = Qf = 1.932 = 0.03252 c c

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CMOS Analog Circuit Design

Page 9.7-29

EXAMPLE 9.7-7 - Continued Stage 2 PB 2103 22 = 52 = f = 105 = 0.06283, c

Stage 3
1 e 33C23 Vin(z)

63C23
2 C23 1 2 1 2

53C23 23C13
2 1

C13 -

V3(z)

Stage 3

PB 2103 23 = 53 = f = 105 = 0.06283, c 33 = 1, and PB 0.06283 63 = Qf = 0.5176 = 0.1214 c

Realization Lowest Q stages are first in the cascade realization. capacitances = 104.62 units of capacitance

2 e V2(z)

52C22 C12
2

62C22
1 2 1

21C12

C22 2 32C22 -

Stage 1
1

61C21
1 2 1 2

51C21 21C11
2 1

31C21 2 C21 -

Chapter 9 - Switched Capacitor Circuits (6/4/01) CMOS Analog Circuit Design

P.E. Allen, 2001 Page 9.7-30

BANDPASS, SC FILTERS USING THE CASCADE APPROACH 1.) Define the passband and stopband as and SW = SB2 - SB1 BW = PB2 - PB1 wherePB2 is the larger passband frequency and PB1 is the smaller passband frequency of the bandpass filter. SB2 is the larger stopband frequency and SB1 is the smaller stopband frequency. 2.) Geometrically centered bandpass filters have the following relationship:

r = PB1 PB2 = SB2 SB1 3.) Define a normalized low-pass to unnormalized bandpass transformation as 2 1 s2 + 2 1 r r b sln = BW s = BW sb + s . b b 4.) A normalized low-pass to normalized bandpass transformation is achieved by dividing the bandpass variable, sb, by the geometric center frequency, r, to get
r sb 1 r 1 sln = BW + (s / ) = BWsbn + sbn r b r

where

sb sbn = .
r

5.) Multiply by BW/r and define yet a further normalization of the low-pass, complex frequency variable as 1 BW sl BW ' sln = sln = bsln = b = sbn + s where b = . bn PB r r ' 6.) Solve for sbn in terms of sln from the following quadratic equation. ' ' sln sln 2 2 ' -1 . sbn - sln sbn + 1 = 0 sbn = 2 2

Chapter 9 - Switched Capacitor Circuits (6/4/01)

P.E. Allen, 2001

C11

+ + + -

PB 0.06283 62 = Qf = 0.707 = 0.08884 c

32 = 1, and

Stage 2
1

2 e

Vout(z)

CMOS Analog Circuit Design

Page 9.7-31

ILLUSTRATION OF THE ABOVE APPROACH

TLPn(jln ) 1 Bandpass Normalization b sln = BW sln s'ln r 1 r ln (rps) PB (a.) TLPn(j'ln ) 1

0 -1 0

0 -b 0 b

1 (b.)

'ln (rps)

Normalized ' s'ln 2 low-pass to sln -1 normalized 2 2 bandpass transformation sbn TBPn (jbn )

TPBn (jb ) 1
BW BW

-r

0 0 (d.)

Bandpass Denormalization sb b sbn = BW sbn r b (rps)

1 b -1 0 0 (c.) b 1 bn (rps)

Figure 9.7-10 - Illustration of the development of a bandpass filter from a low-pass filter. (a.) Ideal normalized, low-pass filter. (b.) Normalization of (a.) for bandpass transformation. (c.) Application of low-pass to bandpass transformation. (d.) Denormalized bandpass filter.

Chapter 9 - Switched Capacitor Circuits (6/4/01) CMOS Analog Circuit Design

P.E. Allen, 2001 Page 9.7-32

BANDPASS DESIGN PROCEDURE FOR THE CASCADE APPROACH 1.) The ratio of the stop bandwidth to the pass bandwidth for the bandpass filter is defined as SW SB2 - SB1 n = BW = . PB2 - PB1 2.) From TPB, TSB, and n, find the order N or the filter. 3.) Find the normalized, low-pass poles, p .
kln

4.) The normalized bandpass poles can be found from the normalized, low pass poles, pkln using pkln pkbn = 2
pkln 2 2 -1 .

For each pole of the low-pass filter, two poles result for the bandpass filter.
j'ln p'jln 'ln p'kln * = p'jln Low-pass Poles Normalized by PB r BW jbn pjbn pkbn bn p* jbn p* kbn Normalized Bandpass Poles

Figure 9.7-11 - Illustration of how the normalized, low-pass, complex conjugate poles are transformed into two normalized, bandpass, complex conjugate poles.

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CMOS Analog Circuit Design

Page 9.7-33

BANDPASS DESIGN PROCEDURE FOR THE CASCADE APPROACH - Continued 5.) Group the poles and zeros into second-order products having the following form K k sbn K k sbn = (s + +j )(s + -j ) Tk(sbn) = * bn kbn kbn bn kbn kbn (sbn + pkbn)(sbn + pjbn) K k sbn = = 2 sbn+(2kbn)sbn+(2bn+ 2 ) kbn
kon Tk(kon) Qk sbn kon 2 2 sbn + Qk sbn + kon

where j and k corresponds to the jth and kth low-pass poles which are a complex conjugate pair, Kk is a gain constant, and

2bn+ 2 kbn . 2bn 6.) Realize each second-order product with a bandpass switched capacitor biquad and cascade in the order of increasing Q. kon =
2 kbn+ 2 kbn

and

Qk =

Chapter 9 - Switched Capacitor Circuits (6/4/01) CMOS Analog Circuit Design

P.E. Allen, 2001 Page 9.7-34

EXAMPLE 9.7-8 - Design of a Cascade Bandpass Switched Capacitor Filter Design a bandpass, Butterworth filter having a -3dB ripple bandwidth of 200 Hz geometrically centered at 1 kHz and a stopband of 1 kHz with an attenuation of 40 dB or greater, geometrically centered at 1 kHz. The gain at 1 kHz is to be unity. Use a clock frequency of 100kHz. Solution From the specifications, we know that TPB = -3 dB and TSB = -40 dB. Also, n = 1000/200 = 5. = 1 because TPB = -3 dB. Therefore, we find that N = 3 will give TSB = -41.94 dB which is the lowest, integer value of N which meets the specifications. Next, we evaluate the normalized, low-pass poles from Table 9.7-1 as p1ln, p3ln = -0.5000 j0.8660 and p2ln = -1.0000 . Normalizing these poles by the bandpass normalization of b = 200/1000 = 0.2 gives p' , p' = -0.1000 j 0.1732 1ln 3ln ' found by using sbn = sln/2 and p' = -0.2000 . 2ln Each one of the p' will contribute a second-order term. The normalized bandpass poles are kln ' sln/2 2 - 1 which results in 6 poles given as follows. For p' = -0.1000 + j0.1732 p1bn, p2bn = -0.0543 + j1.0891, -0.0457 - j0.9159. 1ln For p' = -0.1000 - j0.1732 p3bn, p4bn = -0.0457 + j0.9159, -0.543 - j 1.0891. 3ln For p' = -0.2000 p5bn, p6bn = -0.1000 j 0.9950. 2ln

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CMOS Analog Circuit Design

Page 9.7-35

EXAMPLE 9.7-8 - Continued ' The normalized low-pass pole locations, pkln, the bandpass normalized, low-pass pole locations, pkln , and the normalized bandpass poles, pkbn are shown below. Note that the bandpass poles have very high pole-Qs if BW < r.
jln p1ln
j1 j0.8660

j'ln p1ln p'1ln

j1

p1bn jbn p5bn p3bn

j1

3 zeros at j bn

p2ln
-1 -0.5000

ln

p2ln
-1

p'2ln p'3ln p3ln

-j1

'ln

-1

p2bn p3ln
-j0.8660 -j1

p6bn p4bn

-j1

(a.)

(b.)

(c.)

Figure 2-16 - Pole locations for Ex. 9.7-8. (a.) Normalized low-pass poles. (b.) Bandpass normalized low-pass poles. (c.) Normalized bandpass poles. Grouping the complex conjugate bandpass poles gives the following second-order transfer functions. 1.0904 10.0410 sbn K1sbn K1sbn . T1(sbn) = (s+p1bn)(s+p4bn) = (sbn+0.0543+j1.0891)(sbn+0.0543-j1.0891) = 1.0904 2 sbn+10.0410sbn+1.09042

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P.E. Allen, 2001 Page 9.7-36

EXAMPLE 9.7-8 - Continued K2sbn K2sbn T2(sbn) = (s+p )(s+p = (sbn+0.0457+j0.9159)(sbn+0.0457-j0.9159) = 2bn 3bn) and K3sbn K3sbn T3(sbn) = (s+p )(s+p ) = (s +0.1000+j0.9950)(s +0.1000-j0.9950) = 5bn 6bn bn bn . 1.0000 s2 +5.0000sbn+1.00002 bn
1.0000 5.0000 sbn

. 0.9170 2 sbn+10.0333sbn+0.91592

0.9170 10.0333 sbn

Now we can begin the stage-by-stage design. Note that the Qs of the stages are Q1 = 10.0410, Q2 = 10.0333, and Q3 = 5.0000. Therefore, use the high-Q biquad whose design equations are: K 0T n K1 1 1 = , 2 = | 5| = onT n , 3 = , 4 =Q, and 6 = K2 . on on For the bandpass realization K0 = K2 = 0 and K1 = on/Q, so that the design equations simplify to K1 on/Q 1 on r 1 , 3 = = = Q , 4 =Q, and 6 = 0 . fc on on

1 = 0, 2 = | 5| = on,Tn =
Stage 1

o1 1.09042x103 11 = 61 = 0, 21 = |51| = f = = 0.06815, 31 = 0.09959, and 41 = 0.09959 105 c

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CMOS Analog Circuit Design

Page 9.7-37

EXAMPLE 9.7-8 - Continued Stage 2 12 = 62 = 0,

1 2 e

23C13 C13
1 2

43C13 C23 2

Stage 3
22C12 C12

Stage 3 13 = 63 = 0,

42C12 C22
2

Stage 2
21C11 C11
1 2

Realization

1 2

41C11 C21 2

31C11 -

51C21
1

Stage 1

Chapter 9 - Switched Capacitor Circuits (6/4/01) CMOS Analog Circuit Design

P.E. Allen, 2001 Page 9.7-38

HIGHER ORDER SWITCHED CAPACITOR FILTERS - LADDER APPROACH The ladder approach to filter design starts from RLC realizations of the desired filter specification. These RLC realizations are called prototype circuits. Advantage: Less sensitive to capacitor ratios. Disadvantage: Design approach more complex Requires a prototype realization Singly-terminated RLC prototype filters:
+ Vin (sn ) (a.) + Vin (sn ) (b.) LN,n CN-1,n L3n C2n L1n 1 + Vout (sn ) LN,n CN-1,n C3n L2n C1n 1 + Vout (sn ) -

Figure 9.7-12 - Singly-terminated, RLC prototype filters. (a.) N even. (b.) N odd.

Chapter 9 - Switched Capacitor Circuits (6/4/01)

P.E. Allen, 2001

= 0.06283, 31 = 0.2000, and 41 = 0.2000

o3 1.00002x103 23 = | 53| = f = 105 c

V2(z)

52C22
1

= 0.05755, 32 = 0.09967, and 42 = 0.09967

o2 0.91592x103 22 = | 52| = f = 105 c

Vin(z)

33C13

53C23
1

V3(z)

1 2

32C12

Vout(z)

CMOS Analog Circuit Design

Page 9.7-39

TABLE 9.7-3 - Normalized component values for Fig. 9.7-12 for the Butterworth and Chebyshev singly-terminated, RLC filter approximations.
Use these component designations for even order circuits of Fig. 9.7-12a. C1n L2n C3n L4n C5n L6n C7n L8n C9n 2 0.7071 1.4142 3 0.5000 1.3333 1.5000 Butterworth (1 rps passband) 4 0.3827 1.0824 1.5772 1.5307 5 0.3090 0.8944 1.3820 1.6944 1.5451 6 0.2588 0.7579 1.2016 1.5529 1.7593 1.5529 7 0.2225 0.6560 1.0550 1.3972 1.6588 1.7988 1.5576 8 0.1951 0.5576 0.9370 1.2588 1.5283 1.7287 1.8246 1.5607 9 0.1736 0.5155 0.8414 1.1408 1.4037 1.6202 1.7772 1.8424 1.5628 10 0.1564 0.4654 0.7626 1.0406 1.2921 1.5100 1.6869 1.8121 1.8552 2 0.9110 0.9957 3 1.0118 1.3332 1.5088 1-dB ripple Chebyshev (1 rps passband) 4 1.0495 1.4126 1.9093 1.2817 5 1.0674 1.4441 1.9938 1.5908 1.6652 6 1.0773 1.4601 2.0270 1.6507 2.0491 1.3457 7 1.0832 1.4694 2.0437 1.6736 2.1192 1.6489 1.7118 8 1.0872 1.4751 2.0537 1.6850 2.1453 1.7021 2.0922 1.3691 9 1.0899 1.4790 2.0601 1.6918 2.1583 1.7213 2.1574 1.6707 1.7317 10 1.0918 1.4817 2.0645 1.6961 2.1658 1.7306 2.1803 1.7215 2.1111 L1n C2n L3n C4n L5n C6n L7n C8n L9n Use these component designations for odd order circuits of Fig. 9.7-12b. N

L10n

1.5643

1.3801 C10n

Chapter 9 - Switched Capacitor Circuits (6/4/01) CMOS Analog Circuit Design

P.E. Allen, 2001 Page 9.7-40

EXAMPLE 9.7-9 - Use of the Table 9.7-3 to Find a Singly-Terminated, RLC Low pass Filter Find a singly-terminated, normalized, RLC filter for a 4th-order Butterworth low pass filter approximation. Solution Use Table 9.7-3 with the component designations at the top to get:
L4n =1.5307 H L2n =1.0824 H + Vin (sn ) C3n = 1.5772 F C1n = 0.3827 F 1 + Vout (sn ) -

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CMOS Analog Circuit Design

Page 9.7-41

DOUBLY-TERMINATED RLC PROTOTYPE FILTERS

+ Vin (sn ) (a.) + Vin (sn ) (b.) R LN,n CN-1,n L3n C2n L1n 1 + Vout (sn ) R LN,n CN-1,n C3n L2n C1n 1 + Vout (sn ) -

These structures experience a 6dB loss in the passband.

Chapter 9 - Switched Capacitor Circuits (6/4/01) CMOS Analog Circuit Design

P.E. Allen, 2001 Page 9.7-42

TABLE 9.7-4 - Normalized component values for Fig. 9.7-14 for the Butterworth and 1-dB Chebyshev doubly-terminated RLC approximations.
Use these component designations for even order of Fig. 9.7-14a, R = 1. C1n L2n C3n L4n C5n L6n C7n L8n C9n L10n 2 1.4142 1.4142 3 1.0000 2.0000 1.0000 Butterworth (1 rps passband) 4 0.7654 1.8478 1.8478 0.7654 5 0.6180 1.6180 2.0000 1.6180 0.6180 6 0.5176 1.4142 1.9319 1.9319 1.4142 0.5176 7 0.4450 1.2470 1.8019 2.0000 1.8019 1.2740 0.4450 8 0.3902 1.1111 1.6629 1.9616 1.9616 1.6629 1.1111 0.3902 9 0.3473 1.0000 1.5321 1.8794 2.0000 1.8794 1.5321 1.0000 0.3473 10 0.3129 0.9080 1.4142 1.7820 1.9754 1.9754 1.7820 1.4142 0.9080 0.3129 3 2.0236 0.9941 2.0236 1-dB ripple Chebyshev (1 rps passband) 5 2.1349 1.0911 3.0009 1.0911 2.1349 7 2.1666 1.1115 3.0936 1.1735 3.0936 1.1115 2.1666 9 2.1797 1.1192 3.1214 1.1897 3.1746 1.1897 3.1214 1.1192 2.1797 L1n C2n L3n C4n L5n C6n L7n C8n L9n C10n Use these component designations for odd order of Fig. 9.7-14b, R = 1. N

Note that no solution exists for the even-order cases of the doubly-terminated, RLC Chebyshev approximations for R = 1 . This is a special result for R = 1 and is not true for other values of R.

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CMOS Analog Circuit Design

Page 9.7-43

EXAMPLE 9.7-10 - Use of Table 3-2 to Find a Doubly-Terminated, RLC Low-pass Filter Find a doubly-terminated, RLC filter using minimum capacitors for a fifth-order Chebyshev filter approximation having 1 dB ripple in the passband and a source resistance of 1 . Solution Using Table 9.7-4 and using the component designations at the top of the table gives:
L5n =2.1349 H L3n =3.0009 H L1n =2.1349 H + Vin (sn ) 1 + C4n = 1.0911 F C2n = 1.0911 F 1 Vout (sn ) -

Chapter 9 - Switched Capacitor Circuits (6/4/01) CMOS Analog Circuit Design

P.E. Allen, 2001 Page 9.7-44

FORMULATION OF THE STATE VARIABLES OF A PROTOTYPE CIRCUIT State Variables: The state variables of a circuit can be the current through an element or the voltage across it. The number of state variables to solve a circuit = number of inductors and capacitors inductor cutsets and capacitor loops. An inductor cutset is a node where only inductors are connected. A capacitor loop is a loop where only capacitors are in series. The approach: Identify the correct state variables and formulate each state variable as function of itself and other state variables. Convert this function to a form synthesizable by switched capacitor circuits (i.e. an integrator). A low pass example:
I1 + Vin (sn ) R0n L1n C2n + I3 L3n V2 C4n + I5 L5n V4 R6n + Vout (sn ) -

Fig. 9.7-16 - A fifth-order, low pass, normalized RLC ladder filter. The state variables are I1 , V2, I3, V4, and I5. (The correct state variables will be the currents in the series elements and the voltage across the shunt elements.)

Chapter 9 - Switched Capacitor Circuits (6/4/01)

P.E. Allen, 2001

CMOS Analog Circuit Design

Page 9.7-45

WRITING THE STATE EQUATIONS FOR A RLC PROTOTYPE CIRCUIT Alternately use KVL and KCL for a loop and a node, respectively. Vin(s) - I1(s)R0n - sL1nI1(s) - V2(s) = 0 I1: V2: I3: and V4: I5: I1(s) - sC2nV2(s) - I3(s) = 0 V2(s) - sL3nI3(s) - V4(s) = 0 I3(s) - sC4nV4(s) - I5(s) = 0 V4(s) - sL5nI5(s) - R6nI5n(s) = 0

However, we really would prefer Vout as a state variable instead of I5. This is achieved using Ohms law to get for the last two equations: Vout(s) I3(s) - sC4nV4(s) - R = 0 V4: 6n and sL5nVout(s) Vout: V4(s) - Vout = 0 R6n

Chapter 9 - Switched Capacitor Circuits (6/4/01) CMOS Analog Circuit Design

P.E. Allen, 2001 Page 9.7-46

VOLTAGE ANALOGS OF CURRENT A voltage analog, Vj, of a current Ij is defined as V j = RI j where Ris an arbitrary resistance (normally 1 ohm). Rewriting the five state equations using voltage analogs for current gives: V1: V2: V3: V4: and Vout:
V1(s) Vin(s) - R (R0n + sL1n) - V2(s) = 0 V1(s) V (s) - sC2nV2(s) - 3 R R =0 V3(s) V2(s) - sL3n R - V4(s) = 0 V3(s) Vout(s) R - sC4nV4(s) - R6n = 0

V4(s) -

sL5nVout(s) - Vout = 0 R6n

Chapter 9 - Switched Capacitor Circuits (6/4/01)

P.E. Allen, 2001

CMOS Analog Circuit Design

Page 9.7-47

THE STATE VARIABLE FUNCTIONS Solve for each of the state variables a function of itself and other state variables. R' R0n V1'(s) = sL1n Vin(s) - V2(s) - R' V1'(s) 1 V2(s) = sR'C [V1'(s) - V '(s) ] 3 2n R' V '(s) = sL [V2(s) - V4(s)] 3 3n 1 R' V4(s) = sR'C [V '(s) - R Vout(s)] 3 6n 4n R6n Vout(s) = sL5n [V4(s) - Vout(s)] Note that each of these functions is the integration of voltage variables and is easily realized using the switched capacitor integrators of Sec. 9.3.

Chapter 9 - Switched Capacitor Circuits (6/4/01) CMOS Analog Circuit Design

P.E. Allen, 2001 Page 9.7-48

GENERAL DESIGN PROCEDURE FOR LOW PASS, SC LADDER FILTERS 1.) From TBP, TSB, and n (or APB, ASB, and n) determine the required order of the filter approximation. 2.) From tables similar to Table 9.7-3 and 9.7-2 find the RLC prototype filter approximation. 3.) Write the state equations and rearrange them so each state variable is equal to the integrator of various inputs. 4.) Realize each of rearranged state equations by the switched capacitor integrators of Secs. 9.3.

Chapter 9 - Switched Capacitor Circuits (6/4/01)

P.E. Allen, 2001

CMOS Analog Circuit Design

Page 9.7-49

EXAMPLE 9.7-11 - Fifth-order, Low Pass, Switched Capacitor Filter using the Ladder Approach Design a ladder, switched capacitor realization for a Chebyshev filter approximation to the filter specifications of TBP = -1dB, TSB = -25dB, fPB = 1kHz and fSB = 1.5 kHz. Give a schematic and component value for the realization. Also simulate the realization and compare to an ideal realization. Use a clock frequency of 20 kHz. Adjust your design so that it does not suffer the -6dB loss in the pass band. (Note that this example should be identical with Ex. 9.7-5.) Solution From Ex. 9.7-5, we know that a 5th-order, Chebyshev approximation will satisfy the specification. The corresponding low pass, RLC prototype filter is
L5n =2.1349 H L3n =3.0009 H L1n =2.1349 H + Vin (sn ) 1 + C4n = 1.0911 F C2n = 1.0911 F 1 Vout (sn ) -

Next, we must find the state equations and express them in the form of an integrator. Fortunately, the above results can be directly used in this example. Finally, use the switched-capacitor integrators of Sec. 9.3 to realize each of the five state functions and connect each of the realizations together.

Chapter 9 - Switched Capacitor Circuits (6/4/01) CMOS Analog Circuit Design

P.E. Allen, 2001 Page 9.7-50

EXAMPLE 9.7-11 - Continued R' R0n L1n: V1'(sn) = s L1n Vin(sn) - V2(sn) - R' V1'(sn)
n

(1)

11C1 Vin(ej) +
1 2 2

C1 V' (ej) 1

This equation can be realized by the switched capacitor integrator of Fig. 9.7-17 which has one noninverting input and two inverting inputs. Using the results of Sec. 9.3, we can write that 1 V 1(z) = z-1 11Vin(z) - 21zV2(z) - 31zV1(z) . (2) However, since fPB < fc, replace z by 1 and z-1 by sT. Further, let us use the normalization defined earlier to get 1 V 1(sn) s T 11Vin(s) - 21V2(s) - 31V1(s) . n n

21C1 V2(ej)
2 1

31C1 V'1(ej)
2 1 1

Figure 9.7-17 - Realization of V1'.

(3)

Equating Eq. (1) to Eq. (3) gives the design of the capacitor ratios for the first integrator as RTn R PB 12000 11 = 21 = L = f L = 20,0002.1349 = 0.1472
1n c 1n

and

R0nTn R 0n PB 12000 31 = L = f L = 20,0002.1349 = 0.1472 . 1n c 1n

Assuming that R0n = R = 1. Also, double the value of 11 (11 = 0.2943) in order to gain 6dB and remove the -6dB of the RLC prototype. The total capacitance of the first integrator is 1 2(0.1472) First integrator capacitance = 2 + 0.1472 + 0.1472 = 10.79 units of capacitance.

Chapter 9 - Switched Capacitor Circuits (6/4/01)

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CMOS Analog Circuit Design

Page 9.7-51

V'3(ej)

2 1

Figure 9.7-18 - Realization of V2.

Simplifying as above gives 1 V2(sn) s T 12V1 (sn) - 22V3(sn) . n n Equating Eq. (4) to Eq. (6) yields the design of the capacitor ratios for the second integrator as Tn PB 2000 12 = 22 = RC = Rf C = 120,0001.0911 = 0.2879. 2n c 2n The second integrator has a total capacitance of 1 Second integrator capacitance = 0.2879 + 2 = 5.47 units of capacitance.

Chapter 9 - Switched Capacitor Circuits (6/4/01) CMOS Analog Circuit Design

P.E. Allen, 2001 Page 9.7-52

EXAMPLE 9.7-11 - Continued R' V '(s n ) = s L3n [V2(sn) - V4(sn)] L3n: 3 n

(7)

13C3 V2(ej) 1 2 2

V4(ej)

2 1

Figure 9.7-19 - Realization of V3'.

Equating Eq. (7) to Eq. (9) yields the capacitor ratios for the third integrator as RTn R PB 12000 13 = 23 = L = f L = 20,0003.0009 = 0.1047. 3n c 3n The third integrator has a total capacitance of 1 Third integrator capacitance = 0.1047 + 2 = 11.55 units of capacitance

Chapter 9 - Switched Capacitor Circuits (6/4/01)

P.E. Allen, 2001

Eq. (7) can be realized by the switched capacitor integrator of Fig. 9.7-19 which has one noninverting input and one inverting input. For this circuit we get 1 (8) V 3(z) = z-1 [ 13V2 (z) - 23zV4(z) ] . Simplifying as above gives 1 V 3(sn) s T [ 13V2(sn) - 23V4(sn) ] . n n

23C3

This equation can be realized by the switched capacitor integrator of Fig. 9.7-18 which has one noninverting input and one inverting input. As before we write that 1 (5) V2(z) = z-1 12V1 (z) - 22zV3(z) .

22C2

EXAMPLE 9.7-11 - Continued 1 V2(sn) = s R'C2n [V1'(sn) - V '(s n )] C2n: 3 n

12C2

(4)

V'1(ej)

1 2

C2 V (ej) 2

(6)

C3 V' (ej) 3

(9)

CMOS Analog Circuit Design

Page 9.7-53

EXAMPLE 9.7-11 - Continued 1 R' C4n: V4(sn) = s R'C4n [V '( sn) - R6n Vout(sn)] (10) 3
n

14C4 V'2(ej) +
1 2 2

C4 V (ej) 4

Eq. (10) can be realized by the switched capacitor integrator of Fig. 9.7-20 with one noninverting and one inverting Vout(ej) input. As before we write that 1 V4(z) = z-1 14V3 (z) - 24zVout(z) . (11) Assuming that fPB < fc gives 1 V4(sn) s T 14V3 (sn) - 24Vout(sn) . n n (12)

24C4
2 1 1

Figure 9.7-20 - Realization of V4.

Equating Eq. (10) to Eq. (12) yields the design of the capacitor ratios for the fourth integrator as Tn PB 2000 14 = 24 = RC = Rf C = 120,0001.0911 = 0.2879. 4n c 4n if R = R0n. In this case, we note that fourth integrator is identical to the second integrator with the same total integrator capacitance.

Chapter 9 - Switched Capacitor Circuits (6/4/01) CMOS Analog Circuit Design

P.E. Allen, 2001 Page 9.7-54

EXAMPLE 9.7-11 - Continued R6n L5n: Vout(sn) = s L5n [V4(sn) - Vout(sn)]

n

15C5 V4(ej) 1 2 2

C5 V (ej) out

(13) 25C5 The last state equation, Eq. (13), can be realized by the switched capacitor integrator of Fig. 9.7-21 which has one Vout(ej) 2 1 1 noninverting input and one inverting input. For this circuit we get 1 Figure 9.7-21 - Realization of Vout. (14) Vout(z) = z-1 [ 15V4 (z) - 25zVout(z) ] . Simplifying as before gives 1 (15) Vout(sn) s T [ 15V4(sn) - 25Vout(sn)] . n n Equating Eq. (13) to Eq. (15) yields the capacitor ratios for the fifth integrator as R6nTn R 6n PB 12000 15 = 25 = L = f L = 20,0002.1349 = 0.1472 3n c 3n where R6n = 1. The total capacitance of the fifth integrator is 1 Fifth integrator capacitance = 0.1472 + 2 = 8.79 units of capacitance We see that the total capacitance of this filter is 10.79 + 5.47 + 11.53 + 5.47 + 8.79 = 42.05. We note that Ex. 9.7-5 which used the cascade approach for the same specification required 49.10 units of capacitance.
+

Chapter 9 - Switched Capacitor Circuits (6/4/01)

P.E. Allen, 2001

CMOS Analog Circuit Design

Page 9.7-55

EXAMPLE 9.7-11 - Continued

Vin(ej)

31C1
1 211C1 2 2 1 2

Final realization of Ex. 9.7-11.

C1 1 2 1 2 1 2 1

1 2

21C1
1 2

V'1(ej)
2

C2 -

12C2 1 22C2 C3 1 2

1 2

13C3 23C3

C4 -

14C2 1
2

1 2

15C5 25C5

Chapter 9 - Switched Capacitor Circuits (6/4/01) CMOS Analog Circuit Design

EXAMPLE 9.7-11 - Continued Simulated Frequency Response:

10 0 -10
Magnitude (dB)

200 V1' Output

Phase Shift (Degrees)

150 100 50 0 -50 -100 -150 -200 V1' Phase V4 Phase V2 Phase V3' Phase

V2 Output V3' Output V4 Output Filter Output

-20 -30 -40 -50 -60 -70 0 500 1000

1500 2000 2500 Frequency (Hz)

3000

3500

500

Comments: Both passband and stopband specifications satisfied. Some of the op amp outputs are exceeding 0 dB (need to voltage scale for maximum dynamic range)

Chapter 9 - Switched Capacitor Circuits (6/4/01)

V4(ej)

1 2

V2(ej)

V'3(ej)

24C4 C5
1 2

Vout(ej)

P.E. Allen, 2001 Page 9.7-56

Filter Phase

1000

1500 2000 2500 Frequency (Hz)

3000

3500

P.E. Allen, 2001

CMOS Analog Circuit Design

Page 9.7-57

EXAMPLE 9.7-11 - Continued SPICE Input File:

******* 08/29/97 13:12:51 ********* ******PSpice 5.2 (Jul 1992) ******** **** CIRCUIT DESCRIPTION **** *SPICE FILE FOR EXAMPLE 9.7_5 *Example 9.7-8 : ladder filter *Node 5 is the output at V1' *Node 7 is the output at V2 *Node 9 is the output of V3' *Node 11 is the output of V4 *Node 15 is the final output VIN 1 0 DC 0 AC 1 ************************** * V1' STAGE XNC11 1 2 3 4 NC11 XPC11 7 8 3 4 PC1 XPC12 5 6 3 4 PC1 XUSC1 5 6 3 4 USCP XAMP1 3 4 5 6 AMP ************************** *V2 STAGE XNC21 5 6 19 20 NC2 XPC21 9 10 19 20 PC2 XUSC2 7 8 19 20 USCP XAMP2 19 20 7 8 AMP ************************** *V3' STAGE XNC31 7 8 13 14 NC3 XPC31 11 12 13 14 PC3 XUSC3 9 10 13 14 USCP XAMP3 13 14 9 10 AMP ************************** *V4 STAGE XNC41 9 10 25 26 NC2 XPC41 15 16 25 26 PC2 XUSC4 11 12 25 26 USCP XAMP4 25 26 11 12 AMP ************************** *VOUT STAGE XNC51 11 12 17 18 NC1 XPC51 15 16 17 18 PC1 XUSC5 15 16 17 18 USCP XAMP5 17 18 15 16 AMP ************************* .SUBCKT DELAY 1 2 3 ED 4 0 1 2 1 TD 4 0 3 0 ZO=1K TD=25US RDO 3 0 1K .ENDS DELAY .SUBCKT NC1 1 2 3 4 RNC1 1 0 6.7934 XNC1 1 0 10 DELAY GNC1 1 0 10 0 .1472 XNC2 1 4 14 DELAY GNC2 4 1 14 0 .1472 XNC3 4 0 40 DELAY GNC3 4 0 40 0 .1472 RNC2 4 0 6.7934 .ENDS NC1

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EXAMPLE 9.7-11 - Continued SPICE Input File:

.SUBCKT NC11 1 2 3 4 RNC1 1 0 3.3978XNC1 1 0 10 DELAY GNC1 1 0 10 0 .2943 XNC2 1 4 14 DELAY GNC2 4 1 14 0 .2943 XNC3 4 0 40 DELAYGNC3 4 0 40 0 .2943 RNC2 4 0 3.3978 .ENDS NC11 .SUBCKT NC2 1 2 3 4 RNC1 1 0 3.4730 XNC1 1 0 10 DELAY GNC1 1 0 10 0 .2879 XNC2 1 4 14 DELAY GNC2 4 1 14 0 0.2879 XNC3 4 0 40 DELAY GNC3 4 0 40 0 0.2879 RNC2 4 0 3.4730 .ENDS NC2 .SUBCKT NC3 1 2 3 4 RNC1 1 0 9.5521 XNC1 1 0 10 DELAY GNC1 1 0 10 0 0.1047 XNC2 1 4 14 DELAY GNC2 4 1 14 0 0.1047 XNC3 4 0 40 DELAY GNC3 4 0 40 0 0.1047 RNC2 4 0 9.5521 .ENDS NC3 .SUBCKT NC4 1 2 3 4 RNC1 1 0 3.4730 XNC1 1 0 10 DELAY GNC1 1 0 10 0 .2879 XNC2 1 4 14 DELAY GNC2 4 1 14 0 .2879 XNC3 4 0 40 DELAY GNC3 4 0 40 0 .1472 RNC2 4 0 6.7955 .ENDS NC4 .SUBCKT PC1 1 2 3 4 RPC1 2 4 6.7934 .ENDS PC1 .SUBCKT PC2 1 2 3 4 RPC1 2 4 3.4730 .ENDS PC2 .SUBCKT PC3 1 2 3 4 RPC1 2 4 9.5521
.ENDS PC3

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CMOS Analog Circuit Design

Page 9.7-59

EXAMPLE 9.7-11 - Continued Switcap2 Input File (The results are exactly the same as for the SPICE simulation)
TITLE: EXAMPLE 9-7-11 OPTIONS; NOLIST; GRID; END; TIMING; PERIOD 50E-6; CLOCK CLK 1 (0 25/50); END; SUBCKT (1 4) NC (P:CAP); S1 (1 2) CLK; S2 (2 0) #CLK; S3 (3 0) CLK; S4 (3 4) #CLK; C11 (2 3) CAP; END; SUBCKT (1 4) PC (P:CAP1); S1 (1 2) #CLK; S2 (2 0) CLK; S3 (3 0) CLK; S4 (3 4) #CLK; C21 (2 3) CAP1; END; CIRCUIT /***** V1 STAGE ****/ X11 (1 2) NC (0.2943); X12 (3 2) PC (0.1472); X13 (4 2) PC (0.1472); E11 (4 0 0 2) 1E6; C11 (2 4) 1; /***** V2 STAGE ****/ X21 (1 2) NC (0.2879); X22 (3 2) PC (0.2879); E21 (3 0 0 6) 1E6; C21 (6 3) 1; /***** V3 STAGE ****/ X31 (3 8) NC (0.1047); X32 (7 8) PC (0.1047); E31 (5 0 0 8) 1E6; C31 (8 5) 1; /***** V4 STAGE ****/ X41 (5 9) NC (0.2879); X42 (100 9) PC (0.2879); E41 (7 0 0 9) 1E6; C41 (9 7) 1; /***** VOUT STAGE ****/ X51 (7 10) NC (0.1472); X52 (100 10) PC (0.1472); E51 (100 0 0 10) 1E6; C51 (10 100) 1; V1 (1 0); END; ANALYZE SSS; INFREQQ 20 3000 LOG 80; SET V1 AC 1.0 0.0; PRINT VDB(4) VP(4) VDB(3); PRINT VP(3) VDB(7) VP(7); PRINT VDB(100) VP(100); PLOT VDB(100); END; END;

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P.E. Allen, 2001 Page 9.7-60

HIGH PASS SWITCHED CAPACITOR FILTERS USING THE LADDER APPROACH High pass, switched capacitor filters using the ladder approach are achieved by applying the following normalized, low pass to normalized, high pass transformation on the RLC prototype circuit. 1 sln = shn This causes the following transformation on the inductors and capacitors of the RLC prototype:
Lln Cln sln s1 hn Chn = 1 Lln Lhn = 1 Cln Normalized HighPass Network

Normalized LowPass Network

Design Procedure: 1.) Identify the appropriate RLC prototype, low pass circuit to meet the specifications. 2.) Transform each inductor and capacitor by the normalized, low pass to high pass transformation. 3.) Choose the state variables and write the state functions. 4.) Realize the state functions using switched capacitor circuits. The problem: The realizations are derivative circuits.

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CMOS Analog Circuit Design

Page 9.7-61

SWITCHED CAPACITOR DERIVATIVE CIRCUIT

C1 Vin(z) C1
2 1 C2 2 1

Vout(z)

Vin(z) C1

2 2

1
-

1 1
+

2
Vout(z)

Vin(z) C1
2

C2 Vout(z) C2 + (c.) -

(a.)

Figure 9.7-26 - (a.) Switched capacitor differentiatior circuit. (b.) Stray insensitive version of (a.). (c.) Modification to keep op amp output from being discharged to ground during 1.

Transfer function:

1: (n-1)T < t < (n -0.5)T

o e vc1(n -0.5)T = vin(n -1)T and o vc2(n -0.5)T = 0

vin(n)

C1 e C1 e C1 e e Vout(z) = C V in(z) - z-1 C V in(z) = - C (1-z-1)Vin(z) 2 2 2

Hee(z) =

Vout(z)

= - C (1-z-1) e 2 V in(z)

C1

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P.E. Allen, 2001 Page 9.7-62

FREQUENCY RESPONSE OF THE DERIVATIVE CIRCUIT Replace z by ejT to get, C1 C1 ejT/2 - e-jT/2 C1 = - C ( 2j sin(T/2)) ( e-jT/2) Hee(ejT) = - C ( 1 - e-jT) = - C j T/2 e 2 2 2 or =jTC1 sin(/2) -j sin(/2) -jT/2 -j/2) = ( e ) = (Ideal)x(Mag. Error)x(Phase Error) C2 /2 ( o /2

where o = C2/(C1T). Frequency Response for C2 = 0.2C1:

|Hee(ejT) 5 10 1 0 Continuous Time Discrete Time -90 Phase 0 c c 2 Continuous Time Discrete Time

-180 -270

c 0 o= 10

c 2

Chapter 9 - Switched Capacitor Circuits (6/4/01)

P.E. Allen, 2001

2: (n-0.5)T < t < (n )T C1 e C1 e e vout(n )T = - C vin(n )T + C vin(n -1)T 2 2

(b.)

C1
e

vin(n-1)

C2

e vout(n)

CMOS Analog Circuit Design

Page 9.7-63

EXAMPLE 9.7-12 - High Pass, Switched Capacitor Ladder Filter Design a high pass, switched capacitor ladder filter starting from a third-order, normalized, low pass Butterworth prototype filter. Assume the cutoff frequency is 1kHz and the clock frequency is 100kHz. Use the doubly terminated structure. Solution A third-order prototype filter transformed to the normalized high pass filter is shown below.
R0n =1 Vin L1n =1H C2n =2F L3n =1H R0n =1 I1 C1hn =1F C3hn =1F I3

s = 1 + ln shn R4n Vout Vin =1 -

+ + L2hn R Vout V2 4n =0.5H =1 -

State Variable Eqs: I1 R0n V in = I1R 0n + s C + V2 I1 = snC1hn [Vin - I1R0n - V2] V1 = snC1hnR [Vin - R V1-V2] n 1hn V2 V2 Vout I1 = s L + I3 = s L + R n 2hn n 2hn 4n I3 V 2 = s C + I3R4n n 3hn Vout V2 = snL2hn [I1 - R ] 4n V1 Vout V2 = snL2hn[ R - R ] 4n

I3 = snC3hn [V2 - I3R4n]

Vout = snR4nC3hn [V2 - Vout]

Problem! Derivative circuit only has inverting inputs. Solution? 1.) Use inverters. 2.) Rearrange the equations to get integrators where possible (they will have nonintegrated inputs). 3.) Redefine the polarity of the voltages at internal nodes (180 phase reversal).

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P.E. Allen, 2001 Page 9.7-64

EXAMPLE 9.7-12 - Continued Make the first equation into an integrator, reverse the sign of V2 and V1, and use one inverter. Note that V1 = - V1 andV2 = - V2 . Therefore the rewrite the first state equation as: - V 1 R0n -V1 R R V1=snC1hnR [Vin - R V1 -V2] V1=s C R +R (Vin -V2) V1 =s C R -R (Vin + V2 ) n 1hn 0n 0n n 1hn 0n 0n V1 Vout V2 = snL2hn[ R - R ] 4n Vout = snR4nC3hn [- V2 - Vout] C1hn: This state equation can be realized by the SC integrator shown with two inverting unswitched inputs. We may write that: -11z V1 (z) = z -1 V1 (z) - 21Vin(z) - 31 V2 (z) Assuming that z -1 sT and z 1, we write that -11 V1 (s) sT V1 (s) - 21Vin(s) - 31 V2 (s) Normalizing this equation gives,
31C1 V2 Vin V1 ' 21C1 11C1 + C1 V1 '

V2 = -snL2hn[ R

- V 1

V Vout V out 1 - R ] V2 =-snL2hn R + R 4n 4n

2 1

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CMOS Analog Circuit Design

Page 9.7-65

-11 V1 (sn) s T V1 (sn) -21Vin(sn) -31 V2 (sn) n n 1

Tn 2103 11 = R C = = 0.06283, 21 = 31 = 1105 0n 1hn

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P.E. Allen, 2001 Page 9.7-66

EXAMPLE 9.7-12 - Continued L2hn: This state eq. can be realized by the SC differentiator circuit shown with two inputs. We may write that: V2(z) = -(1-z-1)[12 V1 (z) + 22Vout(z)] V2(s) -sT [12 V1 (s) + 22Vout(s)] Normalizing T by PB gives V2(sn) = -snTn
V1'

12C2

C2

[12 V1 (sn) + 22Vout(sn)] L2hn 0.5105 12 = 22 = T = 2103 = 7.9577 if R = R0n = 1. n L2hn: This state equation can be realized by the SC differentiator circuit shown with two inputs. We may write that: Vout(z) = -(1-z-1)[13 V2 (z) + 23Vout(z)] Vout(s) -sT [13 V2 (s) + 23Vout(s)]

13C3 V2 Vout 23C3

2 1 1
+ -

C3

1 2

Normalizing T by PB gives Vout(sn) = -snTn [13 V2 (sn) + 23Vout(sn)] R4nC3hn 1105 = 2103 = 15.915 if R4n = 1. 13 = 23 = T n capacitances = 100.49 units of capacitance

Chapter 9 - Switched Capacitor Circuits (6/4/01)

P.E. Allen, 2001

Vout 22C2

2 1 1
+ -

V2

V2

1 2

Vout

CMOS Analog Circuit Design

Page 9.7-67

BANDPASS SWITCHED CAPACITOR FILTERS USING THE LADDER APPROACH Bandpass switched capacitor ladder filters are obtained from low pass RLC prototype circuits by applying the normalized, low pass to normalized bandpass transformation given as
r sb 1 r 1 sln = BW + (s / ) = BWsbn + sbn r b r

This causes the following transformation on the inductors and capacitors of the RLC prototype:
Lbn = Lln Cln sn r sbn + s1 BW bn r L C = BW 1 ln bn r Lln BW Cbn = r C BW ln

Normalized Low-Pass Network

Lbn = BW 1 r Cln Normalized Bandpass Network

Design Procedure: 1.) Identify the appropriate RLC prototype, low pass circuit to meet the specifications. 2.) Transform each inductor and capacitor by the normalized, low pass to bandpass transformation. 3.) Choose the state variables and write the state functions. 4.) Realize the state functions using switched capacitor circuits. In this case, the state functions will be second-order, bandpass functions which can be realized by the second-order circuits of Sec. 9.6.

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P.E. Allen, 2001 Page 9.7-68

EXAMPLE 9.7-13 - Design of a Fourth-Order, Butterworth Bandpass Switched Capacitor Ladder Filter Design a fourth-order, bandpass, switched capacitor ladder filter. The filter is to have a center frequency (r) of 3kHz and a bandwidth (BW) of 600 Hz. The clock frequency is 128kHz. Solution The low pass normalized prototype filter is shown (Note that this form is slightly different than the form used in Table 9.7-4) Applying the transformation illustrated in Fig. 9.7-27 gives The state equations for this circuit can be written as illustrated below. V1(s) Vin(s) = I2(s) + Z R0n + 1bn V1(s) where Z1bn V1(s) = R [Vin(s) - I2(s)R0n - V1(s)] 0n sL1bn(1/sC1bn) s/C1bn s/C1bn Z1bn = sL + (1/sC ) = 2 = 2 1bn 1bn s + (1/L1bnC1bn) s +1 V1(s) = s/R0nC1bn s2 + 1 R0n V (s) R V2(s) - V1(s) in (1)
+ Vin (sn ) R0n =1 + Vin (sn ) R0n C1bn = BWC r 1ln C3n = 1.8478F L2n=1.8478H L 4n=0.7659H + R5n =1 + Vout (sn )

C1n = 0.7659F = L2bn = BWL 2ln C2bn L 1 L4bn = BWL4ln C4bn= 1 r 2bn r L 4bn + V1 I2 L 1bn= C3bn = 1 C1bn BWC r 3ln + V3 I4 L 3bn= 1 C3bn +

R5n Vout (sn ) -

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CMOS Analog Circuit Design

Page 9.7-69

EXAMPLE 9.7-13 - Continued I2(s) = Y2bn[V1(s) - V3(s)] V2(s) =

sR/L2bn [V1(s) - V3(s)] s 2+1

(2)

s/RC3bn V2(s) Vout(s) R V3(s) = Z3bn(I2(s)-I4(s)) = Z3bn R - R V3(s) = 2 V2(s)- R Vout 5n s +1 5n and I4(s) =Y4bn[V3(s)-Vout(s)] Vout(s) = R5nY4bn[V3(s)-Vout(s)] or sR5n/L4bn

(3)

[V3(s)-Vout(s)] (4) s 2+1 The design of the state equations requires a re-examination of the low-Q and high-Q biquad circuits. Close examination of the above state equations and these biquads shows that the high-Q biquad can only have inverting inputs. Therefore, we shall use the low-Q biquad to realize the above state equations because it can have both inverting and noninverting inputs. For the low-Q biquad, if we let 1 = 3 = 6 = 0, we get

Vout(s) =

4s - T Hee(s) 2 5 s 2+ 2 T

Normalizing by n gives

4sn - T n Hee(sn) 2 5 sn2+ T n2 r2

fr 2 = (2)2f fc2 c

We see that all 2s and 5s will be given as:

2 5 = Tn2 = n2T 2 =

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P.E. Allen, 2001 Page 9.7-70

EXAMPLE 9.7-13 - Continued 2fr 23x103 Therefore, let 2 = | 5 | = f = = 0.1473 c 128x105 Now all that is left is to design 4 for each stage (assuming R0n = R5n = R = 1). Also, the sum of capacitances per stage will be: | 5 | 4 2 2 capacitances/stage = + + + x (no. of inputs) min min min min Stage 1 Tn 41 rBW 1 2600 41 = R C = f C = = 0.03848 Tn = R0nC1bn 0n 1bn c r 1ln 128x1030.7658 There will be one noninverting input (Vin) and two inverting inputs (V2 and V1). 2 2(0.1437) capacitances = 0.03848 + 0.03848 + 3 = 62.44 units of capacitance Stage 2 T nBW 42 rBW R 2600 =L 42 = L = f L = = 0.01594 Tn 2bn r 2ln c r 2ln 128x1031.8478 There will be one noninverting input (V1) and one inverting input (V3). 2 2(0.1437) capacitances = 0.01594 + 0.01594 + 2 = 145.50 = units of capacitance Stage 3 Same as stage 2. 43 = 0.01594 There will be one noninverting input (V2) and one inverting input (Vout). capacitances = 145.50 units of capacitance

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CMOS Analog Circuit Design

Page 9.7-71

EXAMPLE 9.7-13 - Continued Stage 4 Same as stage 1. 44 = 0.03848. There will be one noninverting input (V3) and one inverting input (Vout). capacitances = 61.44 units of capacitance. Total capacitance of this example is 414.88 units of capacitance. Realization: C
5 2

C1

2C1 1

2 2

C2 -

Using this
C Vin 1 41 21 2 41C21 41C21 2 V' 2 22 = 52 = 0.1473 1 43C23 43C23 2 23 = 53 = 0.1473 1
2

21 = 51 = 0.1473 2

Chapter 9 - Switched Capacitor Circuits (6/4/01) CMOS Analog Circuit Design

GENERAL APPROACH TO DESIGNING SWITCHED CAPACITOR LADDER FILTERS

Choose State Variables Write State Equations Use SC Integrators to Design Each State Equation Low Pass Switched Capacitor Filter

Normalized LP to Normalized High pass Transformation Low pass Prototype RLC Ckt. Eliminate L-cutsets and C-loops Normalized LP to Normalized Bandpass Transformation

Normalized LP to Normalized Bandpass Transformation

Chapter 9 - Switched Capacitor Circuits (6/4/01)

+ 1
Choose State Variables Write State Equations Choose State Variables Write State Equations Normalized LP to Normalized High pass Transformation Choose State Variables

2 1

2 2,5

Ex.9.7-13B

simplification gives:
Vout 24 = 52 = 0.1473 2

1 1 2 V1 V3 C C C C 2 42 22 42 22 1 2 44 42 44 42 1

P.E. Allen, 2001 Page 9.7-72

Use SC Differentiators to Design Each State Equation

High Pass Switched Capacitor Filter

Use SC BP Ckts. to Design Each State Equation

Bandpass Switched Capacitor Filter

Write State Equations

Use SC BS Ckts. to Design Each State Equation

Bandstop Switched Capacitor Filter

P.E. Allen, 2001

CMOS Analog Circuit Design

Page 9.7-73

ANTI-ALIASING IN SWITCHED CAPACITOR FILTERS A characteristic of circuits that sample the signal (switched capacitor circuits) is that the signal passbands occur at each harmonic of the clock frequency including the fundamental.
T(j) T(j0) T(jPB) Anti-Aliasing Filter

2c-PB c+PB 2c+PB Baseband c-PB 0 c 2c -PB 0 PB Figure 9.7-28 - Spectrum of a discrete-time filter and a continuous-time anti-aliasing filter.

The primary problem of aliasing is that there are undesired passbands that contribute to the noise in the desired baseband.

Chapter 9 - Switched Capacitor Circuits (6/4/01) CMOS Analog Circuit Design

P.E. Allen, 2001 Page 9.7-74

NOISE ALIASING IN SWITCHED CAPACITOR CIRCUITS In all switched capacitor circuits, a noise aliasing occurs from the passbands that occur at the clock frequency and each harmonic of the clock frequency.
Magnitude

fc-fB -fB fc+fB 0.5fc fc 0 fsw fB Figure 9.7-31 - Illustration of noise aliasing in switched capacitor circuits.

It can be shown that the aliasing enhances the baseband noise voltage spectral density by a factor of 2fsw/fc. Therefore, the baseband noise voltage spectral density is
kT/C 2fsw 2kT eBN2 = f x f = f C volts2/Hz sw c c

; ;

From higher bands Noise Aliasing Baseband

fc-fsw

;; ;;

fc+fsw f

Multiplying this equation by 2fB gives the baseband noise voltage in volts(rms)2. Therefore, the baseband noise voltage is 2kT 2fB 2kT /C 2kT vBN2 = f C ( 2fB) = C f = OSR volts(rms)2 c c where OSR is the oversampling ratio.

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CMOS Analog Circuit Design

Page 9.7-75

SIMULATION OF NOISE IN SWITCHED CAPACITOR FILTERS The noise of switched capacitor filters can be simulated using the above concepts. 1.) Convert the switched capacitor filter to a continuous time equivalent filter by replacing each switched capacitor with a resistor whose value is 1/(fcC). 2.) Multiply the noise of this resistance by 2fB/fc, to make the resulting noise to approximate that of the switched capacitor filter. Unfortunately, simulators like SPICE do not permit the multiplication of the thermal noise. Another approach is to assume that the resistors are noise-free and build a noise generator that represents the effect of the noise of vBN2. 1.) Put a zero dc current through a resistor identical to the one being modeled. 2.) A voltage source that is dependent on the voltage across this resistor can be placed at the input of an op amp to implement vBN2. The gain of the voltage dependent source should be 2fB/fc. 3.) Model all resistors that represent switched capacitors in the same manner. The resulting noise source model along with the normal noise sources of the op amp will serve as a reasonable approximation to the noise in a switched capacitor filter.

Chapter 9 - Switched Capacitor Circuits (6/4/01) CMOS Analog Circuit Design

P.E. Allen, 2001 Page 9.7-76

CONTINUOUS TIME ANTI-ALIASING FILTERS Sallen and Key, Unity Gain, Low Pass Filter:
C2 R1 R3 C4 Vout (s)
Voltage Amplifier

Vin (s)

K=1

K=1

(a.)

(b.)

Fig. 9.7-29 - (a.) A second-order, low pass active filter using positive feedback. (b.) The realization of the voltage amplifier K by the noninverting op amp configuration. Transfer function: K TLP(0) o2 R1R3C2C4 Vout(s) = = 1 1 K 1 Vin(s) 1 o s 2 + s R3C4 + R1C2 + R3C2 - R3C4+ R1R3C2C4 s 2 + Q s + o2 We desire K = 1 in order to not influence the passband gain of the SCF. Therefore, with K = 1, 1 R1R3C2C4 Vout(s) 1/mn(RC)2 = s 2 + (1/RC)[(n+1)/n]s + 1/mn(RC)2 1 1 1 Vin(s) = 2 s + s R1C2 + R3C2 + R1R3C2C4 and C4 = mC2 = mC. where R3 = nR1 = nR

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CMOS Analog Circuit Design

Page 9.7-77

DESIGN EQS. FOR THE UNITY GAIN, SALLEN AND KEY LOW PASS FILTER Equating Vout(s)/Vin(s) to the standard second-order low pass transfer function, we get two design equations which are 1 o = mnRC m 1 Q = (n +1) n The approach to designing the components of Fig. 9.7-29a is to select a value of m compatible with standard capacitor values such that 1 m 4Q 2 . Then, n, can be calculated from n= 1 1 - 1 2mQ 2 2mQ 2 1-4mQ 2 .

This equation provides two values of n for any given Q and m. It can be shown that these values are reciprocal. Thus, the use of either one produces the same element spread.

Chapter 9 - Switched Capacitor Circuits (6/4/01) CMOS Analog Circuit Design

P.E. Allen, 2001 Page 9.7-78

EXAMPLE 9.7-9 - Application of the Sallen-Key Anti-Aliasing Filter Use the above design approach to design a second-order, low-pass filter using Fig. 9.7-7a if Q = 0.707 and fo = 1 kHz Solution We see that m should be less than 0.5 for this example. Let us choose m = 0.5. m = 0.5 n = 1. These choices guarantee that Q = 0.707. 1 to find the RC product RC = 0.225x10-3. Now, use o = mnRC At this point, one has to try different values to see what is best for the given situation (typically the area required). Let us choose C = C2 = 500pF. This gives R = R1 = 450k. Thus, C4 = 250pF and R3 = 450k. It is readily apparent that the anti-aliasing filter will require considerable area to implement.

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Page 9.7-79

A NEGATIVE FEEDBACK, SECOND-ORDER, LOW PASS ANTI-ALIASING FILTER Another continuous-time filter suitable for anti-aliasing filtering is shown in Fig. 9.7-30. This filter uses frequency-dependent negative feedback to achieve complex conjugate poles.

R1=

1 2|TLP(0)|oQC

R2 =

1 2oQC

C5=C + P.E. Allen, 2001 Page 9.7-80 P.E. Allen, 2001 -

Vin
C4= 4Q2(1+|TLP(0)|)C

R3= 1 2(1+|TLP(0)|)oQC

Vout

Figure 9.7-30 - A negative feedback realization of a second-order, low pass filter.

This gain of this circuit in the passband is determined by the ratio of R2/R1.

Chapter 9 - Switched Capacitor Circuits (6/4/01) CMOS Analog Circuit Design

EXAMPLE 9.7-10 - Design of A Negative Feedback, Second-Order, Low-Pass Active Filter Use the negative feedback, second-order, low-pass active filter of Fig. 9.7-30 to design a low-pass filter having a dc gain of -1, Q = 1/ 2 , and fo = 10kHz. Solution Let us use the design equations given on Fig. 9.7-30. Assume that C5 = C = 100pF. Therefore, we get C4 = (8)(0.5)C = 400pF. The resistors are R1 = R2 = and 2 R3 = (2)(6.2832)(2)(10-6) = 56.27 k . Unfortunately we see that because of the passive element sizes that anti-aliasing filters will occupy a large portion of the chip. 2 = 112.54 k . (2)(1)(6.2832)(10-6) 2 = 112.54 k . (2)(6.2832)(10-6)

Chapter 9 - Switched Capacitor Circuits (6/4/01)

CMOS Analog Circuit Design

Page 9.7-81

SUMMARY Switched capacitor circuits have reached maturity in CMOS technology. The switched capacitor circuit concept was a pivotal step in the implementation of analog signal processing circuits in CMOS technology. The accuracy of the signal processing is proportional to capacitor ratios. Switched capacitor circuits have been developed for: Amplification Integration Differentiation Summation Filtering Comparing Analog-digital conversion Approaches to switched capacitor circuit design: Oversampled approach - clock frequency is much greater than the signal frequency z-domain approach - specifications converted to the z-domain and directly realized, can operate to within half of the clock frequency Switched capacitor circuits can be simulated in the frequency domain by SPICE or SWITCAP Clock feedthrough and kT/C noise represent the lower limit of the dynamic range of switched capacitor circuits.

Chapter 9 - Switched Capacitor Circuits (6/4/01)

P.E. Allen, 2001