Analog VLSI Interview

Questions
A Practical Question Set for Students
Satya Sai Kommana

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FIRST EDITION
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Contents

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I Passive Circuits
1 First and Second Order Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.1 Prerequisites 6
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1.2 RC Circuits 6
1.3 RL Circuits 14
1.4 RLC Circuits 17
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II Active Circuits
2 Single Stage Amplifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
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2.1 Prerequisites 20
2.2 CS,CD,CG amplifiers 20
2.3 5T-OTA Analysis 29
2.4 Differential Amplifiers 32

3 Two Stage OP-amp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

3.1 Prerequisites 35
3.2 Questions 35
4 Op-amp Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
4.1 Prerequisites 37
4.2 Questions 37

5 Current Mirrors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
5.1 Prerequisites 47
5.2 Questions 47

6 Noise Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

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6.1 Prerequisites 51
6.2 Questions 51

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7 Switched Capacitor Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
7.1 Prerequisites 53

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7.2 Questions 53

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Band-gap refrence Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
8.1 Prerequisites 58
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8.2 Questions 58

III Miscellaneous
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9 Miscellaneous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
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9.1 Questions 60

Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
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About the Book
This book is a carefully collected set of real interview questions from Analog VLSI job
interviews. These questions are based on the actual experiences of students from different
IITs and NITs, who were interviewed by various semiconductor companies.
The main goal of this book is to help students build confidence. By solving many
different types of questions on the same topic, students can learn to look at a concept from
different angles. This helps develop a deeper and stronger understanding — which is very
important for success in Analog VLSI interviews.
No new or artificial questions have been added by the author, as the intention is to give
students a clear understanding of actual interview scenarios. Every question included is

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relevant and highlights key concepts that are essential for Analog VLSI engineers.

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About the Author
Satya Sai Kommana completed his M.Tech from IIT Kharagpur with a specialization
in Instrumentation and Integrated Electronics, Department of Electrical Engineering. He

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was the topper of the specialization (2023–2025) and is currently working as an Analog
Design Engineer at a reputed company. m
I would like to express my sincere gratitude to everyone who generously shared their
valuable experience and contributed to this work. My heartfelt thanks also go to those who
supported me and helped make this possible.
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If you have any suggestions, would like to contribute to this material, or if you find any
mistakes, please feel free to get in touch.

Contact Information:
• LinkedIn: https://www.linkedin.com/in/satya-sai-kommana-909451252/
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• Email: satyasaikommana@kgpian.iitkgp.ac.in

About the Second and Third Editions

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In the Second Edition, we plan to include:

• Detailed solutions for all questions
• Additional questions collected from fresh interview experiences
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• Improved formatting and layout for better readability

Due to time constraints during the first edition, diagrams were not drawn for all questions
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and were directly pasted from the source. The main focus of this edition was on collecting
questions.
In the Third Edition, we aim to make the learning experience even more interactive by:
• Providing recorded video solutions and embedding clickable links next to each
solution that redirect to the specific video for that solution.
This feature is designed to make learning more intuitive, efficient, and student-friendly.

First release August 2025

I
Passive Circuits

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1 First and Second Order Circuits . . 6

1.1 Prerequisites
1.2 RC Circuits
1.3 RL Circuits
1.4 RLC Circuits
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1. First and Second Order Circuits

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1.1 Prerequisites
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1. Introduction to Electrical Sciences (Passive Devices) - ES by Chembiyan T.
2. Basics of Signals for Transient Analysis by Himanshu Agarwal.
3. Prep For Interview || RC-RL-RLC-LC by Himanshu Agarwal.
4. Interesting Analysis on the Order of a Circuit || Prep for Interview by Himanshu Agarwal.
5. Transient Response of ALL RL Circuits With Current Source || VLSI Placements Interview
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Questions by Anish Saha.

1.2 RC Circuits
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1. Find the time constant and draw 𝑉out for all three cases.
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2. a) Find the transfer function by inspecting the circuit.

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b) Explain intuitively why the zero is located at − 𝑅𝐶 .
c) Draw 𝑉out for the case when 𝑇2 ≫ 𝜏, where 𝜏 = 𝑅𝐶 is the time constant.
d) Draw 𝑉𝑥 and 𝑉out after a diode is added, for 𝑇2 ≫ 𝜏.
 1.2 RC Circuits 7

3. Is it possible for the output voltage 𝑉out to exceed the supply voltage 𝑉DD in practical

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scenarios? If so, under what conditions, and how is it achieved?

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4. Draw 𝑉out intuitively.

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5. Draw 𝑉out intuitively.

 8 Chapter 1. First and Second Order Circuits

6. Draw 𝑉out and follow up question was why is it trying to settle towards 𝑉dd /2. Draw 𝑉out
after adding 𝐶2 .

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7. Draw 𝑉out intuitively.

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8. Draw 𝑉out for all four cases and observe the differences between the outputs.
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9. Draw 𝑉out for all four figures with the following input types: (a) DC input and (b) square
pulse input, under the following conditions:
(i) 𝑅𝐶 ≫ 𝜏, (ii) 𝑅𝐶 ≪ 𝜏, (iii) 𝑅𝐶 = 𝜏.
Observe the differences between the outputs.
 1.2 RC Circuits 9

10. Find poles and zeros and draw bode plot.

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11. (a) Find the time constant 𝜏 of the given circuit.
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(b) Plot 𝑉𝑜 for a step input.Explain intuitively what would happen by observing the circuit,
without using any mathematics.
(c) Change the input from a step input to a pulse input, and plot 𝑉𝑜 for the following
conditions: (i) 𝑅𝐶 ≫ 𝜏, (ii) 𝑅𝐶 ≪ 𝜏, (iii) 𝑅𝐶 = 𝜏.
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(d) Plot 𝑉𝑜 for Impulse and ramp input.

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12. (a) Find the output voltage 𝑉𝑜 (𝑡) for the given circuit.Explain intuitively what would
happen by observing the circuit, without using any mathematics.
(b) Determine the time constant 𝜏 of the circuit.
(c) Intuitively analyze the poles and zeros of the circuit.
(d) Find the transfer function of the circuit intuitively.
(e) Draw the Bode plot.
(f) If we substitute 𝑠 = − 1𝜏 (where 𝜏 is the time constant of the circuit), it appears that
the transfer function becomes infinite. Why is this not reflected in the Bode plot?
(g) What element can be added to the existing circuit to make the response obtained in
Case (a) faster or to eliminate the delay in reaching steady state?
 10 Chapter 1. First and Second Order Circuits

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13. (a) Find the output voltage 𝑉𝑜 for the following cases: (i) 𝑅1𝐶1 > 𝑅2𝐶2 , (ii) 𝑅1𝐶1 < 𝑅2𝐶2 ,
(iii) 𝑅1𝐶1 = 𝑅2𝐶2 .

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(b) Explain why the voltage 𝑉𝑜 jumps at the beginning of the input.
(c) Determine the order of the system and explain.
(d) What is the 3 dB bandwidth of the circuit?
(e) The response obtained in (a) for the case 𝑅1𝐶1 = 𝑅2𝐶2 shows no delay or zero rise

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time. Then, what does the time constant in (d) represent?
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14. (a) Find the poles and zeroes of the system.

(b) Determine the order of the system.
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(c) Find the output voltage 𝑉𝑜 (𝑡).

(d) Determine whether 𝑉𝑜 (∞) = 𝑉𝑖 is possible or not.
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15. Draw the waveforms of 𝑉out and 𝐼out , and clearly mark important points on the plots.
 1.2 RC Circuits 11

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16. For a sawtooth current input 𝐼in , what will be the output voltage 𝑉𝑜 waveform?

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17. The capacitor is precharged to 𝑉𝑐𝑜 . Plot 𝑉𝑜 , 𝑉𝑐 .

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18. Plot 𝑉𝑜 , 𝐼𝑐 .
 12 Chapter 1. First and Second Order Circuits

19. A pulse input with a period of 100 ns has an on-time and off-time of 50 ns. The value of
𝑅 = 1 kΩ and all capacitors 𝐶 = 20 pF.
(a) Draw 𝑖1 and 𝑉o .
(b) Find the discharge rate of the capacitor 𝐶 that is in parallel with 𝑅.

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20. Find the poles and zeros of the circuit. Plot 𝑉𝑜 for step and impulse inputs.Explain
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21. Steady-state response of 𝑉𝑜 .

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22. Plot 𝑉𝑜
 1.2 RC Circuits 13

23. Explain the significance of poles and zeros in any system, and how to find them.What is
their effect on the behavior of systems or circuits?
24. Draw 𝑉𝑜 (𝑡) for 𝑡 > 0 given that 𝐼 (𝑡) = 𝑢(𝑡).

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25. Plot 𝑉𝑜 for the two types of 𝐼 (𝑡) shown below. These types of questions are conventionally
dealt with by writing voltage and current equations in the time domain, but an interviewer

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may also ask you to establish the relationship in the frequency domain using the Laplace
transform.

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26. Plot 𝑉𝑥 . Plot the current through both resistors. Explain intuitively what would happen by
observing the circuit, without using any mathematics. Also find the time constant.
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27. Determine the output voltage 𝑉𝑜 (𝑡) for the circuit shown below.
 14 Chapter 1. First and Second Order Circuits

28. The two circuits are equivalent. Express 𝑅 𝑝 and 𝐶 𝑝 in terms of 𝑅𝑠 and 𝐶𝑠 . Determine the
frequency range 𝜔 for which the two circuits are equivalent, assuming a high quality factor
(Q).

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29. Plot the output voltage 𝑉out as a function of time based on the given circuit conditions.

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1.3 RL Circuits
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1. (a) Find the order of the circuit with and without capacitor 𝐶.
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(b) Draw 𝑉out and find the steady-state current through 𝑅, with and without capacitor 𝐶.
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2. Draw 𝑉o
 1.3 RL Circuits 15

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3. Draw the output waveform intuitively.

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4. Find 𝑉𝑜 at steady state. Plot 𝑉𝐴 , 𝑉𝐵 , and 𝑖 𝐿 .

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5. Plot 𝑉𝐴 , 𝑉𝐵 , and 𝑖 𝐿 .

6. Plot 𝑉𝐴 , 𝑉𝐵 , and 𝑖 𝐿 . Find the time constant. (Observe the direction of the current source in
the circuit.)
 16 Chapter 1. First and Second Order Circuits

7. Plot 𝑉𝐴 , 𝑉𝐵 , and 𝑖 𝐿 .

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8. Given: 𝐿 = 1 H, 𝑅 = 1 Ω, diode on-voltage = 1 V. A 1 V pulse is applied to the switch
from 𝑡 = 0 to 𝑡 = 1 s. A 2 V step is applied at 𝑡 = 0 s to 𝑉 (or 𝑉𝐷𝐷 ).
(a) 𝐼 𝐿 (𝑡 = 2 s) = ?
(b) Plot 𝐼 𝐿 (𝑡).
(c) Find the slope of 𝐼 𝐿 between 𝑡 = 1 s and 𝑡 = 2 s.
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9. For the given circuit, plot the inductor current 𝑖 𝐿 (𝑡) and the inductor voltage 𝑉𝐿 (𝑡).
 1.4 RLC Circuits 17

10. (a) Plot the output voltage 𝑉𝑜 .

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(b) Determine the time constant of the circuit.
(c) If the circuit has a finite time constant, explain why the output 𝑉𝑜 resembles a step
voltage.

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(d) Alternatively, an interviewer may ask:
Using the calculated time constant, draw the Bode plot of the circuit.
(e) Follow-up question:
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(Assume your answer indicates a low-pass filter characteristic.) If the circuit exhibits
a low-pass filter response, why does the output contain all the frequency components
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of the input signal, despite the low-pass behavior?

1.4 RLC Circuits

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1. Why 𝑉out is oscillating and at t=0+ what is the voltage across capacitor and without any
mathematics justify how it will give sine waveform.
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2. a. Draw the frequency response.

b. Indicate the slopes in the response.
c. Determine the impedance 𝑍 at resonance.
d. Calculate the quality factor (𝑄).
e. Identify the peak of the frequency response plot.
 18 Chapter 1. First and Second Order Circuits

3. Plot the frequency response.

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4. Draw the Bode plot for the complex pole 𝑠 = −1 + 10 𝑗.
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II
Active Circuits

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m Single Stage Amplifiers . . . . . . . . . . 20
2.1 Prerequisites
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2.2 CS,CD,CG amplifiers
2.3 5T-OTA Analysis
2.4 Differential Amplifiers

3 Two Stage OP-amp . . . . . . . . . . . . . . 35

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3.1 Prerequisites
3.2 Questions

4 Op-amp Circuits . . . . . . . . . . . . . . . . . 37
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4.1 Prerequisites
4.2 Questions
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5 Current Mirrors . . . . . . . . . . . . . . . . . . . . 47
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5.1 Prerequisites
5.2 Questions

6 Noise Analysis . . . . . . . . . . . . . . . . . . . . 51
6.1 Prerequisites
6.2 Questions

7 Switched Capacitor Circuits . . . . 53

7.1 Prerequisites
7.2 Questions

8 Band-gap refrence Circuits . . . . . 58

8.1 Prerequisites
8.2 Questions
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2. Single Stage Amplifiers

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2.1 Prerequisites
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1. Razavi Electronics 1 by Prof. Behzad Razavi
2. Razavi Electronics 2 by Prof. Behzad Razavi
3. Electronics – Analog IC Design by Prof. Nagendra Krishnapura
4. Chapters 1–5 from the textbook Design of Analog CMOS Integrated Circuits (2nd Edition)
by Behzad Razavi
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5. MOS Structure and MOSCAP — Das Sir (Initial lectures – deep explanation at design
level)

2.2 CS,CD,CG amplifiers

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1. Find overall gain?

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 2.2 CS,CD,CG amplifiers 21

2. Find out the equivalent impedence.

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3. Find the opamp terminals for negative feedback. then find 𝑉o .

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4. Find the equivalent resistance 𝑅eq . Replace 𝑍1 and 𝑍2 with capacitors 𝐶1 and 𝐶2 ,
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respectively, and determine the new equivalent resistance 𝑅eq .
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5. Find 𝑍in in all three cases (let 𝜆 = 0).

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6. Find the gain and plot the frequency response of common-source (CS), common-drain
(CD), and common-gate (CG) amplifiers.
7. Explain channel length modulation from a device-level point of view.
 22 Chapter 2. Single Stage Amplifiers

8. Find 𝑍in ? (You are not allowed to use the small-signal circuit. You should answer without
lengthy math.)

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9. Draw the common-source (CS) amplifiers you know. After drawing them, explain the
differences between the circuits and the reasons for moving from one circuit to another.
10. Voltage drop across drain to source for large values of 𝑉𝐺𝑆 .
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11. When the overdrive voltage 𝑉𝑂𝑉 = 100 mV, 𝐼 𝐷 = 100 𝜇A, and 𝑉𝑡ℎ = 0.1 V, determine 𝑉𝑜 .
(Do not solve it with unnecessary lengthy calculations.)
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12. (a) Draw the frequency response.

(b) Find the locations of the poles and zeros.
 2.2 CS,CD,CG amplifiers 23

13. (a) Draw the inverter characteristics.

(b) Design an inverter such that the output will be high for an input voltage of 1V.
𝑉𝐷𝐷 = 3V.
(c) Draw the output of the three circuits shown below.

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(d) Can we use an inverter as an amplifier? If yes, how?

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(e) Where should it be biased, and how should it be biased? (Answer: Place a resistor
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(f) What is the difference between the circuits shown below?
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14. Do you recognize this circuit? What is the name of the circuit? Explain its working
principle.
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Note: The figure provided may contain an error. Either the op-amp terminals need to be
reversed, or the transistor should be a PMOS instead of an NMOS for the circuit to function
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correctly.
Analyze the operation of the circuit under the following two scenarios:
(a) When the op-amp terminals are reversed.
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(b) When a PMOS transistor is used in place of the NMOS transistor.

 24 Chapter 2. Single Stage Amplifiers

15. (a) Draw a simple amplifier.

(b) What is the gain?
(c) How can the gain be increased? List different techniques and their limitations.
(d) How can the bandwidth be increased?
16. What happens to 𝑉th with an increase in temperature? Give an intuitive explanation.
17. Draw the cross-sectional view of a MOSFET and explain its structure.Why is specific
doping used at particular regions for PMOS and NMOS devices?Explain the variation of
capacitance under different operating conditions, and why these variations occur.
18. Draw a Common-Gate amplifier and explain its working and voltage gain.Convert the
current source to a voltage source and set 𝑅𝑠 = 0. Find the poles and zeros of this modified

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circuit.

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19. Which MOSFET will enter the triode region first if 𝑉𝑥 decreases?
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20. Draw the cascode amplifier and find its gain.List techniques to further increase the gain.Draw
the gain-boosted circuit and find its gain.
21. a) Find the gain.
 2.2 CS,CD,CG amplifiers 25

b) Plot 𝑉out for a pulse input.

c) Find the pole at the output.
d) Find the pole considering 𝐶𝑔𝑠 .
22. Write the current equation of a MOSFET in the triode region.
23. How does the threshold voltage (𝑉𝑡ℎ ) change with an increase in temperature?
24. How does the mobility (𝜇𝑛 ) change with an increase in temperature?
25. What happens to the overall saturation current of a MOSFET if the temperature increases?
26. Draw the cross-sectional view of an NMOS transistor. Show all the capacitances and
determine their values.
27. Without writing equations, explain how the body voltage affects the drain current (𝐼 𝐷 ) of a

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MOSFET.
28. The gain of the NMOS transistor is 𝐺 1 , and the gain of the PMOS transistor is 𝐺 2 . If their

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outputs are shorted together, determine the resulting small-signal gain of the combined
configuration.

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29. (a) Draw the cross-sectional view of an NMOS transistor structure, labeling all regions
including the gate, source, drain, channel, oxide, and substrate.
(b) Explain the behavior of the NMOS transistor for the following gate-to-source voltage
(𝑉𝐺𝑆 ) conditions:
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• 𝑉𝐺𝑆 < 0
• 0 < 𝑉𝐺𝑆 < 𝑉𝑡ℎ
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• 𝑉𝐺𝑆 > 𝑉𝑡ℎ

(c) Identify the key parameters that influence the threshold voltage 𝑉𝑡ℎ of an NMOS
transistor.
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(d) Discuss the impact on threshold voltage 𝑉𝑡ℎ when the body voltage 𝑉𝐵 is made positive
as compared to when 𝑉𝐵 = 0.
(e) Draw and label all the parasitic capacitances associated with the NMOS structure
from part (a), including gate-to-source, gate-to-drain, and gate-to-body capacitances.
(f) Derive and present the expressions for the intrinsic capacitances in both the linear
(triode) and saturation regions of operation.
(g) Define the pinch-off condition in an NMOS transistor. Explain how pinch-off affects
the 𝐼 𝐷 vs. 𝑉𝐷𝑆 characteristics.
(h) Describe the relationship between channel length, output resistance 𝑟 𝑜 , and drain
current 𝐼 𝐷 . Discuss how short-channel effects influence these parameters.
30. Calculate the output impedance of the given circuit.
 26 Chapter 2. Single Stage Amplifiers

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31. (a) If the inverter is biased at the midpoint of 𝑉DD , what is its small-signal gain?

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(b) Draw the cross-sectional diagram of a CMOS inverter. Clearly indicate the contacts
for power supply (𝑉DD ) and ground (𝐺 𝑁 𝐷).
(c) Using the cross-sectional diagram from part (b), illustrate how parasitic BJTs can
form within the structure, potentially leading to latch-up.
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(d) Describe the methods used to prevent latch-up in CMOS technology. Include
techniques such as guard rings and clamping circuits.
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(e) Draw the layout of a CMOS inverter or a standard logic gate such as NOR or NAND.
Clearly label the PMOS and NMOS regions, polysilicon gates, diffusion areas, and
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metal interconnects.
32. For the given circuits with 𝑉DD = 5 V, determine the output voltages 𝑉𝑜1 and 𝑉𝑜2 for the
following input voltages:
𝑉in = 5 V, 3 V, 2.5 V, 0 V.
 2.2 CS,CD,CG amplifiers 27

33. What is the effective resistance from source to drain for each of the following two transistors?
(Assume the given resistance value is 𝑅.)

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34. For the given circuit, if the input 𝑉𝑖 is a rail-to-rail square wave, sketch the waveform after
the inverter and the output 𝑉𝑜 . Assume 𝑉DD is the supply voltage.

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35. For the following circuit, the threshold voltage of the transistor is 0.7 V. Given 𝑉𝐵1 = 1 V
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and 𝑉𝐵2 = 2 V, plot the current flow through the transistors as a function of the input
voltage 𝑉in , as 𝑉in varies from 5 V to 0 V. (This question was provided by Wang Ge.)
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36. For the following circuit, the small-signal input is 𝐼in and the small-signal output is 𝑣 out .
Determine the small-signal output expression and calculate the corresponding gain.
 28 Chapter 2. Single Stage Amplifiers

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37. Determine the gain of the following circuit. Assume the electron mobility 𝜇𝑛 = 2𝜇 𝑝 , where
𝜇 𝑝 is the hole mobility.

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38. (a) Determine the gain of the circuit.

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(b) What is the output voltage (𝑉out ) for the given input signals 𝑉in and 𝑉𝑏 ?
 2.3 5T-OTA Analysis 29

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(c) Draw the output frequency spectrum, clearly marking the exact magnitudes of each
component.

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Hint: Use the Fourier transforms of sine and square waves.

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2.3 5T-OTA Analysis m
1. If load and parasitic capacitance are not present at 𝑉out in the 5T-OTA shown below:
(a) What happens to the pole at 𝑉out ?
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(b) Now, what is the dominant pole?
(c) Draw the frequency response without using any mathematical calculations. Explain
qualitatively.
(d) Find the Norton’s equivalent current.
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2. Draw a 5T-OTA and a folded cascode op-amp. What happens if there is a mismatch in the
threshold voltage (𝑉th ) of the NMOS and PMOS transistors in both circuits?
3. For the output offset to be zero, what is the required input offset when there is a threshold
voltage (𝑉th ) mismatch between transistors 𝑀3 and 𝑀4 ?
 30 Chapter 2. Single Stage Amplifiers

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4. (a) Find the gain of the circuit.
(b) Determine the input common-mode range (ICMR) and output swing of the circuit.
(c) How do you connect the circuit so that it becomes a unity follower? Find its step
response.

m
(d) Find the transfer function in the mid-frequency range after adding the capacitor 𝐶.
m
i Ko
Sa
a

5. Draw the step response of the circuit.

ty
Sa

6. Let 𝑎, 𝑏, 2𝑎, and 2𝑏 be transistor names. The 𝑟 ds of all transistors is neglected.

Hint: You may assume 𝑖 is the signal current through transistor 𝑎.
(a) Find the signal current through all transistors. With 𝑟 ds , what is the signal current
through 𝑟 ds2𝑏 ?
 2.3 5T-OTA Analysis 31

(b) Find 𝑉𝑥 , 𝑉𝑜1 , and 𝑉𝑜2 when 𝑉in is a small signal.

(c) What happens if the signal is applied at the 𝑉𝐷𝐷 node? Find 𝑉𝑥 , 𝑉𝑜1 , and 𝑉𝑜2 .

a
an
m
𝑉out
7. For the following circuit, determine the voltage gain 𝑉in . Identify the location of the
feedback and explain its function within the circuit.
m
i Ko
Sa
a

8. Determine the slew rate of the output voltage for the given circuit or system.
ty
Sa

9. Calculate 𝐼out as a function of 𝑉in , 𝑔𝑚𝑛 , 𝑔𝑚 𝑝 , and Δ𝑉.

 32 Chapter 2. Single Stage Amplifiers

a
an
2.4 Differential Amplifiers
1. Draw 𝑉𝑂1 , 𝑉𝑂2 , and 𝑉𝑥 versus time (𝑡) for a large 𝑉IN signal. Assume all current sources
are ideal.

m
m
i Ko
Sa
a
ty

2. Find the DC gain and the unity-gain bandwidth (UGB).

Sa

𝐴𝑜,𝑑𝑚
3. If 𝑔𝑚1 ≠ 𝑔𝑚2 , what will be the value of 𝐴𝑖,𝑐𝑚 for the circuit?
 2.4 Differential Amplifiers 33

a
𝑉𝑥 𝑉𝑦
4. Determine 𝑉𝑖𝑛 and 𝑉𝑖𝑛 . Assume channel length modulation.

an
m
m
Ko

5. (a) Draw an op-amp circuit using MOSFETs.

(b) In a differential amplifier with a tail current source and resistive load 𝑅 𝐿 , how can we
replace the current source and 𝑅 𝐿 with other circuitry? Can 𝑅 𝐿 be replaced by a BJT?
i
Sa

6. a) Find ICMR+ and ICMR− .

a
ty
Sa

b) What happens if 𝑀3 is a practical current source?

c) Analyze the circuit with 𝑅 𝐷 mismatch.
𝑉𝐴
7. Both transistors are biased in the saturation region. Calculate the ratio 𝑉in , neglecting the
body effect.
 34 Chapter 2. Single Stage Amplifiers

a
an
8. (a) What is the voltage gain of each circuit?
(b) What technology or layout technique can be used to improve the matching of the input
transistors?
(c) If the bias current is increased, what effect does it have on the gain? (Hint: Gain

m
decreases!)
(d) What happens to the bandwidth when the bias current is increased?
(e) List the advantages and disadvantages of the two amplifier configurations shown.
m
(f) Now replace the NMOS transistors with NPN BJTs, and the PMOS transistors with
PNP BJTs. Answer the above questions again for this bipolar implementation.
Note: In this case, the gain remains approximately constant with increasing bias
Ko

current.
i
Sa
a
ty
Sa
 a
3. Two Stage OP-amp

an
m
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3.1 Prerequisites
Ko
1. Feedback and Stability by Analog Snippets
2. Analog IC Design by Prof. Nagendra Krishnapura

3.2 Questions
i
Sa

1. Explain the design procedure of a two-stage operational amplifier.

2. Explain the working of the circuit.
3. What is compensation?
4. Why is Miller compensation used?
a

5. What do you mean by unity gain bandwidth?

6. Does the unity-gain frequency change after a Miller capacitor is added?
ty

7. Write the expression for the Unity-Gain Bandwidth (UGB).

8. What are the locations of the poles and zeros?
9. How are mirror poles and zeros formed?
Sa

10. Where is the second pole located? Explain how its value is derived.
11. Explain pole splitting and its issues.
12. What happens to the output impedance of the second stage after introducing the compensa-
tion capacitor (𝐶𝑐 )?
13. How can the CMRR be improved?
14. How can you improve the phase margin of the circuit?
15. How do you cancel the RHZ and derive the conditions?
16. How much is the effective capacitance at the mirror node?
17. What if there is a mismatch?
18. What do you mean by a common-mode signal?
19. Draw the unity-gain buffer configuration using an op-amp. If there is a mismatch in the
 36 Chapter 3. Two Stage OP-amp

input transistors, what do you expect at the output?

20. How did you design the bias current values in the two stages? Should the overdrives of the
bias current sources necessarily be equal?
21. How did you ensure that all MOSFETs are in saturation?
22. What are the critical noise sources?
23. Draw the internal structure of a two-stage op-amp. Identify the contributions of poles and
zeros, and explain their effects. What parasitics contribute to the formation of mirror poles
and zeros? Include the Bode plot of the same.
24. Explain the Miller Effect and the need for compensation in op-amps.
25. What is the slew rate?

a
26. What is the slew rate (SR) if the compensation capacitor (𝐶𝑐 ) is not present?
27. Find the input voltage swing.

an
28. What is phase margin, and why is 𝐶𝑐 used?

m
m
i Ko
Sa
a
ty
Sa
 a
4. Op-amp Circuits

an
m
m
4.1 Prerequisites
Ko
1. Analysis of Opamp Circuits by Chembiyan T
2. Prep for Interview by Himanshu Agarwal (Lectures 26 to 39)
3. Analog Electronics GATE Notes/Material
i
Sa

4.2 Questions
1. (a) Find the output resistance with and without 𝑅.
a

(b) Find the input resistance.

(c) Find the input and output resistance after 𝑅 is added between the input terminals.
ty
Sa

2. Find gain of the circuit?

 38 Chapter 4. Op-amp Circuits

a
3. (a) Draw 𝑉out vs 𝑉in when 𝑉in varies from −1 V to 1 V.
(b) What is the value of 𝑉out at 𝑉in = −∞?

an
(c) Draw the hysteresis characteristics and find the trip points without using pen and
paper.

m
m
i Ko

4. Mark the terminals of OP-amp for operating in negative feedback and find overall gain.
Sa
a
ty
Sa

5. For the given circuit, plot the output response for the following cases: (i) 𝑉sat = ±∞ (ii)
𝑉sat = ±15 V.
Moreover, if the duty cycle of the input is 60%, determine the rise time (𝑡rise ) and fall time
(𝑡fall ) from the plot.
 4.2 Questions 39

6. Find the condition for oscillation and the frequency of oscillation, where 𝐺 is the gain of

a
the circuit.

an
m
7. Find 𝑉o .
m
i Ko
Sa

8. (a) How can you obtain a triangular wave from a square wave?
a
ty
Sa

(b) Consider that your answer is an op-amp integrator. What happens after 𝑉𝑜 reaches
𝑉max and the input still persists? Draw 𝑉𝑜 for this situation.
 40 Chapter 4. Op-amp Circuits

9. In a practical network, there is a problem with ground potential differences due to cable
resistances (here, 𝑅4 , 𝑅5 , and 𝑅6 ). All the ground nodes (𝐺 1 , 𝐺 2 , 𝐺 3 , and 𝐺 4 ) have
different potentials in practice. How can this problem be resolved? Hint: Use an op-amp
to solve this problem. When using an op-amp, which feature of the op-amp should be
considered most carefully?

a
an
m
m
10. What will be the output voltage 𝑉𝑜 for the given three input signals 𝑉𝑖1 , 𝑉𝑖2 , and 𝑉𝑖3 ?
i Ko
Sa
a
ty
Sa

11. (a) Design a circuit to convert a given square wave to a trapezoidal waveform.
Hint: Use clipper circuits to clip the voltage at 𝑉max .
 4.2 Questions 41

(b) Determine whether the circuit shown below will function as intended to convert the
square wave into a trapezoidal waveform.

a
an
m
12. Assume an ideal diode with 𝑒𝑛 = 1. What is the value of 𝑉𝑂 ? Will the diode conduct at
m
any point as the input voltage varies from 0 to 𝑉𝐷𝐷 ? Clearly explain the analysis.
i Ko
Sa
a
ty
Sa

13. Plot 𝑉𝑜 and 𝑉𝐴 , and write the equation for 𝑉𝐴 (𝑡).

 42 Chapter 4. Op-amp Circuits

14. (a) Plot 𝑉𝑜 and 𝑉 − .

(b) If 𝜏𝐿 (time constant due to 𝐶 𝐿 ) < 𝜏int (time constant due to 𝐶int ), then plot 𝑉𝑜 and 𝑉 − .

a
an
m
m
(c) Plot the output of a second-order system (critically damped, over-damped, under-
damped) in the time domain and relate to cases a and b.
Ko
(d) Can you make the system critically damped? How? (Hint: Increase delay or decrease
delay. We can decrease delay by decreasing 𝑅1 , 𝑅2 , but the feedback factor should not
change, as shown in the figure below). Now plot 𝑉𝑜 and 𝑉 − after 𝑅1eq , 𝑅2eq decrease.
What are the issues in this approach?
i
Sa
a
ty
Sa

(e) Let’s say we have designed a mobile phone and it got rejected. Can you guess the
reasons? (Hint: Battery lifetime / charging).
(f) Now relate cases c–e to cases a and b. (Answer: more losses.) Cases c–e provide
hints related to cases a and b.
15. A 20 mV offset is present at the inverting terminal. A 1 V is applied to the non-inverting
terminal, and 0.5 V is applied to the inverting terminal side. All resistor values are
𝑅 = 1 kΩ.
(a) Find 𝑉out .
(b) Find the output impedance.
(c) Find the input impedance seen from the 0.5 V source.
 4.2 Questions 43

a
16. (a) Determine the gain.
(b) Find the input impedance.

an
(c) What if the input were a current source?

m
m
Ko

17. Assume finite loop gain. Plot 𝑉𝑥 and 𝑉𝑜 versus time.

i
Sa
a
ty

18. What is feedback? Explain.

19. What are the conditions for oscillation? For a given loop, what happens to other frequencies?
Sa

How is a particular frequency selected for oscillation?

20. Why is a 60-degree phase margin typically chosen over other values?
21. Explain the significance of Gain Margin and Phase Margin.
22. What is loop gain, and how do we calculate or obtain the Bode plot during simulation?
23. (a) Draw the latch circuit.
(b) Draw the ring oscillator.
(c) What is the Barkhausen criterion and what are its conditions?
(d) Explain how oscillations are produced.
(e) What is the loop gain at the start of oscillations and after the oscillations settle?
(f) How does the loop gain decrease to 1?
24. (a) What is the name of this circuit?
 44 Chapter 4. Op-amp Circuits

(b) Plot 𝑉out intuitively for step input.

(c) Why do we prefer this over a conventional low-pass filter?
25. Determine the phase of the output waveform with respect to the input signal in the limit as
the frequency approaches infinity.

a
an
m
26. Plot the output voltage 𝑉out .
m
i Ko
Sa
a

27. Calculate the output voltage under the following conditions:

(i) Voltage gain 𝐴𝑣 = ∞
ty

(ii) Voltage gain 𝐴𝑣 = 10

Sa
 4.2 Questions 45

28. For the given source follower circuit:

(a) Determine its −3 dB bandwidth.
(b) Analyze the stability of the circuit.

a
an
29. In the given circuit, if the two resistors are equal, determine the −3 dB bandwidth. Compare
the stability of this configuration with that of a source follower.

m
m
i Ko
Sa

30. Sketch the output voltage 𝑉𝑜 . Initially, 𝑉𝑜 = +5 V. Assume the saturation voltage
𝑉OSAT = 5 V.
a
ty
Sa

31. Determine the final steady-state value of the output voltage 𝑉out .
 46 Chapter 4. Op-amp Circuits

32. Plot the output voltage.

a
an
m
33. The frequency response of an open-loop operational amplifier is provided. The op-amp is
m
configured as an inverting amplifier with a gain of −2. Plot the corresponding closed-loop
frequency response.
Ko
34. Plot Vout.
i
Sa
a

35. (a) Sketch the output voltage waveform 𝑉𝑜 .

ty
Sa

(b) Design a circuit that produces an ideal half-wave rectified output using a practical
diode. Replace the practical diode with an appropriate configuration to achieve ideal
half-wave rectification.
Hint: Use an op-amp in combination with a practical diode to implement an ideal
rectifier.
 a
5. Current Mirrors

an
m
m
5.1 Prerequisites
Ko
1. Razavi Electronics II by Prof. Behzad Razavi (Lectures 1 to 6)
2. Mismatch in current mirrors:
• Analog Snippets – Mismatch in Current Mirrors
• SSCD – IIT Kanpur: Mismatch and Noise Concepts
3. Chapter 5 from the textbook Design of Analog CMOS Integrated Circuits, 2nd Edition by
i
Sa

Behzad Razavi

5.2 Questions
a

1. (a) Will 𝐼out = 𝐼ref ? If not, why? What can be done to make 𝐼out = 𝐼ref ? Plot voltage
(𝑉𝐷𝑆 ) vs. current (𝐼out ).
ty
Sa

(b) How are MOS devices sized for a high-swing cascode current mirror?
(c) Suppose I want 𝐼out = 𝑥 · 𝐼ref . What changes need to be made? Will it affect anything
if the 𝑊𝐿 ratio is adjusted accordingly?
(d) What is the mismatch due to threshold voltage (𝑉𝑡 ) in a current mirror?
2. (a) What is the effect of 𝑟 𝑜 in a current mirror?
 48 Chapter 5. Current Mirrors

(b) How can mismatch in currents be reduced?

3. Draw the current mirror, explain it, and provide remedies for 𝛽 mismatch, 𝑉𝑡ℎ mismatch,
and 𝑉𝐷𝑆 mismatch considering channel length modulation.
4. Draw the system-level diagram. If we want to obtain a current mirror with a 1:10,000 ratio,
how will it be implemented?
5. (a) What is 𝐼 𝐷 if the current source provides a constant current of 1 mA?

a
an
m
(b) The MOSFET M1 now has a new aspect ratio of 2𝑊/𝐿, and the resistor connected to
m
the source is changed to 𝑅/2. Comment on 𝐼 𝐷 .
i Ko
Sa
a
ty

The interviewer continued this question with more focus on the new current mirror
functions, and how this change is going to affect the current.
Sa

6. Find 𝐼 𝐷2 , 𝐼 𝐷3 , and 𝐼 𝐷4 .
 5.2 Questions 49

7. (a) Do you know the current mirror circuit? Draw it.

(b) What conditions must be satisfied for proper current mirroring?
(c) Why is a diode-connected MOS transistor used in the current mirror?
(d) Considering channel length modulation (CLM), what problem arises, and how can it
be mitigated?
(e) How do you ensure that 𝑉𝑥 = 𝑉𝑦 ? Prove your method.

a
an
m
(f) How can the gain of an operational amplifier be increased without increasing the
m
output resistance 𝑅out ? Provide a method independent of temperature and process
variations. (Hint: Gain boosting)
(g) Draw the circuit and derive gain expressions with and without gain boosting.
Ko
(h) Explain how the method in part (g) can be applied to ensure 𝑉𝑥 = 𝑉𝑦 in the circuit
from part (e).
8. Determine the low-frequency gain of the following circuits, where the input is the input
current 𝐼in . Identify the location of the dominant pole, and specify the position of the pole
at node 1.
i
Sa
a
ty
Sa

9. Determine the minimum value of 𝑉1 required for the proper operation of the circuit.
 50 Chapter 5. Current Mirrors

10. Size the remaining four transistors in the circuit below such that 𝐼out = 𝐼in .

a
an
m
m
i Ko
Sa
a
ty
Sa
 a
6. Noise Analysis

an
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m
6.1 Prerequisites
Ko

1. EE613A: High-Frequency Analog Circuit Design (2023) by SSCD IIT Kanpur (Lectures
29 to 33)
2. Noise in Electronic Circuits by Prof. Behzad Razavi
3. Chapter 7 (Noise) from the textbook Design of Analog CMOS Integrated Circuits, 2nd
i
Sa

Edition by Behzad Razavi

a

6.2 Questions
ty

1. Find the integrated noise spectral density onto the capacitor.

Sa

2. Only 𝑀1 contributes noise to the circuit. What will be the value of 𝑉𝑜1 and 𝑉𝑜2 ?
 52 Chapter 6. Noise Analysis

a
3. (a) Draw a transimpedance amplifier.
(b) Find the noise at 𝑉𝑜 due to the resistor 𝑅. Assume the op-amp is ideal.

an
m
m
4. What are the different noise components associated with a MOSFET?
Ko
5. How can we obtain the noise voltage from the noise PSD?
6. Perform noise analysis of a 5T-OTA.
7. A system has an initial signal-to-noise ratio (SNR) of 60 dB. If an uncorrelated noise
voltage of 1 mV is added to a signal of 1 V, what is the resulting SNR?
i
Sa
a
ty
Sa
 a
7. Switched Capacitor Circuits

an
m
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7.1 Prerequisites
Ko
1. A Very Basic Introduction to Switched Capacitor Circuits by Chembiyan T
2. EE698I: Mixed-Signal IC Design (2024) by SSCD IIT Kanpur (Lectures 4(3) to 9)
i

7.2 Questions
Sa

1. Plot 𝑉𝑥 during the initial pulses and after many pulses for the following cases: (i) 𝐶1 = 𝐶2
(ii) 𝐶1 ≠ 𝐶2
a
ty
Sa

2. Find the steady-state value of 𝑉out . The inputs are 1.8 V and 1 V. The value of all capacitors
is 𝐶 = 1 pF. 𝜙1 and 𝜙2 are non-overlapping clocks.
 54 Chapter 7. Switched Capacitor Circuits

3. The input is 1 V. The value of all capacitors is 𝐶 = 1 pF. Plot 𝑉out for more than two cycles
of the non-overlapping clocks 𝜙1 and 𝜙2 .

a
an
m
m
Ko

4. The switch is non-ideal (finite resistance, non-linear).

(a) Determine the frequency content in 𝑉𝑜 .
(b) Which frequencies are dominant?
i
Sa
a
ty

5. (a) Capacitors 𝐶1 and 𝐶2 are initially charged to 5 V and 2 V, respectively. The switch is
Sa

closed at 𝑡 = 0. Comment on the final voltage.

(b) A resistor 𝑅 is introduced into the circuit shown in the figure.

i. What will be the voltage 𝑉𝐴 ?
 7.2 Questions 55

ii. Can this be represented using mathematical equations?

iii. What will be the equation of the current?

a
an
(c) Is energy conserved in case (a)? Explain. If not, where did the remaining energy go?

m
(d) Is energy conserved in case (b)? Explain.
6. Plot 𝑉out with respect to the given input waveforms.
m
i Ko
Sa
a

7. For the following circuit, at time 𝑡 = 0, the switch transitions from position A to position B.
ty

Determine and sketch the voltage waveform observed at node B.

Sa

8. For the following circuit, determine the voltage values at nodes A and B. Assume the
threshold voltage 𝑉𝑇 of the transistor is 1 V.
 56 Chapter 7. Switched Capacitor Circuits

a
9. In the following circuit, a capacitor is connected between two ideal MOS switches, 𝑇1
and 𝑇2 , which are alternately turned on at a frequency 𝑓c . Determine the average current

an
flowing from node 1 to node 2. Additionally, calculate the equivalent impedance seen from
node 1 to node 2.

m
m
i Ko
Sa

10. Calculate the output voltage after 5 s based on the initial conditions and circuit parameters.
a
ty
Sa

11. Initially, 𝑉1 = 𝑉2 = 1 V and 𝑉in = 0.7 V. If 𝑉in changes to 1.5 V, determine the final states
of the circuit.
 7.2 Questions 57

a
12. What is the equivalent value of resistance.

an
m
m
i Ko
Sa
a
ty
Sa
 a
8. Band-gap refrence Circuits

an
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8.1 Prerequisites
Ko
Bandgap circuit design in CMOS process by Analog Snippets

8.2 Questions
1. a) Draw a BGR (Bandgap Reference) circuit. Explain the op-amp’s role and sign
i
Sa

convention.
b) Can we use MOSFETs instead of PNP transistors?
c) What happens if the resistors used have temperature dependency? How do you deal
with it?
a

d) How do you ensure stability in a BGR circuit?

ty
Sa
III
Miscellaneous

a
an
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m
Ko
i
Sa
a
ty
Sa

9 Miscellaneous . . . . . . . . . . . . . . . . . . . . 60
9.1 Questions

Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
 a
9. Miscellaneous

an
m
m
9.1 Questions
Ko
1. Draw both PMOS and NMOS current mirrors. Determine the voltage at each node
separately. Then, connect the two circuits such that there are no floating nodes. Finally,
find the voltage at the intersection point.
2. Find 𝑉out .
i
Sa
a

3. Draw 𝑉𝑂1 and 𝑉𝑂2 for

(a) the differential input shown in the figure, and
ty

(b) a pulse input of 1 ms duration, assuming the transistors are biased.

Sa
 9.1 Questions 61

4. You are given a train of pulses having a certain rise time and fall time.

a
an
How would you model the pulse train in the frequency domain and time domain to obtain
its Laplace Transform? Hint:

m
m
Ko

5. For a cascode of two amplifiers with gains 𝐴1 and 𝐴2 , noise figures 𝑁 𝐹1 and 𝑁 𝐹2 , and
input third-order intercept points 𝐼 𝐼 𝑃31 and 𝐼 𝐼 𝑃32 , what will be the overall noise figure
i

and 𝐼 𝐼 𝑃3 of the system? (Question for RFIC profile.)

Sa

6. The line is matched to 𝑅𝑠 . The input is a 1 V step.

(a) Find 𝑉1 .
(b) Model the line assuming it is lossless, and verify 𝑉1 using this model.
a
ty
Sa

7. (a) Determine the type of feedback present in the circuit, identify where to break the
loop to analyze the feedback, and specify what should be checked before breaking
any loop.
(b) What are the currents through all transistors? Derive the loop gain expression. (Note:
Drawing the small-signal circuit is not allowed.)
(c) What is the condition for the circuit to exhibit positive feedback?
 62 Chapter 9. Miscellaneous

a
an
8. Find 𝑉. (You are not allowed to use nodal analysis. You should answer without lengthy
math.)

m
m
Ko

9. (a) Draw 𝑉out for an input 𝑉𝑚 sin(𝜔𝑚 𝑡) in an LTI system with its characteristics shown
i

below.
Sa
a
ty
Sa

(b) Draw 𝑉out for the input shown below.

10. (a) Calculate the resistance ratios of both metals.

(b) Calculate the ratio of capacitances of both metals.
 9.1 Questions 63

11. (a) Draw 𝑉out and explain the working of the circuit.

a
an
(b) What is the gain of the inverters at 𝑡 = 0 and at steady state?
(c) In which region will they operate at 𝑡 = 0 and at 𝑡 = ∞?
12. Find 𝑉𝑋 and 𝑉𝑌 for the given different values of 𝑉in shown in the figure.

m
m
Ko

13. Two black boxes are given, each containing an unknown network of resistors along with
i

current and voltage sources. One wire comes out of each of the two black boxes, as shown.
Sa

If we connect a resistor between these wires, can we say anything about the current through
it?
a
ty
Sa

14. An AC source is given by 120 sin 𝜔𝑡, and the transformer has a turns ratio of 12:1. The
diode is ideal. Comment on 𝑉𝑜 and plot it.
 64 Chapter 9. Miscellaneous

15. (a) Draw a CMOS inverter. Plot the input and output characteristics for a pulse input
with minimum = 0 V and maximum = 𝑉𝐷𝐷 .
(b) What happens if both transistors are PMOS?

a
an
(c) What happens if both transistors are NMOS? (Answer: Buffer)
16. a) Draw the cross-section of an NMOS transistor.
b) What is inversion?
c) Explain the body effect when the body is connected to positive and negative voltages.

m
d) Represent the MOS capacitances.
17. Discuss the Voltage Transfer Characteristic (VTC) of an inverter. How does the VTC
m
change with increased sizing of NMOS and PMOS transistors?
18. What is the stability criterion for a system when the loop gain is 1 and the loop phase angle
is 150°? Comment on the system’s stability.
Ko
19. Calculate the voltage at node 𝑉𝑋 . Discuss whether the components 𝑉1 , 𝑅1 , and 𝑅2 have
any impact on the value of 𝑉𝑋 .
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20. Given that 𝑉inz is the complement of 𝑉in , determine the time at which 𝑉out reaches 2.9 V.
Sa
 9.1 Questions 65

21. You are probing a square wave pulse in the laboratory with a rise time of 5 ns and a fall
time of 2 ns. Determine the minimum bandwidth required for the oscilloscope to accurately
observe the signal.
(Answer: The time it takes for an RC circuit to transition from 10% to 90% of its final
value is given by 𝑡 = ln(9) · 𝑅𝐶. To capture the signal’s fall time of 2 ns, the oscilloscope
ln(9)
bandwidth must be greater than BW = 2𝜋·2 ns ≈ 174 MHz. A suitable choice is an
oscilloscope with a bandwidth of at least 200 MHz. To minimize measurement error, it is
recommended to use an oscilloscope with a bandwidth approximately three times higher,
i.e., 600 MHz.)
22. Compare the functionality of the following two circuits. How do they differ in operation,

a
and which one provides a more stable or accurate reference?

an
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i Ko

23. Draw the output waveform corresponding to the given circuit .

Sa
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Sa

24. Describe how 𝐼1 and 𝐼2 vary with temperature. Explain the underlying physical or circuit
 66 Chapter 9. Miscellaneous

mechanisms affecting their temperature dependence.

a
an
25. Determine the output voltage of the circuit based on the given conditions.

m
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Ko

26. Calculate the value of 𝑅. Assume the network is entirely resistive.

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 a
Index

an
m
5T-OTA, 30
m
Band-gap refrence Circuits, 61
Ko

Current Mirrors, 50

Differential Amplifiers, 34

Miscellaneous, 64
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Sa

Noise Analysis, 54

Op-amp Circuits, 40
a

Prerequisites, 7, 22, 38, 40, 50, 54, 56, 61

Questions, 38, 40, 50, 54, 56, 61, 64

ty

RC Circuits, 7
Sa

RL Circuits, 16
RLC Circuits, 18

Single Stage Amplifiers, 22

Switched Capacitor Circuits, 56