ELEN 689 -603
Pipeline ADCs
February 2000
Content
Interest of pipeline ADCs The Origins of Pipeline ADCs Basic Architecture Digital Correction Detailed example Performance evaluation Design-performance relations
Interest of the Pipeline ADCs
A Figure-of-merit to evaluate the performance of an ADC is its information transfer capacity: ITC=2NCS where ITC is the Information Transfer Capacity in symbols/sec, N is the number of bits and CS is the Conversion Speed, For example, an 8-bit, 1GSPS ADC has an ITC of 2.56e11, whereas a 20-bit 44.1KSPS ADC has an ITC of 4.62e10, The state of the art in ADCs is presently given by a 14-bit, 80MSPS pipeline ADC, which provides an ITC of 1.3e12 symbols/sec.
Some Products and Performance
Ref / Year Feature Technology Results Area (mm ) Power/Voltage
2
JSSC 12/1999 JSSC 12/1997 JSSC 12/1998 JSSC 12/1996 ISSCC98 ISSCC98 ISSCC98 ISCAS98 CAS II99
Pipelined deltasigma Pipelined deltasigma Self calibrating Microcontroller calibrating Analog calibrating 2 channels 2 channels Current mode Good linearity
1.2u CMOS 0.6u CMOS 0.5u CMOS 1u BiCMOS 1.0u CMOS 0.5u CMOS 1u CMOS 0.5u CMOS 0.5u CMOS
SNR74dB 18Msps 16 bits 20Msps 12bits 10Msps 16bits 1Msps 10 bits 40Msps 8bits 75Msps 10bits,40Msps 8 bits 20Msps 12 bits3.3Msps
48 35 15 35 47 5.5 42 N/A N/A
324mW/3.3v 550Mw/5v 335mW/3.3v 200mW/5v 650mW/5v 70mW/3.3v 565mW/5v 22mW/2.4v 300mW/5v
Device Texas Instruments Products THS1206 pipeline TLV5580 pipeline TLC5540 semiflash Analog Devices Products AD9202 pipeline AD9203 pipeline MAXIM Products MAX1201
Resolution
Conv. Rate(Msps)
Supply(v)
SNR(dB)
Power(mW)
12 8 8
6 80 40
2.7-5.5 3.3 5
N/A 46 45
210 165 85
10 10 14
32 40 2.2
3 3 5
N/A N/A 83
90 50 269
The Origins of Pipeline ADCs
1- The Flash ADC
Vref Vin 2n-1 Comparators
Digital Output
Encoder
Each comparator has its own threshold voltage, spaced by 1 LSB, The input is fed to all the comparators in parallel, The output of the comparators is in thermometer format, An encoder is used to convert to binary format.
2- Sub-Ranging ADCs
MSB
Vin
3 Bit A/D Converter
D/A Coverter
Gain
Sign 3 Bit A/D Converter LSB
The input is first converted by a simple 3-bits flash ADC, The digital value is converted back in analog format by a 3-bit DAC and subtracted from the input, this gives a residue, The residue is multiplied to get the full range, and then converted by a second flash.
More on Sub-Ranging
First Stage Second Stage
l l l l
l l l
3bits
3bits
l
Very High Speed 1 Conversion/Clock 1/2 Clock Latency Higher Resolution with Less Hardware: 2 X 3bit = 14 Comp. 6bit = 63 Comp. Lower Power Dissipation Smaller Input Capacitance Can be Interleaved Requires High Precision Interstage Processing Hardware Still Increases Exponentially within Each Flash
3- The Pipeline ADC
Basic Architecture
Vin
Analog Stage
Analog Stage
Analog Stage
Analog Stage
MSB
LSB
The principle of sub-ranging ADC can be pushed to the limit of having only one bit per stage, At this point, each flash ADC is nothing more than a simple comparator, Also, the data is transferred in a pipeline fashion: when the data is sent to the second stage, another sampled data is fed to the first stage, The result is a latency delay equal to the number of stages.
Basic Block Architecture
Implemented by a single programmable amplifier + X2
Analog input (from previous stage )
2 bit A/D 1
(Comparators)
Residue (to next stage)
2 1 bit D/A
Digital Out
The analog stage is formed of a 2 bits flash ADC, a 2 bits DAC and a adder/gain stage. The output is called the residue and is sent to the next stage.
Functionality of the Basic Block
Residue
+ Clock In X2
1 bit A/D 1 bit D/A 1 Digital Out
Residue
In
Stage( n) = 2( Stage(n 1) + Vref ) if Stage( n 1) > Vmid Stage( n) = 2( Stage(n 1) Vref ) if Stage(n 1) > Vmid
Example
First Stage Second Stage Third Stage Fourth Stage
1V 0.8V 0.7V
0.2 0.3
0.7/1=11.2/24
0.6V
0.1
0.5V (mid) 0.4V
-0.1
0V
1bit
1bit
1bit
1bit
Output=11
Effect of a Threshold Error
What if we have an error on a comparator in the second stage?
First Stage Second Stage Third Stage Fourth Stage
1V
0.7/1=11.2/24
0.7V
0.2
0.5V (mid)
Shift
0.4V
-0.1
0V 0V 0V
-0.5
1bit
1bit
1bit
-0.5
Saturation
1bit
Saturation
Output=9
Effect on the Residue Plot
Residue
Input range Input range Output range Input range
Residue
Residue
In
Threshold Error
In
Saturated Input Saturated Input
Output range
Output range
In
Second Stage
Third Stage
Fourth Stage
The input of the second stage falls within the threshold error range, The output gets saturated because it is added instead of subtracted, Since we are now at the maximum of the range, all other stages get saturated.
Effect on a Residue Plot
With Wider Range
Residue
Input range
Residue
Input range
Residue
Input range
Saturation
Output range
Output range
In
Threshold Error
In
Output range
In
Second Stage
Third Stage
Fourth Stage
What if we add some Input and Output Overhead Range? The output will not get saturated at the next stage, but it will since the level diverges instead of converging, As a result, the true 1-bit/stage pipeline ADC is not practical.
Digital Redundancy
Clock + In X2
2 bit A/D 2 bit D/A 2 Digital Out
Residue
In
Basic Block
Basic Block
Basic Block
Basic Block
D D D
D D D
D D
D D
Carry
Carry
Carry
D3 (MSB)
D2
D1
D0 (LSB)
Residue Plot with Redundancy
Residue Vinmax 4
2 bit A/D 2 bit D/A 2 In + Clock X2
Residue
Vinmin Vinmax Vinmin 4
Digital Out
Stage( n) = 2( Stage(n 1) + V ref + ) if Stage( n 1) < Vcomp
Out=01 Out=10
Out=00
Stage( n) = 2( Stage( n 1)) if Vcomp < Stage( n 1) > Vcomp+
Stage( n) = 2( Stage(n 1) + Vref ) if Stage( n 1) > Vcomp+
Example of Digital Correction
0.5 Vin 0.3 0.2 Vcomp+ 0.125 0 Vcomp--0.125 -0.1 -0.2 0.1 0.1 0.2
-0.5
10 1 1
01 0
10 0
01 1
00 1
01 0
10
102
0.3+0.5=0.8= 102.4/26
Error Correction with Threshold Error on the Second Stage
0.5 V in 0.3 V comp+ 0.125 0 V comp--0.125 -0.2 -0.3 -0.5 0.1 -0.1 0.2 0.1
10 1 1
10 0
00 0
01 1
00 1
01 0
10
102!
1.5-bit/stage with Digital Correction
Clock + In X2
Detailed Example
Residue
noop
C2 Vref+ Vmid Vrefadd sub 2 C1
2 1'
2 bit A/D
2 bit D/A
2 Digital Out
1 Vin+ Vinadd 1 noop sub
Vout+ Vout-
C1 2 1' 2
The Gain, DAC and Adder blocks can be implemented by a simple MDAC SC circuit,
Vref- Vmid Vref+ C2
Vout=2Vin+[Vref+, Vmid , Vin-]
Precise X2 Block
S 10 C1 VIN S1 S2 S3 S4 S5 S 11 S6 C2 S7 S3 S4 OP1 + S9 S6 S7 OP2 + S8 S8 S9 S10 S11 VOUT S5 S
1
S2
C3
VOUT = 2
C1 C1 VIN = 2 VIN C2 C2
VOUT
C 1*2*V IN C2
C1*2*V IN + C2*2*V IN C2 C1 2*V IN
Op-Amp Structure
Basic Folded Cascode Amplifier
Good output and input dynamic ranges, High gain provided by the cascode structure.
Used for CommonMode Feed-back
The Flash ADC
Clock
Vref+
In
X2
2 bit A/D 2 bit D/A
Residue
Vin
+ -
ADD
Thermometer to MDAC Converter
Digital Out
NOOP SUB
+ -
Vref-
Thermometer to Binary Converter
MSB
LSB
Each comparator has its own threshold, These threshold are the same for all the stages, The thermometer code has to be converted for the MDAC and for the Digital Correction circuit.
Non-Overlapping Clock Generator
clock in phi 1
phi 2
Modeling of Pipeline ADCs
Each analog block is identical, Modeling is easy with a high-level language (Matlab, SpectreHDL, etc). Digital correction can be modeled by ideal computations or basic digital modeling in Verilog. It is assumed ideal.
Pseudo-Code for a FullyDifferential Basic Block
In+=Vin In-=-Vin While simulation is not finished, do Repeat for each stage Diff_in=(In+)-(In-) If Diffin < Vcomp-, then Digital_out = 00 Diffout = 2(Diffin+Vref+) If Vcomp- < Diffin < Vcomp+, then Digital_out = 01 Diffout = 2(Diffin) If Diffin > Vcomp+, then Digital_out = 10 Diffout = 2(Diffin+Vref-) Out+ = Diffout/2 Out- = -Diffout/2 Compute Digital Correction Return
0 0 In+
Vin
In-
DNL with a 5% Gain Error on First Stage
MATLAB Simulation
DNL with a 20% Threshold Error on the Comparator
MATLAB Simulation
Measurement examples
INL of Uncalibrated ADC
Measurement examples
INL of Calibrated ADC
