[Chaudhari, 3(3): March, 2014] ISSN: 2277-9655

Impact Factor: 1.852

IJESRT
INTERNATIONAL JOURNAL OF ENGINEERING SCIENCES & RESEARCH
TECHNOLOGY
Design and Implementation of 1-bit Pipeline ADC in 0.18um CMOS Technology
Bharti D.Chaudhari*1, Priyesh P.Gandhi2
*1 2
PG Student, Assistant Professor, L.C.institute of Technology, Bhandu, India
Chaudhari.bharti18@gmail.com
Abstract
This paper present the design of a single bit Pipeline Analog-to-Digital Converter (ADC) which is realize
using CMOS technology. In this paper, a 1-bit Pipeline ADC is implemented in a standard TSMC 0.18um CMOS
technology using Mentor Graphics Tool. 1-bit Pipeline ADC is design using ±1.8V power supply and simulation
result is plotted using Mentor Graphics Tool.
This paper firstly elaborate about basic introduction of ADC and different ADC architecture and its application.
Further Design of 1-bit Pipeline ADC is to be proposed which consist of sample and hold , DAC, Op-amp and
Comparator as a key component in Pipeline ADC.

Keywords: CMOS technology, Comparator, Op-amp, Mentor Graphics Tool.

Introduction
Analog-to-digital converters (ADCs) are
very important building blocks in modem signal
processing and communication systems. For signal
processing, digital domain is preferred over analog
domain because of its advantages such as noise
immunity, storage capability, security etc. For long
distance, digital communication is more reliable due
to regenerative repeater. Due to these, today nearly
all modern electronics are primarily digitally
operated, allowing for advanced digital signal
processing (DSP). But the real world signals such as
signals coming from various transducers are analog Fig.1 Ideal Block Diagram of Digital to Analog
in nature. This analog signal must be converted into Converter [3].
digital to allow digital signal processing. This is done Different ADC architecture and its
by Analog to Digital Converter (ADC) as shown in application are summarization in table 1. Among
Figure 1. Similarly after signal processing in digital various ADC architectures, the pipelined ADC has
domain, the signal is converted back into analog. the attractive feature of maintaining high accuracy at
This is required for the transducer such as speaker. It high conversion rate with low complexity and power
is done by Digital to Analog converter (DAC). The consumption. Therefore it is used extensively in
applications of ADC include DC instruments, process high-quality video systems, high speed data
control, thermocouple sensors, modems, digital radio, acquisition systems and high performance digital
video signal acquisition etc. The ADC should be communication systems where both precision and
featured with low power and higher speed due to speed are critical.
many reasons. First the rapid advent of battery
operated portable system requires low power Table 1: Comparison of ADC Architectures
dissipation in order to prolong battery life, and a Archit Latenc
Speed Accuracy Area
minimum number of battery cells to reduce the ecture y
volume and weight of the system. Another reason is Flash No High Low High
the smaller feature sizes offered by today's VLSI Foldin
technology. g/inter Medium Low- Medium-
No
polatin -High Medium High
g
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Delta- the comparator the sample signal should lift to the
Yes Low High Medium
Sigma .9V of the DC voltage so that the comparator can
Medium- compare the value to the threshold voltage and give
SAR Yes Low Low the output. The digital output again converted to the
High
Pipelin Medium- analog value through the 1-bit DAC Uses two
Yes Medium Medium reference voltage levels. This converted value will be
e High
subtracted from actual sampled signal to produce an
error signal using a difference circuit. This signal
often called as residue signal. This residue signal
again multiplied by two with an open loop amplifier.
The sub tractor and the multiplier are working at 100
MS/s.
Sample and Hold Circuit
SH circuit can be realized using only a
Fig. 2: Various ADC Architecture [10]. transmission gate and a capacitor. The operation of
this circuit is very straightforward. Whenever CLK is
Architecture of Pieline ADC high, the TG is ON, which in turn allows VOUT to
Typical pipeline architecture is illustrated in track VIN. When CLK is low, the TG is OFF. During
Figure 3. Each stage has the four elements of a SHA, this time, CH will keep VOUT equal to the value of VIN
a sub-ADC, a sub-DAC and an inter-stage gain at the instance when CLK goes low. Implemented
amplifier. The operation of a single stage consists of sample and hold is depicted in Figure 4(a).
four steps. First, the input signal is captured by the
sample and hold amplifier. Second, this signal is
quantized by the sub-ADC, which produces a digital
output. Third, this digital signal goes to the sub-DAC
which converts it to an analog signal. This analog
signal is subtracted from the original sampled signal -
thereby, leaving a residual signal. Fourth, this
residual signal is increased to the full scale through
the inter-stage amplifier. The residual signal is passed
to the next stage and the procedure mentioned above Fig. 4(a)
is repeated.

Fig. 4(b)
Fig. 4: (a) Schematic diagram [1] and (b) output results
of the sample and hold circuit.

Fig. 3: Generalized Pipeline ADC Architecture [3]. Design of CMOS Comparator

The Pipelined ADC consists of a 1-bit ADC
VLSI Implementation Of The 1-Bit Pipeline which is composed of a comparator and a D-flip-flop.
ADC The design of comparator is similar enough to that of
A. 1- Bit Single Stage of Pipelined architecture an Op-amp .The only difference is the use of the
This stage is consist of sample and hold compensation network consists of resistor and
circuit followed by 1-bit ADC, 1-bit DAC, subtracted capacitor and extra multipliers on a biasing NMOS
and multiplier. The analog signal will be sampled and device. The comparator does not need the
fed to the comparator acts as the 1-bit ADC that compensation network because its only function is to
would give the 1-bit digital output. Before giving to switch from rail to rail. Stability is not needed as it
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will only slow down the switching sp speed. When a
sine wave is input to the circuit, th the comparator
switches from positive rail to negativee rrail.

Fig. 6(a)

Fig. 5(a)

Fig. 6(b)

Fig. 6: (a) Schematic Diagram andd (b) output waveform

of 1-Bit DAC

Two stage Operational Amplifier ier

Fig. 5(b) The operational amplifie fier that the integrator
uses must have the high gain to o effectively
e carry out
Fig. 5: (a) Schematic diagram and (b) ou
output results of a smooth integration as welll as a a large enough
the comparator circuit
bandwidth to support the high frequency
fre sine waves
it will be integrating. The OpA pAmp operates at the
1-Bit Digital-to-Analog Converter
clock frequency, since the differences
diff are being
Basically the 1-bit DAC can be implemented
integrated over the region of time. e. Therefore, the gain
using simple 2X1 analog multiplex lexer. Here the
bandwidth product of the OpAm Amp must be greater
multiplexer has to select Vol
olt or 0 Volt than one at the clock frequency to effectively pass the
depending on the output of the compara arator which acts signal. The amplifier used is shown
sh in figure. The
as a selection line. key thing to note to about the th amplifier is the
Here in implementation of 1--bit DAC, two frequency compensation network ork which is used to
TGs are used as shown in Figure 6(a). ). IInputs to these push the high frequency zero out ut of the pass band of
TGs are and ground, while the outputs are the Opamp.
In amplifier, using prop
roper capacitance and
connected together. Based on the comp mparator output
applying negative feedback, gain
gai is adjusted to 2.
or zero voltage is available at the ou
output of DAC. This is because each stage is of 1--bit. If the stage is of
The control signals for TGs are comp mparator output n-bit then gain will
wil be
and its inverted output obtained by an inverter. In 2n.
this design analog input to the DAC ar are 1V and 0V.
Based on comparator output (+1.8V or -1.8V) one of
the analog inputs will be available att th
the output. This
is clearly observed in Figure 6(a).

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Conclusions
In present work, An 1-bi
bit Pipeline analog-to
digital converter system has been
b designed and
simulated in standard TSMC MC 1.8um CMOS
Technology. The circuits are simulated
si in SPICE
with MOSIS Level-53 MOS mo odel parameters. For
simulation I used Power supply voltage
vo is VDD=1.8v
and sampling rate is 100Ms/S anda after simulation
Gain of Op-Amp is 60dB and d Power
P dissipation s
2.706mW.

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