Z80 MICROCOMPUTER SYSTEN\280° MICROCOMPUTER SYSTEN\ EUROCRATIC MOS Since setting up its MOS department in 1966, SGS-ATES has led the way in European MOS technology. Between the major landinarks of the first European-designed MOS calculator in 1968 and the F8 microprocessor in 1977, we brought you a full range of memories: IK static and 4K dynamic RAMs, a 1K x 8 EPROM, a2K x 8 ROM..... and now we bring you the Z-80. Not only the Z-80 but a team of experts dedicated to the development of the Z-80 device family, Z-80 systems, applications and interface devices. Moreover, we've set up a comprehensive European network of “local” micro- computer application centres packed with the most up-to-date equipment available, staffed with highly-experienced software engineers and located in UK, Sweden, Italy, France and Germany. SGS-ATES and Zilog: a vast reserve of know-how and resources committed to the advancement of microprocessors - stay with us and be part of the Z-80 conquest. ‘TM: 280 sa registered trademark of Zilog, IneCONTENTS The Z80 Microcomputer PRODUCT LINE The Z80-CPU/Z80A-CPU CENTRAL PROCESSING UNIT The Z80-PIO/Z80A-PIO PARALLEL INPUT/OUTPUT The Z80-CTC/Z80A-CTC COUNTER TIMER CIRCUIT The Z80-DMA/Z80A-DMA DIRECT MEMORY ACCESS CONTROLLER The Z80-SIO/Z80A-SIO SERIAL !NPUT/OUTPUT ‘The Z80-S109/Z80A-SIO9_- SERIAL INPUT/OUTPUT ‘The Z80-DART/Z80A-DART DUAL ASYNCHRONOUS RECEIVER/TRANSMITTERZ 80 Z 80A Z-80 MICROCOMPUTER PRODUCT LINE Introduction The Z-80 LSI component set includes all of the logic circuits necessary for the user to ‘uild high performance microcomputer systems with virtually no external logic and an absolute minimum number of lowest cost standard mem- ory components. The Z-80 component set is backed by advanced software, a disk based hardware/software development system and complete training and support. The entire Z-80 product line has been developed as a single, highly integrated entity to insure that the user can develop his system quickly and still obtain all the performance advantages of the Z-80 component set High System Throughput The architecture of the Z-80CPU includes a superset of 158 instructions, with more internal registers and addressing modes than second generation microcomputers and extre- mely fast interrupt response time. All of these features mean that in any given amount of time the Z-80 can perform far more work (processor throughput) than any other microcomputer system available today. This throughput advan tage allows users to continually expand the features and capabjlities of their systems with out increasing hardware costs. Low Memory Costs One of the major features of the Z-80 CPU is that it greatly reduces system memory costs, The expanded set of 158 software instruc- tions results in a tremendous reduction in the memory required for any typical application. In addition, the Z-80 CPU provides all refresh and timing signals to directly drive dynamic memo- ries so that the Z-80 LSI components can inter: face to most standard 4K dynamic memories with virtually no external logic. The Z-80 CPU uses @ technique whereby the memory address is generated very early in memory cycles, per mitting the high speed Z-80 CPU to operate with standard speed memories, again reducing system memory costs, The Z-80 CPU was designed to operate with standard memory products from any source since these devices will always be less expensive than custom mem- ories designed for any particular microcomputer. Low 1/0 Costs The Z-80 LSI component set includes four general purpose programmable I/O circuits that contain all of the logic required to imple- ment fast I/O transfers with minimal CPU over- head. These circuits have a built-in ripple priority interrupt control circuit (the device closest to the CPU has the highest priority) and all the logic necessary for nesting of interrupts to any level. Using the programmable features of these circuits, the user can configure the devices to interface with a wide range of peripheral devices with virtually no other external logic. These features make the peripheral device controllers in a Z-80 system much simpler and therefore lower in cost Low System Hardware Costs The Z-80 component set requires very little support circuitry. All devices require a single +5 volt power supply and_a single phase TTL clock. In addition, all contro! signals are directly compatible with I/O and memory devices so that system control circuits are not required. External interrupt control circuits are not required since these are included in every Z.80 1/0 circuit. DMA circuits are generally not required due to an extremely fast interrupt response and powerful 1/0 block transfer capability within the CPU Low Development Costs SGS-ATES offers more than a fully integrated line of LSI components. Everything is provided that is necessary for the user to easily develop his own proprietary system using the 2-80 components. This includes complete software packages, disk based development systems and training. For example, the expanded Z-80 software instruction set coupled with the easy to learn Z-80 assembly language and reference cards make assembly language pro- gramming much easier than previously possible. For larger programs, PL/Z may be used to speed up the development cycle, to enhance program documentation and to improve program ‘maintainability.NN co Z-80 MICROCOMPUTER SUMMARY Central Processor Unit/Z-80-CPU Ci Single chip, N-channel processor © 158 instructions - Includes all 78 of the 8080A instructions with total software com: patibility. New instructions include 4-, 8- and 16-bit operations with more useful addressing modes. 17 internal registers (more than twice the 8080A registers), including two real index registers. Oi Three modes of fast interrupt response plus a nonmaskable interrupt. ©) Directly interfaces standard speed static or dynamic memories with virtually no external logic. © 1.6us instruction execution speed © Single SV supply and single-phase TTL Clock. © Out-performs any other microcomputer in 4- , 8-, 16-bit applications. Gi Requires 25% to 50% less memory space than the 8080A CPU. G Up to $00% more throughput than the 8080A. O TTL compatible tri-state data and address busses, COUNTER, TIMER (Ce) o TANDARO. MEMORY Interface and Control Circuits Parallel Input/Output Controller/Z-80-PIO Programmable circuit that allows for a direct interface to a wide range of parallel in- terface peripherals without other external logic. Serial Input/Output Controller/Z-80-SIO Programmable circuit that allows for a direct interface to a wide range of serial inter- face peripherals without other external logic. Counter Timer Circuit/Z-80-CTC Contains four independent programmable counter timer circuits for control of real time events. Direct Memory Access Controller/Z-80-DMA Programmable circuit that can directly transfer data between the SIO or PIO and memory on a CPU cycle steal basis. All Z-80 controllers have built in nested priority interrupt control and fast interrupt response capability (up to 6 times faster than the 8080A). All Z-80 controllers monitor peripheral status to eliminate any type of CPU polling. DIRECT MEMORY SERIAL (' vO780A Z-80 COMPONENTS Introduction The SGS-ATES third generation micro- computer components are the most advanced and comprehensive set of LSI microcomputer products available today. The major compo- nents in the Z-80 product line are an extremely high performance central processing unit (CPU), a programmable parallel input/output controller (PIO), a programmable serial input/output con- troller (SIO), a versatile counter timer circuit (CTC) and a high speed direct memory access controller (DMA), All of the Z-80 components utilize the industry standard N-channel silicon gate tech- nology to provide the highest density at the lowest cost. Depletion load technology is also used to provide high performance with a single SV power supply. The CPU, PIO, SIO and DMA are packag- es in standard 40-pin DIPs; the CTC comes in a standard 28-pin DIP. All require only a single 5V power supply plus the Z-80 single-phase TTL level clock Z80 CPU The Z-80 CPU is an extremely powerful, third generation CPU which incorporates a number of major features over the standard 8080A CPU while retaining total software compatibi Major improvements include: Gi More than twice as many registers on the CPU chip, including two real index registers C Many more addressing modes C] More than twice as many instructions 1 Three modes of extremely fast interrupt response C1 A separate non-maskable interrupt to a fixed location. Another unique feature of the Z-80 CPU is its ability to generate all of the control signals for standard memory circuits. Static memories can be interfaced using only an external address decoder for chip selects. In addition the Z-80 CPU provides all of the refresh control for dynamic memories, and the Z-80 control bus timing signals are directly compatible with all widely used, standard speed, 18- and 22-pin 4K RAMs (16-pin 4K RAMs require only an extérnal address multiplexer). Thus dynamic RAMs can be interfaced with virtually no additional external logic. This provides the user with the ability to easily interface to the lowest cost dynamic memories without reducing CPU operational speed. By selecting the best standard memory for a given application, the user can reduce his, product manufacturing costs, and the product development expenses will also be much lower. The Z-80 CPU is designed to be totally software compatible with the standard 8080A microprocessor to facilitate the user's transition to the Z-80. By using the Z-80 component set and the most economical memory for the particular application, the user need only re~ layout any 8080 based design and use any exist- ing software programs to obtain an immediate and very significant reduction in system hard- ‘ware costs. A major advantage is that the same ROMs that are used in the 8080 system can be used in the Z-80 system. At a later date the soft- ‘ware programs can be upgraded, taking advan- tage of the powerful Z-80 instruction set and the full capability of the Z-80 component set to obtain increased performance and even further cost reduction for memory components. The Z-80 CPU is an extremely fast and versatile device. Full instruction cycle times for non-memory reference instructions are 1.648, and the CPU responds to interrupts very rapidly (the 8080 requires up to 6 times as long to respond, and uses more than twice as much memory storage). This fast interrupt response, in conjunction with new I/O block transfer instructions, allows the CPU to directly control many peripherals without the costly use of DMA hardware and it greatly reduces the size of software routines required for peripheral control, again saving memory space and costs. Probably the most important feature of the 2-80 microprocessor family is its repertoire of 158 software instructions. The original 78 instructions of the 8080A CPU are included using the same OP codes; thus, the Z-80 can execute 8080 or 8080A programs stored in existing ROMs. The Z-80 new software instruc- tions provide an expanded capability for the user, such as: Cl Additional addressing modes, including indexed and relative Memory to memory block transfers and searches CIBit manipulation and_testing in any register or memory location (i Many new I/O instructions, including block 1/0 transfers [1 A wide range of memory or register rotates and shifts (logical and arithmetic) Expanded 16-bit arithmetic Expanded BCD arithmetic.Z 80 Z 80A Parallel Input/Output (PIO) The Z-80 PIO circuit uses an advanced interrupt driven, program controlled I/O transfer technique for easy handling of virtually any peripheral with a parallel interface. Without other logic, the PIO can interface most line printers, paper tape readers or punchers, card readers, keyboards, electronic typewriters and other similar devices. The PIO contains all of the interrupt control logic nevessary for nested priority interrupt handling with very fast response time. Thus additional interrupt control circuits are not needed and servicing time is minimized. The parallel 1/0 can handle two high speed 1/0 ports, and it interrupts the CPU after each 1/0 transfer is complete The PIO circuit include two independent ports, each with eight 1/O lines and two hand- shake lines which are programmed by the CPU to operate in one of four modes: O Byte output with interrupt driven handshake O Byte input with interrupt driven handshake O Bidi- rectional byte bus with interrupt driven hand- shake C}Control mode wherein any bit can be programmed as an input or output. ‘A major feature of the PIO is its ability to generate an interrupt on any bit pattern at the 1/O pins, thus eliminating the need for the processor to constantly test 1/O lines for a par- ticular peripheral status condition. This feature greatly enhances the ability of the processor to easily handle peripherals, while also reducing software overhead Serial Input/Output (SIO) The SIO circuit is a programmable 1/0 device similar in concept to the PIO, except that it is designed to handle peripherals with a serial data interface such as floppy disks, CRTs and communication terminals. Each SIO circuit can handle a full duplex serial 1/0 channel. The device will handle data that is asynchronous with 5- to 8-bit characters and with 1,1} or 2 stop bits. The SIO will handle 5- to 8-bit syn- chronous data including IBM BiSyne and SDL communication channels. CRC generation and parity checking are also included Counter Timer Circuit (CTC) The CTC circuit contains four versatile clocks, each with its own nested priority interrupt control. All clocks have a minimum. resolution of 8us and can generate interrupts in the range of 84s to 32 ms. The circuit may also be used in a mode in which it counts external events. Another major feature is that an interrupt can be programmed to occur after the occurrence of an external event. The four tim- ing circuits greatly ease the CPU software handl- ing requirements for many real-time control applications. For example, the CTC allows the implementation of a very low-cost TTY or CRT 1/0 port, and simple sector control of floppy disk subsystems Direct Memory Access Controller (DMA) The DMA circuit is provided for those applications in which data must be transferred directly into memory at a very high rate rather than going through the central processor unit This not needed for most applications due to the fast interrupt response and block transfer capabilities of the Z-80 CPU. However, in large systems applications with many high speed peripherals, such as floppy disks, commu nications channels, etc., the DMA circuit can greatly improve system performance by totally controlling block transfers between I/O circuits and the system memory, The DMA circuit contains all control for four I/O circuits including a block length counter and a memory address pointer. The circuits also have a ripple priority chain so that virtually any number of DMA channels can be implemented. The DMA circuit communicates directly between the I/O circuits and the system memory after obtaining a DMA acknow ledge signal from the CPU.Mos INTEGRATED CIRCUITS Z 80-CPU Z 80A-CPU ‘The SGS-ATES Z80 product line isa complete set of micro- computer cOmponents, development systems and support software. The 280 microcomputer component set includes all of the circuits necessary to build high-performance microcomputer systems with virtually no other logie and a minimum number of low cost standard memory elements ‘The Z80 and Z80A CPU’s are third generation single chis microprocessors with unrivaled computational power. This increased computational power results in higher system through-put and more efficient memory utilization when compared to second generation microprocessors, In, addition, the Z80 and Z80A CPU’s are very easy to imple- ‘ment into a system because of theit single voltage requite- ment plus all output signals are fully decoded and timed to control standard memory or peripheral circuits, The circuit is implemented using an N-channel, ion implanted, silicon gate MOS process. Figure 1 isa block diagram of the CPU, Figure 2 details the internal register configuration which contains 208 bits of Read/Write memory that are accessible to the program. mer. The registers include two sets of six general purpose registers that may be used individually as 8-bit registers or as 16-bit register pairs. There are also two sets of accumu- lator and flag registers. The programmer has access to either set of main or alternate registers through a group of ex: ‘change instructions. This alternate set allows foreground] background mode of operation or may be reserved for very fast Interrupt response. Each CPU also contains a 16-bit stack pointer which permits simple implementation of Fig. 1,- 280, 280A CPU BLOCK DIAGRAM Product Specification multiple level interrupts, unlimited subroutine nesting and simplification of many types of data handling, ‘The two 16-bit index registers allow tabular data manipu: lation and easy implementation of relocatable code. The Refresh register provides for automatic, totally transparent refresh of external dynamic memories. The I register is used in a powerful interrupt response mode to form the upper 8 bits of a pointer to a interrupt service address table, while the interrupting device supplies the lower 8 bits of the pointer. An indirect call is then made to this service address. FEATURES © ‘Single chip, N-channel Silicon Gate CPU. ‘© 158 instructions—includes all 78 of the 8OBOA instruc ‘ions with total software compatibility. New instruc- tions include 4-, 8-and 16-bit operations with more useful addressing modes such as indexed, bit and relative 17 internal registers Three modes of fast interrupt response plus 8 non- maskable interrupt Directly interfaces standard speed static or dynamic ‘memories with virtually no external logic. 1.0 ns instruction execution speed © ‘Single 5 VDC supply and single-phase 5 volt Clock Out-performs any other single chip microcomputer in 4-,8., or 16-bit applications. All pins TTL Compatible © Built-in dynamic RAM refresh circuitry 2-780, 280A CPU REGISTERS a aZ 80-CPU Z 80A-CPU Pin Description Output, active low. RFSH indicates that the lower 7 bits of the address bus con- tain a refresh address for dynamic ‘memories and the current MREQ signal should be used to do a refresh read (all dynamic memories. Output, active low. HALT indicates that the CPU has executed a HALT software Instruction and is awaiting either a non: ‘maskable or a maskable interrupt (with the mask enabled) before operation can resume. While halted, the CPU executes NOP's to maintain memory refresh activity Input, active low, WATT indicates to the 2-80 CPU that the addressed memory or VO devices are not ready for a data transfer. The CPU continues to enter wait states for as long as this signal is active Input, active low, The Interrupt Request signal is generated by I/O devices. A request will be honored at the end of the current instruction if the internal soft. ware controlled interrupt enable flip-flop (IFF) is enabled Input, active low. The non-maskable interpt request line hs higher priority than INT and ie alvays recognized at the end of the eurent instruction, indepen- dent of the stats of the interrupt enable Nip-lop. NM automatically Tores the 7-80 CPU to restart to location 0066q Input, active low. RESET initializes the CPU as follows. reset interrupt enable Aip-flop, clear PC and registers { and R and set interrupt to 8080A mode. During reset time, the address and data bus go to ‘thigh impedance state and all control ‘output signals go to the inactive state Input, active low. The bus request signal has a higher priority than NMI and is always rec: ognized at the end of the current machine cycle and is used to request the CPU address bus, data bus and tri-state output control signals to go to a high impedance state so that other devices can control these busses. Output, active low. Bus acknowledge is used 0 indicate to the requesting device Acknowledge) that the CPU address bus, data bus and PIN CONFIGURATION RFSH (Reftesh) WALT & (Halt state) var (Wait) Ag-A15 __Teistate output, ctve high. Ag-A5 (Aaates Bus)consitute a Feit addres bus The address bus provides the adress fr memory (upto 64K bytes) date txchanges and for I/O device data exchanges. TF (Interrupt Dy-D7 Tristate input/output, active high Request) (Buta bus) Dp-D7 constitute an Bit bidivectional data bus. The data bus is sed for data exchanges wth memory and 1/0 devices wh Output, active low. hy indicates thatthe (Machine eurtent machine cycle the OP code rar Cycle one) fetch eycle ofan instruction execution (Non Interop HIRE —Tuistate output, active low. The memory (Memory request signal indicates thatthe address Request) bus holds valid addres for memory read or memory write operation RESET TORT —_ Tristate output, ative low. The TORO (Input) signal indicates that the lover hal ofthe Output address bus holds a vl 1/0 addres for Request) a1/O read or write operation An TORG Sigal is also generated when an interrupt is being acknowledged to indicate that an interupt response Yetorcan be placed onthe data bos , iUSRO (Bus _ Request) ®D “Tristate output, active low. KD indicates (Memory thatthe CPU wants to read dat from Read) memory or an I/O device. The addressed 1/0 device or memory should use this signal to gate data onto the CPU databus, BUSAK _ (us W Tristate output, active tow. WR indicates (Memory thatthe CPU data bus holds valid data to Write) be stored in the addressed memory or I/O. dec. tri-state control bus signals have been set to their high impedance state and the external device can now control these signals. 6Timing Waveforms INSTRUCTION OP CODE FETCH ‘The program counter content (PC) is placed on the address bus immediately at the start of the cycle. One half clock time later MREQ goes active. The falling edge of MREQ can be used directly as a chip enable to dynamic memories. RD when active indicates that the memory data should be enabled onto the CPU data bus. The CPU samples data with the rising edge of the clack state T3 Clock states T3 and Ty of a fetch cycle are used to refresh dynamic memories while the CPU is internally decoding and executing the instruction. The refresh control signal RFSH indicates that a refresh read of all dynamic memories should be accomplished MEMORY READ OR WRITE CYCLES Illustrated here is the timing of memory read or write cycles other than an OP code fetch (My cycle). The MREQ and RD signals are used exactly asin the fetch eycle. In, the case of a memory write cycle, the MREQ also becomes 4. ay active when the address bus is stable so that it can be used directly as a chip enable for dynamic memories. The WR line is active when data on the data bus is stable so that it» can be used directly asa R/W pulse to virtually any type Of semiconductor memory INPUT OR OUTPUT CYCLES IMlstrated here is the timing for an 1/0 read or 1/0 write operation. Notice that during I/O operations a single wait state is automatically insgrted (Tw*). The reason for this is that during I/O operations this extra state allows sufficient time for an 0 port to decode its address and activate the WATT line if a wait is required INTERRUPT REQUEST/ACKNOWLEDGE CYCLE ‘The interrupt signal is sampled by the CPU with the rising edge of the last clock at the end of any instruction. When an interrupt is accepted, a special My cycle is 7 generated. During this My cycle, the TORQ signal becomes active (instead of MREQ) to indicate that the interrupting. device can place an 8-bit vector on the data bus. Two wait states (Tw*) are automatically added to this cycle so that a ripple priority interrupt scheme, such as the one used in the saa 80 peripheral controllers, can be easily implemented r = aIT LOADS EXCHANGES Z 80-CPU Z 80A-CPU Instruction Set The following is a summary of the Z80, Z80A instruction set showing the assembly language mnemonic and the sym: bolic operation performed by the instruction. A more de- tailed listing appears in the Z80-CPU technical manual, and assembly language programming manual. The instructions are divided into the following categories: 8.bit loads Miscellaneous Group 16-bit loads Rotates and Shi Exchanges Bit Set, Reset and Test Memory Block Moves Input and Output Memory Block Searches Jumps S82 arithmetic and logic Calls 16-bit arithmetic Restarts General purpose Accumulator Returns ‘& Flag Operations In the table the following terminology is used 4 any 8-bit destination register or memory location. 44 = any 16-bit destination register or memory location e S:bit signed 2°s complement displacement used in relative jumps and indexed addressing L_— = 8 special call locations in page zero. In decimal notation these are 0, 8, 16, 24, 32, 40, 48 and 56 p any 8-bit binary number nn = any 16-bit binary number r any 8-bit general purpose register (A, B,C, D,E, H, or L) s any 8-bit source register or memory location sb = abit ima specific 8-bit register or memory location ss = any 16-bit source register or memory location subscript “L” = the low order 8 bits of a 16-bit register subscript “H” = the high order 8 bits of a 16-bit register oO the contents within the ( ) are to be used asa b a bit number in any 8-bit register or memory pointer to a memory location or I/O port number location Bit registers are A, B,C, D, E,H, L, land R cc = flag condition code 16-bit register pairs are AF, BC, DE and HL NZ = nonzero l6-bit registers are SP, PC, IX and IY Zz = ze10 NC = non carry Addressing Modes implemented include combinations of C= cary the following: Immediate Indexed PO. = Parity odd or noover flow Immediate extended Register PE = Patity even or over flow Modified Page Zero Implied P= Positive Relative Register Indirect M_ = Negative (minus) Extended Bit [Rncmonie] Syiate Opeaton | Comments Minnonie[Symbole Option [Comments ies [res sera) ii (DE) ~(HL), DE ~ DEN (UX+e), (1¥¢e), 2 HL + HL+1, BC + BC-1 war far dear | g{uom — | wey~au)ve-oes Uxseyciveey |Z HL THL+1. BC ~ BCI wan faen stl. 5 Repeat until BC= 0 Uxte) tive) | 2] LoD (DE) + (HL), DE ~DE-1 was | aes s=(60).(08). | HL + HL=1.BC~ BC-1 fan) LR 2] LopR (DE) ~ (HL), DE = DE-1 waa | ara a2(B),(08),| = HL~HL-1_B¢~ BC-1 (m1. LDdd.en | ddan dd = BC. DE HL.SP.IX.IY «dd = BC, DE. HL.SP,IX.1Y ss BC, DE HL, SP.IX.1Y ss=HL.IX,1V ss = BC, DE, HL, AF,IX.IY dd = BC, DE, HILAR IXY LD dd.inm) | dd -¢nny LD ¢amnss | (any —s5 LDP .ss PUSH ss SP oss (SP-1) = 554: (SP-2) © 55, MEMORY BLOCK SFARCHES POP ad EX DE.HL EX AF, AF" EXX. dy, ~ (SPF: day (SPN) DE=HL AF = AF" (i)(i) (SP) sp (SPH) rr atu EX (SP).s5 “SH Repeat until BC AHL), HL HLT BC = BC-1 AMHL). HL ~HL+1 BC = BC-1, Repeat until BC =O or A = (HL) AMHL).HL ~HL-1 BC = BC-1 AHL), HL = HLL BC ~ BC-1, Repeat until BC= Oor A= (HL) AeAtS Aw AtstcY Awa-s Ar A-s-CY AwAAs ArAYs AcAgs AHL) sets ‘the Mags only Aisnot affected CY isthe carry Mag s=1n.(HL) (42). (1¥82)Z 80-CPU Z 80A-CPU Mnemonic | Symbolic Operation | Comments Mnemonic [Symbolic Operation __| Comments 3 | crs Acs n (HL) | Birb.s 2-5 Zis zero flag 5 ixtey (lve) | 21 set b.s ~ Z)ice fanaet axsevdtvee | afsereys | aya! ss r(HL) F ity | g]reses | s~o Uxte). lve) 21 oe axte.avig | vica | aves WAw [ane wi [eer Set lags ADDHL,s| HHL +s iN ey fey. = HL ADC HL. | HL = HL #4 CY ; (OME HL g| secs | nt -s- cy IR | Ly (CDE “HL B/ ADIN | XX 58 Repeat until B=0 5 IND (HL) © (C),HL + HL - 1 2] apis: | vives Beet E HL) (0). HL = HL Ffincas | aanaars aizoc ne | &/NOR [AHL coum Lt HL. SP,IX.1Y Repeat until B=0 Caen |hesiies ww=acde | 2! ourma faa 7 oun: |cime aR Converts Acontents nto] Operands mus oun feat. nen e packed BCD following add | be im packed BeB-i 3 or subtract 'D format z Bel OTIR (C)~ (HL). HL = HL + 1 = — BeBe geet ack peat until B z]nee aw oo=a ou — fiers eH) cer c+ BeBe scF oer orpr |) cHL, HLL ‘NOP, No operation Re oot 0 HALT Halt CPU e : DI Disable Interrupts Pan [PC mae NZ PO ft Enabie Interrupts sPceam | Ifeondition eis te 2 PE imo Setinterupt mode | gogo mode Remaneconinae |®© 9 NCP m1 Setimenapt mode! | eallio0038y, | | RE Renters ie Setinterupt mode? | Indireer Call” | $[ IR kK. | 1 condition kk iste NZ_NC ce 2 PC HPC He, else continue |**Qz ¢ RICs = ws) PCH ss ss= ALIX e DINZ BHB-1.itB= Rls ao contin. else PC~PC +e ‘| CALL an (SPT) PCy NZ PO RRC s — 7 (52) FBC on Ne fo 5 - 5] CALL ce. nn | If condition ce is False ONC P RRs aa é contin. else sre a5 canal —s CALL nn SLAs Ta peer SLT 2 a ixrecives | 2 . 3] SRAs ah 3 Z ? Cc 5| seis Pep SPH) 2 RETee | Hf condtion eis ase Ne Po e continue.elsesame ss RET] JZ) Py a 3 syn 2| Ret! Return from interrupt = same as RET CoM RRD RETN | Return from non nase interruptZ 80-CPU Z 80A-CPU Z80-CPU A.C. Characteristics Ta=0°C to 70°C, Voc= +5V + 5%, Unless Otherwise Noted. me | awa | mie = «| Sgn | Soe tn oan we fc tots tact, Prior to FORG, RD or WRC (V0 Cycie) B) see : en aR SE a = oP | Rete oe fi ee 15) sem ah] Ren ak m = “oL@iny | TOR Ovty From Roy Ego Cock TORG Low 70 | wee uA ug | Ame Fe ane, me | Bein, ae mas, Sh we [mene] Hoes ate B50 eH ie bent rotten td Ta sm a Ee eee rs vse [gues | Frm on katethof Sct Rtn fae, «200 ores Load circuit for Output ‘Add nse ely for eich SOp increase in oad up 0 & maximum of 2009 for the dat bus 8100p for Mees contr ines Alt ata de ein gate gg 200s atm 10Z80A-CPU A.C. Characteristics Z 80-CPU Z 80A-CPU TA=0°C to 70°C, Veo= +5V 5%, Unless Otherwise Noted. Set [ome | Peance Min [me | one | torconiion 7 Gk od s(t | oe U1 fete ee ef Eie | Ris ans Tap ya aa vas | ie Aiken Suter WOH. RDwewRvoQse — ET cn ia Em gee 24685 a Acie Suton BD. WR, TOR MEG Tr a iat Aste Sse Fron RD WR Du at tr = “og | Sas Onpu ny 150_| wa Ph testo) 4-50 wPAoy |B Pt bing Wie ye a tSenoy | Date Sep Tete Ran ps Cd Dog MIC = 1) tact hans 4 Yon | EIB) | Benepe raya maou Fe Be] c= $001 ; mo s ARID Ter a 181 Maem fe oe Dua Sab Fm ik ti U8) tg tac@ty t= w 1 Ha ie fr Te fe [= Ph ae won) ‘oom, 5 [on wero (| mein) “epee mao BEL] cy sr z Hr oa 8) amy Pt wa BRE gh wr = 1 ain 1 ‘oem | WORD bey From Ren tap o Coos OR Low 75 | owe “! J coro | (Sti | xg Pom teat ORD oe BET opt ‘Dh | TORO Ose Frm Rang tf cic ORD ih pe oo ‘Ent | TORO Oeer om Ft ge ck FORD Hs apm ‘ove no) | Boney Fom Rn yo Coc, Rw os | wo | BEEIRD! | RB uy ror Fat tpt BD tow ST RET Cops *BugtRD) | RD Oy Hom Rime eas Gch RD gh fae 7 L *BUEInop | RB Oey Fo Fal ep ‘pLecwm) | When ron Rang Coca, WE ae 65 | oe am | (OUSt0n) |S oy From uy ga cc Lo BT HET C oge {Ohm | Ry Fan ge a hc Hp pe] oo Ctra | Rivet tne 7 a Wi bay Fon Rina i 100 (RL) *te99 Ri | man | Bt ouey Fe mn ae rc gh pee FAST | Ohtnes | _RFEH by Frm Rg Edo Cl Hae] S00 WaT [wats | _ WATE Setup Tne Flin Faget sk 0 me TACT [wa | BALT One Toe Fong tap Ck 300 | wwe | nF TA [wen | IR Stop Tn vo Rime gro Chk © = St | way | hmm Ai iow a = 4100) | BSR Scop Tinea Rag ge Ck 8 me “ube | BOSAR Oty Fron Rng igo cn, BISA wo [wx |. sae {Gatbay_ | BUSAE bey Promotie Ca BUSAR ah si aca RESET | sens) __ | BERET Supe Rag ag ak @ = eco) [Dey Fo RED TORS RD as ~ | o ‘ 1 Sai Rr WR ope A wm oe 108 tare gon 18S ‘Bt holed nah CPU dt ben I ane Deine aha te Load circuit for Output Souder whe and ORG eh ee a ‘The EET pl mat bate ors mma ack pet ewe ‘Add 1Onsc delay fr each SOp increase in Jad up to maximum of 20p for data bus and 10096 fr Ange aby ei 4 anes gga 2008 mnieZ 80-CPU Z 80A-CPU A.C. Timing DiagramZ 80-CPU Z 80A-CPU Absolute Maximum Ratings ‘Temperature Under Bias Specitied operating range Storage Temperature “65°C to #150°C Voltage On Any Pin with Respect to Ground -0.3V 10 #7 Power Dissipation 13 ‘Note: For 280-CPU all AC and DC characteristics remain the same forthe military grade parts excopt Tec Tce= 200 mA’ = Comment Strestes above those listed under "Absolute Maximum Rating” may cause permanent damage to the device. This isa stress rating only and functional operation of the device at these ot any other condition above those indicated inthe operational sections ofthis specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Z80-CPU D.C. Characteristics Capacitance Tas 25°C, f= 1 Mit, ee ‘vine | Glock Input High Voltage Vee-04| CN | put Capacitance s | ar [Yor | topo High Voltage 2 Vor | Output Low Voltage Thon | Te-State Output Leaks “| Thon | Tri-State Output Laka Z80A-CPU D.C. Characteristics Capacitance = = SSS Vine | Goskinpet ow Voruee “3 vt Co | Gockcapectunce | as | oF ‘Clock input High Voltage 06] Vecroal v | CIN Input Capacitase S| ar Input Low Voltage “09 Cour | Output Capacitance: io | oF | Vou | Outpet High Voltage ae [ar [ena aia isa Thon | Te-Siawe Output Leakage Curcent in Float Thor | Tw-State Ovtput Leskage Current in Float] | [ao ‘Da Bu tgs Caretin nyt Mode | 210 [oA [0 vivever |Z 80-CPU Z 80A-CPU PIN CONNECTIONS zeoceu MECHANICAL DATA (dimensions in mm) 40-PIN CERAMIC DUAL IN-LINE PACKAGE (METAL-SEAL} Z80CPU Z80CPU Z80ACPU Z80ACPU Z0CPU ZB0ACPU ORDERING NUMBERS: D1 for dual in-line ceramic package (metal-seal) 81. for dual in-line plastic package D1 for dual in-line ceramic package (metal-seal) B1_ for dual in-line plastic package F1_ for dual in-line ceramic package (frit-seal) FI. for dual in-line ceramic package (frit-seal). 40-PIN PLASTIC DUAL IN-LINE PACKAGE 40-PIN CERAMIC DUAL IN-LINE PACKAGE (FRIT-SEAL) are [8 JR a eee aMOS INTEGRATED CIRCUITS Z 80-PI0 Z 80A-PIO ‘The SGS-ATES Z80 product line isa complete set of micro- ‘computer components, development systems and support software. The Z-80 microcomputer component set includes all of the circuits necessary to build high-performance ‘microcomputer systems with virtually no other logic and @ ‘minimum number of low cost standard memory elements The Z-80 Parallel I/O (PIO) Interface Controller is a programmable, two port device which provides TTL com: patible interfacing between peripheral devices and the 280-CPU. The Z80-CPU configures the Z80-PIO to inter- face with standard peripheral devices such as tape punches, printers, keyboards, etc Structure © N-Channel Silicon Gate Depletion Load technology 40 Pin DIP © ‘Single 5 volt supply Single phase 5 volt clock ‘© Two independent 8-bit bidirectional peripheral interface ports with “handshake” data transfer control Features © Interrupt driven “handshake” for fast response ‘© Any one of the following modes of operation may be selected for either port Byte output Byte input Fig, 3 - PIO BLOCK DIAGRAM +sy GND INTERNAL, CONTROL tosic Product Specification Byte bidirectional bus (available on Port A only) Bit Mode Programmable interrupts on peripheral status conditions © Daisy chain priority interrupt logic included to provide for automatic interrupt vectoring without external logic © Eight outputs are capable of driving Darlington transistors, © All inputs and outputs fully TTL compatible PIO Architecture AA block diagram of the Z80-PIO is shown in figure 3. The internal structure of the Z80-PIO consists of 2 Z80-CPU bus interface, internal control logic, Port A 1/0 logic, Port B I/O logic, and interrupt controb logic. A. typical application might use Port A as the data transfer channel and Port B for the status and control monitoring The Port 1/0 logic is composed of 6 registers with “handshake” control logic as shown in figure 4. The registers include: an 8-bit input register, an 8-bit output register, a 2-bit mode control register, an 8-bit masktegistet, an 8.bit input/output select register, and a 2-bit mask control register. The last three registers are used only when the port has been programmed to operate in the bit mode. pata OR CONTROL. PERIPHERAL INTERFACE, ru INTERFACE P10 CONTROL LINES bata OR ConrROL Past * Not uae in bit mode. INTERRUPT CONTROL LINESZ 80-PI0 Z 80A-PIO Register Description interface pins that ae to be monitored and, if an inte. rupt should be generated when all unmasked pins are active (AND condition) of, when any unmasked pin is active (OR condition). y Mask Register—8 bits, loaded by the CPU to determine which peripheral device interface pins are to be moni Mode Control Register—2 bits, loaded by CPU to select the operating mode: byte output, byte input, byte bidiree: tional bus or bit mode. Data Output Register—8 bits, permits data to be transferred from the CPU to the peripheral Dats Input Register-8 bits, accepts data from the peri tored for the specified status condition pheral for transfer to the CPU. Input/Output Select Register—8 bits, loaded by the CPU to Mask Control Register~2 bits, loaded by the CPU tospecify "allow any pin to be an output or an input during bit the active state (high or low) of any peripheral device mode operation. Fig. 4 - A TYPICAL PORT 1/0 BLOCK DIAGRAM Neu oureur SELECT REG (arts) ‘oureuT ENABLE Data ourrur REG. (sBtTs) INTERNAL BUS, — para, input REG. sans) QED READY, ann. fase) Mask CONTROL REG. (ens) HANDSHAKE vreRnurr gL staKe REQUESTS JcontROL| crue LINES CONTROL STROBE *+ Used inthe bit mode only to alow generation of Interrupi the peripheral /0 pins go tothe specified stateZ80-PIO Pin Description Z 80-P10 Z 80A-PIO mi & TORO a RD Ere) om i 10 iNT AgAy a8 DyDy _-280-CPU Data Bus (bidvectional, tristate) BJA Sel_ Port Bor A Select (input, active high) ARDY C/D Sel Control or Data Select (input, active high) Bor TE Chip Enable (input, active ow) B STB ® System Clock (input) BROT, Timing Waveforms Machine Cycle One Signal from CPU (input, active low) Input/Output Request from Z80-CPU (input, active low) Read Cycle Status from the Z80-CPU (input, active low) Interrupt Enable In (input, active high) Interrupt Enable Out (output, active high). LEE and IEO form a daisy chain connection for priority interrupt control Interrupt Request (output, open drain, a low) Port A Bus (bidirectional, tristate) Port A Strobe Pulse from Peripheral Device (input, active low) Register A Ready (output, active high) Port B Bus (bidirectional, tristate) Port B Strobe Pulse from Peripheral Device (input, active low) Register B Ready (output, active high) OUTPUT MODE ‘An output cycle is always started by the execution of an output instruction by the CPU. The WR pulse from the CPU latches the data from the CPU data bus into the selected port's output register. The write pulse sets the ready flag after a low going edge of indicating data is available, Ready stays active until the positive edge of the strobe line is received indicating that data was taken by the peripheral. The positive edge of the strobe pulse generates an INT if the interrupt enable flip flop has been set, and if this device has the highest priority. INPUT MODE When STROBE goes low data is loaded into the selected port input register. The next rising edge of strobe activates INT if interrupt enable is set and this is the highest priority requesting device. The following falling edge of resets Ready (0 an inactive state, indicating that the input register is full and cannot accept any more data until the CPU completes a read. When a read is complete the positive edge of RD will set Ready at the next low going transition of . At this time new data can be loaded into the PIO. Te oT =HZ 80-PI0 Z B0A-PIO Timing Waveforms (continued) BIDIRECTIONAL MODE This is a combination of modes 0 and 1 using all four handshake lines and the 8 Port A 1/0 lines, Port B must be set to the Bit Mode. The Port A handshake lines are used for output control and the Port B lines are used for input control. Data is allowed out onto the Port A bus only when ‘ASTB is low. The rising edge of this strobe can be used to latch the data into the peripheral BIT MODE The bit mode does not utilize the handshake signals and a normal port write or port read can be executed at any time. When writing, the data will be latched into the output registers with the same timing as the output mode. ‘When reading the PIO, the data returned to the CPU will be composed of output register data from those port data lines assigned as outputs and input register data from those port data lines assigned as inputs. The input register will contain data which was present immediately prior to the falling edge of RD. An interrupt will be generated if interrupts from the port are enabled and the data on the port data lines satisfy the logical equation defined by the 8:bit mask and 2-bit mask control registers INTERRUPT ACKNOWLEDGE During MI time, peripheral controllers are inhibited from changing their intereupt enable status, permitting the INT Enable signal to ripple through the daisy chain, The peri- pheral with TEI high and IEO low during INTA will place a preprogrammed bit interrupt vector on the data bus at this time. IEO is held low until a return from interrupt (RETI) instruction is executed by the CPU while IEI is high. The 2-byte RETI instruction is decoded internally by the PIO for this purpose RETURN FROM INTERRUPT CYCLE If a 280 peripheral device has no interrupt pending and is not under service, then its IEO=IEI. If it has an interrupt under service (ie. it has already interrupted and received an interrupt acknowledge) then its IEO is always low, in- hibiting lower priority chips from interrupting. If it has an interrupt pending which has not yet been acknowledged, 1E0 will be low unless an “ED” is decoded as the frst byte af a two byte opcode. In this case, IEO will go high until the next opcode byte is decoded, whereupon it will again go low. Ifthe second byte of the opeode was a “AD” theh the opcode was an RET! instruction After an “ED” opcode is decoded, only the peripheral device which has interrupted and is currently under service will have its IEI high and its IEO low. This device i the highest priority device in the daisy chain which has receiv ced an interrupt acknowledge. All other peripherals have IEI-IEO. If the next opcode byte decoded is “4D”, this peripheral device will reset its “interrupt under service” condition. ae a (oes = “es =p ° Rf 181 80-PIO » > Z80A-PIO PIO Programming ae 3 LOAD INTERRUPT VECTOR INTERRUPT CONTROL. ‘The 280-CPU requires an 8-bit interrupt vector be supplied Bit 7= 1 interrupt enable is setallowing by the interrupting device. The CPU forms the address for interrupt to be generated, the interrupt service routine of the port using this vector. Bit 7=0 indicates the enable flag is reset and During an interrupt acknowledge cycle the vector is placed. interrupts may not be generated on the 2-80 data bus by the highest priority device request tenet m ing seve a that time, The desied mterupt vectors BSS by uae te mde tee loaded into the PIO by witing a contr word tothe gpeations otherwise they desired port of the PIO with the following format. e Bits 3,2,10 signify that this command word is an ee eee interrupt control word. ges this conned word isan inerroph a ae SS SELECTING AN OPERATING MODE When selecting an operating mode, the -bit mode con-__ If the “mask follows” bit is high (D4~= 1), the next trol register is set to one of four values, These two bits are control word written tothe port must be the mask the most significant bits of the register, bits 7 and 6: bits 5 and 4 are not used while bits 3 through O areal set to 1111 ye bso obs bs bobo to indicate “set mode.” : ee eS wo; Jao, ] mo, Jo, | ww, | we. m0, | my bbe bs bs bs ste = Cnty those pot tnes whose ai it mlb nontord or mfwofx]x fa fafa | pevesing tert == —S— mode word eis Mode word hee 3 ‘The interrupt enable flip-flop of a port may be set or reset without modifying the rest of the interrupt contcol eae |My word by the following command. bbe psp py? row raeiee oye ef x |x] xfofofi fa Input o fi Bidirectional | 1 |0 Bit uit MODE 0 active indicates that data is to be written from the CPU to the peripheral MODE | active indicates that data is to be read from the peripheral to the CPU. MODE 2 allows data to be written to or read from the peripheral device MODE 3 is intended for status and control applications. When selected, the next control word must set the 1/0. Register to indicate which lines are to be input and Which lines are to be output VO = | sets bit to input 1/0 = 0 sets bit to output. D7 be bs py byt _o a |Z 80-PIO Z 80A-PIO Z80-PIO A.C. Characteristics TA=0°C to 70° C, Vec = +5 V+ 5%, unless otherwise noted Number] Symbol | Parameter Min] Max Unk | Comments 1 (tec ‘lock Cyete Time 20 | ns 2 [Tech | Cock Wiath tight 105 | 2000 | ns, 3 [tect Clock iat (Low 105 | 2000 | ns a fac Clock Fall Time 30 | ns src. Clock fie Time — 30} ns 6 [iscsi [2 8/A-c/e to AD. TORO | Soup Time 50 os | (6) 7 |th ‘Any Hold Time for spectied Setup Time ° ns 8 —[stiicy | RB. ORG 10 Clock T Setup Time ns 8 9 |TaRNOO! | AD. TOAD 1 to Data Out Delay 380} ns | fa} 10—} reai0n—| HO, TORO T x0 Data Out Float Delay 110—b-ns 11 [Ts0uc! | Data tn wo Clock T Setup Time 50 ns | cL =50 oF 12 |raioKBon | TORG 4 to Bata Out Delay {INTA Cycle) 250 ns | (3) 13, ftshinica | 1 10 Clock T Setup Time 90 ns 14 [tstnici | RE T te Clock 1 Setup Time (Mt Cycle) 0 ns 15—framiieo) | MF E10 10.1 Delay tinterupe 190-}=ns immediately preceding M1) 190 [ons | (5}See Note 16 frstewior J fi 10 ORO. Setup Time (INTA Cyete) 140 ns | See Note A 17 fraieii€o |iei 1 t0 1€0 1 Delay 130 | ns | (51CL= 809 18 [Taiewion | 1E1 1 to 1€0. 1 Delay falter ED Decode! veo | os | 15) 19 }rstoic) | TORO T to Clack | Setup Time (To Activate EADY on Nex Clock Cycle) 220 ns 20—|TacinDvo-| Clock 1 0 READY T Delay 200. ns | [5]CL=509F 21 |racinDviy | clock | to READY | Delay 150 ns | I5) 22 |twsts | STHOBE Pulse wistn 150 (41 1 23 |restaic) | STROBE T 10 Clock | Setup Time (To Activate READY on Nest Clock Cycle) 200 ns 24 Jratoveo) | TORD 1 to PORT data stable Delay (Mode 01 reo} ons | 5 25-——{sPOISTBI- PORT DATA 10 STROBE 1 Setup Time (Mode 11 230. ns 26 [Tasted | STROBE | to PORT OATA Stable (Mode 2) 210 [ns | Is) 27 [rd5te(PDa | STROBE T to PORT OATA Float Delay (Mode 2) 180 | ns | CL= 50 pF 28 frapount) | PORT DATA Match to INT | Delay (Made 3) 490 | ns 29 [rdstaunti | STROBE T wo INT 1 Delay 4a0 | ns Output Load circuit Notes A 25 ToC > IN-2) Tall IEOG) + TAM INIEO) + TSIEIIO)¢TTL Butfer Dey. i any BM Must be acive lor @ minimum of 2 clock cyeles to reset the PIO U1] ToC wm Tah + TwCl + THC + TIC [2] increase TaRIID0) by 10 nsee for each 60 pF increase in loading up to 200 pF max [3] increase TaIOIDOT) by 10 nsec for each 60 pF inctease in loading up 10 200 pF mex [4] For Mode 2. TwSTB > TsPDISTB) 15] increase these values by 2 nsec fr each 10 pF ncrease in loBcing up to 100 pF max [6] TSCSIAI may be reduced However the ume subtracted from TsCStRI} will be added to TéRIIDO) Capacitance TA = 25°C, f= 1 MHz ‘Sybor [Porn [Mav [ Uni | Tes Condition Go| Chose Capiance | 10 | pF Unease Pins Co | Tare Capone |S] we] Retwned wv Gromnd Tour | Dorp Capacance] 10] pF 20Z80A-PIO A.C. Characteristics TA=0° C10 70° C, Vee = +5 V + 5%, unless otherwise noted Number] Symbol | Parameter min [ Max [unt | Comments 1 rec Clock Eyele Time oo [i | as 2 [tecn J cock wth (High) 170 | 2000 | ns 3 fect | Clack wien (Low 170 | 2000 | ns a rc Clock Fal Time s—re Clock Rige Time — 68 [rscsimn [CE 6/A c/t wo AD, TORO | Seup Time 50 a 7 | Any Hole Time lor spaced Setup Time ° & — fremuicr | RO, TORD to Clock 1 Setup Time 115 9 |rario0) |HB TOAD 1 w Oata Out Delay ago} ons | tl 10—fTaRi00r AO, TORT t to Data Out Flast Delay 160+ —ns 11 [repute | Date into Clack T Setup Time 50 ne | cL= 60 pF 12 fraioto0 | RG 4 to Data Out Delay {NTA Cyete) 340 ns | 13 frente | ML 10 Clock T Setup Time 210 ns 14 fremrien | iM T 20 Clock 4 Setup Time t Cyc) ° ns 18—fraMiieor4 M7 | 10 180 1 Daley nreropt 300 ns immediately preceding ML} ns | [5]SeeNoteA 16 4rstewioy 4161 to 1ORG “| Setup Time {NTA Cycle) 140 ns | See Note A 17 |raiesigoy Jet t to 1£0 | Delay yoo | ns | (s)cL=S00F 18 [ration | tei 1 to 0.1 Delay (ater EO Decode) 210 | ns | (6) 19 fTsi01C) | FORD. v0 Clock 1 Setup Time (To Activate READY on Nex Clock Creel 220 ns 20——| taciROvn Clock 1 to READY T Delay 200 ns | (s)cL=500F 21 |raciaow | Clock 4 to READY | Delay 150 ns | 81 22 |twste | STAOBE Pulse wath 150 (4 ne 23 [restarc) | StAOBE T 10 Clock 4 Setup Time (To Actwate READY on Next Clock Gye! 220 ns 24 [ratovPor [TORS T to PORT dato stable Delay (Mode 0) 200 | ns | is! 25 | 12PD(ST81-4 PORT DATA t0 STROBE T Setup Time (Mode 1h 260 fons 26 [rasrate0) | STROBE 1 wo PORT DATA Stable (Mode 2) 20 | ns | (5) 27 |TasTaieOa!| STROBE I to PORT DATA Float Delay (Mode 2) 200 | ns | cL = 50 oF 2a [rapouwn | PORT DATA Match 1o INT | Oslay (Mode 3) 540 | ns 2a [rastaunn | ST@ORE T to INT | Delay 430 | ns Notes A 25 TeC > (N-2) TAIE! UEOG) + TEMIKIEO! + TSIEMIO} + TTL Butter Delay. any B_MI Must be actve for @ minimum of 2 clock cycles to reset the PIO [n] Tec = Twch + TwCl + Tre + TIC [2] Increase TARI(DO} by 10 nsec for each 60 pF increase in loading up to 200 pF max [3] Increase TAIOIDOT! by 10 nsee for each 60 pF increase in loading up 10 200 pF max |] For Mode 2 TwSTB > TsPDISTE) [5] increase these values by 2 nsec for each 10 pF increase in loading up 10 100 pF max [6] TsCS(RI may be reduced However the time subtracted from TsCS{RI will be added 10 TAROO}Z 80-PI0 Z 80A-PIO A.C. Timing Diagram Timing measurements are made at the following voltages, Unless otherwise specified: " “ Lock Vg¢-06v aay ouruT av oav input av osv FLOAT av +05V —o— O41 PO{-@ or | Ae teenc® = ——\__~ | os | _ h—@f4 pO -4@t | mi a aay oy a4 ovo 4 toro m eT ek | e~ ve. D GxRor on 8Rov) ‘STROBE _ ®@ (AST on BSTB) i ove! aorZ 80-PI0 Z B0A-PIO Absolute Maximum Ratings ‘Temperature Under Bias Storage Temperature Voltage On Any Pin with Respect to Ground Power Dissipation ‘Specified operating range “65°C to +150°C -0.3V 10 1V 06 Note: All ACand DC characteristics remain the same for the military grade parts except Toe Tec= 130 mA + Comment Stresses above those listed under "Absolute Maximum Rating” may eause permanent damage to the device. This isa stress rating only and functional operation of the device at these or any other condition above those indicated in the operational sections of this specification is not implied. ! xposure to absolute maximum rating conditions lor extended periods may alfect device reliability Z80-PIO and Z80A-PIO_ D.C. Characteristics TA= 0°C to 70°C, Veo= +5V + Se, unless otherwise noted Symbol Parameter Min. [ Max. | Unit | _ Test Condition ViLc Clock Input Low Voltage -03 | 045 [ V VinC Clock Input High Voltage Voo-0.6 [Vecr0.3] V Vit Tapa Cow Voltage “os Por PV Vin Tapa High Voltage 2 [ve PV Vou Ouipui Low Voltage OF | V_] tors20ma Vou ‘Output High Voltage ia VT] ton. 25000 Tec Power Supply Current 70 | wa ty Tpit Leakage Current TO [aA] Vjy = O10 Vee Ton TriSiate Output Leakage Corrent mn Float 10 [BA | Voyr= 2440 Vee ion Tri Stave Ovipav Leakage Corvent in Float <10[#A | Voyp=04V un) Data Bus Leakage Current in Input Mode 210 | WA | O". —— write signal, it intemally generates its own from the lack of an RD signal. CTC READ CYCLE Illustrated here is the timing for reading a channel's, Down Counter when in Counter Mode. The value read PULL. onto the data bus reflect the numberof external clocks op eC rising edges prior to the rising edge of cycle (T), No wait states are allowed for reading the CTC other than the auto- ee matically inserted (Ty). INTERRUPT ACKNOWLEDGE CYCLE. Some time after an intereupt is requested by the CTC.the 5 PPL CPU will send out an interrupt acknowledge (Mi and IORQ). During this time the interrupt logic of the CTC will determine, “——\ _ the highest priority channel which is requesting an interrupt. To insure that the daisy chain enable lines stabilize, channels are inhibited from changing their interrupt request status when Mi is active, If the CTC Interrupt Enable Input (IE1) is active, then the highest priority interrupting channel places the contents ofits interrupt vector register onto the Data Bus when TORO goes active. Additional wait cycles are allowed. onaZ 80-CTC Z 80A-CTC Timing Waveforms (continued) RETURN FROM INTERRUPT CYCLE If a Z80 peripheral device has no interrupt pending and is, not under service, then its IEO = IEI. If it has an interrupt under service (i. it has already interrupted and received an interrupt acknowledge) then its IEO is always low, inhibit: hob om oN eo om ing lower priority chips from interrupting. If it has an inter. PULL nn rupt pending which has not yet been acknowledged, IEO will be low unless an “ED is decoded as the first byteofa = LY NLS two byte opcode. In this case, 1EO will go high until the next opcode byte is decoded, whereupon it will again go low. If \—/ Law the second byte of the opcode was a“4D" then the opcode 9,» @ C= was an RET! instruction, un @) C=) After an “ED” opcode is decoded, only the peripheral se device which has interrupted and is currently under service will have its IEI high and its IEO low. This device isthe high- © 9 est priority device in the daisy chain which has received an interrupt acknowledge. All other peripherals have TEI = IEO. Ifthe next opcode byte decoded is “4D”, this peripheral device will rset its “interrupt under service” condition, Wait cycles are allowed in the BT cycles. DAISY CHAIN INTERRUPT SERVICING eg ae wets owns Illustrated at right is a typical nested interrupt sequence | FOEeTY TERNGFT Gait CONE EEFORE ew Se Which may occur in the CTC. In this sequence channel 2 LG ae ae fap interrupts and is granted service. While this channel is being + emNTTWT0ans a tTaRST apa cE serviced, higher priority channel 1 interupts and is granted Lap fra} ff GS service. The service routine for the higher priority channel 2 cnaNnECTNTERRUPIS, SEPENUSTERTING 0” CRNRNETT is completed and a RET! instruction is executed to indicate Stewed cme See so to the channel that its routine is complete At ths time the Sf} for eh for off coer a a eS Ane Ne eo TERE a RTT iy, aN TE CTC COUNTING AND TIMING In the counter mode the rising or falling edge of the CLK LL input causes the counter to be decremented. The edge is detected totally asynchronously and must have a minimum xx f—-~ /——-* CLK pulse width. However, the counter is synchronous with therefore a setup time must be met when itis desired to. gem [wai have the counter decremented by the next rsing edge of a, eS PL In the timer mode the prescaler may be enabled by a rising or falling edge on the TRG input. As in the counter mode, the edge is detected totally asynchronously and must have ‘a minimum TRG pulse width. However, when timing is to start with respect to the next rising edge of a setup time must be met. The prescaler counts rising edges of & a [waning 28CTC Programming Z 80-CTC Z 80A-CTC SELECTING AN OPERATING MODE When selecting a channel’s operating mode, bit ® is set to | to indicate this word isto be stored in the channel control register. a = Bit7=9 Channel interrupts disabled Bit7=1 Channel interrupts enabled to occur every time Down Counter reaches a count of zer0. Setting Bit 7 does not let a preceding count of zero cause an interrupt. Bit6=9 Timer Mode ~ Down counter is clocked by the prescaler. The period of the counter is + Pe TC te = system clock period P= presale of 16 or 256 TC = 8 bit binary programmable time constant (256 max) Bit Counter Mode ~ Down Counter is clocked by external clock. The prescaler is not used. BitS=@ Timer Mode Only-System clock # is divided by 16 in prescaler. Bit Timer Mode Only-System clock @is divided by 256 in prescaler Bit4=@ Timer Mode ~ negative edge trigger starts timer operation Counter Mode — negative edge decrements the down counter Bit ‘Timer Mode — positive edge trigger starts timer operation Counter Mode — positive edge decrements the down counter Bit 3=9 ‘Timer Mode Only ~ Timer begins operation con the rising edge of T2 of the machine cycle following the one that loads the time constant. Timer Mode Only — External trigger is valid for starting timer operation ater rising edge of Tp of the machine eycle following the cone that loads the time constant. The Pre- scaler is decremented 2 clock cycles later if the setup time is met, otherwise 3 clock cycles. Bit2=9 No time constant will follow the channel, control word. One time constant must be written to the channel to initiate operation Bit 2 The time constant for the Down Counter will be the next word written to the selected channel. [fa time constant is loaded while a channel is counting, the present count will be completed before the new time constant is loaded into the Down Counter Bit 1=9 Channel continues counting, Bit | Stop operation. If Bit 2= 1 channel will resume operation after loading a time constant, otherwise a new control word ‘must be loaded. LOADING A TIME CONSTANT ‘An 8.bit time constant is loaded into the Time Constant register following a channel control word with bit 2 set. All zeros indicate a time constant of 256 LOADING AN INTERRUPT VECTOR ‘The Z80-CPU requires that an 8-bit interrupt vector be supplied by the interrupting channel, The CPU forms the address for the interrupt service routine of the channel using this vector. During an interrupt acknowledge cycle the vector is placed on the Z80 Data Bus by the highest priority channel requesting service at that time. The desired interrupt vector is loaded into the CTC by writing into channel @ with a zero in DQ. D7-D3 contain the stored in terrupt vector, D2 and Dy are not used in loading the vector ‘When the CTC responds to an interrupt acknowledge, these two bits contain the binary code of the highest priority channel which requested the interrupt and Dg contains a zero since the address of the interrupt service routine starts at an even byte, Channel @ is the highest priority channeli Z80-CTC A.C. Characteristics TA=0°C 10 70° C, Veo= +5 V # 56, unless otherwise noted Number] Symbol _| Parameter Min | Max Unit | Comments 1 [rec Clack Cyele Time 250 | 1d ns 2 fwch | Clock wrath tHigh 108 | 2000 ns 3 |twet | Clock Wieth Low! 105 | 2000 ne a fic Glock Fall Time 30 rs sre Clock Rise Time 30 ne 6 |tm All Hold Times. 0 rs +7 |tscsicr | CS to Clack T Setup Time 160 ns +8 |tsce(c) | CE to Clock 1 Setup Time 180 ns 9 [si0(C) | TORE 1 10 Clock T Setup Time ns ns 10—JTsRDIC) | FD to Clock 1 Setup Time 118 ns sit ]facioor | Clock Ito Data Out Delay 200 rs | 2 12 |TaCiDGz) | Clock 1 to Data Out Finet Delay 110 ne 13, |ts01Ic) | Data in to Clack} Setup Time 50 ns 14 [Tswnic) | RAT to Clock 1 Setup Time (INTA or MI Cyciel 80 ne 15—fTawn iO) | RTF to 1EO L Delay interrupt 190. ns Isl immediately preceding M1 1 | See Note A 16 |TalOlOOTI | TORD 1 to Data Our Delay {INTA Cycle) 160 ns |i) 17 Jraienigon | 1611 10 10 1 Delay 130 as |3) ta |rateieon | 111 to 160 1 Delay (ater ED Decoded 160 ns | 131 sig |racunt) | Clock t to INT 4 Delay TeC+160 | ns | Timer Made *20—4TaCTRIINT!] CLK/TRG T to INT 1 TsCTAIC) Sausied TeC+160 | ns | Counter Mode TsCTAIC) not Satsties 27eC+370 | ne 21 frectr | CLK cycle Time Det ns | Counter Made 22 ;rectR | CLk/TAG Rise Time 50 ns 23° |rictR | CLk/TRG Fall Time 50 ne 24 fTweTRL | CLK/TAG width (Low) 200 ne 25—fTweTRn—] CLK/TRG Width (High) 200: 8 26 |TsCTRICe) | CLK’ to Clock 1 Setup Time for Immediate Count | 210 1s | Counter Mode 27 [TSCTAICH) |.TRG 7 to Clack 1 Setup Time for 210 ns | Timer Mode enabling of Prescaler an following Clock 1 28 fracizcton)| clock T te 2¢/TO | Delay 190 ns 29 |Tacizcron] Clock 1 to 2¢/T0 1 Delay 180 ne — Notes. A 25 TeC > (N-2) THIEIIEOF)+ TAM I1EO) +TSIEIIO) 8 RESET rmust be actwe for a minimum of 3 clock cycles In] ToC = TwCh + TwCl + Toc + TC {2| increase delay by 10 nsec lor each 80 pF increase in loading. 200 pF maximum for data lines and 100 pF for control hme [3] Increase delay by 10 nsec for each 10 pF increase in losding. 100 pF maximvin OUTPUT LOAD CIRCUIT 30Z 80-CTC Z 80A-CTC Z80A-CTC A.C. Characteristics TA=0°C to 70°C, Vec=45 Ve Number symbol | Parameter Min | Max Unit [ Comments 1 fre Clock Cycle Time 400 | 111 ns 2 |rwen | Clock whath tHigh) 170 | 2000 ns 3 Jrwet | Chock wrath (Low) 170 | 2000 ns a lnc Clock Fall Time 30 ns pre Clock fise Time 30: ns 6 [tm All Hold Times, 0 ns 17 |Tscsic) | cS to Clock 7 Setup Time 250 ns sa |tsceici | EE to Clock 1 Setup Tme 200 ns 9 |rsi01c} | TORG F to clock 1 Setup Time 250 ns 10-4 TsADIC)— RD 10 Clock 1 Setup Time 240 ns sir |racioo) | ciock 1 te Data Out Delay 240 ns | 21 12 |acid02 | Clock 1 to Date Out Float Delay 230 fs 13, [TsDI(C) "| Data in 10 Clock 1 Setup Time 60. 5 14 [fsM110)_ | MI to Clack 1 Setup Time MINTA or M1 Cycle) 210 vs 15—raMni€O)4 ML 10 1E0 1 Delay linterupt 300 ns | Ia) immediately preceding M1) See Note A Tai0100T1 | 1ORG I to Data Out Delay LINTA Cycle) 340 ns | 2) TAIENIEOD | JEL 1 to {EO | Delay 190 ns | 13) TaIEIIEGH | 1E1 T 10 EO 1 Delay (alter EO Decode! 220 ns | (3) TéCUNT) | Clock 1 10 INT 1 Delay rec+230_| ns | Timer Moge 20 —JTACTKUNTY CLR/TAG 1 to INT L TsCTAIC) Satisted rec+230 | ne TSCTAIC) not Saustod 2tec+530 | ns 21 [recta | CLK cycle Time. ec ns 22 [rcTA | CLK/TAG Rize Time 50 ns 23° |ricta | ctk/TAG Fall Tme 50 2 2a [rwctaL | CLk/TAG Wath (Low) 200 ns 25 —fweTah—t CuK/TAG With [High 200. ns 26 [rsctricel | CLK’ T to Clock 1 Setup Time for imme 300 ns | Counter Mode 27 [tsctRico | TAG T to Clock 1 Setup Time for 210 ns | Timer Mode enabling of Prescaler on follawing Clack T 28 |racizcton] Clock T 10 2c/70 1 Delay 260 ns 29° frac@cton| clock 1 10 2/70 | Delay 190 as Noles A 28 ToC > IN-2} TAIEIIEOF)4TAM EO) +TsIEILO) 8 ESET must be actwe for a minimum of 3 clack cycles In] Tec = Twch + TwCl + TeC + TH 12] increase delay by 10 nsec for each 50 pF increase in loading, 200 pF maximum for data lines and 100 pF for contol ines 13] Increase delay by 10 nsec for each 10 pF increase in loading, 100 pF maximum OUTPUT LOAD CIRCUIT 31Z 80-CTC Z 80A-CTC A.C. Timing Diagram unless otherwise specified: ‘Timing measurements are made at the following voltages, clock vec: oureur 2 NeuT 2 Fiat a \ Pa as 1 ee a 2 a ® «+ » =. Nee a CON a ° Osv 0.4sv v oav Vv av v 205Z 80-CTC Z 80A-CTC Absolute Maximum Ratings Temperature Under Bias Storage Temperature Voltage On Any Pin with Respect to Ground Power Dissipation Toc 65°C to H150°C -0.3V to HV 0.8W + Comment Stress above those listed under "Absolute Maximum Rating” may cause permanent damage to the device. This i stress rating only and functional operation of the device at these or any other condition above those indicated in the operational sections ofthis specification is ‘not implied, Ixposure o absolute maximum rating conditions for extended periods may affect device lability Z80-CTC D.C. Characteristics TA= 0°C to 70°C, Veo= SV + 5% unless otherwise specified Symbol Poramet Min | Max | Unit| Test Condition Vite _| Clock input Low Voltage -03 | 048 v Vine _| Clock input High Voltage [1 ~__[vec-06 | vecro3 Vit___| input Low Voltage 7 03 08 Vint _| lnput High Voltage 2 Vee Vor _| Output Low Voltage oa Von __| Output High Voitage 24 loc___| Power Supply Current a 120 mA | Te = 400 nsec tu Input Leakage Current — 10 HA | Vin=0t0 Voc, WLOH | TriState Output Leakage Current in Float 10 | wA | Vout =24 1 Voc WoL _| Tri-State Output Leakage Current in Float} =10 [| #A | Vout | lop | Darlington Drive Current - “18 mA | Vou = _ _ _ | Rext Z80A-CTC D.C. Characteristics TA=0°C to 70°C, Veo= SV + 5% unless otherwise specified Parameter Max _| Unit| Test Condition | Clock Input Low Voltage ~ 0.45 v Clock Input High Votiage (1) vecto3| Vv Input Low Voltage - [os fv Input High Voltage 2 Vec__| Vv Output Low Voltage - 0.4 V_] to. =2ma Output High Voltage 24, V_| ton = -250 HA Power Supply Current 120 mA | To = 250 nsec Input Leakage Current 7 10 | #A | Vin =0t0 Voc Tri-State Output Leakage Current in Float 10 | uA | Vour=24t0 Vee Tri-State Output Leakage Current in Float x10 | «A | Vour=04v Darlington Drive Current 15 mA | Von = 15V Rext = 39082 33Z 80-CTC Z 80A-CTC Capacitance TA= 25°C, f= 1 MHz Symbol Parameter Max Unit “est Condition Clock Capacitance 20 °F Tnmeasured Pine civ Input Capacitance 5 7 Returned to Ground Cour ‘Output Capacitance 0 °F PIN CONNECTIONS ORDERING NUMBERS: Z80CTC D1 for dual in-line ceramic package (metal-seal) % — ZB0CTC 81 for dual in-line plastic package & — Z80ACTC D1 for dual in-line ceramic package (metal-seal) % Z80ACTC B1 for dual in-line plastic package x Z80CTC —F1_ for dual in-line ceramic package (frit-seal) wr zeocTe gnmmey Z8QACTC FI for dual in-line ceramic package (frit-seal) Ea zeoactc 3) ‘om mt 28-PIN PLASTIC DUAL IN-LINE PACKAGE 28-PIN CERAMIC DUAL IN-LINE PACKAGE (FAIT-SeAL) A ws ms T Te amt 34MOS INTEGRATED CIRCUITS Z 80-DMA Z 80A-DMA The Z-80 DMA (Direct Memory Access) circuit is a pro- ‘grammable single-channel device which provides all address, timing and control signals to effect the transfer of blocks of data between two ports within most microprocessor-based systems. These ports may be either system main memory or any system peripheral I/O device. The DMA can also search a block of data for a particular byte (bit maskable), with or without a simultaneous transfer. Structure © ‘Nechannel Silicon Gate Depletion Load Technology © 40 Pin DIP © Single 5 volt supply © Single phase 5 volt clock © Single channel, two port Features © Three classes of operation: ~Transfer Only Search Only ~Search-Transfer © Address and Block Length Registers fully buffered Values for next operation may be loaded without dis: turbing current values. © Dual addresses generated during a transfer (one for read port and one for waite port). © Programmable data transfers and searches, automatic ally incrementing or decrementing the port addresses from programmed starting addresses (they can also remain fixed), Fig. 7 - DMA INTERNAL BLOCK DIAGRAM Product Specification © Thee modes of operation: —Byteatactime’ One byte transferred per request Burst: Continues as long as ports are ready Continuous: Locks out CPU until operation complete © Timing may be programmed to match the speed of any port © Interrupts on Match Found, End of Block, or Ready, may be programmed. © An entire previous operation may be repeated automat ically or on command. (Auto restart or Load) ‘© The DMA can signal when a specified number of bytes has been transferred, without halting transler ‘© Multiple DMA’s easily configured for rotating priority © The channel may be enabled, disabled or reset under software control © Complete channel status upon program (CPU) request Up to 1.25 megabyte/second Search, © Daisy-chain priority interrupt and bus acknowledge in cluded to provide automatic interrupt vectoring and bus fequest control, without need for additional external logic © TTL compatible inputs and outputs © The CPU can read current Port counters, Byte counter, or Status Register. A mask byte can be set which defines which registers can be accessed during read operations sv GND INT 11 1c0 @USRG oxi BRD ROY aE BVTEIPULSE THT PRIORITY Gountee COMPARATOR, tote eusrRioniry = BkOR PULSE INTERVAL ee teste LENGTH TNT VECTOR ASAT F TORRE] | a wenn ADDRESS COMPARE MASK cours = corre COMPARATOR as ao o7 tit 50 TENG (ORG 35Z 80-DMA Z 80A-DMA DMA Architecture AA block diagram of the Z80 DMA is shown in Figure 7. ‘The internal structure consists of the following circuitry © Bus Interface. provides driver and receiver circuitry 10 interface to the Z80-CPU Bus. © Controt Logicand Registers. set the class, mode and other basic control parameters of the DMA © Address, Byte Count and Pulse Circuitry: generates the proper port addresses for the read and write operations, with provisions for incrementing or decrementing the address. When zero bytes remain to be handled, the byte count circuitry sets a lag in the status register. Pulse circuitry generates a pulse each time the byte counter lower 8-bits equal the pulse register. © Timing Circuitry: allows the user to completely specify the read/write timing for each port © Match Circuitry. holds the match byte and a mask byte which allows for the comparison of only certain bits within the byte. If a match is encountered during a Search of Transfer, this circuitry sets «flag in the status register. © INT and BUSRO Circuitry: includes a control regis- tet which specifies the conditions under which the DMA. can generate an interrupt; priority encoding logic to select, between the generation of an INT or BUSRO output under these conditions; and an interrupt vector register for automatic vectoring to the interrupt service routine ‘© Status Register: holds current status of DMA Register Description ‘The following DMA-internal registers are available to the programmer: Control Registers: Write only; 8 bits. Hold DMA control information: such as, when to initiate an interrupt or pulse, what mode or class of operation to perform, etc. Timing Registers: Write only; 8 bits. Hold read/write timing parameters for the two ports. Interrupt Vector Register: Read/write; 8 bits. Holds the bit vector that the DMA will put onto the data bus after receiving an TORO during an interrupt acknowledge se- quence if itis the highest priority device requesting an interrupt. (This register is readable only during interrupt acknowledge cycles.) Block Length Register: Write only; 16 bits. Contains total block length of data to be searched and/or transferred, Byte Counter: Read only; 16 bits. Counts number of bytes transferred (or searched). On 2 Load or Continue the Byte Counter is reset to zero. Thereafter, each byte transfer o- peration increments it until it matches the contents of the Block Length Register, at which time End of Block is set in. the status register and operation is suspended if program- med. Also if so programmed the DMA will generate an Interrupt. Match Register: Write only; 8 bits, Holds the byte for which a match is being sought in Search operations Mask Register: Write only; 8 bits. Holds the 8-bit mask to determine which bits in the match register are to be ex- amined for a match. Starting Address Registers (Port A and Port B): Write only: 16 bits each. Hold the starting addresses (upper and lower 8 bits) for the two ports involved in Transfer operations. In Search Only operations, only one port address would have to be specified. Only memory starting addresses require both upper and lower 8 bits; 1/0 ports are generally ad- dressed with only the lower 8 bits, and in this case the ad- ress contained in the register isa generally fixed address. Address Counters (Port A and Port B): Read only; 16 bits each. These counters are loaded with the contents of the corresponding Starting Address Registers whenever Search- es or Transfers are initiated with a Load or Continue, They are incremented, decremented or remain fixed, a& prow grammed. Pulse Control Register: Write only; 8 bits. The content of this register is continuously compared with the lower eight bits of the byte counter. When they become equal, the INT Output _is activated. Since this occurs while BUSRO and BUSAK are both active, the CPU does not interpret this as ‘an interrupt request. Instead, the signal is used to commun- ‘cate with a peripheral I/O device. When the Pulse Control Register contains a value n, the frst pulse is generated after n+ I bytes of search or transfer. The next and all subse quent pulses occur at 256-byte intervals Status Register: Read only; 8 bits. Match, End of Block, Ready Active, Interrupt Pending, and DMA Cycle Occurred bits indicate these functions when set Modes of Operation The DMA may be programmed for one of three modes of operation. (See Command Register 2B.) ‘© Byte at a rime. control is returned to the CPU after each one-byteeyele 4 Burst: operation continues as long as the DMA’s RDY input is active, indicating that the relevant port is ready Control returns to the CPU when RDY is inactive or at end of block or a match if so programmed © Continuous: the entire Search and/or Transfer of a block of data is completed before control is returned to CPU 36Z 80-DMA Z 80A-DMA Classes of Operation The DMA has three classes of operation: Transfer only, Search Only and 2 combined Search-Transfer. (See Com ‘mand Register 1A.) During a Transfer, data is first read from one port and then written to the other port, byte by byte. (The DMA's two ports are termed Port A and Port B.) The ports may be programmed to be either system main memory or peripher- al 1/0 devices. Thus, a block of data might be written from 4 peripheral to another; or it might be written from one area in main memory to another; or from a peripheral to main memory During a Search, data is read only. and compared byte by byte against two DMA-internal registers, one of which con tains a match byte and the other an optional mask byte which allows only certain bits to be compared. It any byte of searched data matches, a DMA-internal status bit is set Hf programmed to do so, the DMA will then suspend operation andor generate an interrupt The third class of operation is a combined Search- Transfer. in such an operation a block of data is transferred 4s described above until a match is found; then, as in a Search Only operation, the transfer may be suspended and/ (or an interrupt generated Addressing ‘The DMA’s addressing of ports is either fixed or sequen- tial, incrementing or decrementing from a starting address. ‘The length of the operation (number of bytes) is specified by the programmed contents of a block length register. The DMA can address block lengths of up to 64K bytes. During a . transfer two separate port addresses are generated, one dur- ing the Read cycle and one during the Write cycle. Operating Sequence Once the DMA has been progammed it may be “En- abied" (Command Regster 28 08 2D), In the enabled con dition when Ready gee tle the DMA wil requ fhe bus by bringing BUSRG low. The CPU will acknowledge this wih's BUSACK whl normaly be atached fo BAL When the DMA recenes BAT wl sat is progam med operation relesing BUSRE fo “high sate hen Tt is through. Z-80 DMA Pin Description Ap-Ais System Address Bus. All sixteen of these pins are used by the DMA to address system main mem ory or an YO port (output) Do-D; System Data Bus. Commands from the CPU, DMA status and data from memory or peripher: als are transferred on these tristate pins (input) output) sv Power GND Ground o System clock (input) WI Machine cycle One signal from CPU (input) TORG Input/Output Request to and from the System Bus (inputfoutput) MREQ — Memory REQuest to the System Bus (input/ output) RB ReaD to and from the System Bus (inputfoutput) WR WRite toand from the System Bus (inpuyoutput) CEIWATT Chip Enable: may also be programmed to be WAIT during time when BAT is low (input) BUSRQ BUS ReQuest. Requests control of the CPU Address Bus, Data Bus and Status/Control Bus Gnput/output, open drain) BAT Bus Acknowledge In. Signals that the system buses have been released for DMA control (input) BRO Bus Acknowledge Out. BAT and BAO form a daisy-chain connection for system-wide priority bus control (output) INT —_INTerrupt request (output, open drain) te Incerrupt Enable In (input) TEO Interrupt Enable Out IEl and IEO form a daisy- chin connection for systemwide priority inter rupt control (output) RDY ReaD is monitored by the DMA to determine whena peripheral device associated with a DMA. port is ready for a read or write operation input. programmable as active high or low) 37Z 80-DMA Z 80A-DMA DMA Timing Waveforms : +m DMA Command Write Cycle ati Iustrated here is the timing associated with a command byte or control byte being written to the DMA which is to be loaded into internal registers. 280 Output instructions satisfy this timing, DMA Register Read Cycle ‘This timing is used when a read operation is performed on, the DMA to access the contents of the Status Register, ‘Address Counter or other teadable registers. 280 Input in: structions satisly this timing. STD Memory Timing This timing is exactly the same a5 used by the Z80-CPU to acest system main memory, either ina Read or Write operation. The DMA will default to this timing after 3 power-on reset, or when a Reset or Rest Timing command Brariten toi and unless otherwise programmed, will se =m ihstimingduringal Transfer or Search operations involving system main memory. During the memory Read portion of : 2 transfer cycle, data is latched inthe DMA onthe negative rm tage of @ during Ty and hed into the fllowing Write eyce Daring the memory Write portion ofa transfer cycle, data = is held from the previous Read cycle and celessed atthe end OF the present eyce 4 NOTE: The DMA is normally programmed for a 3 T-cycle ----| duration in-memory transactions. But WATT is spun sampled during the negative transition of Tp, and *EADOAAr sotto if it is low, Ty will be extended another Tyee, ante during which WAIT will again be sampled. The aie auras Heo rnowranwoue ead [}—— duration of a memory transaction cycle may thus be indefinitely extended. “atone oma om ps puninsa manaree STD Peripheral Timing ‘This timing is identical to the Z80-CPU's Read/Write timing 00 —t{ to WO peripheral devices. The DMA will default to this { timing after a power-on reset, or when a Reset or Reset — | Timing command is weitten to it; and unless otherwise pro- a ie | / grammed, wall use this timing during all Transfer or Search | of a transfer cycle, data is latched on the negative edge of during T3 and is then held into the Write cycle. During an WO Write, data is held from the previous Read cycle until = \ the end of the Write cycle neoune NOTE. If WAIT is low during the negative transition of © “*®08¢ Slee Tw*. then Ty* will be extended another T-eyele t and WATT will again be sampled. The duration of @wmteanra:”-nevormonrnawousniao peripheral transaction eycle may thus be indefinitely extended 38DMA Timing Waveforms (continued) Z 80-DMA Z 80A-DMA Variable Cycle ‘The Variable feature of the DMA allows the user to program the DMA's memory or peripheral transaction timing to values different than given above inthe standard default diagrams This permits the designer to tailorhis timing to the particular requirements of his system components, and maximizes the data transfer rate while eliminating external signal condition ing logic. Cycle length can be two to four T-eyeles (more if WATT is used). Signal timing can be varied as shown. During a transfer, data willbe latched by the DMA on the clock edge causing the rising edge of RD and will be held on the date lines until the end ofthe following Write eycle (See Timing Control Byte, page 9). DMA Bus Request and Acceptance for Byte-at-a-Time, Burst, and Continuous Mode Ready is sampled on every rising ee of . When it is found to be active the following ning edge of ® generates BUSRO. After receiving BUSRO the CPU will trant a BUSAR which wil be connected to BAT either Sirecy oF through the Bus Acknowledge Dasy Chain When 1 ow is detected on BAT for two consecutive edges of ©, the next rang edge of wl start an sete DMA cyte DMA Bus Release at End of Block for Burst or Continuous Mode nv ‘Timing for End of Block and DMA sot programmed "®*® for Auto-restart DMA Bus Release with ‘Ready’ for Burst and Continuous Mode The DMA will relinquish the bus after RDY has gone inactive (Burst mode) or after an End of Block or a Match is found (Continuous mode). With RDY inactive, the DMA in Continuous mode is inactive but maintains control of the bus (BUSRQ low) until the cycle is re sumed when RDY goes active = ~\ ata Inactive —ele—oMa ACTIVE J a —'=: uU LAL LU IKUUUUL 39Z 80-DMA Z 80A-DMA Reading from the DMA Internal Registers DMA Bus Release for Byte-at-a-Time Mode In the Byte mode the DMA will release BUSRO on the rising edge of ¢ prior to the end of each Read cy cle in Search Only or each Weite cycle in a Transfer, re sgardless of the state of RDY, The next bus request will come after both BUSRO and BAI have returned high DMA Bus Release with Match for Burst or Continuous Modes When a Match is found and the DMA is programmed to stop on Compare, the DMA performs an operation on the next byte and then releases bus ‘The CPU can read seven intemal DMA registers, always in the following order: Status, lower byte of the Block Length register, upper byte of the Block Length register, Tower byte of the Port A Address, upper byte of the Port A Address, lower byte of the Port B Address and the upper byte of the Port B Address. ‘The Read Mask register must be programmed to either include or exclude any of these seven registers by program: LIL Reading the DMA Internal Registers ring a 1 (include) or 0 (exclude) in the appropriate posi tions of the Read Mask register. After a Reset or Load, the read sequence must be initiated through an Initiate Read Sequence command (Command Byte 2D). The sequence of reading all registers that are not excluded by the Read Mask register must be completed before s new Initiate Read Se- quence or RD Status command. Programming the DMA Previous sections of this specification have indicated the various functions and modes of the DMA. The diagrams and charts below show how the DMA is programmed to select, among these functions and modes and to adapt itself to the requitements of the user system. ‘The Z80-DMA chip may be in an“ enable” state, in which it can gain control of the system buses and direct the trans fer of data between its ports, or in a “disable” state, when it cannot gain control of the bus Program commands can be written (it in either state, but writing a command to it automatically puts it in the disable state, which is maintained tuntil an enable command is issued to the DMA. The CPL ‘must program it in advance of any data search or transfer by addressing it as an 1/0 port and sending it a sequence of ‘command bytes via the system data bus using Output in- structions, When the DMA is powered up or reset by any means, the DMA is automatically placed into a disable state, in which it can initiate neither bus requests nor data transfers nor interrupts. The command bytes contain information to be loaded Into the DMA’s control and other registers and/or informa: tion (oalter the state of the chip, such as an Enable Interrupt command. The command structure is designed so that cer tain bits in some commands can be set to alert the DMA 10 expect the next byte written to it to be for a particular internal register The following diagrams and charts give the {unetion of each bit in the six different command bytes. Two of these are defined as being from Group 1. and are termed command bytes 1A and IB These Group | commands contain the most basic DMA setup information. The other tour are categorized as Group 2, and are termed commands 2A, 2B, 2C and 2D. Group 2 words specily more detailed setup information 40Programming the DMA (continued) Z 80-DMA Z 80A-DMA Command Register 1A boos os os oso ® y PORT ASTARTING ADDRESS (LOWER BYTE) ¥ PORT A STARTING ADDRESS (UPPER BYTE) T—¥ BLOCK LENGTH (LONER BYTE) BLOCK LENGTH (UPPER BYTE) NVA (command 18) sequence A “1” in positions D3 through Dg ‘means that the indicated byte will fol- low. Note that the sequence of bytes is absolutely rigid. ‘The DMA always transfers or search es one byte more than the number written into the Block Length registers. AO" in the block length register re- sults in the transfer or search of 2'° + 1 bytes. The shortest programmable block length is therefore two bytes Tong, programmed by writing a 1 into the Block Length register. Command Register 1B Command Register 2A. py os os ok soot oy 06 ps sos ° ofa 1 o|o a = a Port A-Memory 1 nterrpt Enable 1 Or Port 8-0) = 12 OMA Enable 1 Ypon Aa 8 fot As Duron y {= Port Ares Fined MASK BYTE (1 = MASK - IGNORE; 0 UNMASK = COMPARE) ¥ Timiog Byte matcn evTE. T | | 9 O=CyeleLengn = 4 2 $=Gyele Leng 23 1 or Gye Leng =2 8 rORa ens Cyr | B= RD end cy ey dean cnarorce eon For transfers, this byte is normally written twice, once for Port A and again for Port B. 41