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DLD Report 4

This lab report describes implementing Boolean functions using sum of products (SOP) and product of sums (POS) forms. An in-lab task involves deriving the SOP and POS forms for a 3-input Boolean function with the inputs A, B, and C. The SOP form is derived as F = A'C + AB'C'. A Verilog code and circuit diagram are provided to implement the SOP form. In the post-lab, the truth table and SOP form are derived for another 3-input Boolean function as F = A'C' + ABC.

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50 views7 pages

DLD Report 4

This lab report describes implementing Boolean functions using sum of products (SOP) and product of sums (POS) forms. An in-lab task involves deriving the SOP and POS forms for a 3-input Boolean function with the inputs A, B, and C. The SOP form is derived as F = A'C + AB'C'. A Verilog code and circuit diagram are provided to implement the SOP form. In the post-lab, the truth table and SOP form are derived for another 3-input Boolean function as F = A'C' + ABC.

Uploaded by

zain ghuman zain
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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LAB

EEE241 DIGITAL LOGIC DESIGN


LAB Report # 04
Submitted by: ABDULLAH KHALID
Roll no: FA17-BCS-005
Section: 3A Submitted to: Mr. Shahid Mehmood
OBJECTIVE

In this lab we implement Boolean functions by using SOP (sums of product) and POS (products
of sum)

Apparatus

KL-31001 Digital Logic Lab, Bread Board, Logic gate ICs (NAND &NOR).

IN LAB TASKS

A B C Minterms Maxterms F F’

0 0 0 mo= x’y’z' M0 = x + y + z 0 1

0 0 1 m 1= x’y’z M 1 = x + y + z’ 1 0

0 1 0 m2= x’yz' M 2 = x + y’ + z 0 1

0 1 1 m3= x’yz M 3 = x + y’ + z’ 1 0

1 0 0 m4 = xy’z' M 4 = x’ + y + z 1 0

1 0 1 m5= xy’z M 5 = x’ + y + z’ 0 1

1 1 0 m6= xyz' M 6 = x’ + y’ + z 0 1

1 1 1 m 7= xyz M 7 = x’ + y’ + z’ 0 1

SOP FORM

F = A’B’C + A’BC + AB’C’

F = A’C (B’ + B) + AB’C’

F = A’C (1) + AB’C’ As B + B’ = 1

F = A’C + AB’C’
SOP CIRCUIT DIAGRAM

VERILOG CODE
DIAGRAM

Pulse width is 200ns.


POST LAB

Truth table of function

A B C F

0 0 0 1

0 0 1 0

0 1 0 1

0 1 1 0

1 0 0 0

1 0 1 0

1 1 0 0

1 1 1 1

SOP FORM

F = A’B’C’ + A’BC’ + ABC

F = A’C’ (B’ + B) + ABC

F = A’C’ (1) + ABC as B + B’ = 1

F = A’C’ + ABC

POS FORM

F = (A + B + C’).(A + B’ + C’).(A’ + B + C).(A’ + B + C’).(A’ + B’ + C)

SOP CIRCUIT DIAGRAM


VERILOG CODE
DIAGRAM

Pulse width is 200ns in first cycle but it changed and disordered cycle.

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