Vewlog HDL rn lo * Evoiu * The frase commewal Tc wos developed in 1960. nye ant egated unurts rove cmerged krrough A generations namuly W Smelt Scale dat “on ($82) Gi) Medium Scale Integration (mgr) (iii) Large Scale Integration CLSz) Gy Veg Lorge Scale Tntegucion ( Visz) eae ive lea ron 2G) ie. $8f Cbrrall Scale Tnkeqradi on) ips sented voy few tranuttou ena dup (L100) qe Logic goku 3 fp plop Ics * The 1 generation IG, ce MST (Medium Avole Trt equation) ups vontarned duuidreds a EAanats boy pe «hip Gir tountes $ mubtiplener Ie, * the a IBECSE Module - 4 Jloverveew OF Dtgttat Destqn Wet VERTLOG Hou] DC Computer Arded Dorn) Digitol werk design Aras evolved rapidly ov the dost 26 yoo The eorliut digital acneutts uure Aucgred wucth vacuum ules anid dE ronsiabou, The invention the tnxariskr in 1447 Jy Wellam. B Shockley , Walta-H. Brattain and John Bardeen ot the Bell Lalerctevies ond the subsequent tavent'on of the Tntegrated Grout (Ic) head te o ne oa ot age tel design. on Tes ie LST ( Lange Zale Intepation) ups deontatred thousands 4 tronicstou pe chap a B-dvt prouuors RAM 4 Nayana+K , Asst. Prof , SvirVewloy HDL ISECS6 ¥ As he dustgn proceuss started guiting complicated, esters fe the reed te automa) ture pacceues , ¥ Electacuie Design Automotion (EDA) Feces Legan to evolve, ¥ thup sales igiees degen te ae rant and Lege Armuladion Fechuquur te veu fy the farttonadety 4 trac teaing Lock, ef Ake veuden 4 1op's | daaucstou , The Atak re shill Luted wn tre dteadtood , and the Layout Mes dent on paper ai ly hand en a pape compute tewuinal . Wirth the invention q Visa ( Vey bange Seale Integration) Vist ( , dese could Aaa: hups uurth moe than 100, ovo Eranitsbou . x Bunue of the ommptimcty of Bune writ, ot ues net Pemble to veufy tse urn en a beadtoard. Komputa - Avded Fechucqu keeume artical fo and Busca 4} Vise Avgctal wee acuts + Aomputer programs ulu'h would do oute matic placement ound, poudeng 4 wu ancu'k tagouts decame peputar : Logie acowalotou , town inte enskense to veufy the funrctionatity ef tres cerned defou Huy wou wn a dup vou fication farce ¥ Tas CAD toss evolved to case the prow 4 dug Zz veufrealion 4 digetal Acu'ts, Nayana+Kk, Asst. Prof , SVIT a12Ecsé Veeley HDL J Emergenck OF HDLs_ eee * Programming downrguoges such wr FORTRAN, Pascal & C wey sted ke dese computer Pregrams that art sequential Tn the degetal desta fied, ducgnen lt the reed for Me standard danguegs to .desuuche aegetal erncucts . ¥ The Horde Deseupdion fe CHDL) came inte eustene| * HDLs olloured the alacgness do model tHe soneunneney prccenes fous in hardware elements, 4 ¥ Tuo Hardon Desurphron Lavequaeges CHOY) Leeame popular rand} () Vewteg HDL @® vuor—> vaste Hot (vey Hegh Speod Trkegoted Lex HoL) Vouley HDL suginabed in “1983” at “Gateway Deruge Ruktmaton” * VHDL suas developed ander contract fom 4 DARPA ( Defence advaned Arsearch projects Tnctatly » Lhe desires od te HDL- Lared dusign us department agey) Franslete Lhe tale O sehemabic ener en dntacnnedios ketwen gets. The invention af tegee Ayethens an the dete “1ag05" tho design mmettvodolegy droati cally « 9 Digetal arrcuts ould Le ducted ak &@ RTL (Regust, Thansper_Lovet) ty aseng HL. Rigi. ¥ Thu, the dusigner Aad te spew dttwan Arguakers and trou dato.» Nayorns Ky Asst. Prof, Svit 3IeEC 56 Vewttog Hot * The detocts + votes wand tug interconnection: Leéween gets dim plement He newt ute vabomods entaacted ay tegee ayrthancs tools per RIL descuption, * HDL s alo Legon te be sued fe “syotern— devel dusign' * HDLs sere sued fe avmulotion. 4 system oards , dnkarennect dusts) FPGAs (Lietd Pro Ole Gate Arn wand PALS ( Programmable A. Logec:) * A cemmen appaoach followed was durign tach Te whip uacag an HOL and then vary system frrctronality weal atmulet' on Vowleg HDL is an acupted “TEEE standard”, * am 1995, the woruginah standerd LEEE 1364 -laqe LEER 1864“ Jaas approved pore * GEER 1364-2001 ie He tatest ee] HDL standard Brat mode sugrefreat smparovement fb the Suginal standau| ——« Nayona-k , Asst. Prof , SVIT ;Vewleg HDL TYPICAL DESIGN FLOW eA kyptcal Aesigr flow for descgning VLST LC -etrewits es sheun| DESTQN SPECLFACATI ON BEHAVIORAL DEScRIPTION RTL DESCRIPTION CHbL) AND TestING Logic SyYNTHEsTs — i GATE - LeveL NETLTST LOGZCAL VeRtrEcATIOn AND TeSTIN, FlLooR PLANNING Avtomatte PLAce & Route PuystcaL Layout Lavour WeRrtFrcation pv FUNCTIONAL VERIFICATION IMPLEMENTATION 1eECs6 Nayanas K, Asst, Prof, SVIT18 E56 Vectog HDL DEstqn SPECIFICATION ;- * fr song soncgn flow, speefi cations are auwilen jut * Speci frrations dole obs tnathly Hu Tenality » interfae send overall architecture af the cltgetal eral te Le ders * Spee frcodions fdentify the acquoremente of He design [ex- To duscga a Abt vountr » ue need ty Pderdify sbether ko ue neonous /arndvonous asset + poh jects Dare Ke kuggeud Pep flops » oq o]Ps eke 7 [meget cag BEHAVIORAL DESCRIPTION:- BEHAVIORAL DESCRIPTION:- 4 A igh - Wwe kehavoral dusutphion is uutten to analyze te desig in toms 4 furvctioncabity ) Perfermence , compliane te standards and rothor dugh: devel visues, + Behavioral deuphenS are walter in HDL RTL _DE€scrtPtion t- * The Ieheweral ducupion sinclogen sbepuuse 4efinement and ue venvated fe cat RTL deception in HoL, ¥ kA - Trou fer Level CRTL) is oe dag aletrathon uted te ductle the dataflow trat surit dmplement the cesvred alegctal ecreurt, FunertonAL VERTEICATION & Testrme 1 ATION be TESTING 1 + Ane the RTL derygn bs ready , *t needs te be veuped for fundenal tonecbrau, marth te help a EDA cimutaten Logic Synrneszs ; * The functionally eoueck (RTL duvgn ts converted lunte ardurars Ataemetic « This step 4 tolled ayn thus, ¥ Loge Ayrthurs keels wonvet the RTL desir; Aeavent a ution to a gate -level: te GAte- Lever Nemsst ;- * RK gate devel nethat is a desurption of the Aue or fame of gatis and “cakaconnect'ons between them. — & Nayana-k, Asst. Prof, SVaTIe ECSE Verhog HDL _ 2 ist meeb * dogee dynthescs tools ensure that the gots devel net tin Aimung , area cand power spew prrabvens LOGtcCAL VERIFICATION & TESTING ! REAL NERIFECATION & TESTING! ate OE eect ersE es Dae are pee fu tegical eepuvaleng Muckh ble RTL dusetpion amd ip “gote~ Luvel Yeu iatien” ai Pefouned semetrmes, _Froor PLANNING - Avromattc PLace & Roure -- ¥ Th gets Level net Lent % input te the parysccal lesign flew, | bikers Autemat’c Place g ReuteWpis done auth te tule of EDA decks . * The APR tec sult select and place Atendard <4 inte rouns, wefvne tnput cand wut put connections Puystcal Layour 9 VERIFICATION: Wa, tre automatic pla 2 rou is dene ya tage as qeroked . uitich 4 Hhen vetted . IMPLEMENTATION! + The veupred design is fabucated en a dup. Note :- tf dbsvgn Auge wore found sok tong design stage, ve mud be fud in RTL, Ae-veutfred sand aut the sheps Hak fellow mul dove te Le ig Pefered gna ant wrn Aemoved , 7 Nayana-K, Agct, Prof, SvirIe ecsé Verlog HDL ¢ OF HDLs Advantages of HDLs Compared tp traditional schematic — based destgn * Designs won Le durled of a vey wlebaat evel waing HDLs. * Designs wan wrth RTL deatphen utheut shoosing 1a Apeefre fobucation technology» ¥ Bogee Ayretheses took con ute mali cally sonvert He design fe ony folweation technology and Hus auignes need net Acduvgn thety wrat . The Legee agrtheis eet wu optimize dhe wemurk in area ond ming fm the new technology. * By dur diag desges in HDL, A ena veu wotton +4 the deste van Le done tanky in the Aurign eye» dk meet the oles rredd forchienality, Umwaated ot this pents This rcduces sdescgn ye Sime. ¥ Desgring auth HDL ds avmeler te omputer program fertuol duvption i x 1A pion is ean to da comporrd be pak Level schematics wa J eat, TRENDS IN HDL ENDS EN HDL * The mot peputou. trend ently as te duane dn HDL wt an RTL devel, since Legee « tA tools can create Gots: levet nek list fom RTL Level daacgn. Reeeed HDL tt cong t » thay us “OE Ae emake nstdls ad atid veateration re © Reewal vesfiation and asetion checking “a BH oten Uwe , trangia « a VU have Foxmal veufratien ce ‘ enplre poumal mothemot al He vey Hue worrectrys 4 Vea, 4 Ulobish taprvalenig debween RTL echrtqptes HDL. welescuptions ancl by and gate bevel aektese,, Riser woken whack, allow checking to de embedded 4 the RTL cody r rm Nayana: ky Asst. Prof, svir a+ Fo voy tugh- sped and Aamviag - wheal arcu Uke IeECs¢ Vertleg HDL * Nw veufrcetion danguoges drone qrined roped weceptance, These Languages aombine the peraltelsm and hrerdurouy on bau cky, fem Hols uuth He olyect ouented nobue of Cte, Puasprouson , Lhe gatr-level netliut paowded ty togee syntheses drely is net optimal. In auch tates, desgnes mtn gate lever # dnethu Fecluuque used aa system = level dasa is amined tettem- up mittodelagy , whew the Aesgrens sie evther oncsting Vewlog HDL meduly , Luce building Alouks , or vender- Popucarity OF Versio HDL ROG HDL ¥ Veat'log HDL or wolved wy we 4tanderd Hardurcr Desurpdcon Language . Vurteg HDL apfes as fete for Ararduvare lusvan. ma > Veurleg HDL bow gursod - Purpose hraroluroug lepton Lenguege Hak is caty fe darn and eouy te ase, Te 4 svewter in syntax de Hue c PAD gramming tanguage. > Veackog HDL ollouw ae ferent devels ad hetrackon ty te mined in the same model, Ths oe eles gnen tor defvas oe Nordica, model in tums + suwtches , gots RTL ow behavioral ede, Peg de te Mann ant ore Jeguage for inal b dweardu'cal welescgn > Rae fobvication vender, provide Voutog HDL Ledrowes Nayana-k ; Aect. Prof, Svartwee sé Veowleg HL E fw pork-Legee aynthucs amulet on, > The paogranumuing Languagt Gntafau CPLI) & we powerful febue thet ollour Hu mer be ure gustom C cod Ae intuak auth He antennal data slructuroy of Veulog. — tor wustoneze oe Veteg HDL Avmuletor by Heir needs scth the PLT. Nayana: Ky Asst. Prof, Svar* Lees Ven'leg HDL 7 Mopure - 1 HIERARCHTCAL MODELING Concepts I DESIGN METHODOLogzes ST OH Thee wore dwo bare Aypes 4} digital velenign methodologies ; GY Tor- Down Design MeTHODOLOG y GY Botrom- up DESTGN METHODOLOgy Top-Down Dessgn Mernovoro EON METHODOLOGY Tew dep douse denign methodology , deck and talents fy te subltocys top-level Mock « The tube blocks re further subdivided aut oe obtain deaf Aell ) udich ware He wells Hat ccannet be utter dinided > Fegune Helou a urkrates tep- down ducge muthodology TOP-LEVEL BLocy wet efsne he top tea receuosy 0 truth te Svar SuB- suB- Brocks BLOck a Block 3 LEAF Lene Len CELL Ce cele ce Nayanak, Asst. Prof, Svtr "IG ECSE Yetbeg HDL Botrom- UP De METHODOLOGY > th a deltem- up clungr methodology , ut fut adentefy the bustding Ahecks that wre mvarlelle We tuctd drgget veelts noun vas “rvmero celts wucag these durtaing bhecks | > Thue ells ore then sued fr Aighor~ Level Mocks until sue Auld He Lop level block ait Har desgn. > Figs etow chew the Lette up selesvgn proces ToP Lever Block MACRO MACRO Macro MACRO CeLe 4 cou 2 CEL 3, Cou Lear LEAF Lear Lear Lene Lear Lear LenF ce cet Ceu ceu ceLe CEL cou cou ¥ Typeeally , 0 scomininabion of top-down and Lrottem up flour is med, ¥ Davgr arcrihects define dhe Ape freaki ons of the top-devel block, » Logie sdencgnen deade drew the clusvgn should Le struchired dividing Hee fundionatity inte shod sand al -Mocks, ¥ AL He same time, werneu't rolesry ee noatts, fa teat devel «ells, ‘yy sacag Huse deaf a, « Th womertr ot van anteamediate peat shew Hy Avutkdh = devel venue dusgaus drove crated a Wy of deal aus by auiag ductor sand Hegee Javeh designen have alusigned from top-down untid wilt moduler au defred Se Meg eg optima Anuld As ghar-levet cell ta teams d L 12 Nayena: K, Aest. Prof, Svir(ESE > Vewlog HDL Exampce : Destan HEeRaecHy +> Levuvder the design, sof oe negative echge- triggued 4 bit supple count er > The supple sounter shown in fig above, is wonsbaucted Mee mgebie edge kuygued toggle (7 fuip-plope [7 FF], > Each the TFRs con be xonpbauched wag negate edgy Hacggqued D- fp flops Cd-FF) wand inverters Consuming qyoar output a net avaulalte en D- FF) . ‘y | Reset | a | ney ' | 1 }rjo | 1 o} o j“* ' oye] tie : 1 o } a] | at \ ' ta f_._ ft Tice + Thus, He Acpplo eon conte, as burt tn a hireaduiay frslwon dry susengy Anuldarng Mocks , TF The lisegn Mv eranetey Ps pple any counter a a tr the diagram aa follows Naysnask, Asst. Prof, everVewlog HPL I8ecse Desir Hrerarchy i a Z TPF T_FF T_FF TPE CElfo) Ce) (yp) CHL) ‘ \ D-FF Taverter| D-FF Taverlir D-rF | [Invi DF feet ate gate ate (Oren En ee bop- clown wclesry outhedology, sus frst specily ee functieratitly of He Atpple vag uountt) uluch is ty Fep- level Ateck » —> Then, He wont & implemented wath TFs | | > The LFF, ox buclt fom the D-FF and on AAV gale. + Ths, we beak ty; Hocks inks smaller Arutlding Lute teed suntil sue comme olivde the docks voy pote + A bettom- up ruttodelegy flows an ts wepyposiite lire chron , he vombar anal dratldang fecks and utd brgger Mocks. > use con duit DFE from wand" 2 “og gates at Awd wo ustom D-FF fom kraruistou . + Thus , Ene bottom. up flow meets the top- down flow at Hrs level of, D-FFs Nawjanak, Ass. Prof, overWwe C56 Vewbey Hol + Mopvues FA module ik the dmave duitding beck tn Verilog. 4A module can Le on cement ot a «ollecdion of Louies level duscgn Atocks « Typecally , ements ore prouped into moclules te pronde commen functtonality that can Le used of ran Places in Hee valesvgn. + A module prowder Ho neceu Aéonolity be ths shugherteve] Mock Hrssugh 1 port intedaw ( tapubr and outputs) + Tn Vertog, a module is declared wing the krywerd “meclule” +A scomsipending Keyword “endmodule” must appeoar at the end ef module defrartion. + Back module mut have a modulename, uluch is wer defened (tdertiprer) for the module cand oo module bermural- Lest wae dusccles He onput end output kemcrali of the module. | Generar Synrax OF MopvLe r | module ( module teminallest ) 5 | module inkunals eee endmodule Exampe- The T- flip plop wdesurbed corer sar Le Aehned 4 fadlow module T-FF( y, «lock, suet) 5 cfuncienality oh T-fLp flop> endmodute Navgaua + K y Assts Prof , svat 1SVewlog HDL [8 ECsb Types OF Mopute LeveL OR Levers OF ABSTRACTION > Tntenas of tack module con be defined ak four Lets of alukraction , Aependaing on the needs 4 He dasgn. > The module Lehoves Faerdicolly wuth He entenod enuedonment —asaapective + Hu lw af abstrachion ab ubur the module ds durcuted. AH Me antenals of the module vere duidden from the enveranmen| Thus, blue devel 4 whitraction te duvuibe module con he changed wa Hout won change an He environment, 4 The feu devel of alakraction ary ‘) Behavioral or salgeuthrucc Level ") Dataflow level ti) Gab Svet §t) Sut bevel C) BeHAvroraL OR ALGORITHMIC LEVEL, * Ths i the Jaghest deve -f alitrach'on prow'deat fy Veteg not +d module aan be unplemented an Leumi of the sdesred alsa slgeuithm awu'Hhouk concen for He hordusa amplumentation lta, ¥ Pencgnsng ok this Level us veug simular to Peqrameng Gi) DATAFLON LeveL — * Ae thi devel, the module iu duvgned +4 Apeahyag the wlota flew. * The ugar 4 autores of how data flours detwen hardware Mysteu and how tu data u prowued (x) GATE Lever 4% The module is implemented ww teams of begec gets ond dnkecomectionn Lebwen tue qets. L Nayena: K, Asst, Prof, SvtrIg ECS 2 Vewhog HOL * Durgr ot got level eueeee cg ee dean om eos 4 pau gote— devel ogee wtagrom, @ Swaren Lever ¥ Tha ib tHe Lowest Level alitrachion provided 4y Veutog #4 module von Le implemented din Lermi suuitches , shoroge nodes and tle inkaronneckons Letween them, + Dey ot ts devel Acqua Rrowseclge ved au beh doves smplemuentation detarls an Vewlog vollous the descgne te min ond metch au four levels of alitraction ie wa luscga. —+ The teem Reguaber Trans fe tevel C RTL) a veulog descarptton Hak ss) ao vombinat on > thw vduiga contains four modules , Vew! of Hes modules to Le wutlen at a effet | obs track on, — Hegher He Level wo} walstraction , the mor fll wand Hechnelogy andependint the .duscga. + As one dev of fouier tourards suuteh level selescgn, the estgn decomes Hecnology - dependent and or ferutte, I Nayona +R, Asst. Prof, SVITIPECSE Vewlog Hol INSTANCES * A module paovedes a template from wduth ane can wdcole ckuod abject . ¥ When a module is invoked , Verrtog wtales a uncape object from Fhe Lemplate . Fach olject has ct oun name, vaw'ablu , porametir pnol Llo intafac, ¥ The prcus wrscding objects due Lemplate i P i ct “a0h from a mo emplate is wold “instantiator” avd ty ebjeds wae called 7 sus bans Fon Enample oan br Ank Apple corng counter y Lye Hop devel Atock few tntkanes from the T- bp flep (tre) template, eee tare Anshortioter a De ¥ FE nd on dnvert, / gate, - Foch imtone mutt be given & unvque Paoquon fe racdule Grttarchiahon - ¥ Defense top tovel medate alle supple eae Te tha tantiates a fque Letew * Lock inshance des o@ un 4- T- pep fore» Interconnections are Ahan. : qpe rome (to et) ancl a4 Aqneds . foc dutana ow Copy of} the. modute FE. Ripple Cary Counter ' 4 1 | TPF eho lox _| § lauact. L Ig Noyana. K y Asst. Prof, evarVewheg HDL Ie ees module pple cary counter Cy, tk, auck) 5 durpuk wk, Atsck s wutput [3:0] y ; T-FF tf{0( GC0], tk, react) ; T_FF Eyes ( yC1I, »yfo1, duct); TFE ER? C fo), ali, Auset)s T LFF Abe C 463), qr) Audet) ; enolrrodule * Devas the module FF. Te inttantiakr a D- blip flop doctored dseuhee in He wclusega. Module TEE Cy, tk, suet) 5 cpt ky ansek D-FF Afo(y, 4, ky reset)» net at (d, wy) 5 endinodule Mnok got o & veaslog. prinitie NOTE i- Tnstent’otien anyntam medul nome inutanunome ( £10 parcunten) * ge T-FF -£HO( q fol, ck, Auet) Lyfe exder dusting bhe Z/0 vowably wut mote tly preter tol an the wo dule J "Naysna:k, Asst.frof, ever 412EcS6 Vewlog HDL Components OF A StmULATION. A Mnce 2 deavgn block is completed, LE must Le tested . The remality of te duugn Lock stan be tesbed try eyiplying stimulus curd checking Atsults, Auth a debock is called 09" faints Block" and corr Ae atten in Vewlog. The stimulus block is cermmanly Holle a “best bench”, > Two bypes of stimulus applications au poste . W Abimatus tdock inakantiatey leg Lock CO Trrtentiate astinulus send cletgn bocks in wa top level duro mo. (O Stamvorvs Brocc Insranirares Design Brox * In this style, the stimulus Jock tnskont ates Le desvgn AHock ond line chly hives the signals wn He aera block ¥ TE moncpulate aguols tk wand rniet ) Computer seund atplays out put argual a. CStimutus Plock ) ke neat |__| (DESIGN Brock ) RIPPLE CARRY COUNTER { vy t Noyena-K, Asst. Prof, svarIBECSS Vewlog HDL a2 ©) Stimerus & Destan Brocks INSTANTIATED In A Dummy Tor-Levet “'% Ca this thle) both the «emul and duvgn Hocks ay, tnskontiaked sin bop devel dur ¥ The stir dou dntoacs auth Me descgn block only Hheough dhe inteaw ¥ Then atyte of anplgcag stimuli iy Aheun 14 bau bebo, The 4d ruts module olriver tle Agrals date and A ietes clic eausek wu ere connected te te argnals «dn the design Mork, * TE wlio chee ond aluaplays Cy) tulich & Connected bp the argnal y in the descgn Hock. * The function a te top-level Louk is Gut 40 trtontite the dusegn ond stimulus Atocky TOP-LEVEL Lock so2t Noyane-k, Asst. Prof, ¢var18EC Verto g HDL % ¢ Exampce- Build tu complete acmulation ef we Arle courte, mp eee ty seefvaung ihe lest Move vnd He stimulus Aock. C Draw Aupple Cassy Count, tock avagnarn 2 TPF focstfeence 7 DESIGN BLock:. ¥ We use a top- doun sdleavgn muthodelogy . we ah the Men'fog Alesuuption 4 the kop- devel design block Me apple ory counter Ripple Camy Count Top block Medaka Aappleewcany coneten Cay) chk, aeset) 5 cut put [3:04 ; wtp elk, Ate 5 WA instance ci the modulo TFF ore created TFE kbto ( yLoJ, tk, auset ) TRF ett (q [1], 4f01, Auset) » Fe Affo C4027 aCtJ, suck); Terr kB> C403), yl], Auseh) > tmdmodute ¥ In te olove module} tnstances 4 Hy module T FF C7 §uep flop) Ou wed. Trento, wae mune defvne He vabernals of module ay T-FF module Shousn belo} module TFF (a, tk, Actet) ; output y inpuk alk, Aue ; wan ds DFF Aff 0 ( %, 4, ck, Aue) » Not nid, 4), endn odulo ’ Nowgona: K, Asst. Prof, Svir 22Wecse Veleg HDL * Aince TPF dnstontrote: D-FF , we now lepine the sinternaty wf modute D-FF+ Ke auume eaynchronous suck for ths D-FF. D-FF modu _ module D-FF(q,d, ak, duck) 5 aukput gy 5 caput vd) wth, Awset 7 ag oy; always © C posedge kere er negedge uk ) , Cauek) y <= Ibo. cle | Vinay) | enetmodute b (Thus, all moduler hawe been defiasdl dleun ty the Lowest - | devel deat eels en He ducgn rmuthodology. The design block now completes StimuLus Brock ¥ One the sdascgn. Hock 4 complited , ame must uch tHe 4timulus block do heck ef He arpple ONG count wlesign is func ening wou clly + + kle must contrcl the atqnals wk and “Aeret , 0 that Hy Aegater function 4 the Acpple vay courts and Hla ovynustency| Auck war herbed, ¥ Wave fous fe Uk, Aue ond ytd voutput Wy Are shower (acct - The aye Bie for able is 10 wuts - The rAcsee ageel Aig ep fem 0 15 and than gees Mp agasin fom UUme 145 to Qos - Put puk q counts fom Obs 23 Nayana-k, Asste Prof, SVITAq duet + ware [3ro]y 5 W sinskontiots the wlesegn Stock Apple cory counter" 44 (q, clk, Auret); ini bral atk = 1'bO + Il see Uk te 0 owanys HS k= wale, logge sikh cseny § berne wns wetiol in saree = I'b) : HIS reset < Ibo; HD Auek = I'bI; #10 reset = Ibo; #20 $ hash by NM kemuinads the semulation Avett ak A onto tHe uk puts Fmonctor (ftcme, " Output qe hd", “); endmocuule Nowy ana k, Asst. Prof , Svar 24L Vew'leg HDL. ¥ Onte He utimublu Adore U wmplebed » due can Aun thy Avmutation and veu'fy He furcticnad ourchnes of Hho des Ato , » Ms output ebtorred uhen atid ure design detects ary Armutated 4 shown 0 20 30 40 50 60 10 80 90 too 110 120 130 Iho 15d 160 110 1 ¢0 140 las 210 220 Output Suk put Oukput oO ut put a utput Output Output Output Output Output Output Oukput Output Output Output Output Oukput Oukput- Output Output Outpud- Ordpuk- | Nagena-k, Asses Prof, svit Aelow- 2 " 2 BID 2 zee vy hoy tl < ep icge 1 224 a ue LREC ST. + gr 25seecse v pve bog HDL ILLEGAL Modure NESTING Dn Verilog, ch Wag al te nuk moduler , ¥ Ane module athion wannet contain anette module alepattion wutiin te “module” and *endeodusle” 4 beter x A medute defiatbion con dinuerporat sopce sf % Enomple 4 legal module atsting module Axpple veut put (Caro]y; sinput lk, auret » —taunt er ( wy, Uk, wack), module TPE (4 , ubock, Aeset) > Tega wmedle resting < module — intenrals> endline dle enelimo dil 26 Nayona+k, Asst. Pol, SVIT