Central Processing Unit 1
Module 4:
CENTRAL PROCESSING UNIT
By:
Mitul Patel
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Central Processing Unit 2
CENTRAL PROCESSING UNIT
• Introduction
• General Register Organization
• Stack Organization
• Instruction Formats
• Addressing Modes
• Data Transfer and Manipulation
• Program Control
• Reduced Instruction Set Computer
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Central Processing Unit 3
CPU
• The part of the computer that performs the bulk of
data processing operations is called the central
processing unit(CPU).
• The CPU is made up of three major parts as shown in
Figure.
• Computer Architecture sometimes defined as the
computer structure and behaviour as seen by the
programmer that uses machine language
instructions.
• This includes the instruction formats, addressing
modes, the instruction set and the general
organization of the CPU registers.
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Central Processing Unit 4 Introduction
MAJOR COMPONENTS OF CPU
• Storage Components
Registers
Flags
• Execution (Processing) Components
Arithmetic Logic Unit(ALU)
Arithmetic calculations, Logical computations, Shifts/Rotates
• Transfer Components
Bus
• Control Components
Control Unit Register
File ALU
Control Unit
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Central Processing Unit 5
REGISTERS
• In Basic Computer, there is only one general purpose register,
the Accumulator (AC)
• In modern CPUs, there are many general purpose registers
• It is advantageous to have many registers
– Transfer between registers within the processor are relatively fast
– Going “off the processor” to access memory is much slower
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Central Processing Unit 6 General Register Organization
GENERAL REGISTER ORGANIZATION
Clock Input
R1
R2
R3
R4
R5
R6
R7
Load
(7 lines)
SELA { MUX MUX } SELB
3x8 A bus B bus
decoder
SELD
OPR ALU
Output
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Central Processing Unit 7 Control
OPERATION OF CONTROL UNIT
The control unit
Directs the information flow through ALU by
- Selecting various Components in the system
- Selecting the Function of ALU
Example: R1 ← R2 + R3
[1] MUX A selector (SELA): BUS A ← R2
[2] MUX B selector (SELB): BUS B ← R3
[3] ALU operation selector (OPR): ALU to ADD
[4] Decoder destination selector (SELD): R1 ← Out Bus
3 3 3 5
Control Word SELA SELB SELD OPR
Encoding of register selection fields
Binary
Code SELA SELB
SELD
000 Input Input None
001 R1 R1 R1
010 R2 R2 R2
011 R3 R3 R3
100 R4 R4 R4
101 R5 R5 R5
110 R6 R6 R6
111 R7 R7 R7
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Central Processing Unit 8 Control
ALU CONTROL
Encoding of ALU operations OPR
Select Operation Symbol
00000 Transfer A TSFA
00001 Increment A INCA
00010 ADD A + B ADD
00101 Subtract A - B SUB
00110 Decrement A DECA
01000 AND A and B AND
01010 OR A and B OR
01100 XOR A and B XOR
01110 Complement A COMA
10000 Shift right A SHRA
11000 Shift left A SHLA
Examples of ALU Microoperations
Symbolic Designation
Microoperation SELA SELB SELD OPR Control Word
R1 ← R2 − R3 R2 R3 R1 SUB 010 011 001
00101
R4 ← R4 ∨ R5 R4 R5 R4 OR 100 101 100 01010
R6 ← R6 + 1 R6 - R6 INCA 110 000 110
00001
R7 ← R1 R1 - R7 TSFA 001 000 111 00000
Output ← R2 R2 - None TSFA 010 000 000 00000
Output ← Input Input - None TSFA 000 000 000 00000
R4 ← shl R4 R4 - R4 SHLA 100 000 100
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Central Processing Unit 9 Stack Organization
REGISTER STACK ORGANIZATION
Stack
- Very useful feature for nested subroutines, nested interrupt services
- Also efficient for arithmetic expression evaluation
- Storage which can be accessed in LIFO
- Pointer: SP
- Only PUSH and POP operations are applicable
stack Address
Register Stack Flags 63
FULL EMPTY
Stack pointer 4
SP C 3
6 bits B 2
A 1
Push, Pop operations 0
DR
/* Initially, SP = 0, EMPTY = 1, FULL = 0 */
PUSH POP
SP ← SP + 1 DR ← M[SP]
M[SP] ← DR SP ← SP − 1
If (SP = 0) then (FULL ← 1) If (SP = 0) then (EMPTY ←
1)
EMPTY ← 0 FULL ← 0
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Central Processing Unit 10 Stack Organization
MEMORY STACK ORGANIZATION
1000
Memory with Program, Data, Program
PC (instructions)
and Stack Segments
Data
AR (operands)
SP 3000
stack
3997
3998
3999
4000
4001
- A portion of memory is used as a stack with a Stack grows
processor register as a stack pointer In this direction
- PUSH: SP ← SP - 1
M[SP] ← DR
- POP: DR ← M[SP]
SP ← SP + 1
- Most computers do not provide hardware to check stack overflow (full
stack) or underflow (empty stack) 🡪 must be done in software
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Central Processing Unit 11 Stack Organization
REVERSE POLISH NOTATION
• Arithmetic Expressions: A + B
A+B Infix notation
+AB Prefix or Polish notation
AB+ Postfix or reverse Polish notation
- The reverse Polish notation is very suitable for stack
manipulation
• Evaluation of Arithmetic Expressions
Any arithmetic expression can be expressed in parenthesis-free
Polish notation, including reverse Polish notation
(3 * 4) + (5 * 6) ⇒ 34*56*+
6
4 5 5 30
3 3 12 12 12 12 42
3 4 * 5 6 * +
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Central Processing Unit 12
REEVERSE POLICE NOTATION
• Exercise 1:
• Reverse polish notation of A*B + C*D ???
• Stack content ???
• Exercise 2:
• Reverse polish notation of (A + B)*[C*(D + E) + F]???
• Stack content???
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Central Processing Unit 13
EXERCISE
• Convert the following numerical arithmetic
expression into reverse polish notation and show the
stack operations for evaluating the numeric result.
(3 + 4)[10 ( 2 + 6) + 8]
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Central Processing Unit 14
PROCESSOR ORGANIZATION
• In general, most processors are organized in one of 3 ways
– Single register (Accumulator) organization
» Basic Computer is a good example
» Accumulator is the only general purpose register
» ADD X
– General register organization
» Used by most modern computer processors
» Any of the registers can be used as the source or destination for
computer operations
» ADD R1,R2,R3
» MOV R1,R2
– Stack organization
» All operations are done using the hardware stack
» For example, an OR instruction will pop the two top elements from the
stack, do a logical OR on them, and push the result on the stack
» ADD
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Central Processing Unit 15 Instruction Format
INSTRUCTION FORMAT
• Instruction Fields
OP-code field - specifies the operation to be performed
Address field - designates memory address(es) or a processor register(s)
Mode field - determines how the address field is to be interpreted (to
get effective address or the operand)
• The number of address fields in the instruction format
depends on the internal organization of CPU
• The three most common CPU organizations:
Single accumulator organization:
ADDX /* AC ← AC + M[X] */
General register organization:
ADDR1, R2, R3 /* R1 ← R2 + R3 */
ADD R1, R2 /* R1 ← R1 + R2 */
MOV R1, R2 /* R1 ← R2 */
ADD R1, X /* R1 ← R1 + M[X] */
Stack organization:
PUSH X /* TOS ← M[X] */
ADD
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Central Processing Unit 16 Instruction Format
THREE, AND TWO-ADDRESS INSTRUCTIONS
• Three-Address Instructions
Program to evaluate X = (A + B) * (C + D) :
ADD R1, A, B /* R1 ← M[A] + M[B] */
ADD R2, C, D /* R2 ← M[C] + M[D] */
MUL X, R1, R2 /* M[X] ← R1 * R2 */
- Results in short programs
- Instruction becomes long (many bits)
• Two-Address Instructions
Program to evaluate X = (A + B) * (C + D) :
MOV R1, A /* R1 ← M[A] */
ADD R1, B /* R1 ← R1 + M[B] */
MOV R2, C /* R2 ← M[C] */
ADD R2, D /* R2 ← R2 + M[D] */
MUL R1, R2 /* R1 ← R1 * R2 */
MOV X, R1 /* M[X] ← R1 */
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Central Processing Unit 17 Instruction Format
ONE, AND ZERO-ADDRESS INSTRUCTIONS
• One-Address Instructions
- Use an implied AC register for all data manipulation
- Program to evaluate X = (A + B) * (C + D) :
LOAD A /* AC ← M[A] */
ADD B /* AC ← AC + M[B] */
STORE T /* M[T] ← AC */
LOAD C /* AC ← M[C] */
ADD D /* AC ← AC + M[D] */
MUL T /* AC ← AC * M[T] */
STORE X /* M[X] ← AC */
• Zero-Address Instructions
- Can be found in a stack-organized computer
- Program to evaluate X = (A + B) * (C + D) :
PUSH A /* TOS ← A */
PUSH B /* TOS ← B */
ADD /* TOS ← (A + B) */
PUSH C /* TOS ← C */
PUSH D /* TOS ← D */
ADD /* TOS ← (C + D) */
MUL /* TOS ← (C + D) * (A + B) */
POP X /* M[X] ← TOS */
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Central Processing Unit 18
EXERCISE
• Write a program to evaluate the arithmetic statement:
a. Using a general register organization with three
address instructions.
b. Using a general register organization with two
address instructions.
c. Using a accumulator type computer with one address
instructions.
d. Using a stack organized computer with zero address
operation instructions.
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Central Processing Unit 19 Addressing Modes
ADDRESSING MODES
• Addressing Modes
* Specifies a rule for interpreting or modifying the
address field of the instruction (before the operand
is actually referenced)
* Variety of addressing modes
- to give programming flexibility to the user
- to use the bits in the address field of the
instruction efficiently
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Central Processing Unit 20 Addressing Modes
TYPES OF ADDRESSING MODES
• Implied Mode
Address of the operands are specified implicitly
in the definition of the instruction
- No need to specify address in the instruction
- EA = AC, or EA = Stack[SP]
- Examples from Basic Computer
CLA, CME, INP
• Immediate Mode
Instead of specifying the address of the operand,
operand itself is specified
- No need to specify address in the instruction
- However, operand itself needs to be specified
- Sometimes, require more bits than the address
- Fast to acquire an operand
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Central Processing Unit 21 Addressing Modes
TYPES OF ADDRESSING MODES
• Register Mode
Address specified in the instruction is the register address
- Designated operand need to be in a register
- Shorter address than the memory address
- Saving address field in the instruction
- Faster to acquire an operand than the memory addressing
• Register Indirect Mode
Instruction specifies a register which contains
the memory address of the operand
- Saving instruction bits since register address
is shorter than the memory address
- Slower to acquire an operand than both the
register addressing or memory addressing
• Autoincrement or Autodecrement Mode
- When the address in the register is used to access memory, the
value in the register is incremented or decremented by 1
automatically
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Central Processing Unit 22 Addressing Modes
TYPES OF ADDRESSING MODES
• Direct Address Mode
Instruction specifies the memory address which
can be used directly to access the memory
- Faster than the other memory addressing modes
- Too many bits are needed to specify the address
for a large physical memory space
- EA = IR(addr) (IR(addr): address field of IR)
• Indirect Addressing Mode
The address field of an instruction specifies the address of a memory
location that contains the address of the operand
- When the abbreviated address is used large physical memory can be
addressed with a relatively small number of bits
- Slow to acquire an operand because of an additional memory access
- EA = M[IR(address)]
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Central Processing Unit 23 Addressing Modes
TYPES OF ADDRESSING MODES
• Relative Addressing Modes
The Address fields of an instruction specifies the part of the address
(abbreviated address) which can be used along with a designated
register to calculate the address of the operand
- Address field of the instruction is short
- Large physical memory can be accessed with a small number of
address bits
- EA = f(IR(address), R), R is sometimes implied
3 different Relative Addressing Modes depending on R;
* PC Relative Addressing Mode (R = PC)
- EA = PC + IR(address)
* Indexed Addressing Mode (R = IX, where IX: Index Register)
- EA = IX + IR(address)
* Base Register Addressing Mode
(R = BAR, where BAR: Base Address Register)
- EA = BAR + IR(address)
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Central Processing Unit 24 Addressing Modes
ADDRESSING MODES - EXAMPLES -
Address Memory
200 Load to AC Mode
PC = 200 201 Address = 500
202 Next instruction
R1 = 400
399 450
XR = 100
400 700
AC
500 800
600 900
Addressing Effective Content 702 325
Mode Address of AC
Direct address 500 /* AC ← (500) */ 800
Immediate operand - /* AC ← 500 */ 500 800 300
Indirect address 800 /* AC ← ((500)) */ 300
Relative address 702 /* AC ← (PC+500) */ 325
Indexed address 600 /* AC ← (RX+500) */ 900
Register - /* AC ← R1 */ 400
Register indirect 400 /* AC ← (R1) */ 700
Autoincrement400 /* AC ← (R1)+ */ 700
Autodecrement 399 /* AC ← -(R) */ 450
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Central Processing Unit 25
EXERCISE
• An instruction is stored at location 300 with its
address field at location 301.The address field has
the value 400.A processor register R1 contains the
number 200.Evaluate the effective address if the
addressing mode of the instruction is
a. Direct
b. Immediate
c. Relative
d. Register indirect
e. Index with R1 as the index register.
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Central Processing Unit 26 Data Transfer and Manipulation
DATA TRANSFER INSTRUCTIONS
• Typical Data Transfer Instructions
Name Mnemonic
Load LD
Store ST
Move MOV
Exchange XCH
Input IN
Output OUT
Push PUSH
Pop POP
• Data Transfer Instructions with Different Addressing Modes
Assembly
Mode Convention Register Transfer
Direct address LD ADR AC ← M[ADR]
Indirect address LD @ADR AC ← M[M[ADR]]
Relative address LD $ADR AC ← M[PC + ADR]
Immediate operand LD #NBR AC ← NBR
Index addressing LD ADR(X) AC ← M[ADR + XR]
Register LD R1 AC ← R1
Register indirect LD (R1) AC ← M[R1]
Autoincrement LD (R1)+ AC ← M[R1], R1 ← R1 + 1
Autodecrement LD -(R1) R1 ← R1 - 1, AC ← M[R1]
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Central Processing Unit 27 Data Transfer and Manipulation
DATA MANIPULATION INSTRUCTIONS
• Three Basic Types: Arithmetic instructions
Logical and bit manipulation instructions
Shift instructions
• Arithmetic Instructions
Name Mnemonic
Increment INC
Decrement DEC
Add ADD
Subtract SUB
Multiply MUL
Divide DIV
Add with Carry ADDC
Subtract with Borrow SUBB
Negate(2’s Complement) NEG
• Logical and Bit Manipulation Instructions • Shift Instructions
Name Mnemonic Name Mnemonic
ClearCLR Logical shift right SHR
Complement COM Logical shift leftSHL
AND AND Arithmetic shift right SHRA
OR OR Arithmetic shift left SHLA
Exclusive-OR XOR Rotate right ROR
Clear carry CLRC Rotate left ROL
Set carry SETC Rotate right thru carry RORC
Complement carry COMC Rotate left thru carry ROLC
Enable interruptEI
Disable interrupt DI
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Central Processing Unit 28 Program Control
PROGRAM CONTROL INSTRUCTIONS
+1
In-Line Sequencing (Next instruction is fetched
from the next adjacent location in the memory)
PC
Address from other source; Current Instruction,
Stack, etc; Branch, Conditional Branch,
Subroutine, etc
• Program Control Instructions
Name Mnemonic
Branch BR
Jump JMP
Skip SKP
Call CALL
Return RTN
Compare(by − ) CMP
Test(by AND) TST
* CMP and TST instructions do not retain their
results of operations ( − and AND, respectively).
They only set or clear certain Flags.
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Central Processing Unit 29
FLAG, PROCESSOR STATUS WORD
• 8-bit ALU with 4 status registers:
– C (Carry): Set to 1 if the carry out of the ALU is 1
– S (Sign): The MSB bit of the ALU’s output
– Z (Zero): Set to 1 if the ALU’s output is all 0’s
– V (Overflow): Set to 1 if there is an overflow
– Let A=11110000 and B=00010100
– Perform A-B
Status Flag Circuit
A B
8 8
c7
c8 8-bit ALU
F7 - F 0
V Z S C
F7
Check for 8
zero output
F
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Central Processing Unit 30 Program Control
CONDITIONAL BRANCH INSTRUCTIONS
Mnemonic Branch condition Tested condition
BZ Branch if zero Z = 1
BNZ Branch if not zero Z=0
BC Branch if carry C = 1
BNC Branch if no carry C=0
BP Branch if plus S = 0
BM Branch if minus S = 1
BV Branch if overflow V=1
BNV Branch if no overflowV = 0
Unsigned compare conditions (A - B)
BHI Branch if higherA > B
BHE Branch if higher or equal A ≥ B
BLO Branch if lower A < B
BLOE Branch if lower or equal A ≤ B
BE Branch if equal A = B
BNE Branch if not equal A ≠ B
Signed compare conditions (A - B)
BGT Branch if greater than A>B
BGE Branch if greater or equal A ≥ B
BLT Branch if less than A < B
BLE Branch if less or equal A≤B
BE Branch if equal A = B
BNE Branch if not equal A ≠ B
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Central Processing Unit 31 Program Control
SUBROUTINE CALL AND RETURN
Call subroutine
• Subroutine Call Jump to subroutine
Branch to subroutine
Branch and save return address
• Two Most Important Operations are Implied;
* Branch to the beginning of the Subroutine
- Same as the Branch or Conditional Branch
* Save the Return Address to get the address
of the location in the Calling Program upon
exit from the Subroutine
CALL
• Locations for storing Return Address SP ← SP - 1
• Fixed Location in the subroutine (Memory) M[SP] ← PC
• Fixed Location in memory PC ← EA
• In a processor Register
• In memory stack RTN
- most efficient way PC ← M[SP]
SP ← SP + 1
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Central Processing Unit 32 Program Control
PROGRAM INTERRUPT
Types of Interrupts
External interrupts
External Interrupts initiated from the outside of CPU and Memory
- I/O Device → Data transfer request or Data transfer complete
- Timing Device → Timeout
- Power Failure
- Operator
Internal interrupts (traps)
Internal Interrupts are caused by the currently running program
- Register, Stack Overflow
- Divide by zero
- OP-code Violation
- Protection Violation
Software Interrupts
Both External and Internal Interrupts are initiated by the computer HW.
Software Interrupts are initiated by the executing an instruction.
- Supervisor Call → Switching from a user mode to the supervisor mode
→ Allows to execute a certain class of operations
which are
not allowed in the user mode
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Central Processing Unit 33 Program Control
INTERRUPT PROCEDURE
Interrupt Procedure and Subroutine Call
- The interrupt is usually initiated by an internal or
an external signal rather than from the execution of
an instruction (except for the software interrupt)
- The address of the interrupt service program is
determined by the hardware rather than from the
address field of an instruction
- An interrupt procedure usually stores all the
information necessary to define the state of CPU
rather than storing only the PC.
The state of the CPU is determined from;
Content of the PC
Content of all processor registers
Content of status bits
Many ways of saving the CPU state
depending on the CPU architectures
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Central Processing Unit 34
RISC
• Reduced Instruction Set Computer.
• Use of Load and Store instructions when
communicating with CPU. All other instructions are
executed within Registers of the CPU without
referring to the memory.
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Central Processing Unit 35
THANK YOU
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