Unit-2 (Part-1)

Microprogrammed Control

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 Control Unit Implementation
• Hardwired
Memory Instruction code

Combinational . Control
Sequence Counter
Logic Circuits . signals

• Microprogrammed
CAR: Control Address Register
Memory Instruction code CDR: Control Data Register

Next Address . 2
Control CDR Decoding Control
Generator CA .
Memory Circuit signals
(sequencer) R

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 Microprogrammed Control Unit
• Control signals
– Group of bits used to select paths in multiplexers, decoders, arithmetic
logic units
• Control variables
– Binary variables specify microoperations
• Certain microoperations initiated while others idle
• Control word
– String of 1’s and 0’s represent control word

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 Microprogrammed Control Unit
• Control memory
– Memory contains control words
• Microinstructions
– Control words stored in control memory
– Specify control signals for execution of microoperations
• Microprogram
– Sequence of microinstructions

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 CONTROL MEMORY
• Read-only memory (ROM)
• Content of word in ROM at given address specifies
microinstruction
• Each computer instruction initiates series of
microinstructions (microprogram) in control memory
• These microinstructions generate microoperations to
– Fetch instruction from main memory
– Evaluate effective address
– Execute operation specified by instruction
– Return control to fetch phase for next instruction

Control
Address Control word
memory
(microinstruction)
(ROM)
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 Microprogrammed Control
Organization
External Next Address Control
input CDR Control
Generator CA Memory word
(sequencer) R (ROM)

Control memory
– Contains microprograms (set of microinstructions)
– Microinstruction contains
• Bits initiate microoperations
• Bits determine address of next microinstruction
• Control address register (CAR)
– Specifies address of next microinstruction
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Microprogrammed Control Organization

• Next address generator (microprogram

sequencer)
– Determines address sequence for control memory
• Microprogram sequencer functions
– Increment CAR by one
– Transfer external address into CAR
– Load initial address into CAR to start control
operations

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 Microprogrammed Control
Organization
• Control data register (CDR)- or pipeline register
– Holds microinstruction read from control memory
– Allows execution of microoperations specified by control
word simultaneously with generation of next
microinstruction
• Control unit can operate without CDR

External Next Address Control

input Control
Generator CA Memory word
(sequencer) R (ROM)

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 ADDRESS SEQUENCING
• Address sequencing capabilities required in control unit
– Incrementing CAR
– Unconditional or conditional branch, depending on status bit
conditions
– Mapping from bits of instruction to address for control memory
– Facility for subroutine call and return

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 Address Sequencing

Instruction code

Mapping
logic

Status Branch MUX Multiplexers (addr)

bits logic select
Subroutine
Register
Control Address Register (SBR)
(CAR)

Incrementer

Control memory (ROM)

select a status
bit
Microoperations
Branch address

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 Conditional Branching
• Branching from one routine to another
depends on status bit conditions
• Status bits provide parameter info such as
– Carry-out of adder
– Sign bit of number
– Mode bits of instruction
• Info in status bits can be tested and actions
initiated based on their conditions: 1 or 0
• Unconditional branch
– Fix value of status bit to 1

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 Microprogram Routines
• Routine
– Small Group of microinstructions stored in
control memory
• Each computer instruction has its own
microprogram routine to generate
microoperations that execute the
instruction.

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 Microprogram Routines
• Subroutine
– Sequence of microinstructions used by other routines to accomplish
particular task
• Example
– Subroutine to generate effective address of operand for memory reference
instruction
• Subroutine register (SBR)
– Stores return address during subroutine call

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 Mapping of Instruction
• Each computer instruction has its own microprogram
routine stored in a given location of the control memory
• Mapping
– Transformation from instruction code bits to address in control
memory where routine is located

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 Mapping of Instruction
• Example
– Mapping 4-bit operation code to 7-bit address

OP-codes of Instructions
1. ADD 0000
2. AND 0001
3. LDA 0010 Control
memory
Mapping bits 0 xxxx 00 Address
0 0000 00 ADD Routine

0 0001 00 AND Routine

0 0010 00 LDA Routine

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 MICROPROGRAM EXAMPLE
MUX
10 0
Computer AR
Configuration Address Memory
10 0 2048 words x 16
PC

1 word= 8 bytes
MUX

15 0
6 0 6 0 DR
SBR CAR
AR= Address register
DR= Data register Control memory Arithmetic
128 x 20 logic and
shift unit
Control unit
15 0
AC
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 Microprogram Example
Computer instruction format
15 14 11 10 0
I Opcode Address

Four computer instructions

Symbol OP-code Description
EA is the effective address
ADD 0000 AC  AC + M[EA]
BRANCH 0001 if (AC < 0) then (PC  EA)
STORE 0010 M[EA]  AC
EXCHANGE 0011 AC  M[EA], M[EA]  AC

Microinstruction Format
3 3 3 2 2 7
F1 F2 F3 CD BR AD

F1, F2, F3: Microoperation fields

CD: Condition for branching
BR: Branch field
AD: Address field

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 Microinstruction Fields
F1 Microoperation Symbol F2 Microoperation Symbol
000 None NOP 000 None NOP
001 AC  AC + DR ADD 001 AC  AC - DR SUB
010 AC  0 CLRAC 010 AC  AC  DR OR
011 AC  AC + 1 INCAC 011 AC  AC  DR AND
100 AC  DR DRTAC 100 DR  M[AR] READ
101 AR  DR(0-10) DRTAR 101 DR  AC ACTDR
110 AR  PC PCTAR 110 DR  DR + 1 INCDR
111 M[AR]  DR WRITE 111 DR(0-10)  PC PCTDR

F3 Microoperation Symbol
000 None NOP
001 AC  AC  DR XOR
010 AC  AC’ COM
011 AC  shl AC SHL
100 AC  shr AC SHR
101 PC  PC + 1 INCPC
110 PC  AR ARTPC
111 Reserved

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Microinstruction Fields

CD Condition Symbol Comments

00 Always = 1 U Unconditional branch
01 DR(15) I Indirect address bit
10 AC(15) S Sign bit of AC
11 AC = 0 Z Zero value in AC

BR Symbol Function
00 JMP CAR  AD if condition = 1
CAR  CAR + 1 if condition = 0
01 CALL CAR  AD, SBR  CAR + 1 if condition = 1
CAR  CAR + 1 if condition = 0
10 RET CAR  SBR (Return from subroutine)
11 MAP CAR(2-5)  DR(11-14), CAR(0,1,6)  0

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 Symbolic Microinstruction
 Sample Format Label: Micro-ops CD BR AD

 Label may be empty or may specify symbolic address

terminated with colon

 Micro-ops consists of 1, 2, or 3 symbols separated by commas

 CD one of {U, I, S, Z}
U: Unconditional Branch
I: Indirect address bit
S: Sign of AC
Z: Zero value in AC

 BR one of {JMP, CALL, RET, MAP}

 AD one of {Symbolic address, NEXT, empty}

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 Fetch Routine
 Fetch routine
- Read instruction from memory
- Decode instruction and update PC
Microinstructions for fetch routine:
AR  PC
DR  M[AR], PC  PC + 1
AR  DR(0-10), CAR(2-5)  DR(11-14), CAR(0,1,6)  0

Symbolic microprogram for fetch routine:

ORG 64
FETCH: PCTAR U JMP NEXT
READ, INCPC U JMP NEXT
DRTAR U MAP

Binary microporgram for fetch routine:

Binary
address F1 F2 F3 CD BR AD
1000000 110 000 000 00 00 1000001
1000001 000 100 101 00 00 1000010
1000010 101 000 000 00 11 0000000

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 Symbolic Microprogram
• Control memory: 128 20-bit words
• First 64 words: Routines for 16 machine instructions
• Last 64 words: Used for other purpose (e.g., fetch routine and other subroutines)
• Mapping: OP-code XXXX into 0XXXX00, first address for 16 routines are
0(0 0000 00), 4(0 0001 00), 8, 12, 16, 20, ..., 60

Partial Symbolic Microprogram

Label Microops CD BR AD
ORG 0
ADD: NOP I CALL INDRCT
READ U JMP NEXT
ADD U JMP FETCH

ORG 4
BRANCH: NOP S JMP OVER
NOP U JMP FETCH
OVER: NOP I CALL INDRCT
ARTPC U JMP FETCH

ORG 8
STORE: NOP I CALL INDRCT
ACTDR U JMP NEXT
WRITE U JMP FETCH

ORG 12
EXCHANGE: NOP I CALL INDRCT
READ U JMP NEXT
ACTDR, DRTAC U JMP NEXT
WRITE U JMP FETCH

ORG 64
FETCH: PCTAR U JMP NEXT
READ, INCPC U JMP NEXT
DRTAR U MAP
INDRCT: READ U JMP NEXT
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U RETOrganization 22
 Binary Microprogram
Address Binary Microinstruction
Micro Routine Decimal Binary F1 F2 F3 CD BR AD
ADD 0 0000000 000 000 000 01 01 1000011
1 0000001 000 100 000 00 00 0000010
2 0000010 001 000 000 00 00 1000000
3 0000011 000 000 000 00 00 1000000
BRANCH 4 0000100 000 000 000 10 00 0000110
5 0000101 000 000 000 00 00 1000000
6 0000110 000 000 000 01 01 1000011
7 0000111 000 000 110 00 00 1000000
STORE 8 0001000 000 000 000 01 01 1000011
9 0001001 000 101 000 00 00 0001010
10 0001010 111 000 000 00 00 1000000
11 0001011 000 000 000 00 00 1000000
EXCHANGE 12 0001100 000 000 000 01 01 1000011
13 0001101 001 000 000 00 00 0001110
14 0001110 100 101 000 00 00 0001111
15 0001111 111 000 000 00 00 1000000

FETCH 64 1000000 110 000 000 00 00 1000001

65 1000001 000 100 101 00 00 1000010
66 1000010 101 000 000 00 11 0000000
INDRCT 67 1000011 000 100 000 00 00 1000100
68 1000100 101 000 000 00 10 0000000
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 Design of Control Unit
microoperation fields
F1 F2 F3

3 x 8 decoder 3 x 8 decoder 3 x 8 decoder

7 6 54 3 21 0 7 6 54 3 21 0 76 54 3 21 0

AND
ADD AC
Arithmetic
logic and DR
DRTAC shift unit
PCTAR

DRTAR
From From
PC DR(0-10) Load
AC

Select 0 1
Multiplexers

Load Clock
AR

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Microprogram Sequencer
External
(MAP)

L
I 3 2 1 0
Input Load
I0 S1 MUX1 SBR
logic
T1 S0

1 Incrementer
I MUX2 Test
S
Z Select
Clock CAR

Control memory

Microops CD BR AD
... ...

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 Input Logic for Microprogram
Sequencer
1 L L(load SBR with PC)
From I MUX2 Test
CPU S T for subroutine Call
BR field Input
Z Select I0 logic S0 for next address
of CS I
S1 selection
1

CD Field of CS

Input Logic
I1I0T Meaning Source of Address S1S0 L

000 In-Line CAR+1 00 0

001 JMP CS(AD) 01 0
010 In-Line CAR+1 00 0
011 CALL CS(AD) and SBR <- CAR+1 01 1
10x RET SBR 10 0
11x MAP DR(11-14) 11 0

S1 = I1
S0 = I0I1 + I1’T
L = I1’I0T
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 Unit-2 (Part-2)
Central Processing Unit

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 MAJOR COMPONENTS OF CPU
Storage Components:
Registers
Flip-flops

Execution (Processing) Components:

Arithmetic Logic Unit (ALU):
Arithmetic calculations, Logical computations, Shifts/Rotates

Transfer Components:
Bus

Control Components:
Control Unit
Register
File ALU

Control Unit
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GENERAL REGISTER ORGANIZATION
Clock Input

R1
R2
R3
R4
R5
R6
R7
Load
(7 lines)
SELA { MUX MUX } SELB
3x8 A bus B bus
decoder

SELD
OPR ALU

Output

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 OPERATION OF CONTROL UNIT
The control unit directs the information flow through ALU by:
- Selecting various Components in the system
- Selecting the Function of ALU

Example: R1 <- R2 + R3
[1] MUX A selector (SELA): BUS A  R2
[2] MUX B selector (SELB): BUS B  R3
[3] ALU operation selector (OPR): ALU to ADD
[4] Decoder destination selector (SELD): R1  Out Bus
3 3 3 5
Control Word SELA SELB SELD OPR

Encoding of register selection fields

Binary
Code SELA SELB SELD
000 Input Input None
001 R1 R1 R1
010 R2 R2 R2
011 R3 R3 R3
100 R4 R4 R4
101 R5 R5 R5
110 R6 R6 R6
111 R7 R7 R7
30
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 Control

ALU CONTROL
Encoding of ALU operations OPR
Select Operation Symbol
00000 Transfer A TSFA
00001 Increment A INCA
00010 ADD A + B ADD
00101 Subtract A - B SUB
00110 Decrement A DECA
01000 AND A and B AND
01010 OR A and B OR
01100 XOR A and B XOR
01110 Complement A COMA
10000 Shift right A SHRA
11000 Shift left A SHLA

Examples of ALU Microoperations

Symbolic Designation
Microoperation SELA SELB SELD OPR Control Word
R1  R2 - R3 R2 R3 R1 SUB 010 011 001 00101
R4  R4  R5 R4 R5 R4 OR 100 101 100 01010
R6  R6 + 1 R6 - R6 INCA 110 000 110 00001
R7  R1 R1 - R7 TSFA 001 000 111 00000
Output  R2 R2 - None TSFA 010 000 000 00000
Output  Input Input - None TSFA 000 000 000 00000
R4  shl R4 R4 - R4 SHLA 100 000 100 11000
R5  0 R5 R5 R5 XOR 101 101 101 01100
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 Instruction Format

INSTRUCTION FORMAT
Instruction Fields
OP-code field - specifies the operation to be performed
Address field - designates memory address(s) or a processor register(s)
Mode field - specifies the way the operand or the
effective address is determined
The number of address fields in the instruction format
depends on the internal organization of CPU

- The three most common CPU organizations:

Single accumulator organization:
ADD X /* AC  AC + M[X] */
General register organization:
ADD R1, R2, R3 /* R1  R2 + R3 */
ADD R1, R2 /* R1  R1 + R2 */
MOV R1, R2 /* R1  R2 */
ADD R1, X /* R1  R1 + M[X] */
Stack organization:
PUSH X /* TOS  M[X] */
PUSH Y /* TOS <- M[Y] */
ADD /* TOS <- M[X] + M[Y] */ 32

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 Types of Address Instruction
Three-Address Instructions: Uses each address field to specify either a
processor register or memory operand

Program to evaluate X = (A + B) * (C + D) :
ADD R1, A, B /* R1  M[A] + M[B] */
ADD R2, C, D /* R2  M[C] + M[D] */
MUL X, R1, R2 /* M[X]  R1 * R2 */

Adv - Results in short programs

Disadv - Instruction becomes long (many bits)

Two-Address Instructions: - Most common in the commercial computer

- Uses each address field to specify either a processor register or memory
operand
Program to evaluate X = (A + B) * (C + D) :
MOV R1, A /* R1  M[A] */
ADD R1, B /* R1  R1 + M[B] */
MOV R2, C /* R2  M[C] */
ADD R2, D /* R2  R2 + M[D] */
MUL R1, R2 /* R1  R1 * R2 */
MOV X, R1 /* M[X]  R1 */ 33
One-Address Instructions:
- Use an implied AC register for all data manipulation
- Program to evaluate X = (A + B) * (C + D) :
LOAD A /* AC  M[A] */
ADD B /* AC  AC + M[B] */
STORE T /* M[T]  AC */
LOAD C /* AC  M[C] */
ADD D /* AC  AC + M[D] */
MUL T /* AC  AC * M[T] */
STORE X /* M[X]  AC */
Zero-Address Instructions:
- Can be found in a stack-organized computer
- Program to evaluate X = (A + B) * (C + D) :
PUSH A /* TOS  A */
PUSH B /* TOS  B */
ADD /* TOS  (A + B) */
PUSH C /* TOS  C */
PUSH D /* TOS  D */
ADD /* TOS  (C + D) */
MUL /* TOS  (C + D) * (A + B) */
POP X /* M[X]  TOS */
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 ADDRESSING MODES

Addressing Modes:

* Specifies a rule for interpreting or modifying the

address field of the instruction (before the operand
is actually referenced)

* Variety of addressing modes

- to give programming flexibility to the user

- to use the bits in the address field of the
instruction efficiently

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 TYPES OF ADDRESSING MODES
Implied Mode
Address of the operands are specified implicitly
in the definition of the instruction
- No need to specify address in the instruction
- EA = AC, or EA = Stack[SP], EA: Effective Address.

Immediate Mode
Instead of specifying the address of the operand,
operand itself is specified
- No need to specify address in the instruction
- However, operand itself needs to be specified
- Sometimes, require more bits than the address
- Fast to acquire an operand

Register Mode
Address specified in the instruction is the register address
- Designated operand need to be in a register
- Shorter address than the memory address
- Saving address field in the instruction
- Faster to acquire an operand than the memory addressing
- EA = IR(R) (IR(R): Register field of IR)
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 TYPES OF ADDRESSING MODES
Register Indirect Mode
Instruction specifies a register which contains
the memory address of the operand
- Saving instruction bits since register address
is shorter than the memory address
- Slower to acquire an operand than both the
register addressing or memory addressing
- EA = [IR(R)] ([x]: Content of x)

Auto-increment or Auto-decrement features:

Same as the Register Indirect, but:
- When the address in the register is used to access memory, the
value in the register is incremented or decremented by 1 (after or
before the execution of the instruction)

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 TYPES OF ADDRESSING MODES
Direct Address Mode
Instruction specifies the memory address which
can be used directly to the physical memory
- Faster than the other memory addressing modes
- Too many bits are needed to specify the address
for a large physical memory space
- EA = IR(address), (IR(address): address field of IR)

Indirect Addressing Mode

The address field of an instruction specifies the address of a memory
location that contains the address of the operand
- When the abbreviated address is used, large physical memory can
be addressed with a relatively small number of bits
- Slow to acquire an operand because of an additional memory
access
- EA = M[IR(address)]

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 TYPES OF ADDRESSING MODES
Relative Addressing Modes
The Address fields of an instruction specifies the part of the address
(abbreviated address) which can be used along with a
designated register to calculate the address of the operand

PC Relative Addressing Mode(R = PC)

- EA = PC + IR(address)

- Address field of the instruction is short

- Large physical memory can be accessed with a small number of
address bits

Indexed Addressing Mode

XR: Index Register:
- EA = XR + IR(address)
Base Register Addressing Mode
BAR: Base Address Register:
- EA = BAR + IR(address)
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ADDRESSING MODES - EXAMPLES
Address Memory
200 Load to AC Mode
PC = 200 201 Address = 500
202 Next instruction
R1 = 400

399 450
XR = 100
400 700

AC
500 800

600 900
Addressing Effective Content
Mode Address of AC
Direct address 500 /* AC  (500) */ 800 702 325
Immediate operand - /* AC  500 */ 500
Indirect address 800 /* AC  ((500)) */ 300
Relative address 702 /* AC  (PC+500) */ 325 800 300
Indexed address 600 /* AC  (XR+500) */ 900
Register - /* AC  R1 */ 400
Register indirect 400 /* AC  (R1) */ 700
Autoincrement 400 /* AC  (R1)+ */ 700
Autodecrement 399 /* AC  -(R) */ 450

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