12001006
Iniredoekion of so85 Microprocessor (AP) :
INTR TRAT SID SOD
Seria
Intrrubt Control 1/o Control
AC TembR nShrueion 1 Multtblexer
RegiSter
Flo TembRe3 Tem Rea
Flp-Flop
Re ReR
InstrucHon ReA
ALU 9eco der
Ma.chine Reg Re
ck Pobfet
Cle
bnco din Frogra ounter
Adressemeit
Touwer SupP +5Va.
GND
Timing and Control Address Data/Addre
CLk Butfer 8utte
RES
GEN Conrol StoBus DMA
Ais-Ag ADa AD
CLE OUT RD OR RESET OUT Address Acd dress/path
Ready ALE
HOLD RE SET IN BUS
BUS
NO. acNo,
losa.02
Introduction of 8085 Micropracessor (uP):
Ihemicrobrocessor is the central pmtessing unit (CPu) at a
Combuter. It is the heart of the combuter
ule
can detine microhroce.ssor as a hrogram.mable device
Similarto CPUot a Combuter Luhich is resbonsthle for Com=
-uhing and taking Logical de.cisions.
Intel808s is one of he mbst þakular R-bit MicmbrocesSor
Intel 80855:
It is an R-bit general-hurbse micrahro.cessor designed by
Tntel in 1946 using NM0S echnolaq-
t uas the tirs Tntel?s micrabracessor uith NMOs Ci.e
N-channel meal-Dxide. Semiconduckor) Technlog The
NMOS Techialogy atfered taster Sheed and Higher-densitu
than PMS Cie P-channel Metal-Oxi.de.Semiconduchar
T i5 0 Ho bin I.backage tabric.ated ona Single LST
chib Large Scale Integration chib).
Ihe Tntel 208SA USesa Single 5Vdc Subply for it's
Oberation
TS clock Sheed is ahgut 3MHz,Hhe clock Cycle is.ot 320
H has 80 basit Tnsrúchions and 246 0bcode.s
Tt Consists.of hxee main Secions:
LiArithemetic and Logic Unit (ALU)
Ci) Timming and Contral Unit and
Gi
Set ot Registers.
Teochers Signature 1
Expl. NO. PageNo.
0403202.2.
Date
1.ALU (Arithmetic and Logic Unit):
The Arithmetic and Log1c UnitCALU) Þerfor m$ the Arithmeic
and Logttal Oberations Such aS:
iAddition
iSubtraction vi) Comblement
CiDLogicalAND (uii) In&rement
Liv logitoal OR (vii) Decreme.nt
9Logical EXOR Lix) clear etc
2.iming and ControlUnit:
Ihe Timing and Control Unit is a Section uhich generares
Himing and Capkral Signals uuhich are necess.aru for the
Execuion ot TnsBructions.
TtComtrols data flau between CPUand Tne Iloberiph-
-erals InoludingMemaru)
trovides Stotds,contröl and iming Signals which are
required for the oheratiam ct Memory and Llo devices
It controls the enié Oberations t theMitrobra.cesSor
and theberiphevdls Connected i t
to
Thus,it is Spen thot the Control Unit of the cPu acts
as a broin ot the Computer System
3. Registers:
There are yarious type.s of RegisterS.in 8085 mbu
Registers are used by miGobrote.sSor for Temhorary Storage
leochers Signcture
Expt. No.
Page No. 0l an2.2
and manibulatio at dota & Instru.ctHons.
Dota rebmains in ne Registers ill they Sent to the memor
or TloDevices
Intel 808S microbro.cess.or has the tollouwing RegistersS
CiOne8-bit Acumulator (AC)
Ci Six &-bit general Purhose Register.s(B-C,D-E,H-L)
Cii lemboraru RegisterS
Civ)InStrucion Register
One 16-bit Stack PoinBer CiSP)
i One i6-bit Program Counter (PC)
Tn Addition of theSe
RegiSters Microbro.ce.ssor Contain S a Set
of five tlip-tlos LServe as Status tlags)_ar status Signals
Lhich Indfootes Some Condiionsuhidh arlses ofter the
eXecution otf an Ariihematic ar togical InstrucHions.
Accumulator CAC):
TheActumulatopis an &-bit register aSSoc.iated with ALU.
Tt1S USed to Kold ane of thepherands at an Arithmeticor
Logical Oberotion.
It Serves asone inbut fo the Alu.
The ofher obershd or an Arithmetic ar Logital dherotion
may be Store.d eithér in the mem.ony or in one of the
Generol Porbose Reg1sters.
The final RESult 0f an Arithmetic or Logicol Oberation is
blaced in the Accumulator.
Teocher's Signcture:
xpt. Noo.
Page
o4l0202.2
Caeneral Purbose Re9isters
Ihe &o&5 micrabracess.or conkains Six 8-bit General-blurbo
-Se RegiSters.
Ihey are B-C, D-E, H-1 to hald 16-bit dat.a
The Combination ot 2 8-bit registers is_knauuna s register
bair Such as (B-C,D-E, H-1).
The H-L bair is US.ed to Oct 0& 0 memory bointer and
for ihis burbose tholds fhe 16-bit AddieSs ot fhe
memory LoGation.
he general urbose registers and the Actumulator are
aCcessible to thé þrogtam mer, he can store data in_
hese registe.rs during uriting oT Program
rogram Counter (Pc):
It iS a A6-bit Shecial þurhose.register.
i s USed to hold fhe memoru Address at the next
InStruction in aprogramwhile they are being Executed
he microprocessor increments the Content the
Pmgram Counter PC) during the Executi.on of the Tnst
-UGtion 50 t h a t boinfs to the Address of the next
Insimuthion Pine proqram ot the end ot he Executian
of an TnStruction.
Sta.ck Painter(SP):
It iS.a 16-bit Special Function Register.
eochers Signoture
Expt Nod PageNo.
The stackis the Sequence at the memory Locahion set
USed toStore retrieve the Contents ot the ACCumulator,
Elags,progro.m Counter etc.during the Execution at the
rog.ram
Ang portHon of he memor4 Can be USed to act as a
Stack. Sinte, it uun.rks on LIEO þrinciple.,iEs Oþeradtion iS
mster as Gombared to Normal Store ret.rieve at the
Memory LO.cation.
Ihe Stück bointerS P ) ContoolS addressing ot the Stach.
he Stck bointer (SP) holds the Address f the tobmost
element af data Store.d in the Stack.
Instructian Register
TheTnshruction Resisher TR)holds the ObCadeCoberation
Gode)or Insteucion Code ot he Instruchion uwhich is
being decoded Executed..
Tembotary Register:
t is an 8-bit register Asspefated uith ALU.
Itholds Dotu uring an Arihmetio or Lbgital 0keration.
It is uSed by microsro.o.esSor
It is not AccesibkE to þrogrommer.
Flags:
AFlag iS a Plib-flop.Tt indicotes Some Candittons þmduced
Teochers rgncu
Bit No.
Status Plags of Intel ao85
D2 D1 Do
D Ds Du Da
D
SZxACXPX CS
Sian Zero Auxillory Parihy Corry Flag
Flag Fla Carty Flag Flag
Undetined Flags
Example:
ADD 10111010 and 01401001
One-byte No. (4 byte -2bits)
1011 1010
+0i1 0io 0 1
O010 O0 1/1 Non Zero
(z=0)
Cary(Cs= 1)
Apxillo Carry (CS)
Expt No.
age No. o4082022
by the Execution of an Tnstruc.Hon
The Flag register is Connecked uith ALU
ohen an 0berotion is berformed by ALU, the reSut uill
be transterred on data bus and Status of
be Stored in lib-Flohs. result will
Ihe Flib-FlopS are
seB or res et aCcording to the conditti-
-on uhich arises during an Arithmeti.c or Logic.al
Oerations.
Theditferemt Flags and there basitioms ino Hlag register
are shown in
Fq
ive Stahus Elags ot 808 5 LPare as
.The Carry flag CcS):
AFter the Execution ot an Arithmetic Tnstruchiog i
Car ry i S
broducedine Carry Elag (i.e CS) is Set to 1,
otherwise it ia o.
TheCaru Plag is Set or reset in Case ot Addikon as
Lell
CSuhtra kion
ThisFlag isused by Instruchions that add.or Sulktract
muHibute Numbtrs
Conclusion:
CS1 Carry ouf fro mMSB bit on Addition_on borrauw int
MSE bit onSubtraction.
|C.S=0 No Carry or borrou into MSB hit.
eothers Sgnature :
1 032.0.2.2
Date
ENple
2TheTaridy Flag (P)
This Flag is Set Cie Pai) uhenever the resulE of the
Arithme Hic or Logioal Oberation has Even Parity (ie
even
E
number ot 'S in Result).
result ContainS 0dd Number of 1's i t will be res e t
Ci.e P= 0)
Conclusio
Pa1 Result has Even Number o1
P0 Result has odd Number ot 1S
3. The Auxiliary Carry Flag CACAE
This Flag ts_Set ke AC:4) whenever there has been.a
Carry out at Ane Louwer ibble into the Higher Nibble
ar 6orrou tromhigher nibble into the lower nibble.ot
an8 bit quantity.
ACeo)
Otherwise AG Luill be resetli.e
This Flagisu s e d by decimal Arithmetic.
Conclusion:
AC-1 Carry outfcom Louer nibble to Higher on Addition
orborrou inta a. Higher nibble o LoLaer nibble.
AG0atherwise.
.The Zex Flog (z):
TeochersSgnalure.
Ou o.3/2.022
Expt.NO
his FlagiS 5t (ie_z=1) if the result of ArithmeHic
or Logical Oheration_is O, atherwise it willhe reset (z0
Conclusion:
1:1 Resut iS
Z 0 Non-Zero Result.
5TheSign ElagS):_
This Elag iS the Sign of the Result.
It is 5et li.e S= 4) it the Result ot fhe Arithmetic
or Logteal Oberadionis Negatiye
Otheruise,in Case.of Postive Result,it will be Reset
Comclusinn:
S=1 MSB ot Result isi CNegadive)
S=0 M5B 1 Result iso CPaSitive
Dato and Address Bus:
Theintel 808.5 S a 8-bit Mic.ropric.essor
It6 dota Bus is &-bit wice and Hence, &-bit at data
Con be transmitte.d in parallel trom or to ihe Micmbrocessor.
TheTntel2085 reguifes a 16-bit uide address bus as
the memory Adaress are o 16-bits.
The 8-most
significantbits ot he AddresS are tranS
-mitted b Addrèss bus,A-bus(hins Asta Ais calledL
as Highec-order BuS.
Teochers gnoure
Expl. No. No.
D08a02
Date
The &-Least Significant bitsof the Address are tranSmi-
-thed by Address
OsLowe-order BUS
/Dato. BUS AD-bus (AD-ADEJcalled
Ihe Address/Data bus tranSmit either data. and Address
at ditferent moments.
At o articular moment it teanSmit either data orthe
Address. Thus, AD-Bus 0berates in Time-SharedMade
Ihis Technlque iS knaun as Muliblexing.
2-5536=64K,where 1ks 1024 memory locations,
Can be Addressed directly by Intel 8085
Each Memory Lotation Contafn.s ibyte.of dafa
leochers Signcture
Drauw and Explain Prn Digram ot 8085 P :
Vec = t 5Vl. c +5Y
Vss = CtND
Vce
22- 12
4oVec s1P5 HO
39HOLD So AD AD
REMETOU 3 38-HLDA 12-19
H
SoD 4 31CLK 0UT
SiD 5 36RESET I TRAP o E
35READY 21 So
FST-5 34
RST5
M RST 6:5 33 Si
RTS8 33 RST5 34 o/M
RT 55 8085A 32 32 RD
NTR
NTA
30
34
INTR
HINTA
b 808 A 34usR
30 -ALE
ADO 12 23 RESETI36
ADI 13 AI5 D
AD 14 23 A 38 HLDA
D3 15 26A3 RESET
ESET OuT
OUT
25A
ADS 4 2.4 Au
AD 18 BENDY
AD 19
23AD
22 A3
20
21 Ag
20
CLK COUT)
Vss
Fig Phin Configurotion of a085A
Guround Signal
Fvnt No 0403/202.2
Dra and xblain fin Diagram at 8o8S uP
The&085 uP iSa uOPin L.c Package fabricated on a. Single
LSI.Clarge-Scale Tntegration.) chi.
TheDisCription of Various Pins are as Follou:
Ag-Ais (outhut):
These are Address.bus and are used for the most signifitant
bitsof the memory Address or Abiks ot lo Addres.
These are Also called High-0rder Bus Lines.
ADo-AD- (Tnput/output J:
Ihese are time muliplexed addressdata huS ie they
Serve dual burbose
Iheyare uSed tor the least Sianitrcant &bits of the
memory Address D r TO Addre sa during the tirst clock
Cucle of a machine cgcle
Again They are uSed tor data during he Second clock
Gucle and hicd clock Cucle
To/M Coutput):
It is a Status Signal which diSHnguishes uhether the
Address is for Memory or IlO
Luhen it gbes high, the Address on the Address bus is
tor an Ilo device.
luhen it goes low, the Address an he Address buS is
Por Memory Location..
Tecchers Srgnolu
