11-3 Asynchronous Data Transfer The internal operations in a digital system are synchronized by means of clock pulses supplied by a common pulse generator. Clock pulses are applied to all registers within a unit and all data transfers among internal registers occur simul- taneously during the occurrence of a clock pulse. Two units, such as a CPU and an I/O interface, are designed independently of each other. If the registers in the interface share a common clock with the CPU registers, the transfer between the two units is said to be synchronous. In most cases, the internal timing in each unit is independent from the other in that each uses its own private clock for internal registers. In that case, the two units are said to be asynchronous to each other. This approach is widely used in most computer systems. Asynchronous data transfer between two independent units requires that control signals be transmitted een the communicating units to int cate the time at wl lich data is being transmitted. One way of achieving this Eby means of 4 Grob? pulse supplied by one of the units to indicate to the other unit when the transfer has to occur. Another method commonly used “js to accompany each data item being tdnsferred with a control signal that_ indicates the presence of data in the bus. The unit receiving the data item. Fesponds will Tontrol signal to’ acknowledge receipt of the data. Thi of agreement between two independent units is referred to as _ eset, pulse method and the handshaking method of asynchronous data transfer are riot restricted to I/O transfers. In fact, they are used extensively on numerous occasions. requiring the transfer of data between two independent units. In the general case we consider the transmitting unit as the source and the receiving unit as the destination. For example, the CPU is the source unit dur- ing an output or a write transfer and it is the destination unit during an input or a'read transfer. It is customary to specify the asynchronous transfer between two independent units by means of a timing diagram that shows the timing rela- Jionship thar must 2 between the control signals and the data in the buses. ‘The sequence sequence of control during an asynchronous transfer depends on whether the transfer is initiated by the source or by the destination unit. Scanned with CamScanner394 gum nv © ae" i (b) Timing diagram oF Figure 11-3 Source-initiated strobe for data transfer. = ——— Input-Output Organization @) Data bus. Destination. unit Source unit (0) Block diagram —yshann : 4 wv, tu Data i Valid tu ——] Strobe 4 Strobe Control \ The strobe control method of asynchronous data transfer employs a si control line to time each transfer. (The strobe, may be activated by either th solirce or the destination unit. Figure 11-d[a) shows a source-initiated transfel ¢ data bus carries the binary informationyom source unit to the destinatia it) Typically, the bus has multiple lines to transfer an entire byte or wo strobe is a single line that informs the destination unit when a valid d: word is available in the bus} ~ in the timinig diagram of Fig. 11-3(b), the source unit fir places the data on the data bus. After_a brief delay to ensure that the data te to a steady value, the source activates the strobe pulse. The information 0 the data bus and the strobe signal remain in the active state for a sufficient tim period to allow the destination unit to receive the dat) Often, the destinatio “unit uses the falling edge of the strobe pulse to transfer the contents of the dat bus into one of its internal registersThe source removes the data from the b a brief period after it disables its strobe pulse) Actually; the source does a Rave to change the information in the data bu’. The fact that the strobe sign is disabled indicates that the data bus does not contain valid data, New vi data yill be available only after the strobe is enabled again. igure 11-4 shows a data transfer initiated by the destination unit. In th case the destination unit activates the strobe pulse, informing the source, rovide the data. The source unit responds by placing the requested bin IBTORRRE OB the data bun. The dais must be valid sad renin in the long enough for the destination unit to accept i) The falling edge of the strob pulse can be used again to trigger a destination tegister.(The destination um then disables the inert souitce removes the data from the bus after determined time interval. Scanned with CamScannerSECTION 11-3. Asynchnonous Data Transfer 395 Data bus( 2) Strobe i (@) Block oS Fofrvon He Fornre os J— Valid data —] fe wep \ (b) Timing diagram Figure 11-4 Destinati Destination 2 tiated strobe for data transfer. ~~ In many computers the strobe pulse is actually controlled by the clock pulses in the CPU. The CPU is always in control of the buses and informs the external units how to transfer data. For example, the strobe of Fig. 11-3 could be a memory-write control signal from the CPU to a memory unit. The source, being the CPU, places a word on the data bus and informs the memory unit, which is the destination, that this is a write operation. Similarly, the strobe of Fig. 11-4 could be a memory-read control signal from the CPU to a memory unit. The destination, the CPU, initiates the read operation to inform the mem- ory, which is the source, to place a selected word into the data bus. The transfer of data between the CPU and an interface unit is similar to the strobe transfer just described. Data transfer between an interface and an 1/O device is commonly controlled by a set of handshaking lines. dora. de hae Pus /Bandshaking Preoasace a disadvantage of the strobe method is that the source unit that initiates the transfer has no way of knowing whether the destination unit hi received the data item that was placed in the bus. Similarly, a destit un “that initiates the transfer has no way of knowing whether the source unit has actually placed the data on the bus. The handshake method solves this prob- lem by introducing a second control signal that provides a reply to the unit that initiates the transfer. The basic principle of the two-wire handshaking method of data transfer is ds follows. One control line is in the same direction as the data flow. in the bus from the source to the destination, It is used by the source unit to inform the destination unit whether there are valid data in the bus. The other control line is in the other direction from the destination to the source. It is used by the destination unit to inform the source whether it can accept data. The sequence of control during the transfer depends on the” Sn tbaE Eas the transfer Scanned with CamScannerif CHAPTER ELEVEN Input-Ourput Organization i Data bus, Source Data valida Destination unit ~~ Data accepted 3 unt (a) Block diagram Data bus_/* [ana data—| Data valid Data accepted (b) Timing diagram Source unit Destination unit Place data on bus. Enable data valid. = I~ [Accept data from bus. Pn Enable data accepted. [——+] Disable data accepted. Reaidy to accept data {initial state.) * -| Disable data valid. linvalidate data on bus} (c) Sequence of events Figure 11-5. So ated transfer using handshaking. —S" ° re 11-5 shows the data transfer procedure when initiated by source. The two handshaking lines“are “data valid, which is generated by source unit, and data accepted, generated by the destination unit. The timi diagram shows the exchange of.signals between the two units. The sequel of events listed in part (c) shows the four possible states that the system can at any given time. The source unit initiates the transfer by placing the data the bus and enabling its. data valid signal. The data accepted signal is activ' by the destination unit after it ‘accepts the data from the bus. The source ~ then disable data valid signal, which invalidates the data on the bus. destination unit then disables its data accepted signal'and the system goes i Scanned with CamScannerSICTION 11-3 Asynchronous Data Transfer 397 is ini state. The source does not send the next data item until after the pester on uit shows its readines to acept new data by disabling is data ind permits ee allows arbitrary delays from one sate tothe next 2 n nit to respond at its 1 transfer is determined by eeclmer ee data transfer rate. The rate of righ cae transfer ug handshaking lines is shown in Fee ace crane thatthe name of the signal generated by the destination unit inged to ready for data to reflect its new meaning. The source unit Figure 11-6 Destination-initiated transfer using handshaking. Destination unit £ (a) Block diagram Ready for data Data valid ais ‘Valid data (b) Timing diagram Source unit Destination unit Ready tovaccept data. Enable ready for data, [Accept data from bus. Disable ready for data, Scanned with CamScanner398 timeout CHAPTER ELEVEN Input-Output Organization in this case does not place data on the bus until after it receives the ready jy data signal from the destination unit. From there on, the handshaking procedie, follows the same pattern as in the source-initiated case. Note that the Sequence of events in both cases would be identical if we consider the ready for day signal as the complement of data accepted. In fact, the only difference between the source-initiated and the destination-initiated transfer is in their choice of initial state. Sin scheme provides a high degree of flexibility and relia. bility because the successful completion of a data transfer relies on active ar. Feipation by both unitd) If one unit is faulty, the data transfer will not be ‘completed: Such an error can be detected by means of a timeout mechanism, which produces an alarm if the data transfer is not completed within a prede. termined time. The timeout is implemented by means ofan internal clock that starts counting time when the unit enables one of its handshaking control sig- nals, If the return handshake signal does not respond within a given time period, the unit assumes that an error has occurred. The timeout signal can be used to interrupt the processor and hence execute a service routine that takes appropriate error recovery action. ‘ 47 Scanned with CamScanner