Verilog Codes
for Basic Digital Components
W. J. Dally and E. C. Harting, “Digital
Design, a Systems Approach,” 2012
Chap. 8: Combinational Building Block
1
Outlines
• Combinational Logic
– multiplexers, de-multiplexers
– encoder, decoder, priority encoder
– ripple carry adder
– logical and arithmetic shifter
– shift registers
– ALU
– ROM, RAM
• Sequential Logic
– latch, asynchronous reset latch
– flip-flop, asynchronosu/synchronous reset flip-flop
– register file
– pipeline
– finite state machine (FSM)
– clock gating 2
Combinational Logic
3
multiplexer (1/2)
module mux4_1 ( module mux4_1 (
output reg out, output out,
input i0, i1, i2, i3,
s1, s0); input i0, i1, i2, i3, s1, s0);
always @(*) assign out = s1 ? (s0? i3 : i2) : (s0 ?
begin i1 : i0);
case ({s1, s0})
2’d0 : out = i0;
2’d1 : out = i1; endmodule
2’d2 : out = i2;
2’d3 : out = i3;
end
endmodule
4
multiplexer (2/2)
// MUX3 with one-hot select // MUX3 with binary select
module MUX3_onehot (a2, a1, a0, s, module MUX3_onehot (a2, a1, a0,
b); s, b);
parameter k = 32; parameter k = 32;
input [k-1:0] a0, a1, a2;
input [k-1:0] a0, a1, a2; input [1:0] s; // binary select
input [2:0] s; // one-hot select output [k-1:0] b;
output [k-1:0] b; reg [k-1:0] b;
reg [k-1:0] b;
always @ (*) begin
case (s)
always @ (*) begin 0: b = a0;
case (s) 1: b = a1;
3’b001: b = a0; 2: b = a2;
3’b010: b = a1; default: b = {k{1’bx}};
3’b100: b = a2; endcase
end
default: b = {k{1’bx}}; endmodule
endcase
end
5
endmodule
demultiplexer
module demux1_4 (
output reg out0, out1, out2, out3;
input in,
input [1:0] s );
always @(s, in)
case (s)
2’b00: begin out0 = in; out1=1’bz; out2=1’bz; out3=1’bz; end
2’b01: begin out0 = 1’bz; out1=in; out2=1’bz; out3=1’bz; end
2’b10: begin out0 = 1’bz; out1=1’bz; out2=in; out3=1’bz; end
2’d11: begin out0 = 1’bz; out1=1’bz; out2=1’bz; out3=in; end
default: $display (“Invalid control signals”);
endcase
6
encoder
module encoder (
input i3, i2, i1, i0,
output reg [1:0] out);
always @(i3, i2, i1, i0)
valid = 1;
case ({i3, i2, i1, i0})
4’b1000: out = 2’b11;
4’b0100: out = 2’b10;
4’b0010: out = 2’b01;
4’b0001: out = 2’b00;
endcase
endmodule
7
priority encoder // 8:3 priority encoder
module priority_enc83 (r, b);
module priority_enc42 input [7:0] r;
(input i3, i2, i1, i0, output [2:0] b;
output reg [1:0] out;) reg [2:0] g;
always @(i3, i2, i1, i0) assign b = g;
casex ({i3, i2, i1, i0}) always @ (*) begin
4’b1xxx: out = 2’b11; casex®
4’b01xx: out = 2’b10; 8’bxxxxxxx1: g = 0;
4’b001x: out = 2’b01; 8’bxxxxxx10: g = 1;
default : out = 2’b00; 8’bxxxxx100: g = 2;
endcase 8’bxxxx1000: g = 3;
8’bxxx10000: g = 4;
8’bxx100000: g = 5;
8’bx1000000: g = 6;
8’b10000000: g = 7;
default: g = x;
endcase
end
endmodule 8
decoder (1/3)
module decoder (
input [1:0] in;
output reg out0, out1, out2, out3) ;
always @(in)
case (in)
2’b00: begin out0=1; out1=0; out2=0; out3=0; end
2’b01: begin out0=0; out1=1; out2=0; out3=0; end
2’b10: begin out0=0; out1=0; out2=1; out3=0; end
2’d11: begin out0=0; out1=0; out2=0; out3=1; end
endcase
endmodule
9
decoder (2/3)
module decoder_index (in1, module decoder_loop (in1, out1);
out1); parameter N=8;
parameter N=8; parameter log2N = 3;
parameter log2N = 3; input [log2N-1: 0] in1;
input [log2N-1: 0] in1; output reg [N-1:0] out1;
output [N-1:0] out1;
integer i;
always @ (in1) begin
out1 = 0; always @ (in1)
out1[in1] = 1’b1; for (i=0; i<N; i=i+1)
end out1[i] = (in1 == i);
endmodule endmodule
10
decoder (3/3)
// n-to-m decoder
module Dec (a, b);
parameter n=3;
parameter m=8;
input [n-1: 0] a;
output [m-1:0] b;
assign b = 1 << a;
endmodule
11
ripple carry adder (1/2)
module ripple_adder(co, sum, a0, a1, ci); module ripple_adder(co, sum, a0, a1, ci);
parameter N=4; parameter N=4;
output [N-1:0] sum; output [N-1:0] sum;
output co; output co;
input [N-1:0] a0, a1; input [N-1:0] a0, a1;
input ci; input ci;
wire [N-1:0] carry;
wire [N-1:0] p = a0 ^ a1;
assign carry[0]=ci; wire [N-1:0] g = a0 & a1;
wire [N:0] carry = {g | ( p & carry[N-1:0] ), ci};
genvar i; // carry[0] = ci;
generate // carry[1] = g[0] | ( p[0] & carry[0] );
for (i=0; i<N; i=i+1) // carry[2] = g[1] | ( p[1] & carry[1] );
begin: r_loop // carry[3] = g[2] | ( p[2] & carry[2] );
wire t1, t2, t3; // carry[4] = g[3] | ( p[3] & carry[3] );
xor g1(t1, a0[i], a1[i]);
assign sum = p ^ carry[N-1:0];
xor g2(sum[i], t1, carry[i]); assign co = carry [N];
and g3(t2, a0[i], a1[i]);
and g4(t3, t1, carry[i]); endmodule+
or g5(carry[i+1], t2, t3);
end
endgenerate
assign co = carry[N]
12
endmodule
Ripple Carry Adder (2/2)
module ripple_adder(co, sum, a0, a1, ci);
parameter N=4;
output [N-1:0] sum;
module ripple_adder(co, sum, a0, a1, ci); output co;
parameter N=4; input [N-1:0] a0, a1;
output [N-1:0] sum; input ci;
output co; wire [N:0] carry;
input [N-1:0] a0, a1;
input ci; assign carry[0]=ci;
wire [N:0] carry;
always @ (a0 or a1)
assign carry[0]=ci; begin
for (i=0; i<N; i=i+1)
always @ (a0 or a1) begin
begin carry[i+1] = a0[i]&a1[i] | a0[i]&carry[i] |
for (i=0; i<N; i=i+1) a1[i]&carry[i];
{carry[i+1], sum[i]} = a0[i] + a1[i] + sum[i] = a0[i]^a1[i]^carry[i];
carry[i] ; end
end end
assign co = carry[N] assign co = carry[N]
endmodule 13
endmodule
left/right shifter
module shifter (
input left,
input [2:0] shift_amt,
input [7:0] data_in,
output [7:0] shifted_data);
assign shifted_data = (left) ? data_in << shift_amt : data_in >>
shift_amt;
endmodule
14
wrap-around barrel shifter
module barrel_shift (n, a, b);
parameter k=8;
parameter lk=3;
input [lk-1:0] n; // how much to shift
Input [k-1:0] a; // number to shift
output [k-1:0] b; // the output
wire [2*k-2:0] x = a << n; // output before
wrapping
assign b = x[k-1 : 0] | {1’b0, x[2k-2 : k] };
endmodule
15
arithmetic shift (<<<, >>>) in Verilog-2001
// Verilog-2001
integer data_value,
data_value_1995,
data_value_2001;
…
data_value = -9; // stored as 1111_…_1111_0111
…
data_value_1995 = data_value >> 3; // stored as 0001_..._1111_1110
…
data_value_2001 = data_value >>> 3; // stored as 1111_...._1111_1110
// repeat sign bit during arithmetic right shift
…
data_value_1995 = data_value << 3; // stored as 1111_..._1011_1000
…
data_value_2001 = data_value <<< 3; // stored as 1111_..._1011_1000
// repeat sign bit during arithmetic left shift
// give an example where the logical left shift << 3 is different from arithmetic shift
// e.g., data_value2 = 32’b 1110_xxx ….
16
shift register with parallel load
module shiftreg #(parameter N=32)
(input clk, reset, load, si,
input [0:N-1] d,
output [0:N-1] q,
output so);
always @(posedge clk)
if (reset) q <= 0;
else if (load) q <= d;
else {q, so} <= {si, q};
endmodule
17
left/right/load shift register
module LRL_Shift_Register(clk, rst, left,
right, load, sin, in, out) ;
parameter n = 4 ;
input clk, rst, left, right, load, sin ;
input [n-1:0] in ;
output [n-1:0] out ;
reg [n-1:0] next ;
DFF #(n) cnt(clk, next, out) ;
// always @ (posedge clk) out <= next;
always @(*) begin
casex({rst,left,right,load})
4'b1xxx: next = 0 ; // reset
4'b01xx: next = {out[n-2:0],sin} ; // left
4'b001x: next = {sin,out[n-1:1]} ; // right
4'b0001: next = in ; // load
default: next = out ; // hold
endcase
end
endmodule
18
ALU
module MIPSALU (
input [31:0] a, b;
input [3:0] ALU_ctl;
output reg [31:0] ALU_out;
output Zero );
assign Zero = (ALU_out == 0);
always @ (ALU_ctl, a, b)
case (ALU_ctl)
4’d0 : ALU_out = a & b;
4’d1 : ALU_out = a | b;
4’d 2 : ALU_out = a + b;
4’d6 : ALU_out = a – b;
4’d 7: ALU_out = (a < b) ? 1 : 0;
4’d12: ALU_out = ~(a | b);
default: ALU_out = 32’b0;
endcase
endmodule
19
Synthesis of ROM/RAM
• If synthesis tool supports pragmas to control the structure of the
synthesized netlist or to give direction to the synthesis tool, synthesis
attributes shall be used
– The first attribute within the attribute instance shall be synthesis
followed by a comma separated list of synthesis-related attributes.
20
Ref.: IEEE Std. 1364.1 Verilog Register Transfer Level Synthesis
module rom_case (a, d) ;
input [3:0] a;
Two Implementations of ROM
output [7:0] d; (using case, or using input text file)
reg [7:0] d; module rom_reg (a, d) ;
always@(*) parameter b =8;
begin
parameter w = 4;
case(a)
4'h0: d=8'h00; parameter fileName = "datafile";
4'h1: d=8'h11; input [w-1:0] a;
4'h2: d=8'h22; output [b-1:0] d;
4'h3: d=8'h33; reg [b-1:0] memory [2**w-1:0] ;
4'h4: d=8'h44; initial
4'h5: d=8'h12; begin
4'h6: d=8'h34; $readmemb (fileName, memory);
4'h7: d=8'h56;
end
4'h8: d=8'h78;
4'h9: d=8'h9a; assign d = memory[a];
4'ha: d=8'hbc; endmodule
4'hb: d=8'hde;
// content of file “datafile” memory[0]=xxxxxxxx
4'hc: d=8'hf0;
// address in hexadecimal memory[1]=xxxxxxxx
4'hd: d=8'h12;
@002 memory[2]=11111111
4'he: d=8'h34;
11111111 01010101 memory[3]=01010101
4'hf: d=8'h56;
00000000 10101010 memory[4]=00000000
default: d=8'h0;
@006 memory[5]=10101010
endcase
1111zzzz 00001111 memory[6]=1111zzzz
end
… memory[7]=00001111 21
endmodule
…
ROM
• Three types of ROM models
– one-dimensional array with data in case
statement
– two-dimensional array with data in initial
statement
– two-dimensional array with data in text file
Ref.: IEEE Std. 1364.1 Verilog Register Transfer Level 22
ROM: 1D array using case
• Synthesis attribute rom_block model ROM
• Attribute logic_block implies combinational logic
23
ROM: 2D array using initial
• initial statement shall be supported when synthesis
attributes logic_block or rom_block is used
• without specifying attributes, a synthesis tool may opt to
implement either as random combintional logic or as a
ROM
24
ROM: 2D array with data in text file
• use $readmemb to read ROM data from a text file
25
RAM
26
Edge-sensitive RAM
• RAM shall be modeled with synthesis attribute ram_block
• If latch or register logic is desired instead of a RAM, use the
attribute logic_block instead of ram_block
• RAM could be edge- or level-sensitive
• e.g. we (write-enable) control signal is synchronized with clock
signal
27
level-sensitive RAM
• we (write-enable) is the level-sensitive control signal
– not clock signal is used
28
dual-port (one-read, one-write) RAM
• check definitions of two-port or dual-port in document
– 1R/1W, 2R, or 2W, or
– 1R/1W only module RAM(ra, wa, write, din, dout) ;
parameter b = 32;
parameter w = 4;
input [w-1:0] ra, wa;
input write;
input [b-1:0] din;
output [b-1:0] dout;
reg [b-1:0] ram [2**w-1:0];
assign dout = ram[ra]; // one read port
always@(*) begin
if(write == 1)
ram[wa] = din; // one write port
end
endmodule 29
RAM with bidirectional data bus
module ram #(parameter N=6, M=32)
(input clk, we,
input [N-1:0] adr,
inout [M-1:0] data);
reg [M-1:0] mem [2**N-1:0];
always @ (posedge clk)
if (we) mem[adr] <= data;
assign data = we ? ‘z : mem[adr];
endmodule
30
RAM: 2D array using always
• in general, standard cell library vendors or FPGA
synthesis tools usually provide automatic generator
(compiler) of memory, such as RAM, ROM, register
file which are usually custom designs
31
Sequential Logic
32
Latches and Flip-Flops
33
register inference
• D latch
– with asynchronous set
– with asynchronous reset
– with asynchronous set/reset
• D flip flop
– with asynchronous set
– with asynchronous reset
– with asynchronous set/reset
– with synchronous set
– with synchronous reset
– with synchronous and asynchronous load
34
D Latches in TSMC 0.18um Cell Library
TLAT
active-high
TLATN
active-low
TLATNR
asynchronous
active-low
reset
TLATNSR
asynchronous
active-low
35
set/reset
DFFs in TSMC 0.18um Cell Library
DFF
DFFR
asynchronous
active-low
DFFTR
synchronous
active-low
DFFSR
asynchronous
active-low
36
set/reset
inferring simple D-latch
module d_CL (
input gate, data,
output reg q );
// infer a combinational logic,
// not a latch
always @ (gate or data)
if (gate)
q <= data;
else
q <= ‘b0;
endmodule
37
D Latch Circuit using CMOS
• constructed from back-to-back inverters
φ Q VDD
X
D
φ A Y
φ
GND
φ
A Y 38
D-latch with asynchronous set (active-low)
39
D-latch with asynchronous reset (active-low)
• sensitive list includes control signals and input
data signals
40
D-latch with asynchronous set and reset
(active-low)
41
latch with asynchronous set and reset
module d_latch_async (
input gate, data, reset_n, set_n;
output reg q;
always @ (gate, data, reset_n, set_n)
if (!set_n) q <= 1’b1;
else if (!reset_n) q <= 1’b0;
else if (gate) q <= data;
endmodule
42
inferring D-flipflop
43
Logic of D Flip-Flop
• composed of master and slave D-latches
• triggered at the time instance of clock edge
– unlike latch which is active (transparent) when clock is at
logic level of high
44
D Flip-Flop using CMOS
• constructed from two D latches (either dynamic or
static)
– cell library usually adopts static design
φ φ
X
Dynamic D Q
DFF
φ φ
φ φ Q
Static X
D Q
DFF φ φ
φ φ
φ φ 45
DFF with asynchronous set (active-low)
• sensitive list includes edges of both clock and
control signals
– synthesized into hardware different from normal DFF
46
DFF with asynchronous reset (active-high)
47
DFF with asynchronous set and reset (active-high)
48
DFF with asynchronous set and reset
module dff_async (
input clk, reset, set, data,
output reg q);
always @ (posedge clk or posedge reset or posedge set)
if (reset) q <= 1’b0;
else if (set) q <= 1’b1;
else q <= data;
endmodule
49
DFF with synchronous set (active-high)
• sensitive list includes only clock signal
– synthesized into normal DFF with extra combinational
logic for the input data
50
DFF with synchronous reset (active-low)
51
DFF with synchronous and asynchronous load
52
Resettable DFF Circuits using CMOS
φ φ
Symbol
Latch
Flop
D Q D Q
reset reset
Synchronous Reset
φ Q φ φ Q
reset reset
Q
D D
φ φ
φ
φ φ φ
φ φ
φ
Q
Q φ
Asynchronous Reset
φ φ
reset
reset
D
D φ
φ φ
φ
φ φ
reset
reset
φ
φ
φ 53
register file
• register file is compose of registers
• can access many registers at the same time
• cp. single-port RAM which can access only one data
module RegisterFile (r_adr1, r_adr2, data1, data2, w_adr, w_data, w_cntl, clk)
input [5:0] r_adr1, r_adr2, w_adr;
input [31:0] w_data;
input w_cntl, clk;
output [31:0] data1, data2;
reg [31:0] RF [0:31];
// read from register f ile
assign data1 = RF[r_adr1];
assign data2 = RF[r_adr2];
// write to register file
always @ (posedge)
if (w_cntl) RF[w_adr] = w_data;
endmodule
54
Two types of Sequential Logic
• Pipeline
– break long datapath into several stages, each realized in
one clock cycle
– use pipelined registers to cut the combinational logic into
several stages
– better pipelining with balanced delay for each pipeline
stage
• Finite State Machine (FSM)
– generate control signals for datapath components
– use registers to store the states
– output depends on either the current states, and/or the
current inputs
55
Pipeline
module pipelined (
input [31:0] A, B, C;
input clk;
output [63:0] out);
reg [63:0] C_pipe1;
reg [63:0] out_pipe1, out_pipe2;
always @ (posedge clk) begin
out_pipe1 <= A*B;
C_pipe1 <= C;
end
always @(posedge clk)
out_pipe2 <= out_pipe1 + C_pipe1;
assign out = out_pipe2;
endmodule
56
Moore vs. Mealy FSM
• Moore FSM
– output is a function of only present state
• Mealy FSM
– output is a function both present state and input
57
FSM (Finite State Machine)
// lower section of FSM
always @ (posedge clk, posedge rst) begin
if (rst == 1) pr_state <= … ;
else pr_state <= nx_state;
// out <= temp_out; // for stored output
end
// upper section of FSM
always @ (pr_state, input) begin
case pr_state
state1: begin
tmp_out = ...;
if ( input == …) nx_state = …; else Mealy FSM:
nx_state = …; output = f(input, pr_state)
end nx_state = g(input, pr_state)
state2: …
…
endcase
end
// output section for not non-stored output
assign out = tmp_out;
58
Example of FSM: Vendor Machine
• Newspaper vendor machine
. newspaper costs 15 cents
. accept coins of nickels (5 cents)
and dimes (10 cents) only
. do not return extra money 59
FSM Example: Vendor Machine (1/7)
binary encoding of states
module vend(coin, clock, reset, newspaper);
input [1:0] coin;
input clock;
input reset;
output newspaper;
wire newspaper;
wire [1:0] NEXT_STATE;
reg [1:0] PRES_STSTE;
// state encodings (binary)
// cp. one-hot encoding
parameter s0 = 2’b00;
parameter s5 = 2’b01;
parameter s10 = 2’b10;
parameter s15 = 2’b11;
60
FSM Example: Vendor Machine (2/7)
generate output/next states
(combinational logic in upper FSM)
// combinational logic
function [2:0] fsm;
input [1:0] fsm_coin;
input [1:0] fsm_PRES_STATE;
reg fsm_newspaper;
reg [1:0] fsm_NEXT_STATE;
begin
case (fsm_PRES_STATE)
61
FSM Example: Vendor Machine (3/7)
generate output and next state for each
present state
s0: // state = s0
begin
if (fsm_coin == 2’b10) begin
fsm_newspaper = 1’b0;
fsm_NEXT_STATE = s10; end
else if (fsm_coint == 2’b01) begin
fsm_newspaper = 1’b0;
fsm_NEXT_STATE = s5; end
else begin
fsm_newspaper = 1’b0;
fsm_NEXT_STATE = s0; end
end
62
FSM Example: Vendor Machine (4/7)
generate output and next state for each
present state
s5: // state = s5
begin
if (fsm_coin == 2’b10) begin
fsm_newspaper = 1’b0;
fsm_NEXT_STATE = s15; end
else if (fsm_coint == 2’b01) begin
fsm_newspaper = 1’b0;
fsm_NEXT_STATE = s10; end
else begin
fsm_newspaper = 1’b0;
fsm_NEXT_STATE = s5; end
end
63
FSM Example: Vendor Machine (5/7)
generate output and next state for each
present state
s10: // state = s10
begin
if (fsm_coin == 2’b10) begin
fsm_newspaper = 1’b0;
fsm_NEXT_STATE = s15; end
else if (fsm_coint == 2’b01) begin
fsm_newspaper = 1’b0;
fsm_NEXT_STATE = s15; end
else begin
fsm_newspaper = 1’b0;
fsm_NEXT_STATE = s10; end
end
64
FSM Example: Vendor Machine (6/7)
generate output and next state for each
present state
s15: // state = s15
begin
fsm_newspaper = 1’b1;
fsm_NEXT_STATE = s0;
end
endcase
fsm = {fsm_newspaper, fsm_NEXT_STATE};
end
endfunction
65
FSM Example: Vendor Machine (7/7)
store next state
(sequential logic in lower FSM)
// reevaluate combinational logic each time a coin is put or
// the present state changes
assign {newspaper, NEXT_STATE} = fsm(coin, PRES_STATE);
// clock the state FFs using synchronous reset
always @(posedge clock)
begin
if (reset == 1’b)
PRES_STSTE <= s0;
else
PRES_STATE <= NEXT_STSTE;
end
endmodule
66
Stimulus for the FSM Vendor Machine
module stimulus; // put 3 nickles
reg clock, reset #80 coin=1; #40 coin=0;
reg [1:0] coin; #80 coin=1; #40 coin=0;
wire newspaper; #80 coin=1; #40 coin=0;
vend vendY(coin, clcok, reset, // put 1 nickle and 1 dime
newspaper); #180 coin=1; #40 coin=0;
always #80 coint=2; #40 coin=0;
#20 clcok = ~clock; // put 2 dimes
#180 coin=2; #40 coin=0;
initial #80 coint=2; #40 coin=0;
begin // put 1 dime and 1 nickle
clock = 0; #180 coin=2; #40 coin=0;
coin = 0; #80 coint=1; #40 coint=0;
reset = 1;
#50 reset = 0; #80 $finish;
@(negedge clock); end
endmodule
67
Divide-by-3 counter using FSM
module divideby3FSM (input clk, input reset, output y);
reg [1:0] state, nextstate;
parameter S0 = 2’b00;
parameter S1 = 2’b01;
parameter S2 = 2’b10;
// state register
always @(posedge clk, posedge reset)
if (reset) state <= S0;
else state <= nextstate;
// next state logic
always @ (*)
case (state)
S0: nextstate = S1;
S1: nextstate = S2;
S2: nextstate = S0;
default: nextstate = S0;
endcase
// output logic
assign y = (state == S0);
endmodule 68
Clock Gating
69
Register Output
• Regular register
– waste dynamic power when accessing unused data
D Q
clk reset
nrst
• Waveforms
CLK
data_in 1111 2222 3333 4444
data_out 1111 2222 3333 4444
Green = Unnecessary data
Red = Valid data 70
Clock gating
• Normal waveforms
CLK
data_in 1111 2222 3333 4444
data_out 1111 2222 3333 4444
• Clock-gated waveforms
– Controlled by ENCLK
CLK
ENCLK
data_in 1111 2222 3333 4444
data_out 2222 71
clock gating
module dff(Q, D, clk); module dff(Q, D, clk);
input D, clk; input D, clk;
output Q; output Q;
reg Q; reg Q;
wire en;
wire gclk, en;
// clock signal is from the output of AND // data input from MUX
// glitch might cause extra clock edges always @(posedge clk)
assign gclk = clk & en; if (en) begin
always @(posedge gclk) Q <= D;
Q <= D; end
endmodule endmodule
gclk might have glitches !!! The clk portmight still have switching power!
cause unexpected latching not efficiently reduce dynamic power
72
Latch-based clock gating (Safe Design)
• Avoid glitches in clock signals
– Glitches incur unwanted signal edges
73
Clock gating methods
• Method 1 (unsafe gclk with possible glitches)
• Method2 (high switching activity of clk )
74
Synthesize lock gating with Synopsys
• use Synopsys synthesis script set_clock_gating_style
which automatically merge two methods into the safe clock-
gating design
en
clk
75
version 1 (AND gate at clock input)
(Manual Clock Gating)
module dff(Q, D, clk, set, rst);
input D, Clock, set, rst;
output Q;
reg gclk;
wire gclk, Enable;
// clock input is from the output of AND
assign gclk = Clock & Enable;
always @(posedge gclk)
if (rst)
Q <= 1’b0;
else if (set)
Q <= 1’b1;
else
Q <= D;
endmodule
76
version 2 (MUX at data input)
(Auto Clock Gating)
module dff(Q, D, clk, set, rst);
input D, CLK, set, rst;
output Q;
reg Q;
wire EN;
// data input from MUX controlled by en
always @(posedge CLK)
if (EN) begin
if (rst)
Q <= 1’b0;
else if (set)
Q <= 1’b1;
else
Q <= D;
end
endmodule
77
Synthesized Clock Gating
• When synthesis is done with proper commands
– Both design leads to safe clock gating circuit (with latch)
en
clk
78
