MASTER VERILOG: ACE YOUR

SKILLS WITH TOP 50 INTERVIEW

QUESTIONS!
module half_adder(
input A,
input B,
output Sum,
output Carry
);
assign Sum = A ^ B;
assign Carry = A & B;
endmodule

Prasanthi Chanda
1.Write a verilog code for 4:1 MUX using a
case statement.
module mux4to1 (
input [3:0] in,
input [1:0] sel,
output reg out
);
// Select one of the 4 inputs based on the 2 -bit select signal
always @(*) begin
case (sel )
2'b00: out = in[0]; // Select input 0
2'b01: out = in[1]; // Select input 1
2'b10: out = in[2]; // Select input 2
2'b11: out = in[3]; // Select input 3
default: out = 1'b0; // Default case for invalid select
endcase
end
endmodule

2. Implement a D Flip-Flop with asynchronous reset.

module d_flip_flop (input d, clk, reset, output reg q);
// On a rising edge of clk or reset, update the output
always @(posedge clk or posedge reset) begin
if (reset)
q <= 1'b0; // Asynchronous reset sets output to 0
else
q <= d; // Output follows input on clock edge
end
endmodule
3. Design a 4-bit ripple carry adder using full
adders
module full_adder(input a, b, cin, output sum, cout);
// Full adder for one-bit addition
assign {cout, sum} = a + b + cin; // Compute sum and carry-out
endmodule
module ripple_carry_adder(input [3:0] a, b, input cin, output [3:0] sum,
output cout);
// Ripple carry adder connects multiple full adders
wire c1, c2, c3; // Intermediate carry signals
full_adder fa0(a[0], b[0], cin, sum[0], c1); // First bit
full_adder fa1(a[1], b[1], c1, sum[1], c2); // Second bit
full_adder fa2(a[2], b[2], c2, sum[2], c3); // Third bit
full_adder fa3(a[3], b[3], c3, sum[3], cout); // Fourth bit
endmodule

4. Create an always-on blinking LED using a clock divider

module led_blink(input clk, output reg led);
reg [23:0] counter; // Counter to divide the clock
always @(posedge clk) begin
counter <= counter + 1; // Increment counter on each clock
if (counter == 24'd12000000) begin // Divide clock by 12M
led <= ~led; // Toggle LED
counter <= 0; // Reset counter
end
end
endmodule
5. Write a Verilog code to detect a 101
pattern in a serial input
module pattern_detector(input clk, rst, in, output reg match);
reg [2:0] state; // State register
always @(posedge clk or posedge rst) begin
if (rst)
state <= 3'b000; // Reset state
else begin
case (state)
3'b000: state <= (in == 1'b1) ? 3'b001 : 3'b000; // Start with 1
3'b001: state <= (in == 1'b0) ? 3'b010 : 3'b001; // Check for 0
3'b010: state <= (in == 1'b1) ? 3'b011 : 3'b000; // Check for 1
3'b011: state <= 3'b000; // Match found
default: state <= 3'b000; // Default state
endcase
end
match <= (state == 3'b010 && in == 1'b1); // Output high on match
end
endmodule

6. Implement a 3 -bit counter with an enable signal

module counter3bit(input clk, reset, enable, output reg [2:0] count);
// 3 -bit counter with enable and reset
always @(posedge clk or posedge reset) begin
if (reset)
count <= 3'b000; // Reset counter to 0
else if (enable)
count <= count + 1; // Increment counter if enabled
end
endmodule
7. Write a Verilog code for a 4 -bit Gray code
counter
module gray_counter(input clk, reset, output reg [3:0] gray);
reg [3:0] binary; // Binary counter
always @(posedge clk or posedge reset) begin
if (reset) begin
binary <= 4'b0000; // Reset binary counter
gray <= 4'b0000; // Reset Gray code
end else begin
binary <= binary + 1; // Increment binary counter
gray <= binary ^ (binary >> 1); // Convert to Gray code
end
end
endmodule

8. Design a priority encoder for 8 inputs

module priority_encoder(input [7:0] in, output reg [2:0] out, output reg valid);
// Priority encoder gives the highest priority input
always @(*) begin
casez (in)
8'b1???????: begin out = 3'b111; valid = 1; end // Highest priority
8'b01??????: begin out = 3'b110; valid = 1; end
8'b001?????: begin out = 3'b101; valid = 1; end
8'b0001????: begin out = 3'b100; valid = 1; end
8'b00001???: begin out = 3'b011; valid = 1; end
8'b000001??: begin out = 3'b010; valid = 1; end
8'b0000001?: begin out = 3'b001; valid = 1; end
8'b00000001: begin out = 3'b000; valid = 1; end
default: begin out = 3'b000; valid = 0; end // No valid input
endcase
end
endmodule
9. Implement an 8-bit shift register with
parallel load
module shift_register(input clk, reset, load, input [7:0] data_in, output reg
[7:0] q);
// Shift register with parallel load
always @(posedge clk or posedge reset) begin
if (reset)
q <= 8'b00000000; // Reset shift register
else if (load)
q <= data_in; // Load data
else
q <= {q[6:0], 1'b0}; // Shift left
end
endmodule

10. Write Verilog code for an 8 -bit even parity

generator
module parity_generator(input [7:0] data, output parity);
// Even parity: XOR all bits and invert
assign parity = ~^data; // Invert XOR of all bits for even parity
endmodule

11. Implement a 3 -bit up/down counter

module up_down_counter(input clk, reset, up, output reg [2:0] count);
always @(posedge clk or posedge reset) begin
if (reset)
count <= 3'b000; // Reset counter
else if (up)
count <= count + 1; // Increment if up is high
else
count <= count - 1; // Decrement if up is low
end
endmodule
12. Design a Mealy FSM to detect a 110
pattern in a serial input
module pattern_detector_mealy(input clk, reset, in, output reg match);
reg [1:0] state; // State register
always @(posedge clk or posedge reset) begin
if (reset)
state <= 2'b00; // Reset state
else begin
case (state)
2'b00: state <= (in) ? 2'b01 : 2'b00; // Look for first '1'
2'b01: state <= (in) ? 2'b01 : 2'b10; // Look for second '1'
2'b10: state <= (in) ? 2'b11 : 2'b00; // Look for '0'
2'b11: state <= (in) ? 2'b01 : 2'b00; // Match state
default: state <= 2'b00; // Default state
endcase
end
end
assign match = (state == 2'b10 && in); // Match condition for "110"
endmodule

13. Design an 8-bit barrel shifter

module barrel_shifter(input [7:0] data_in, input [2:0] shift, input dir, output
reg [7:0] data_out);
always @(*) begin
if (dir) // Right shift
data_out = data_in >> shift;
else // Left shift
data_out = data_in << shift;
end
endmodule
14. Write a Verilog module to generate a
PWM signal
module pwm_generator(
input clk, reset,
input [7:0] duty_cycle,
output reg pwm
);
reg [7:0] counter; // Counter for PWM
always @(posedge clk or posedge reset) begin
if (reset)
counter <= 8'b0; // Reset counter
else
counter <= counter + 1; // Increment counter
end
always @(posedge clk) begin
pwm <= (counter < duty_cycle); // Generate PWM based on duty cycle
end
endmodule

15. Implement a 16-bit Linear Feedback Shift Register

(LFSR)
module lfsr(input clk, reset, output reg [15:0] lfsr_out);
always @(posedge clk or posedge reset) begin
if (reset)
lfsr_out <= 16'h1; // Initial seed
else
lfsr_out <= {lfsr_out[14:0], lfsr_out[15] ^ lfsr_out[13]}; // Feedback logic
end
endmodule

16. Create a Verilog code for a signed multiplier

module signed_multiplier(input signed [7:0] a, b, output signed [15:0]
product);
assign product = a * b; // Multiply two signed numbers
endmodule
17. Write a Verilog code for a traffic light
controller using FSM
module traffic_light(
input clk, reset,
output reg [2:0] light // R=100, G=010, Y=001
);
reg [1:0] state; // State register
always @(posedge clk or posedge reset) begin
if (reset)
state <= 2'b00; // Reset state to red
else
state <= state + 1; // Move to next state
end
always @(*) begin
case (state)
2'b00: light = 3'b100; // Red
2'b01: light = 3'b010; // Green
2'b10: light = 3'b001; // Yellow
default: light = 3'b100; // Default to red
endcase
end
endmodule

18. Design a priority arbiter for 4 requests

module priority_arbiter(input [3:0] req, output reg [3:0] grant);
always @(*) begin
casez (req)
4'b1???: grant = 4'b1000; // Highest priority
4'b01??: grant = 4'b0100;
4'b001?: grant = 4'b0010;
4'b0001: grant = 4'b0001; // Lowest priority
default: grant = 4'b0000; // No request
endcase
end
endmodule
19. Implement a Verilog module for a binary
to BCD converter
module binary_to_bcd(input [7:0] binary, output reg [11:0] bcd);
integer i;
always @(*) begin
bcd = 12'b0; // Initialize BCD output
for (i = 7; i >= 0; i = i - 1) begin
bcd = {bcd[10:0], binary[i]}; // Shift in binary bit
if (bcd[3:0] > 4) bcd[3:0] = bcd[3:0] + 3; // Add 3 if > 4
if (bcd[7:4] > 4) bcd[7:4] = bcd[7:4] + 3;
if (bcd[11:8] > 4) bcd[11:8] = bcd[11:8] + 3;
end
end
endmodule

20. Write a Verilog code for a dual-port RAM.

module dual_port_ram(
input clk, we_a, we_b,
input [3:0] addr_a, addr_b,
input [7:0] data_in_a, data_in_b,
output reg [7:0] data_out_a, data_out_b
);
reg [7:0] ram [15:0]; // 16x8 RAM
always @(posedge clk) begin
if (we_a)
ram[addr_a] <= data_in_a; // Write to port A
else
data_out_a <= ram[addr_a]; // Read from port A
if (we_b)
ram[addr_b] <= data_in_b; // Write to port B
else
data_out_b <= ram[addr_b]; // Read from port B
end
endmodule
21. Implement a pipelined 4-stage RISC
processor
module risc_processor(input clk, reset, input [31:0] instruction, output reg
[31:0] result);
reg [31:0] IF, ID, EX, MEM;
always @(posedge clk or posedge reset) begin
if (reset) begin
IF <= 32'b0; ID <= 32'b0; EX <= 32'b0; MEM <= 32'b0; result <= 32'b0;
end else begin
IF <= instruction; // Fetch stage
ID <= IF; // Decode stage
EX <= ID + 1; // Execute stage (example: add 1)
MEM <= EX; // Memory stage
result <= MEM; // Write-back stage
end
end
endmodule
22. Implement 4x4 Matrix Multiplication
module matrix_mult(
input clk, reset,
input [15:0] A [3:0], B [3:0],
output reg [31:0] C [3:0][3:0]
);
integer i, j, k;
always @(posedge clk or posedge reset) begin
if (reset)
for (i = 0; i < 4; i++)
for (j = 0; j < 4; j++)
C[i][j] <= 32'b0; // Reset result
else
for (i = 0; i < 4; i++)
for (j = 0; j < 4; j++) begin
C[i][j] = 0;
for (k = 0; k < 4; k++)
C[i][j] = C[i][j] + A[i][k] * B[k][j]; // Multiply and accumulate
end
end
endmodule
23. Implement a parameterized FIFO with full
and empty flags
module fifo #(parameter WIDTH = 8, DEPTH = 16)(
input clk, reset, wr_en, rd_en, // Clock, reset, write enable, and
read enable
input [WIDTH-1:0] data_in, // Input data
output reg [WIDTH-1:0] data_out, // Output data
output reg full, empty // Flags for full and empty states
);
reg [WIDTH-1:0] mem [DEPTH-1:0]; // Memory array for FIFO
reg [4:0] rd_ptr, wr_ptr, count; // Read pointer, write pointer, and
element count
always @(posedge clk or posedge reset) begin
if (reset) begin
// Reset pointers, counters, and flags
rd_ptr <= 0; wr_ptr <= 0; count <= 0;
full <= 0; empty <= 1;
end else begin
// Write operation
if (wr_en && !full) begin
mem[wr_ptr] <= data_in;
wr_ptr <= wr_ptr + 1;
count <= count + 1;
empty <= 0;
if (count == DEPTH - 1) full <= 1;
end
// Read operation
if (rd_en && !empty) begin
data_out <= mem[rd_ptr];
rd_ptr <= rd_ptr + 1;
count <= count - 1;
full <= 0;
if (count == 1) empty <= 1;
end
end
end
endmodule
24. Design an AXI4 -Lite Slave Interface.
module axi4lite_slave(
input clk, reset,
input [31:0] awaddr, wdata, // Address and data for write
input awvalid, wvalid, // Valid signals for address and data
output reg awready, wready, // Ready signals for address and
data
output reg [31:0] rdata // Read data
);
reg [31:0] mem [255:0]; // Memory for storing data
always @(posedge clk or posedge reset) begin
if (reset) begin
// Reset ready signals and memory
awready <= 0; wready <= 0; rdata <= 0;
end else begin
if (awvalid && !awready) begin
awready <= 1; // Accept address
mem[awaddr[7:0]] <= wdata; // Write data to memory
end
if (wvalid && awready) begin
wready <= 1; // Accept data
end
rdata <= mem[awaddr[7:0]]; // Read data from memory
end
end
endmodule
25. Implement a DDR3 Memory Controller
module ddr3_controller(
input clk, reset,
input [31:0] addr, data_in, // Address and input data
input read, write, // Read and write signals
output reg [31:0] data_out // Data output
);
reg [31:0] mem [1023:0]; // DDR3 memory array
always @(posedge clk or posedge reset) begin
if (reset)
data_out <= 32'b0; // Reset data output
else begin
if (read)
data_out <= mem[addr]; // Perform read operation
else if (write)
mem[addr] <= data_in; // Perform write operation
end
end
endmodule

26. Design a High-Speed Serializer for a 64-bit Parallel

Input
module priority_encoder_64(
input [63:0] in,
output reg [5:0] out
);
always @(*) begin
out = 6'b0;
for (integer i = 63; i >= 0; i = i - 1) begin
if (in[i]) begin
out = i; // Capture highest priority
break;
end
end
end
endmodule
27. Implement an Interrupt Controller with
Priority Encoding
module interrupt_controller(
input clk, reset,
input [7:0] interrupts, // 8 interrupt requests
output reg [2:0] highest_priority, // Encoded priority
output reg valid // Valid interrupt flag
);
integer i;
always @(posedge clk or posedge reset) begin
if (reset) begin
highest_priority <= 3'b0;
valid <= 0; // Reset priority and valid flag
end else begin
valid <= 0; // Clear valid flag initially
for (i = 7; i >= 0; i = i - 1) begin
if (interrupts[i]) begin
highest_priority <= i[2:0]; // Assign highest active interrupt
valid <= 1; // Set valid flag
break;
end
end
end
end
endmodule
28. Design a Configurable ALU with 4
Operations: ADD, SUB, AND, OR.
module alu(
input [31:0] A, B, // Operands
input [1:0] op_code, // 00=ADD, 01=SUB, 10=AND, 11=OR
output reg [31:0] result
);
always @(*) begin
case (op_code)
2'b00: result = A + B; // Addition
2'b01: result = A - B; // Subtraction
2'b10: result = A & B; // Bitwise AND
2'b11: result = A | B; // Bitwise OR
default: result = 32'b0; // Default to zero
endcase
end
endmodule

29. Create a 16-bit barrel shifter that performs logical

left, right, and circular shifts based on a control signal
module barrel_shifter(
input [15:0] data_in,
input [3:0] shift_amount,
input [1:0] shift_type, // 00: Logical Left, 01: Logical Right, 10: Circular Left
output reg [15:0] data_out
);
always @(*) begin
case (shift_type)
2'b00: data_out = data_in << shift_amount; // Logical left
2'b01: data_out = data_in >> shift_amount; // Logical right
2'b10: data_out = (data_in << shift_amount) | (data_in >> (16 -
shift_amount)); // Circular left
default: data_out = 16'b0;
endcase
end
endmodule
30. Implement a Dual-Port RAM with
Independent Read/Write Ports
module dual_port_ram(
input clk,
input [3:0] addr_a, addr_b,
input [7:0] data_in_a, data_in_b,
input we_a, we_b,
output reg [7:0] data_out_a, data_out_b
);
reg [7:0] ram [15:0]; // 16x8 RAM
always @(posedge clk) begin
if (we_a)
ram[addr_a] <= data_in_a; // Write to Port A
else
data_out_a <= ram[addr_a]; // Read from Port A
if (we_b)
ram[addr_b] <= data_in_b; // Write to Port B
else
data_out_b <= ram[addr_b]; // Read from Port B
end
endmodule

31. Write a Verilog code for a 4-bit binary up/down

counter with enable and reset
module up_down_counter(
input clk, reset, enable, up,
output reg [3:0] count
);
always @(posedge clk or posedge reset) begin
if (reset)
count <= 4'b0000;
else if (enable)
count <= up ? count + 1 : count - 1;
end
endmodule
32. Create a Traffic Light Controller for a 4
way Intersection.
module traffic_light_controller(
input clk, reset,
output reg [2:0] NS_light, EW_light // 3-bit outputs: 001=Green, 010=Yellow,
100=Red
);
reg [1:0] state; // FSM states: 00=NS Green, 01=NS Yellow, 10=EW Green,
11=EW Yellow
integer counter;
always @(posedge clk or posedge reset) begin
if (reset) begin
state <= 2'b00; // Reset to initial state
counter <= 0;
end else begin
counter <= counter + 1;
case (state)
2'b00: if (counter == 10) begin state <= 2'b01; counter <= 0; end
2'b01: if (counter == 3) begin state <= 2'b10; counter <= 0; end
2'b10: if (counter == 10) begin state <= 2'b11; counter <= 0; end
2'b11: if (counter == 3) begin state <= 2'b00; counter <= 0; end
endcase
end
end
always @(*) begin
case (state)
2'b00: begin NS_light = 3'b001; EW_light = 3'b100; end // NS Green,
EW Red
2'b01: begin NS_light = 3'b010; EW_light = 3'b100; end // NS Yellow,
EW Red
2'b10: begin NS_light = 3'b100; EW_light = 3'b001; end // NS Red, EW
Green
2'b11: begin NS_light = 3'b100; EW_light = 3'b010; end // NS Red, EW
Yellow
endcase
end
endmodule
33. Design a CRC (Cyclic Redundancy Check)
Generator for Error Detection.
module crc_generator(
input clk, reset,
input [7:0] data_in, // Input data
output reg [7:0] crc_out // CRC output
);
reg [7:0] crc; // Intermediate CRC register
always @(posedge clk or posedge reset) begin
if (reset)
crc <= 8'b0; // Reset CRC
else begin
crc[7] <= crc[6] ^ data_in[7]; // XOR MSB
crc[6] <= crc[5];
crc[5] <= crc[4];
crc[4] <= crc[3];
crc[3] <= crc[2] ^ data_in[7];
crc[2] <= crc[1];
crc[1] <= crc[0];
crc[0] <= crc[7] ^ crc[3];
end
end
assign crc_out = crc; // Output CRC
endmodule

34. Design a Verilog module for a synchronous FIFO

queue with parameterized depth.
module d_flip_flop(
input clk, rst_n, en, d,
output reg q
);
always @(posedge clk or negedge rst_n) begin
if (!rst_n)
q <= 0;
else if (en)
q <= d;
end
endmodule
35. Design a Pipelined Multiplier with 4 Stages
module pipelined_multiplier(
input clk, reset,
input [7:0] A, B, // Inputs
output reg [15:0] result // Final result
);
reg [15:0] stage1, stage2, stage3;
always @(posedge clk or posedge reset) begin
if (reset) begin
stage1 <= 0; stage2 <= 0; stage3 <= 0; result <= 0; // Reset stages
end else begin
stage1 <= A * B[3:0]; // Stage 1: Partial product
stage2 <= stage1 + (A * B[7:4] << 4); // Stage 2: Add shifted partials
stage3 <= stage2; // Stage 3: Carry propagate
result <= stage3; // Final result
end
end
endmodule

36. Write a Verilog code to implement an LFSR based

pseudo-random number generator
module lfsr(
input clk, rst_n,
output reg [15:0] random_number
);
reg [15:0] lfsr;
always @(posedge clk or negedge rst_n) begin
if (!rst_n)
lfsr <= 16'hACE1; // Initial seed
else begin
lfsr[15:1] <= lfsr[14:0]; // Shift left
lfsr[0] <= lfsr[15] ^ lfsr[13] ^ lfsr[12] ^ lfsr[10]; // Feedback
random_number <= lfsr;
end
end
endmodule
37. Create a Generic FIFO with Configurable
Depth and Data Width
module generic_fifo #(
parameter WIDTH = 8, // Data width
parameter DEPTH = 16 // Depth
)(
input clk, reset,
input write_enable, read_enable,
input [WIDTH-1:0] data_in,
output reg [WIDTH-1:0] data_out,
output reg full, empty
);
reg [WIDTH-1:0] fifo [DEPTH-1:0];
reg [4:0] read_ptr, write_ptr; // 5-bit for DEPTH=16
always @(posedge clk or posedge reset) begin
if (reset) begin
read_ptr <= 0; write_ptr <= 0; full <= 0; empty <= 1;
end else begin
if (write_enable && !full) begin
fifo[write_ptr] <= data_in; // Write operation
write_ptr <= write_ptr + 1;
end
if (read_enable && !empty) begin
data_out <= fifo[read_ptr]; // Read operation
read_ptr <= read_ptr + 1;
end
full <= (write_ptr + 1 == read_ptr);
empty <= (read_ptr == write_ptr);
end
end
endmodule
38. Implement a 32-bit Floating-Point ALU
Supporting Addition, Subtraction, and Multiplication
module floating_point_alu(
input clk, reset,
input [31:0] A, B, // IEEE 754 inputs
input [1:0] op_code, // 00=ADD, 01=SUB, 10=MUL
output reg [31:0] result
);
reg [31:0] temp_result;

always @(posedge clk or posedge reset) begin

if (reset)
result <= 32'b0; // Reset result
else begin
case (op_code)
2'b00: temp_result = A + B; // Floating-point addition
2'b01: temp_result = A - B; // Floating-point subtraction
2'b10: temp_result = A * B; // Floating-point multiplication
default: temp_result = 32'b0;
endcase
result <= temp_result;
end
end
endmodule
39. Design a High-Speed Serializer for a 64-bit
Parallel Input
module high_speed_serializer(
input clk, reset, load,
input [63:0] parallel_in,
output reg serial_out
);
reg [63:0] shift_reg;
reg [5:0] bit_counter;

always @(posedge clk or posedge reset) begin

if (reset) begin
shift_reg <= 0; bit_counter <= 0; serial_out <= 0; // Reset
end else if (load) begin
shift_reg <= parallel_in; // Load parallel data
bit_counter <= 0;
end else begin
serial_out <= shift_reg[63]; // Shift out data
shift_reg <= {shift_reg[62:0], 1'b0};
bit_counter <= bit_counter + 1;
end
end
endmodule
40. Implement an AXI4 Lite Protocol Slave
Interface
module axi4lite_slave(
input clk, reset,
input [31:0] awaddr, wdata, araddr,
input awvalid, wvalid, arvalid,
output reg awready, wready, arready,
output reg [31:0] rdata
);
reg [31:0] memory [255:0]; // 256x32 memory

always @(posedge clk or posedge reset) begin

if (reset) begin
awready <= 0; wready <= 0; arready <= 0; rdata <= 0; // Reset
signals
end else begin
if (awvalid && !awready) begin
awready <= 1; // Accept address
memory[awaddr[7:0]] <= wdata; // Write to memory
end
if (arvalid && !arready) begin
arready <= 1; // Accept read address
rdata <= memory[araddr[7:0]]; // Provide data
end
end
end
endmodule
41. Design a dual-port RAM with separate
read and write ports and asynchronous operations.
module dual_port_ram(
input clk,
input [7:0] write_address, read_address,
input [15:0] write_data,
input write_enable,
output reg [15:0] read_data
);
reg [15:0] ram [255:0]; // 256x16 RAM
always @(posedge clk) begin
if (write_enable)
ram[write_address] <= write_data; // Write operation
end
always @(*) begin
read_data = ram[read_address]; // Asynchronous read
end
endmodule

42. Create a clock divider that divides the input clock

frequency dynamically based on an input division factor
module clock_divider(input clk, reset, input [3:0] division_factor, output reg
clk_out );
reg [3:0] counter;
always @(posedge clk or posedge reset) begin
if (reset) begin
counter <= 0; clk_out <= 0;
end else begin
counter <= counter + 1;
if (counter >= (division_factor - 1)) begin
counter <= 0;
clk_out <= ~clk_out; // Toggle output clock
end
end
end
endmodule
43. Implement a Verilog code for a priority
encoder with enable.
module priority_encoder(
input [7:0] in,
input enable,
output reg [2:0] out,
output reg valid
);
always @(*) begin
if (enable) begin
valid = 1;
casez (in)
8'b1???????: out = 3'd7;
8'b01??????: out = 3'd6;
8'b001?????: out = 3'd5;
8'b0001????: out = 3'd4;
8'b00001???: out = 3'd3;
8'b000001??: out = 3'd2;
8'b0000001?: out = 3'd1;
default: out = 3'd0;
endcase
end else begin
valid = 0;
out = 3'd0;
end
end
endmodule
44. Create a Verilog module that implements
a digital lock using a finite state machine
module digital_lock(
input clk, rst_n,
input [3:0] code_input,
output reg locked, unlocked
);
typedef enum reg [1:0] {LOCKED, UNLOCKED} state_t;
state_t state, next_state;
always @(posedge clk or negedge rst_n) begin
if (!rst_n)
state <= LOCKED;
else
state <= next_state;
end
always @(*) begin
case (state)
LOCKED: begin
unlocked = 0; locked = 1;
if (code_input == 4'b1010)
next_state = UNLOCKED;
else
next_state = LOCKED;
end
UNLOCKED: begin
unlocked = 1; locked = 0;
if (code_input != 4'b1010)
next_state = LOCKED;
else
next_state = UNLOCKED;
end
endcase
end
endmodule
45. Implement a Verilog module for a 4-bit
Gray Code Counter.
module gray_code_counter(
input clk, rst_n,
output reg [3:0] gray_code,
output reg cycle_complete
);
reg [3:0] binary_count;
function [3:0] bin_to_gray(input [3:0] bin);
begin
bin_to_gray = {bin[3], bin[3] ^ bin[2], bin[2] ^ bin[1], bin[1] ^ bin[0]};
end
endfunction
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
binary_count <= 4'b0000;
gray_code <= 4'b0000;
cycle_complete <= 0;
end else begin
if (binary_count == 4'b1111) begin
binary_count <= 4'b0000;
cycle_complete <= 1;
end else begin
binary_count <= binary_count + 1;
cycle_complete <= 0;
end
gray_code <= bin_to_gray(binary_count); // Convert to Gray code
end
end
endmodule
46. Design a MUX that cycles through 8
input and outputs each channel sequentially.
module time_division_multiplexer(
input clk, reset,
input [7:0] data_in [7:0], // 8 channels of 8-bit data
output reg [7:0] data_out
);
reg [2:0] current_channel;
always @(posedge clk or posedge reset) begin
if (reset) begin
current_channel <= 0;
data_out <= 8'b0;
end else begin
data_out <= data_in[current_channel]; // Output current channel
current_channel <= current_channel + 1; // Cycle to next channel
end
end
endmodule
47. Implement a Verilog module to compute the Fibonacci
sequence iteratively
module fibonacci(
input clk, rst_n,
output reg [31:0] fib_out
);
reg [31:0] fib_1, fib_2;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
fib_1 <= 32'd0;
fib_2 <= 32'd1;
fib_out <= fib_1;
end else begin
fib_out <= fib_2;
{fib_2, fib_1} <= {fib_2 + fib_1, fib_2}; // Update Fibonacci numbers
end
end
endmodule
48. Implement a Verilog module that detects
and counts the no. of rising edges in a signal.
module edge_counter(
input clk, rst_n, signal_in,
output reg [7:0] edge_count
);
reg signal_prev;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
edge_count <= 8'b0;
signal_prev <= 0;
end else begin
if (signal_in && !signal_prev)
edge_count <= edge_count + 1; // Increment on rising edge
signal_prev <= signal_in;
end
end
endmodule

49. Design a Verilog module to implement an N-bit

multiplier using the array multiplication method.
module array_multiplier #(parameter N = 4)(
input [N-1:0] A, B,
output reg [(2*N)-1:0] product
);
reg [(2*N)-1:0] partials [(N-1):0];
integer i, j;
always @(*) begin
for (i = 0; i < N; i = i + 1)
for (j = 0; j < N; j = j + 1)
partials[i][i + j] = A[i] & B[j]; // Partial products
product = partials[0];
for (i = 1; i < N; i = i + 1)
product = product + partials[i]; // Accumulate partial products
end
endmodule
50. Write a Verilog code to implement a
configurable PWM generator with adjustable
duty cycle.
module pwm_generator(
input clk, rst_n,
input [7:0] duty_cycle,
output reg pwm_out
);
reg [7:0] counter;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
counter <= 8'b0;
pwm_out <= 0;
end else begin
counter <= counter + 1;
if (counter < duty_cycle)
pwm_out <= 1;
else
pwm_out <= 0;
if (counter == 8'd255)
counter <= 8'b0; // Reset counter after max value
end
end
endmodule