Capacitor Voltage Balancing with Reduction of Arm Current and

THD Control of MMC: A Modified Triangular Injection Approach

M. A. Munjer1*, M. R. I. Sheikh2, Venkatesh Boddapati3, M. A. Alim4
1
Department of EEE, Begum Rokeya University, Rangpur-5404, Bangladesh
2
Department of EEE, Rajshahi University of Engineering & Technology, Rajshai-6204, Bangladesh
3
Department of EEE, BMS College of Engineering, Bengaluru, Karnataka, India
4
Department of EEE, University of Rajshahi, Rajshai-6204, Bangladesh
*
corresponding authors: abulmunjer@yahoo.com

Abstract – For high power applications, in recent time, Modular Multilevel Converter (MMC) has
become popular because it consists of number of DC sources. Stair voltage output waveform of this
type of converter can be controlled by different modulation techniques. Harmonic profile of a
converter with a modulation scheme much depends on the carrier frequency used in it. On the other
hand, with the importance of lower Total Harmonic Distortion (THD), the arm current control is
also the necessity to drive an MMC in smooth operation. Moreover, imbalance of the Sub-Module
(SM) capacitor voltages affects the arm current as well as the life time of the capacitors. In this way
the overall performance of the converter could be affected. As a result, several efforts of research
in this area focused on to minimize the THD, balance the capacitor voltage of Sub-module (SM) and
to control the arm current of the converter. This paper proposed a modified triangular injection
modulation structure for MMC converters to maintain minimum harmonic profile as well as to
achieve lower arm current and capacitor voltage balancing of SM within a single algorithm
structure. Several well-known modulation methods have been compared with the proposed method
so that percentage of THD and the arm current can be identified as minimum and SM’s capacitor
voltages could be compared.

Keywords: MMC, THD, arm current, SM voltage

Article History
Received 17 July 2020
Received in revised form 6 October 2020
Accepted 7 October 2020

I. Introduction is the redundancy of the output, which in turn increases

the complexity [5]. There are also some level-shifted or
Voltage Source Inverter (VSI) topologies have been sub-harmonic deposition modulation which shows good
accepted for its high operating voltage as well as lower THD profile at higher number of output level such as the
losses, in many power converter applications. Modular Phase Deposition (PD) [6]. A modified PD method called
Multilevel Converter (MMC) is one type of VSI where triangular injection has been applied to both MMC and
several modulation techniques have been discussed in cascaded bridge converter to achieve lower THD profile
literature. Depending on the switching frequency in a by M.A. Munjer et. al [6]. The work found a lower THD
modulation, a method could be high frequency modulation profile, but the arm current investigation was absent. In
or low frequency modulation technique. Selective this paper an algorithm has been proposed for MMC,
Harmonic Elimination PWM (SHE-PWM) is a low which is based on triangular injection method. This single
frequency switching method, which depends on look up algorithm structure has confirmed minimum harmonic
tables [1]. However, among different high frequency profile as well as lower arm current and a balanced
PWM methods phase-shifted or carrier deposition are the capacitor voltage of the Sub-module (SM). Several well-
most common for easy control of operation. The known modulation methods have been compared with the
sinusoidal pulse width modulation (SPWM), Bus proposed method.
Clamping PWM (BCPWM), Third Harmonic injected
Pulse Width Modulation (THPWM) techniques are also
working well in multilevel converters [2]- [3]. The II. Structure of MMC
Circular Space Vector Modulation (CSVM) is considered
as a standard for pulse width modulation techniques [4]. The three-phase configuration of Modular Multilevel
Converter (MMC) has been shown in Fig. 1 where each
However, the main drawback of CSVM based modulation

ISSN: 2600-7495 eISSN: 2600-9633 IJEEAS Vol. 3, No. 2, October 2020

International Journal of Electrical Engineering and Applied Sciences

SM is composed of only two switches in cascade and a 𝑅𝑎𝑟𝑚 𝑛𝑝 𝑛𝑛

capacitor paralleled to the switches. Depending on the − − −
𝐼 𝐿𝑎𝑟𝑚 2𝐿 𝑎𝑟𝑚 2𝐿𝑎𝑟𝑚 𝐼𝑐𝑖𝑟𝑐
switching states of an SM for MMC, an arm of any leg can 𝑑 𝑐𝑖𝑟𝑐 𝑛𝑝
be considered as a voltage source that can be regulated. [∑𝑉𝑐𝑝 ] = 0 0 [∑𝑉𝑐𝑝 ]
𝑑𝑡 𝐶𝑎𝑟𝑚
The number of SM inserted to the current path can be ∑𝑉𝑐𝑛 𝑛𝑛 ∑𝑉𝑐𝑛
considered as the number of sources having voltage Vc. If 0 0
[ 𝐶𝑎𝑟𝑚 ]
insertion index n(t) which sets the number of sub-modules 𝑉𝑑𝑐
inserted to the current path, N sub-modules in an arm
2𝐿𝑎𝑟𝑚
containing each a capacitance C makes total capacitance 𝑛𝑝
Carm, then the applicable capacitance to the inserted SM + 𝐼 (5)
becomes 𝐶𝑎𝑟𝑚 = 𝑛(𝑡) ∗ 𝐶𝑚 . The upper and lower arm 2𝐶𝑎𝑟𝑚 𝑙
𝑛𝑛
currents can be expressed as, 𝐼
[2𝐶𝑎𝑟𝑚 𝑙 ]
𝐶𝑎𝑟𝑚 𝑑∑(𝑉𝑐𝑝 ) 𝐼𝑙
𝐼𝑝 = × = 𝐼𝑐𝑖𝑟𝑐 + (1)
𝑛𝑝 𝑑𝑡 2 III. Methodology
𝐶𝑎𝑟𝑚 𝑑∑(𝑉𝑐𝑛 ) 𝐼𝑙
𝐼𝑛 = × = 𝐼𝑐𝑖𝑟𝑐 − (2)
𝑛𝑛 𝑑𝑡 2 A. Modulation Method
𝑑𝐼𝑐𝑖𝑟𝑐 𝑉𝑑𝑐 𝑅𝑎𝑟𝑚
= − × 𝐼𝑐𝑖𝑟𝑐 − ¥(𝑉𝐶 ) (3) Nowadays, to achieve minimum THD several
𝑑𝑡 2𝐿𝑎𝑟𝑚 𝐿𝑎𝑟𝑚 modulation techniques are available in literature such as
𝑛𝑝 𝑛𝑛
¥(𝑉𝐶 ) = (∑𝑉𝑐𝑝 ) + (∑𝑉𝑐𝑛 ) (4) CSVPWM, SPWM, THPWM, SDBCPWM, TDBCPWM,
2𝐿𝑎𝑟𝑚 2𝐿𝑎𝑟𝑚 and TRPWM [7]-[9]. The following techniques differ
from each other by their reference signals. Figure 3 shows
the reference signals of the SPWM, CSVPWM,
SDBCPWM, and THPWM modulation approach.

(a) SPWM (b) CSVPWM

1 1

Reference signal (p.u)

Reference signal (p.u)

0.5 0.5

0 0

-0.5 -0.5

-1 -1
0 10 20 0 10 20
Time (ms) Time (ms)
(c) SDBCPWM (d) THPWM
1 1
Reference signal (p.u)

Reference signal (p.u)

0.5 0.5

0 0
Fig. 1. Circuit diagram of three phase MMC. -0.5 -0.5

where 𝐼𝑐𝑖𝑟𝑐 is loop current that circulates between each -1 -1

0 10 20 0 10 20
phase leg and the dc-link, np and nn are upper and lower Time (ms) Time (ms)
arm insertion index respectively. Under balanced load Fig.2. Reference signals for different modulation schemes.
conditions, the dc-link current 𝐼𝑑𝑐 is shared equally
between the three phase legs. 𝑉𝑐𝑝 and 𝑉𝑐𝑛 are individual The reference signals of the triangular injection
SM capacitor voltages of positive and negative arm. modulation scheme can be represented as in Fig. 3(a). In
Equation (3) can be calculated from (1) and (2). Finally, a this method, a triangle signal represented by δ(ξ⍵t) is
continuous model of a phase leg of MMC is obtained as in added with the sine wave containing the desired frequency
(5) by using (1), (2) and (3) which best describes the of the converter output but the reference and carriers
operation principal of MMC. should be same when they will be added up. For having
(n+1) level of output voltage there should have n number
of carriers shown in Fig. 3(b). The frequency of the
triangular signal for the current scheme maintains a
multiple factor ξ concerning the frequency of the reference
signal, which can be noticed from equations (6) to (8). The
relative comparison between the reference and carriers

ISSN: 2600-7495 eISSN: 2600-9633 IJEEAS Vol. 3, No. 2, October 2020

 Capacitor Voltage Balancing with Reduction of Arm Current and THD Control of MMC: A Modified Triangular
Injection Approach

generates pulses which denotes the insertion index 𝑛𝑎𝑏𝑐

for the switching devices of the converter as represented
in (9) [6],[10].

Ma = Am sin ⍵t + am δ(ξ⍵t) (6)

Mb = Am sin (⍵t - 120°) + am δ(ξ⍵t) (7)

Mc=Am sin (⍵t + 120°) + am δ(ξ⍵t) (8)

𝑛𝑎𝑏𝑐 = ℛ{Mabc,ℓk δ(ξ⍵t)}k=1,,n (9)

Fig. 4. Determination of Nc in Sort & Slect (S&S) Method.

Moreover, a method called carrier rotation is used for

the capacitor voltage balancing where sub-module
capacitor voltage measurement and arm current polarity
are not required [11]. This method is governed with the
common reference signal and individually assigned carrier
signal for each SM. In order to equate insert or bypass
times of different submodules, the participation of carriers
(a) should be changed periodically. By this way, insert/bypass
durations of sub-modules are equated to each of them.
Therefore, a balance submodule capacitors voltage could
be achieved. In Fig. 5 rotated carriers for N=4 is
illustrated. As seen from figure, each carrier has been
shifted to higher magnitude for 20ms. When a particular
carrier has reached to a maximum value (0.5) of the carrier
band, it is shifted to minimum value (-0.5) of the band.

(b)

Fig. 3. (a) Reference signals (b) carrier with reference signal of

the proposed modulation scheme.

B. Voltage balancing methods

In literature, there are number of methods to maintain
equal amount of voltage for the SM capacitor. In this work
two methods known as Sort & Selection method (S&S)
and carrier rotation method are analyzed to be
incorporated with the triangular injection modulation Fig. 5. Carrier Rotation for Voltage Balancing.
approach.
According to S&S method, capacitor voltages of all the
sub-modules and polarity of the arm current are measured. C. Proposed Balancing Algorithm
All the capacitor voltages in an arm are measured and
sorted from the highest to the lowest. The number of For the conventional Sine PWM (SPWM) method, the
“required” SM (Nc) to be connected with the upper and number of carriers required to be compared with the
lower arm’s current path should be determined. Fig. 4 reference signal is equal to the number of SM used in
shows the procedure to determine Nc. At the time of either positive or negative arm of a phase of the converter.
comparing reference and carrier, if the reference is greater As a result, the pulses for the switching devices are
than a carrier, one SM for this carrier should be inserted to generated in such a way that conduction period of SM
the current path, corresponding to increment of Nc by one. decreases with the distance of the neutral point to SM
On the other hand, if the reference is lower, one SM should connected in an arm of a phase of the converter. In this
be bypassed, without changing the value of Nc. All the N way an unbalanced charging voltages will be carried out
carriers are compared with the reference and Nc is by the capacitor connected with the SM. The most upper
determined [10]. capacitor in an arm is being charged in lower voltage
where the capacitor at nearest to the neutral get charged at

ISSN: 2600-7495 eISSN: 2600-9633 IJEEAS Vol. 3, No. 2, October 2020

International Journal of Electrical Engineering and Applied Sciences

higher voltage level. This causes a circulating current

which causes a variation in the life time of SMs.
In this work an improved level-shifted carrier rotation
pulse-width modulation scheme has been proposed to
balance the voltage of the floating capacitor. This method
also maintains a lower THD by avoiding some major
disadvantages found in the conventional voltage balancing
methods, such as the use of extra switching action,
interference with output voltage and periodic carrier
rotation which lead to high performance of the converter.
To do so, triangular injection method has been
incorporated.
In the present work, the level of the carriers is
maintained according to the magnitude of the capacitor
voltage of the corresponding SM. Fig. 6 shows the flow
chart of the proposed capacitor voltage balancing Fig. 7. Carrier rotation according to the rank of SMs capacitor voltage.
algorithm. At the very beginning, the algorithm verifies
that all SMs capacitors voltages are same or not. If all the
voltages are same, the corresponding carrier signal will be
arranged in the same level. The magnitude of voltage will
determine at which level the carrier will be arranged. On
the other hand, if the values of voltage are not equal then
they are sorted in large to small order. The ranking of
largest voltage would be first, next highest voltage’s rank
will second and sequentially third up to k. Now the
corresponding carriers of voltages that ranked from 1 to
k/2 will be arranged at the lower half (0 to -11) of the
carrier rotation window as shown in Fig. 7 and rest carriers
would be arranged at the upper half (0 to 1) of the window.

Fig. 8. Capacitor voltage balancing module in MATLAB Simulink.

For both positive and negative arm of the converter, two

of the modules will be needed. Taking the voltages, it sorts
the values of the voltage according to descending order
and rank them from 1 to N as N number of carriers is
required for number of N SM.
The ranked-1 (one) SM’s capacitor voltage implies that
corresponding carrier stands on the lower level of the
carrier rotation pane. Similarly, the higher ranked SM’s
capacitor voltage implies that corresponding carrier stands
on the lower level of the carrier rotation pane. However,
the other ranked voltage’s corresponding carrier rotates to
higher or lower level of the carrier pane depending on the
voltage. The above Fig. 8 shows the carrier rotation pane
of upper arms for 5-level MMC.
It can be seen that, as corresponding capacitor voltages
of SM1 and SM4 are higher and lower ranked accordingly,
they interchanged their level but carriers which relative to
SM2 and SM3 stepped down and up instantly. For an
example, as in case of SM3’s capacitor voltage, at first
instant its voltage rank was k=2. In order to have a uniform
Fig. 6. Flow chart of the proposed balancing algorithm. charging of the capacitors, corresponding carrier should
be stepped down on the carrier pane. Capacitor voltage
According to the proposed algorithm a voltage was lower compared to any other capacitor voltage at
balancing module for an arm of MMC in MATLAB specific arm. For that, carrier signal of SM3 was placed to
Simulink environment is shown in Fig. 8. The input rank=4. After that its voltage starts to rise and at instant its
terminals of this module, vc1, vc2, vc3, vc4 corresponds to the voltage goes to more than SM4 but less than the other. As
capacitor voltage input terminal of a specific arm. a result, corresponding carrier get a rank=2.

ISSN: 2600-7495 eISSN: 2600-9633 IJEEAS Vol. 3, No. 2, October 2020

 Capacitor Voltage Balancing with Reduction of Arm Current and THD Control of MMC: A Modified Triangular
Injection Approach

IV. Simulation and Results be seen that the THD of phase voltage and line voltage are
20.55% and 17.67% respectively.
Circuit configuration of the simulated system in
MATLAB Simulink is shown in Table I. The dc-link is set
to be 800 V and the ac side line-to-line voltage of the
system is set at 325 Vrms 50Hz. Rated power of the
converter is 5 kVA with 6.25 Arms output current. Base
impedance of the system is calculated in equation (10).
2
𝑉𝑏𝑎𝑠𝑒 (325)2
𝑍𝑏𝑎𝑠𝑒 = = = 21.125𝛺 (10)
𝑆𝑏𝑎𝑠𝑒 5000

TABLE I
SIMULATED CIRCUIT PARAMETERS (WITHOUT LOAD)
Meaning Value
Dc-link voltage 800V
Fundamental frequency 50Hz
Carrier frequency 2.5kHz
Number of submodules per arm 4
Arm inductance 50mH
Arm resistance 400Ω
Sub module capacitance 500μF
Modulation index 1

The sub-module capacitors selection is based on

maximum total energy stored in the converter and
converter rated power. Energy-power ratio (EP), which is
used in (11) should be kept in a range of 10 J/kVA to 50
J/kVA, depending on the application and converter [11].
In order to keep the EP equals to 48 J/kVA, the value of
capacitor would be as, Fig. 9. Output waveform of (a) phase voltage (b) THD of phase voltage
(c) line voltage (d) THD of line voltage.
𝐸𝑃 × 𝑁 × 𝑆𝑛
𝐶= 2 (11) The voltage levels of sub-module capacitors using
3𝑉𝑑𝑐
−3
48 × 10 × 4 × 5 × 103 different methods of modulation at any arm is presented in
= = 5 × 10−4 Fig. 10. Capacitor voltages of sub-modules using SPWM,
3 × (800)2
= 500𝜇𝑓 THPWM, SDBCPWM, SVPWM and the proposed
method has been arranged in Fig. 10 (a), (b), (c), (d) and
In order to satisfy the following equation (12), the (e) respectively. It is obvious that the fourth sub-module
fundamental frequency of the converter should be above (SM4) capacitor voltage is greater than any others for any
the highest resonant frequency, which results in big values modulation methods. The reason is that, the highest
of 𝐿𝑎𝑟𝑚 and/or 𝐶 values. Therefore, neither the voltage should be found at capacitor of the SM which
fundamental frequency nor the harmonics coincide with connected at the nearest to the neutral point of the
the resonant frequency [12]. converter. the fourth sub-module (SM4) was connected at
adjacent to the neutral point and SM1 was at far distance.
5𝑁 All capacitors were charged at equal voltage when using
𝐿𝑎𝑟𝑚 𝐶 > ( 12) the proposed method of modulation which can be seen
24𝜔02
5∗4 from Fig. 10(e).
=> 𝐿𝑎𝑟𝑚 > The arm current waveforms of the simulated converter
24 ∗ (2𝜋 ∗ 50)2 ∗ 500 ∗ 10−6 based on SPWM, THPWM, SDBCPWM, SVPWM and
=> 𝐿𝑎𝑟𝑚 > 16.68 × 10−3 proposed methods are shown in Fig. 11(a), (b), (c), (d) and
=> 𝐿𝑎𝑟𝑚 > 16.68 𝑚𝐻 (e) respectively. The proposed modulation has confirmed
a lower arm current in comparison with other methods
Based on the above, the arm inductor value is fixed to 50 which can be observed from Fig. 11(e).
mH in the simulation work.
The output phase voltage signal (without load) of the
converter and the corresponding THD profile is shown in
Fig. 9(a) and 9(b) respectively. On the other hand, Fig.
9(c) and 9(d) depicts the line to line voltage of the
converter and the corresponding THD percentage. It can

ISSN: 2600-7495 eISSN: 2600-9633 IJEEAS Vol. 3, No. 2, October 2020

International Journal of Electrical Engineering and Applied Sciences

Fig. 11. Output waveforms of arm current using (a) SPWM (b)
THPWM (c) SDBCPWM (d) SVPWM (e) proposed method.

Fig. 10. Output waveform of capacitor voltages of sub-modules using

lowest profile. In this regard, the proposed algorithm will
(a) SPWM (b) THPWM (c) SDBCPWM (d) SVPWM (e) proposed
method. perform with lower THD profile in both of phase and line
voltage for the MMC device. Moreover, in search of
capacitor voltages by different method (without proposed
V. Summary and Conclusion method) from Table II, it can be seen that the magnitude
of voltages for different SM are not same and it fluctuates
Triangular injection modulation strategy has been used
in range between 119 to 224. In case of the proposed
in this work in modified form to reduce the THD as well
modulation, the SM capacitor voltages were all in a same
as arm current and to balance the capacitor voltage of the
level between 193 V to 194 V.
SM. All simulation results revealed some important
The proposed method has also confirmed a lower arm
outcomes about the modulation methods that have been
current at 32 mA in comparison with the others.
applied on a typical MMC device. Table II shows the
Considering the THD profile, capacitor voltage and arm
summary of the simulation which was performed in this
current, the proposed method has shown a good data point.
work. In comparison with the phase voltage THD,
It can be noticed that although the proposed technique
proposed method shows 20.55% THD which is lower than
performs well in respect to the THD profile, arm current
in case of any other switching methods that have been
and SM capacitor voltage balancing, the performance
performed in the analysis. Having a close look on the THD
analysis of the proposed method in the view of switching
level of line voltage of the MMC with abovementioned
and conduction losses of the switching devices should be
configuration, a lower value of THD was achieved in case
analyzed in the future work
of SVPWM. However, the corresponding phase voltage
THD was quite high which is 31.60%, higher than the

ISSN: 2600-7495 eISSN: 2600-9633 IJEEAS Vol. 3, No. 2, October 2020

 TABLE II
SUMMARY OF RESULTS

Methods SPWM THPWM SDBCPWM SVPWM Proposed

Phase voltage THD (%) 29.36 29.87 33.33 31.60 20.55

Line-to-line voltage THD (%) 17.53 15.62 19.83 15.59 17.67

SM1 145 160 143 162 193

SM2 176 185 172 185 193

SM capacitor voltage (Vc)
SM3 193 195 195 197 194

SM4 224 222 222 119 194

Arm current (ip) (mA max) 70 50 80 45 32

(without load)

References [7] S. Allebrod.; R. Hamerski.; R. Marquardt., "New transformerless,

scalable Modular Multilevel Converters for HVDC-
[1] BARIŞ ÇİFTÇİ, “Selection of suitable PWM switching and
transmission," Power Electronics Specialists Conference, June
control methods for modular multilevel converter drives” M. Sc
2008.
thesis, Middle East Technical University, December 2014.
[8] Saeedifard, Maryam, and Reza Iravani. "Dynamic performance of
[2] Li, B., Yang, R., Xu, D., Wang, G., & Wang, W. “Analysis of the
a modular multilevel back-to-back HVDC system." Power
Phase-Shifted Carrier Modulation for Modular Multilevel
Delivery, IEEE Transactions on 25.4 (2010): 2903-2912.
Converters”, IEEE transaction of Power Electronics, Jan 2014.
[9] M. R. Islam, Y. G. Guo, and J. G. Zhu, “A high-frequency link
[3] N. V. Nguyen, B. X. Nguyen, and H. H. Lee, “An optimized
multilevel cascaded medium-voltage converter for direct grid
discontinuous PWM method to minimize switching loss for
integration of renewable energy systems,” IEEE Trans. Power
multilevel inverters,” IEEE Trans. Ind. Electron., vol. 58, no. 9,
Electron., vol. 29, no. 8, pp. 4167–4182, Aug. 2014.
pp. 3958–3966, Sep. 2011.
[10] M. A. Munjer, M. R. I. Sheikh, M. A. Alim, V. Boddapati and M.
[4] T. D. Nguyen, J. Hobraiche, N. Patin, G. Friedrich, and J. Vilain,
A. Musaib, " Minimization of THD for MMC with triangular
“A direct digital technique implementation of general
injection approach" International Conference on Electrical,
discontinuous pulse width modulation strategy,” IEEE Trans. Ind.
Electronics, Computers, Communication, Mechanical and
Electron., vol. 58, no. 9, pp. 4445–4454, Sep. 2011.
Computing (EECCMC-2018), Tamil Nadu, India, 2018.
[5] Ghazal Falahi, Wensong Yu, Alex. Q. Huang, “THD
[11] M. Zygmanowski, B. Grzesik, and R. Nalepa, "Capacitance and
Minimization of Modular Multilevel Converter With Unequal DC
inductance selection of the modular multilevel converter," Power
Values” IEEE Energy Conversion Congress and Exposition
Electronics and Applications (EPE), 2013 15th European
(ECCE) September 2014): pp. 2153-5158.
Conference on, pp.1-10, 2-6 Sept. 2013.
[6] M. A. Munjer, M. R. I. Sheikh, M. A. Alim, V. Boddapati, and M.
[12] S. Sedghi, A. Dastfan, and A. Ahmadyfard, "A new multilevel
A. Musaib, "Minimization of THD for Multilevel Converters with
carrier based pulse width modulation method for modular
triangular injection approach," 2018 3rd International Conference
multilevel inverter," Power Electronics and ECCE Asia (ICPE &
for Convergence in Technology (I2CT), Pune, 2018, pp. 1-4.
ECCE), 2011 IEEE 8th International Conference on, pp.1432-
1439, May 30 - June 3 2011.

ISSN: 2600-7495 eISSN: 2600-9633 IJEEAS Vol. 3, No. 2, October 2020