Z80 ASSEMBLY LANGUAGE PROGRAMMING MANUAL

Copyright© 1977 by Zilog, Inc. All rights reserved. No part of this

publication may be reproduced, stored in a retrieval system, or transmitted.
In any form or by any means, electronic, mechanical, photocopying,
recording, or otherwise, without the prior written permission of Zilog.
Zilog assumes no responsibility for the use of any circuitry other than
circuitry embodied in a 2ilog product. No other circuit patent licenses
are implied.

TABLE OF CONTENTS
I. INTRODUCTION 1
II. SPECIFICATION OF Z80 ASSEMBLY LANGUAGE
A. THE ASSEMBLY LANGUAGE 2
B. OPERANDS , 4
C. RULES FOR WRITING ASSEMBLY STATEMENTS (SYNTAX).. 6
D. ASSEMBLY LANGUAGE CONVENTIONS , 7
E. ASSEMBLER COMMANDS 13
III. MACROS 15
IV. SUBROUTINES ig
V. Z80 CPU FLAGS 20
VI. Z80 INSTRUCTION SET 24
INSTRUCTION INDEX 275
APPENDIX:
A. ERROR MESSAGES 280
C. INSTRUCTION SORT LISTING (ALPHABETICAL) 284
C. INSTRUCTION SORT LISTING (NUMERICAL) 290

Z80 ASSEMBLY LANGUAGE PROGRAMMING MANUAL

INTRODUCTION :
The assembly language provides a means for writing a program
without having to be concerned with actualmemory addresses
or machine Instruction formats. It allows the use of
symbolic addresses to Identify memory locations and mnemonic
codes (opcodes and operands) to represent the
Instructionsthemselves.
Labels (symbols)can be assigned to a particular instruction
step in a source program to identify that step as an entry
point for use in subsequent instructions. Operands following
each instruction represent storage locations, registers, or
constant values. The assembly language also includes
assembler directives that supplement the machine
instruction. A pseudo-op, for example, is a statement which
is not translated into a machine instruction, but rather is
Interpreted as a directive that controls the assembly
process.
A program written in assembly language is called a source
program. It consists of symbolic commaiids called
statements. Each statement is written on a single line and
may consist of from one to four entries: A label field, an
operation field, an operand field and a comment field. The
source program is processed by the assembler to obtain a
machine language program (object program) that can be
executed directly by the Z80-CPU.
Zilog provides several different assemblers which differ in
the features offered. Both absolute and relocatable
assemblers are available with the Development and
Microcomputer Systems. The absolute assembler Is contained
in base level software operating in a 16K memory space while
the relocating assembler is part of the RIO environment
operating in a 32K memory space.

II SPECIFICATION OF THE Z80 ASSEMBLY LANGUAGE

A. THE ASSEMBLY LANGUAGE
The assembly language of the Z80 is designed to minimize the number of
different opcodes corresponding to the set of basic machine operations and to
provide for a consistent description of instruction operands. The
nomenclature has been defined with special emphasis on mnemonic value and
readability.
The movement of data is indicated primarily by a single opcode, LD for
example, regardlfiss of whether the movement is between different registers
or between registers .and memory locations.
The first operand of an LD instruction is the destination of the operation,
and the Second operand is the source of the operation.
For example:
LD A,B
indicates that the contents of the second operand, register B, are to be
transferred to the first operand, register A. Similarly,
LD C,3FH
indicates that the constant 3FH is to be loaded into the register C. In
addition, enclosing an operand wholly in parentheses indicated a memory
location addressed by the contents of the parentheses. For example,
LD HL, (1200)
indicates the contents of memory locations 1200 and 1201 are to be loaded
into the 16-bit register pair HL. Similarly,
LD (IX+6),C
indicates the contents of the register C are to be stored in the memory
location addressed by the current value of the 16-bit index register
IX plus 6.
The regular formation of assembly Instructions minimizes the number of
mnemonics and format rules that the user must learn and manipulate.
Additionally, the resulting programs are easier to interpret which in turn
reduces programming errors and improves the maintainability of the software.

B. OPERANDS
Operands modify the opcodes and provide the information needed by the
assembler to perform the designated operation.
Certain symbolic names are reserved as key words in the assembly language
operand fields.
They are:

1) The contents of 8-blt registers are specified by the character

corresponding to the register names. The register names are

A , B , C . D , E , H , L , I , R .

2) The contents of 16-bit double registersand register pairs consisting of

two 8-bitregisters are specified by the two characters corresponding to
the register name or register pair. The names of double registers are
 IX, lY and SP.
The names of registers pairs are AF,BC,DE and HL.
3) The contents of the auxiliary register pairs consisting of two 8-bit
registers are specified by the two characters corresponding to the
register pair names followed by an apostrophe.The auxiliary register
pair names are AF'.BC'.DE' and HL'. Only the pair AF ' is actually
allowed as an operand, and then only in the EX AF.AF' Instruction.

4) The state of the four testable flags is specified as follows:

FLAG ON CONDITION OFF CONDITION
Carry C NC
Zero Z NZ
Sign N (minus) P (plus)
Parity PE (even) PO (odd)

OPERAND NOTATIOM

The following notation Is used In the descriptionof the assembly language:

1) r specifies any one of the following registers!

A , B , C , D , E , H ,L .

2) (HL) specifies the contents of memory at the location addressed by

the contents of the register pair HL .
3) n specifies a one-byte expression in the range (0 to 255) nn
specifies a two-byte expression in the range (0 to 65535).

4) d specifies a one-byte expression in the range (-128,127).

5) (nn) specifies the contents of memory at the location addressed by

the two-byte expression nn.

6) b specifies an expression in the range (0,7).

7) e specifies a one-byte expression in the range (-126,129).

8) cc specifies the state of the Flags for conditional JR, JP,

 CALL and RET instructions .
9) qq specifies any one of the register pairs BC, DE, HL or AF .
10) ss specifies any one of the following register pairs:
BC,DE,HL,SP.
11) pp specifies any one of the followingregister pairs: BC,DE,IX,SP.
12) rr specifies any one of the following register pairs:
BC,DE,IY,SP.
13) s specifies any of r , n , (HL ) , ( IX+d ) , ( I Y+d ) .
14) dd specifies any one of the following register pairs:
BC,DE,HL,SP.
15) m specifies any of r , (HL ) , (IX+d ) , ( I Y+d ) .

C. RULES FOR WRITING ASSEMBLY STATEMENTS (SYNTAX)

An assembly language program (source program) consists of labels,

opcodes, operands, comments and pseudo-ops In a sequence which defines
the user's program.

There are 74 generic opcodes (such as LD;) , 25 operand key words

(such as A), and 694 legitimate combinations of opcodes and operands
In the Z80 Instruction set .

ASSEMBLER STATEMENT FORMAT ;

Statements are always written in a particular format. A typical

Assembler statement is shown below:
LABEL OPCODE OPERANDS COMMENT
LOOP: LD HL, VALUE ;GET VALUE

In this example, the label, LOOP, provides a means for assigning a

specific name to the instruction LOAD (LD), and is used to address the
statement in other statements. The operand field contains one or two
entries separated by one or more commas, tabs or spaces. The comment
field is used by the programmer to quickly Identify the action defined
by the statement. Comments must begin with a semicolon and labels must
be terminated by a colon, unless the label starts in column No. 1.
D ASSEIIBLY LANGUAGE CONVENTIOUS
LABELS
A label is a symbol representing up to 16 bits of
inforraation and is used to specify an address or
data. By using labels effectively, the user can
write assembly language programs more rapidly and
make fewer errors. If the progranmer attempts to
use a symbol that has been defined as greater than
8 bits for an 8-bit data constant, the assembler
will generate an error message,

A label is composed of a string of one or more

characters, of which the first six must be unique.
For example, the labels "longname' and
^ longnamealso ' will be considered to be the same
label. The first character must be alphabetic and
any following characters must be either
alphanumeric, the question mark (?) or the under
bar character (_). Any other characters within a
label will cause an error, A label can start in
any column if immediately followed by a colon. It
does not require a colon if started in column one.

The assembler maintains a location counter to

provide addresses for the symbols in the label
field. When a symbol is found in the label field,
the assembler places the symbol and the
corresponding location counter value in a symbol
tab le ,
The symbol table normally resides in RAH, but it
will automatically overflow to disk, so there is no
limit to the number of labels that can be
processed ,

EXPRESSIOHS

An expression is an operand entry consisting of

either a single terra (unary) or a combination of
terms (binary). It contains a valid series of
constants, variables and functions that can be
connected by operation symbols. The Z80 Assembler
will accept a wide range of expressions involving
arithmetic and logical operations. The assembler
will evaluate all expressions from left to right in
the order indicated in the table below:

OPERATOR

FUNCTION
PRI ORITY

+ UNARY PLUS 1

UUARY IIIDUS 1

.NOT. or \ LOGICAL NOT 1

.RES. RESULT 1

** EXPONENTIATION 2

* MULTIPLICATIOU 3
/ DIVISION 3
.UOD. UODULO 3
.3HR. LOGICAL SHIFT RIGHT 3
.SHL. LOGICAL SHIFT LEFT 3
+ ADDITION 4

SUBTRACTION 4

• AND. or 6. LOGICAL AND 5

.OR. or T LOGICAL OR 6
.XOR, LOGICAL XOR 6
.EQ. or = EQUALS 7
.GT. or > GREATER THAN 7
.LT. or < LESS THAN 7
.UGT, UNSIGNED GREATER THAN 7
.ULT. UNSIGNED LESS THAN 7
Parenthesis can be used to ensure correct
expression evaluation. Note, however, that
enclosing an expression wholly in parenthesis
indicates a memory address.

Delimiters such as spaces or commas are not allowed

within an expression since they serve to separate
the expression from other portions of the
statement ,

16-bit integer arithmetic is used throughout.

Note that the negative of an expression can be

formed by a preceding minus sign -, For example:

LD HL,-0EA9H,

The five comparison operators (,EQ., .GT., .LT.,

.UGT. and. ULT.) will evaluate to a logical True (all
ones) if the comparison is true logical False
(zero) otherwise. The operators .GT. and .LT. deal
with signed numbers V7hereas .UGT. and .ULT. assume
unsigned arguments.

The Result operator (.RES.) causes overflow to be

suppressed during evaluation of its argument, thus

overflow is not flagged with an error message.
For example :

LD BC,7FFFH+1 would cause an error message,

whereas LD BC , .RES, ( 7FFFU+1 ) would not.

The Modulo operator (,MOD,) is defined as:

X,MOD,Y. = X-Y*(X/Y) where the division (X/Y)

is integer division.

The Shift operator ( , SlIR , , . SHL , ) shifts the first

argument right or left by the number of positions
given in the second argument. Zeros are shifted
into the high-order or low-order bits,
r espec t ively ,

In specifying relative addressing with either the

JR (Jump Relative) or DJNZ (Decrement and Jump if
Not Zero) instructions, the Assembler automatically
subtracts the value of the next instruction's
reference counter from the value given in the
operand field to form the relative address for the
jump instruction. For example:

JR C,LOOP

will jump relative to the instruction labeled LOOP

if the Carry flag is set. The limits on the range
of a relative address is 128 bytes in either
direction from the reference counter of the next
instruction. An error message will be generated if
this range is exceeded.
The symbol $ is used to represent the value of the
reference counter of the current instruction, and
can be used in general expressions. An expression
which evaluates to a displacement in the range
<-126,+129> can be added to the reference counter
to form a relative address. For example:

JR C,$+5

will jump relative to the instruction which is 5

bytes beyond the current instruction.

PSEUDO-OPS (ASSEMBLER DIRECTIVES)

There are several pseudo-ops which the various

Zllog assemblers will recognize. These assembler
directives, although written much like processor
Instructions, are commands to the assembler instead
of to the processor. They direct the assembler to
perform specific tasks during the assembly process
but have no meaning to the Z80 processor. These
assembler pseudo-ops are:
ORG nn Sets address reference counter to
the value nn.

EQU nn Sets value of a label to nn in the

program: can occur only once for
any label.

DEFL nn Sets value of a label to nn and can

be repeated in the program with
different values for the same
label .

END Signifies the end of the source

program so that any following

statement will be ignored. If
there is no end statement, then the
end-of-file mark In the last source
file will designate the end of the
source program.

DEFB n Defines the contents of a byte at

the current reference counter to be

Defines the content of one byte of

memory to be the ASCII
representation of character s.

Defines the contents of a two-byte

word to be nn. The least
significant byte is located at the
current reference counter while the
most significant byte is located at
the reference counter plus one.

Reserves nn bytes of memory

starting at the current value of
the reference counter.

10

Defines the content of n bytes of

memory to -be the ASCII
representation of string s, where n
is the length of s and must be in
the range 0<=n<-63.

#Po //Pl,.,#Pn Declares the label

to be a macro name with formal
parameters Po through Pn,
Subsequent stateiaents define the
body of the macro.

Harks the end of a macro

de f init ion ,
Pseudo-ops are assembled exactly like executable
instructions, and may be preceded by a label and
followed by a comment. (The label is required for
EQU, DEFL and HACK pseudo-ops.) In the above
pseudo-op definitions, the reference counter
corresponds to the program counter and is used to
assign and calculate machine-language addresses for
the object file.

CONDITIONAL PSEUDO-OPS

Conditional pseudo-ops provide the programmer with

the capability to conditionally include or not
Include portions of his source code in the assembly
process. Conditional pseudo-ops are:

COMD nn Evaluates expression nn. If the

expression is true (non-zero) j the

COND pseudo-op is ignored. If the
expression Is false (zero), the
assembly of subsequent statements
is disabled, COND pseudo-ops
cannot be nested,

ENDC Re-enables assembly of subsequent

s tatements ,
DELIMITERS

A delimiter is used to specify the bounds of a

certain related group of characters in a source
program. The delimiters recognized by the
assembler are commas or spaces, A delimiter cannot

11

occur within an expression.

COtlMENTS

Comments are not a functional part o£ an assembly

program, but instead are used for program
documentation to add clarity, and to facilitate
software maintenance. A comment is defined as any
string following a semicolon in a line, aikd is
ignored by the assembler. Comments can begin in
any column,

I/O BUFFERS

The Z80 Assembler uses a buffered I/O technique for

handling the assembly language source file, listing
file, "object file and temporary files. The
assembler automatically determines the available
work space and allocates the buffer sizes
accordingly. Hence there are no constraints on the
size of the assembly language source file that can
be assembled,

UPPER/LOWER CASE

The assembler processes source text which contains

both upper and lower case alphabetic characters in
the following manner. All opcodes and keywords,
such as register names or condition codes, must be
either all capitals or all lower case. Label names
may consist of any permutation of upper and lower
case, however, two names which differ in case will
be treated as two different names. Thus, LABEL,
label and LaBel will be considered as three
different names. Notice that one could use a
mixture of case to allow definition of labels or
macros which look similar to opcodes, such as Push
or LdiR, without redefining the meaning of the
opcode. All assembler commands, such as *List or
*lnclude (see below) can be in either upper or
lower case, as can arithmetic operators such as
HOT,,, AND, or ,EQ,, and numbers can be any mixture
of case, such as Offffh, OAbCdH or OllOOlb.

NUMBER BASES

The Assembler will accept numbers in several

12

different bases: binary, octal, decimal and

hexadecimal. Numbers must always start with a
digit (leading zeros are sufficient), and may be
followed immediately by a single letter which
signifies the base of the number ('B' for binary,
'0' or 'Q' for octal, 'D' for decimal and 'H' for
hexadecimal) . If no base is specified decimal is
assumed. For example, the same number is
represented in each of the four bases:

lOlllOOB, 134Q, 13A0, 92, 92D, 05CH

E. ASSEMBLER COMMANDS

The Z80 Assembler recognizes several commands to

modify the listing format. An assembler command is
a line of the source file beginning with an * in
column one. The character in column two identifies
the type of command. Arguments, if any, are
separated from the command by any number of blanks
or commas. The following commands are recognized
by the assembler:
*Ej ect

* Heading s

*List OFF

*llaclist OFF

*Maclist ON

Causes the listing to advance to a

new page starting with this line.

Causes string s to be taken as a

heading to be printed at the top of
each new page. Strings s may be
any string of zero to 28
characters, not containing leading
blanks. This command does an
automatic Eject,

Causes listing and printing to be

suspended, starting with this line.

Causes listing and printing to

resume, starting with this line.

Causes listing and printing of

macro expansions to be suspended,
starting with this line.

Causes listing and printing of

macro expansions to resume,
starting with this line.

*Include filename Causes the source file filename to

be included in the source stream
follovjing the conmand statement.

13

The expected use of *Include Is for files of macro

definitions, lists of EQUates, or commonly uSed
subroutines, although it can be used anywhere in a
program that the other commands would be legal*
The filename must follow the normal convention for
specifying filenames, and furthermore only file
types 'F' through 'T' are allowed. The default
type is 'S'. The Included file may also contain a
*Include command, up to a nested level of four,

*Include will always try to shoe-horn the file in

inside a macro definition, and although the
*Include statement will appear in a macro
expansion, the file will not be included again at
the point of expansion, *Include works in the
expected manner in conjunction with conditional
assembly .
For example:

COND exp

*Include FILEl

ENDC

;FXLE1 is included only if the value of exp is

non-zero .

14

III. MACROS

Macros provide a means for the user to define his

own opcodes, or to redefine existing opcodes, A
macro defines a body of text which will be
automatically inserted in the source stream at each
occurrence of a macro call. In addition,
parameters provide a capability for making limited
changes in the macro at each call.

If a macro is used to redefine an existing opcode,

a warning message is generated to indicate that
future use of that opcode will always be processed
as a macro call. If a program uses macros, then
the asembly option M must be specified,

MACRO DEFINITION

The body of text to be used as a macro is given in

the macro definition. Each definition begins with
a MACRO statement and end with an ENDM statement.
The general forms are:

<name> MACRO [ #<P0> , #<P 1 >,,,,, #<Pn> ]

[<label>] ENDM

The label <name> Is required, and must obey all the

usual rules for forming labels. The quantity in
brackets is an optional set of parameters.

There can be any number of parameters, each

starting with the symbol The rest of the

parameter name can be any string not containing a

delimiter (blank, comma, semicolon) or the symbol

However, parameters will be scanned left to

right for a match, so the user is cautioned not to
use parameter names which are prefix substrings of
later parameter names. Parameter names are not
entered in the symbol table.

The label on an ENDM is optional, but if one is

given it must obey all the usual rules for forming
labels ,

Each statement between the MACRO and ENDM

statements is entered into a temporary macro file.
The only restriction on these statements is that
they do not include another macro definition,
(Nested definitions are not allowed,) They may

15

include macro calls. (Recursion is allowed,)

The statements of the macro body are not assembled

at definition time, so they will not define labels,
generate code, or cause errors. Exceptions are the
assembler commands such as *List, which are
executed wherever they occur. Within the macro
body text, the formal parameter names may occur
anywhere that an expansion-time substitution is
desired. This includes comments and quoted
strings. The symbol # nay not occur except as the
first symbol of a parameter name.

Macros must be defined before they are called,

MACRO CALLS AND MACRO EXPANSION

A macro is called by using its name as an opcode at

any point after the definition. The general form
is:

[<label>] <name> [' <S0> ',' <S 1 >',,,,,' Sn> ' ]

The <label> is optional, and <name> must be a

previously defined macro. There may be any number
of argument strings, <Sn>, separated by any number
of blanks or commas. Commas do not serve as
parameter place holders, only as string delimeters.
If there are too few parameters, the missing ones
are assumed to be null. If there are too many, the
extras are ignored. The position of each string in
the list corresponds with the position of the macro
parameter name it is to replace. Thus, the third
string in a macro call statement will be
substituted for each occurrence of the third
parameter name.

The strings may be of any length and may contain

any characters. The outer level quotes around the
string are generally optional, but are required if
the string contains delimiters or the quote
character itself. The quote character is
represented by two successive quote marks at the
inner level. The outer level quotes, if present,
will not occur in the substitution. The null
string, represented by two successive quote marks
at the outer level, may be used in any parameter
position.
After processing the macro call statement, the
assembler switches its input from the source file

16

to the macro file. Each statement of the macro

body is scanned for occurrences of parameter names,
and for each occurrence found, the corresponding
string from the macro call statement is
substituted. After substitution, the statement is
assembled normally.

SYUBOL GENERATOR

Every macro definition has an implicit parameter

named #$YM. This may be referenced by the user in
the macro body, but should not explicitly appear in
the MACRO statement. At expansion time, each
occurrence of #$YM in the definition is replaced by
a string representing a 4-digit hexadecimal
constant ,

This string is constant over a given level of macro

expansion, but increases by one for each new macro
call. The most common use of #$YH is to provide
unigue labels for different expansion of the same
macro. Otherwise, a macro containing a label would
cause multiple definition errors if it were called
more than once,

LISTING FORUAT

By default, each expanded statement is listed with

a blank STMT field. If the llaclist flag is turned
off by the UOM option or *1I OFF, then only the
macro call is listed.

17

IV. SUBROUTINES

Subroutines are blocks of instructions that can be

called during the execution of a sequence oi,
instructions. Subroutines can be called from main
programs or from other subroutines. A subroutine is
entered by the CALL opcode as in:

CALL REWIND

Parameters such as those used by the macros are not

used with subroutines. When a call instruction is
encountered during execution of a program, the PC
is changed to the first instruction of the
subroutine. The subsequent address of the invoking
program is pushed on the stack. Control will
return to this point when the subroutine is
finished. The processor continues to execute the
subroutine until it encounters a RET (return)
instruction. At this point the return address is
popped off the stack into the PC, and the processor
returns to the address of the instruction following
the CALL, to continue execution from that point.

Subroutines of any size can be invoked from

programs or other subroutines of any size, without
restriction. Care must be taken when nesting
subroutines (subroutines within subroutines) that
pushes and pops remain balanced at each level. If
the processor encounters a RET with an un-popped
push on the stack, the PC will be set to a
meaningless address rather than to the next
instruction following the CALL.

Tradeoffs must be considered between:

a) using a block of code repetitively in line,

and

b) calling the block repetitively as a

subroutine ,

Program size can usually be saved by using the

subroutine. If the repetitive block contains N
bytes and it is repeated on II occasions in the
program,

a) MxN bytes would be used in direct

programming, while
b) 311 (for CALLS)

18

+ N (for the block)

+ 1 (for the RET)

3M+N+1 bytes would be required if using a

subrout Ine .

For example, for a block of 20 bytes used 5 times,

in-line programming would require 100 bytes while a
subroutine would require 36.

An added advantage of subroutines is that with

careful naming, program structures become clearer,
easier to read and easier to debug and maintain.
Subroutines written for one purpose can be employed
elsewhere in other programs requiring the same
f unc t ion .

Subroutines differ from Macros in several ways:

a) Subroutine code is assembled into an object

program only once although it may be called
many times. Macro code is assembled in
line every place the macro is used.

b) Registers and pointers required by a

subroutine must be set up before the
CALL. No parameters are used and no
argument string can be issued. Macros,
through their use of parameters, can modify
the settings of registers on each
occurrence .

19

V. Z80 STATUS INDICATORS (FLAGS)

The flag register (F and F') supplies information to the

user regarding the status of the Z80 at any given time.
The bit positions for each flag is shown below:

7 6 5 4 3 2 1

S Z X H X P/V N C
WHERE:

C - CARRY FLAG

N = ADD/SUBTRACT FLAG

P/V = PARITY/OVERFLOW FLAG

H - HALF-CARRY FLAG

Z = ZERO FLAG

S = SIGN FLAG

X = NOT USED

Each of the two Z-80 Flag Registers contains 6 bits of

status information which are set or reset by CPU
operations. (Bits 3 and 5 are not used.) Four of these
bits are testable (C,P/V,Z and S) for use with
conditional jump, call or return instructions. Two
flags are not testable (H,N) and are used for BCD
arithmetic .

CARRY FLAG (C)

The carry bit is set or reset depending on the operation

being performed. For 'ADD' instructions that generate a
carry and 'SUBTRACT' instructions that generate a
borrow, the Carry Flag will be set. The Carry Flag is
reset by an ADD that does not generate a carry and a
'SUBTRACT' that generates no borrow. This saved carry
facilitates software routines for extended precision
arithmetic. Also, the "DAA" instruction will set the
Carry Flag if the conditions for making the decimal
adjustment are met.

For Instructions RLA, RRA, RLS and RRS, the carry bit is
used as a link between the LSB and MSB for any register
or memory location. During Instructions RLCA, RLC s and
SLA s, the carry contains the last value shifted out of
bit 7 of any register or memory location. During

20

Instructions RRCA, RRC s, SRA s and SRL s the carry

contains the last value shifted out of bit of any
register or memory location.

For the logical instructions AND s, OR s and XOR s,

the carry will be reset.

The Carry Flag can also be set (SCF) and complemented

(CCF) .

ADD/SUBTRACT FLAG (N )

This flag is used by the decimal adjust accumulator

Instruction (DAA) to distinguish between 'ADD' and
'SUBTRACT' instructions. For all 'ADD' instructions, N
will be set to an '0'. For all 'SUBTRACT' instructions,
N will be set to a '1'.

PARITY/OVERFLOW FLAG

This flag is set to a particular state depending on the

operation being performed.

For arithmetic operations, this flag indicates an

overflow condition when the result in the Accumulator is
greater than the maximum possible number (+127) or is
less than the minimum possible number (-128). This
overflow condition can be determined by examining the
sign bits of the operands.

For addition, operands with different signs will never

cause overflow. When adding operands with like signs
and the result has a different sign, the overflow flag
is set. For example:

+120 = 0111 1000 ADDEND

+105 = Olio 1001 AUGEND
+225 1110 0001 (-95) SUM

The two numbers added together has resulted in a number

that exceeds +127 and the two positive operands has
resulted in a negative number (-95) which Is incorrect.
The overflow flag is therefore set.

For subtraction, overflow can occur for operands of

unlike signs. Operands of like sign will never cause
overflow. For example:

+ 127 01 11 nil MINUEND

(-) -64 1100 0000 SUBTRAHEND
+ 191 1011 nil DIFFERENCE

21

The minuend sign has changed from a positive to a

negative, giving an incorrect difference. Overflow is
therefore set.

Another method for predicting an overflow is to observe

the carry into and out of the sign bit. If there is a
carry in and no carry out, or if there is no carry in
and a carry out, then overflow has occurred.

This flag is also used with logical operations and

rotate- instructions to indicate the parity of the
result. The number of 'I' bits in a byte are counted.
If the total is odd, 'ODD' parity (P«0) is flagged. If
the total is even, 'EVEN' parity is flagged (P=l).
During search instructions (CPI , CPIR , CPD , CPDR ) and block
transfer instructions (LDI,LDIR, LDD.LDDR) the P/V flag
monitors the state of the byte count register (BC).
When decrementing, the byte counter results in a zero
value, the flag is reset to 0, otherwise the flag is a
Logic 1.

During LD A, I and LD A,R instructions, the P/V flag will

be set with the contents of the interrupt enable
flip-flop (IFF2) for storage or testing.

When inputting a byte from an I/O device, IN r,(C), the

flag will be adjusted to indicate the parity of the
data .

THE HALF CARRY FLAG (H)

The Half Carry Flag (H) will be set or reset depending

on the carry and borrow status between bits 3 and 4 of
an 8-blt arithmetic operation. This flag is used by the
decimal adjust accumulator instruction (DAA) to correct
the result of a packed BCD add or subtract operation.
The H flag will be set (1) or reset (0) according to the
following table:

ADD
SUBTRACT

There is a carry from

Bit 3 to Bit 4

There is
borrow from
bit 4

There is no carry
from Bit 3 to Bit 4

There is no
borrow from
Bit 4

22
THE ZERO FLAG (Z)

The Zero Flag (Z) Is set or reset If the result

generated by the execution of certain Instructions
is a zer o .

For 8-bit arithmetic and logical operations, the Z

flag will be set to a '1' if the resulting byte in
the Accumulator is zero. If the byte is not zero,
the Z flag is reset to '0'.

For compare (search) instructions, the Z flag will

be set to a '1' if a comparison is found between
the value in the Accumulator and the meiiory
location pointed to by the contents of the register
pair HL.

When testing a bit in a register or memory

location, the Z flag will contain the complemented
state of the indicated bit (see Bit b,s).

When Inputting or outputting a byte between a

memory location and an I/O device (INI ;IND ;OUTI and
OUTD), if the result of B-1 is zero, the Z flag is
set, otherwise it is reset. Also for byte inputs
from I/O devices using IN r,(C), the Z Flag is set
to indicate a zero byte input.

THE SIGN FLAG (S )

The Sign Flag (S) stores the state of the most

significant bit of the Accumulator (Bit 7). When
the Z80 performs arithmetic operations on signed
numbers, binary two's complement notation is used
to represent and process numeric information. A
positive number is identified by a '0' in bit 7. A
negative number is identified by a '1'. The binary
equivalent of the magnitude of a positive number is
stored in bits to 6 for a total range of from
to 127. A negative number is represented by the
two's complement of the equivalent positive number.
The total range for negative numbers is from -1 to
-128.

When inputting a byte from an I/O device to a

register, IN r,(C), the S flag will indicate either
positive (S=0) or negative (S=l) data.

23

VI. Z80 INSIRUCTIOU SET

UOTE: Execution time (E.T.) for each Instruction is

given in microseconds for an assumed 4 MHZ clock. Total
machine cycles (H) are indicated with total clock
periods (T States). Also indicated are the number of T
States for each M cycle. For example:
M CYCLES: 2 T STATES: 7(4,3) 4 MUZ E.T.: 1.75

indicates that the instruction consists of 2 machine

cycles. The first cycle contains 4 clock periods (T
States) . The second cycle contains 3 clock periods for
a total of 7 clock periods or T States. The instruction
will execute in 1.75 microseconds.

Register format Is shown for each instruction with the

most significant bit to the left and the least
significant bit to the right.

24

Z80 INSTRUCTION SET

TABLE OF CONTENTS

PAGE

-8 BIT LOAD GROUP 26

-16 BIT LOAD GROUP 52

-EXCHANGE, BLOCK TRANSFER

AND SEARCH GROUP 76
-8 BIT ARITHMETIC AND LOGICAL GROUP 99

-GENERAL PURPOSE ARITHMETIC

AND CPU CONTROL GROUPS 131

-16 BIT ARITHMETIC GROUP 146

-ROTATE AND SHIFT GROUP 163

-BIT SET, RESET AND TEST GROUP 202

-JUMP GROUP 219

-CALL AND RETURN GROUP 237

-INPUT AND OUTPUT GROUP 252

-INSTRUCTION INDEX 275

25

8 BIT LOAD GROUP

26
LD n, p'

Operation : r •<- r

Format :

Opcode Operands

LD r,r'

1 1 1 1 1 1 1

__l I I I I I I

Description:

The contents of any register r' are loaded into any

other register r. Note: r,r' identifies any of the
registers A, B, C, D, E, H, or L, assembled as follows
in the object code:

Register r,r'
A - ill
B - 000
C - 001
D - 010
E - Oil
H - 100
L - 101

M CYCLES: 1 X STATES: 4 4 MHZ E.T.: 1.0

Condition Bits Affected: None

Example :

If the H register contains the number 8AH, and the E

register contains lOH, the instruction

LD H, E

would result in both registers containing lOH.

27
LD

Operation: r ■•

Format :

Opcode

Operands

0-

►110

— \ — I —
Description:

The eight-bit Integer n is loaded into any register

where r identifies register A, B, C, D, E, H or I, ,
assembled as follows in the object code:

Register

A
B
C
D
E
H
L

111
000
001
010
Oil
100
101

M CYCLES: 2 T STATES: 7(4,3) 4 MHZ E.T.: 1.75

Condition Bits 1\f£ected: None

Example :

After the execution of

LD E, ASH

the contents of register E will be A5H.

28

LD p. CHLD

Operation: r-<-(HL)

Foriaat ;

Opcode Operands

LD r, (HL)

1 1 1 1 1 1 1
1^ r «►! 1

I I I I I i_— I I

Description:

The eight-bit contents of memory location (HL) are

loaded into register r, where r identifies register A,
B, C, D, E, H or L, assembled as follows in the object
code:

Register r

A - 111
B - 000
C - 001
D - 010
E - on
H - 100
L - 101

M CYCLES: 2 T STATES; 7(4,3) 4 MHZ E.T.: 1.75

Condition Bits Affected: None
Example ;

If register pair HL contains the number 75A1H, and

memory address 75A1H contains the byte 58H, the
execution of

LD C, (HL)

will result in 58H in register C.

LD p, ClX + d]

Operation ; r-«-(IX+d)
Format ;

Opcode
LD

Operands
r, (IX+d)

— I —

1 1
1
I

LI

1 1

DD

Description ;

The operand (IX+d) (the contents of the Index Register

IX summed with a two's complement displacement Integer
d) Is loaded into register r, where r identifies
register A, B, C, D, E, H or L, assembled as follows in
the object code:

Register £

A = 111
B ■= 000
C - 001
D - 010
E - Oil
H - 100
L - 101

M CYCLES: 5 T STATES: 19(4,4,3,5,3) 4 MHZ E.T.: 4.75

Condition Bits Affected ; None

Example ;

If the Index Register IX contains the number 25AFH, the

instruction

30

LD B, (IX+19H)

will cause the calculation of the sum 25AFH + 19H, which

points to memory location 25C8H. If this address
contains byte 39H, the instruction will result in
register B also containing 39H.

31
LD p. CIY+d3

Operation ! r-*-(IY+d)
Format !

Opcode
LD

Operands
r, (lY+d)

— I 1 —

1 1
I I

-I — I —

FD
Description ;

The operand (lY+d) (the contents of the Index Register

lY summed with a two's complement displacement Integer
d) Is loaded Into register r, where r Identifies
register A, B, C, D, E, H or L, assembled as follows In
the object code:

Register £

ill
000
001
010

on

100
101

T STATES: 19(4,4,3,5,3) 4 MHZ E.T.: 4.75

Condition Bits Affected: None

32

Examp 1 e :

If the Index Register lY contains the number 25AFH, the

instruction

LD B, (IY+I9H)

will cause the calculation of the sum 25AFH + 1 9H , which

points to memory location 25C8H. If this address
contains byte 39H, the instruction will result in
register B also containing 39H.

LD CHU.

Operation: (HL)-<-r
Fornat :

Opcode Operands

LD (HL) , r
I 1 1 1 1 1 1 1 1

111 -« — r—
' I I I I I — I

Description:

The contents of register r are loaded Into the memory

location specified by the contents of the IIL register
pair. The symbol r Identifies register A, B, C, D, E, U
or L, assembled as follows in the object code;

Register r

A - 111
B - 000
C - 001
D - 010
E - Oil
H - 100
L - 101

M CYCLES: 2 T STATES: 7(4,3) 4 MHZ E.T.z 1.75

Condition Bits Affected: None

Example :

If the contents of register pair HL specifies memory

location 2146H, and the B register contains the byte
29H, after the execution of

LD (HL) , B

memory address 2146H will also contain 29H.

LD CIX + dD, n

Operation: (IX+d)-<-r
Format :

Opcode Operands

LD (IX+d) , r

1 DD
Description;

The contents of register r are loaded into the meifiory

address specified by the contents of Index Register IX
summed with d, a two's complement displacement Integer.
The symbol r identifies register A, B, C, D, E, H or L,
assembled as follows In the object code:

Register r

A - 111

B - 000

C - 001

D - 010

E - Oil

H - 100

L - 101

M CYCLES: 5 T STATES: 19(4,4,3,5,3) 4 MHZ E.T.: 4.75

Condition Bits Affected: None

35

Example :

If the C register contains the byte ICH, and the Index

Register IX contains 3100H, then the instruction

LD (IX+6H), C

will perform the sum 3100H + 6H and will load ICH into
memory location 3106H.

36

LD ClY + d], p

Operation ; (IY+d)<*-r
Format ;
Opcode Operands

LD (lY+d) , r

1 1

1 FD

Description:

The contents of register r are loaded into the memory

address specified by the sum of the contents of the

Index Register lY and d, a two's complement displacement

integer. The symbol r is specified according to the

following table.

Register r

A - 111
B - 000
C - 001
D - 010
E - Oil
H - 100
L - 101

M CYCLES: 5 T STATES: 19(4,4,3,5,3) 4 MHZ E.T.: 4.75

Condition Bits Affected: None

37

Example ;

If the C register contains the byte 48H, and the Index

Register lY contains 2A11H, then the Instruction

LD (IY+4H), C

will perform the sum 2A11H + 4H, and will load 48H Into
memory location 2A15.

38
LD CHLD, n

Operation! (HL)-^n

Format :

Opcode

Operand

LD

(HL) ,n

110 110
36

Description:

Integer n Is loaded into the memory address specified by

the contents of the HL register pair.

M CYCLES: 3 T STATES: 10(4,3,3) 4 MHZ E.T,: 2.50

Co ndition Bits Affected : None

Example :

If the HL register pair contains 4444H, the instruction

LD (HL) , 28H

will result In the memory location 4444H containing the

byte 28H.

39

LD ClX + d],
Operation: (IX+d)*-n

Opcode

1 1

1
I

Operands
(IX+d) , n

DD

36

Description :
The n operand is loaded into the raemory address
specified by the sum of the contents of the Index
Register IX and the two's complement displacement
operand d .

M CYCLES: 5 T STATES: 19(4,4,3,5,3) 4 MHZ E.T.: 4.75

Condition-Bits Affected: None

Example ;

If the Index Register IX contains the number 219AH the

instruction

LD (IX+5H), 5AH

would result in the byte 5AH in the memory address

219FH.

40

LD ClY + d], n

Operation : (IY+d)-<-n
Forma t ;

Opcode
LD

Operands
(lY+d) ,n

1111

FD

36

Description :

Integer n Is loaded Into the memory location specified

by the contents of the Index Register summed with the
two's complement displacement Integer d.

M CYCLES: 5 T STATES: 19(4,4,3,5,3) 4 MHZ E.T.: 4.75

Condition Bits Affected : NONE
Example :
If the Index Register lY contains the number A940H, the
instruction

LD (lY+lOH), 97H

would result in byte 97 in memory location A950H.

41

LD A. CBC]

Operation; A *- (BC)

Format :

Opcode

Operands
LD

A, (BC)

1 1

OA

Description:

The contents of the memory location specified by the

contents of the BC register pair are loaded into the
Accumulator .

M CYCLES: 2 T STATES: 7(4,3) 4 MHZ E.T.: 1.75

Condition Bits Affected: None

Example:

If the BC register pair contains the number 4747H, and

memory address 474711 contains the byte 12H, then the
instruction

LD A, (BC)

will result in byte 12H in register A.

42

LD A, CDED

Operation! A ^ (DE)

Fo rmat :
Opcode

Operands

LD

A, (DE)

1 1 1

lA

Description:

The contents of the memory location specified by the

register pair DE are loaded into the Accumulator.

M CYCLES: 2 T STATES: 7(4,3) 4 MHZ E,T.: 1.75

Condition Bits Affected : None

Example :

If the DE register pair contains the number 30A2H and

memory address 30A2H contains the byte 22H, then the
instruction

LD A, (DE)

will result in byte 22H in register A.

43

LD A, Cnn]

Operation : A (nn)
Fo rma t :

Op code
LD

Ope rands
A, (nn)
1

1 1 '0 1

3A

De script Lon :

The conttints of the memory location specified by the

operands nn are loaded Into the Accumulator. The first

n operand after the op code Is the low ordder byte of a

two-byte memory address.

M CYCLES: 4 T STATES: 13(4,3,3,3) 4 MHZ E.T.: 3.25

Condition Bits Affected : None

Exampl e ;

If the contents of nn is number 8832H, and the content

of memory address 8832H is byte 04H, after the
inst rue t ion

LD A, (nn)

byte 04H will be in the Accumulator.

44

LD CBC). A

Operation: (BC) *- A

Format :

Opcode

Operands
LD

(BC) ,A

0. 1

02

Description:

The contents of the Accumulator are loaded into the

memory location specified by the contents of the
register pair BC,

M CYCLES: 2 T STATES: 7(4,3) 4 MHZ E.T.: 1.75

Cond ition Bits Affected ; None

Example:

If the Accumulator contains 7AH and the BC register pair

contains 1212H the instruction
LD (BC) , A

will result in 7AH being in memory location 1212II,

45

LD CDE3

Operation : (DE)*-A

Format ;

Opcode

Ope rands
LD

(DE) .A

1 1

12

Description :

The contents of the Accumulator are loaded into the

memory location specified by the contents of the DE
register pair.

M CYCLES: 2 T STATES: 7(4,3) 4 MHZ E.T,: 1.75

Condition Bits Affected : None

Examp 1 e :

If the contents of register pair DE are 1128H, and the

Accumulator contains byte AOH, the instruction

LD (DE),A
will result In AOH being in memory location 1128H.

46

LD Cnn], A

Operation : (nn) ^ A
Fo rma t :

Opcode
LD

Ope rands
(nn) ,A

32
Description ;

The contents of the Accumulator are loaded into the

memory address specified by the operand nn . The first n
operand after the op code is the low order byte of nn .

M CYCLES: 4 T STATES: 13(4,3,3,3)

4 MHZ E.T. : 3.25

Condition Bits Affected: None

Examp 1 e :

If the contents of the Accumulator are byte D 7H , after

the execution of

LD (3141H),A

D7H will be in memory location 3141H.

47
LD A, I

Operation : A <- I
Format :

Opcode
LD

Operands
A, I

1110 110 1
I I I I I I I

10 10 111
I I I I I I I

ED
57
Description :

The contents of the Interrupt Vector Register I are

loaded Into the Accumulator.

M CYCLES:2 T STATES: 9(A,5) 4 MHZ E.T.: 2.25

Condition Bits Affected :

S: Set if I-Reg. is negative;

reset otherwise
Z: Set if I-Reg. is zero;

reset otherwise
H: Reset
P/V: Contains contents of IFF2
N: Reset
C: Not affected

Note:

If an interrupt occurs during execution of this

instruction, the Parity flag will contain a 0.

48

LD A. R

Operation : A <- R

Opcode
LD

Operands
A.R

1 ' 1 ' 1 ' ' 1 ' 1 ' ' 1

t__J I L L_J U_

10 11111
ED
5F

Description :

The contents of Memory Refresh Register R are loaded

into the Accumulator.

M CYCLES: 2 T STATES: 9(4,5) 4 MHZ E.T.: 2.25

Condition Bits Affected :

S: Set If R-Reg. is negative;

reset otherwise
Z: Set If R-Reg. Is zero;

reset otherwise
H: Reset
P/V: Contains contents of IFF2
N : Reset
C: Not affected
49

LD I, A

Operation : I <- A

Format ;

Opcode

Operands

LD

I ,A

1110 110 1
ED

1 1 1 1

47

Descr Ipt Ion ;

The contents of the Accumulator are loaded into the

Interrupt Control Vector Register, I.

M CYCLES: 2 T STATES: 9(4,5) 4 MHZ E.T.: 2.25

Condition Bits Affected ; None

50

LD R. A
Operation : R A
Fo rmat :

Opcode
LD

Operands
R,A

— I 1 1 1 1 1 1 —

1110 110 1

I I I I I I I

— I — I — I — I — I — I — I —

1 n 1 1 1 1
■ I I I I I I I

ED

4F
Description :

The contents of the Accumulator are loaded into the

Memory Refresh register R.

M CYCLES: 2 T STATES: 9(4,5) 4 MHZ E.T.: 2.25

Condition Bits Affected: None

51

-16 BIT LOAD GROUP-

52

LD dd, nn

Operation : dd nn
Fo rma t :

Opcode

LD

— I 1 1 1 1 1 1 —

d d 1
__i I I 1 I I J

— I — I — I — I — I — I — I —

• n ^

I I I — I — I — I — I —

-* n

I \ I I I I I I

Description :

The two-byte integer nn is loaded Into the dd register

pair, where dd defines the BC, DE , HL , or SP register
pairs, assembled as follows in the object code:
Pair dd

BC 00
DE 01
HL 10
SP 11

The first n operand after the op code is the low order

by te .

M CYCLES: 3 T STATES: 10(4,3,3) 4 MHZ E.T.: 2.50

Condition Bits Affected : None
Example :

After the execution of

LD HL, 5000H

the contents of the HL register pair will be 5000H.

Operands
dd , nn

53

LD IX. nn
Operation : IX-e-nn
Fo rmat :

Opcode

Operands
IX, nn

DD
21

De script Ion :

Integer nn Is loaded into the Index Register IX. The

first n operand after the op code Is the low order byte.

M CYCLES: 4 T STATES: 14(4,4,3,3) A MHZ E.T.: 3.50

Condition Bits Affected : None

Example :

After the instruction

LD IX,45A2H
the Index Register will contain integer 45A2H.

54

LD lY. nn

Operation ; IY<-nn
Format :

p c o d.e

1 1

Operands
lY.nn

FD

21
Description ;

Integer nn Is loaded into the Index Register lY. The

first n operand after the op code Is the low order byte.

M CYCLES: 4 T STATES: 14(4,4,3,3) 4 MHZ E.T.: 3.50

Condition Bits Affected : None

Example :

After the Instruction:

LD IY,7733H

the Index Register lY will contain the integer 7733H,

LD HL, CnnD

Operation : H-*-(nn+1), L«-(nn)

Format ;

Opcode Operands

LD
HL, (nn)

' ■ 1 ' ' 1

2A

Description ;

The contents of memory address (nn) are loaded Into the

low order portion of register pair HL (register L), and
the contents of the next highest memory address (nn+1)
are loaded Into the high order portion of HL (register
H). The first n operand after the op code is the low
order byte of nn.

M CYCLES: 5 T STATES: 16(4,3,3,3,3) 4 MHZ E.T.: 4.00

Condition Bits Affected ; None
Example :

If address 4545H contains 37H and address 4546H contains

AlH after the instruction
LD HL, (4545H)

the HL register pair will contain A137H.

56

LD dd, Cnn3

Operation ; ddH-«-(nn+1) ddL *- (nn)

Format ;

Opcode Operands
LD dd,(nn)

1 1

1 ED
Description !

The contents of address (nn) are loaded into the low

order portion of register pair dd, and the contents of
the next highest memory address (nn+1) are loaded into
the high order portion of dd. Register pair dd defines
BC, DE, HL, or SP register pairs, assembled as follows
in the object code:

Pair dd

BC 00

DE 01

HL 10

SP 11

The first n operand after the op code is the low order

byte of (nn).

M CYCLES: 6 T STATES: 20(4,4,3,3,3,3) 4 MHZ E.T.: 5.00

Condition Bits Affected : None

57

Example :

If Address 2130H contains 65H and address 2131M contains

78H after the instruction

LD BC, (2130H)

the BC register pair will contain 7865H.

58

LD IX, Cnn]

Operation ; IX^ (nn+1), IXl (nn)

Format !

Opcode Operands
LD

IX, (nn)

1 1

DD
2A

Description ;

The contents of the address (nn) are loaded Into the low
order portion of Index Register IX, and the contents of
the next highest memory address (nn+l) are loaded into
the high order portion of IX. The first n operand after
the op code is the low order byte of nn .
M CYCLES: 6 T STATES: 20(4,4,3,3,3,3) 4 MHZ E.T.: 5.00
Condition Bits Affected ; None
Example ;

If address 6666H contains 92H and address 6667H contains

DAH, after the Instruction

LD IX, (6666H)

the Index Register IX will contain DA92H.

59

LD lY, Cnn]

Operation; I (nn+1) , IYL-«-(nn)

Format ;

Opcode Operands

LD

I Y , ( nn )
110

FD
2A

Descr Ipt Ion ;

The contents of address (nn) are loaded Into the low

order portion of Index Register lY, and the contents of
the next highest memory address (nn+1) are loaded into
the high order portion of lY. The first n operand afte.r
the op code is the low order byte of nn.

M CYCLES: 6 T STATES; 20(4,4,3,3,3,3) 4 MHZ E.T.: 5.00

Condition Bits Affe<?ted; None
Example ;

If address 6666H contains 92H and address 6667H contains

DAH, after the instruction

LD lY, (6666H)

the Index Register lY will contain DA92H.

60

LD Cnn], HL

Operation ; (nn+1)-^H„ (nn) •«- L

Format ;

Opcode Operands

LD

(nn

— I I i| — r— I —

1 .0
I I — I — I, I.

-I — T — f — r

n r..
,HL

22

Description ;

The contents of the low order portion of register pair

HL (register L) are loaded Into memory addreiss (nii) , and
the contents of the high order portion of HL (register
H) are loaded Into the next highest memory address
(nn+1). The first n operand after the op code Is t^he
low order byte of tan. > '

4 MHZ E.T. : 4.00

M CYCLES: 5 T STATES: 16(4,3,3,3,3)

Condition Bits Affected : None
Example :

If the content of register pair HL Is 483AH, after the

Instruction
LD (B229H),HL

address B229H) will contain 3AH, and address B22AH will

contain 48H.

LD Cnn]

Operation ! (nn+1) -(-dclH. (nn)-<-ddL

Format !

Opcode Operands

LD

(nn) ,dd

ED
Description :

The low order byte of register pair dd is loaded Into

memory address (nn); the upper byte Is loaded Into
memory address (nn+1). Register pair dd defines either
BC, DE, HL, or SF, assembled as follows In the object
code :

Pair dd

BC 00

DE 01

HL 10

SP 11

The first n operand after the op code Is the low order

byte of a two byte memory address.

M CYCLES: 6 T STATES: 20(4,4,3,3,3,3) 4 MHZ E.T.; 5.00

Condition Bits Affected: None

62

Example :

If register pair BC contains the number 4644H, the

instruction

LD (1000H),BC

will result in 44H in memory location lOOOH, and 46H

memory location lOOlH.

63

LD Cnn],

Operation : (nn+1)*-IXH, (nn)«-IX|_

Format ;

Opcode Operands
LD (nn),IX
1 1

DD
22

Description ;

The low order byte In Index Register IX Is loaded Into

memory address (nn); the upper order byte is loaded Into
the next highest address (nn+1). The first n operand
after the op code is the low order byte of nn .

M CYCLES: 6 T STATES: 20(4,4,3,3,3,3) 4 MHZ E.T.: 5.00

Condition Bits Affected ; None

Example :

If the Index Register IX contains 5A30H, after the

instruction

LD (4392H),IX
memory location 4392H will contain number 30H and
location 4393H will contain 5AH.

64

LD CnnD. lY

Operation ; (nn+D^-IYn, (nn)-<-IYL

Foripat ;

Opc ode Operands

1 1
L.

L.

(nn) ,IY

FD
22

Description ;

The low order byte in Index Register lY is loaded into

memory address (nn); the upper order byte is loaded into
memory location (nn+1). The first n operand after the
op code is the low order byte of nn.

M CYCLES: 6 T STATES: 20(4,4,3,3,3,3) 4 MHZ E . T . : 5 . 00

Condition Bits Affected ; None

Exampl e ;

If the Index Register lY contains 4I74H after the

instruction

LP (8838H),IY

memory location 8838H will contain number 74H and memory

location 8839H will contain 41H.
65

LD SP. HL

operation! SP-«-HL

Format :

Opcode

Operands

LD

SP.HL
111110 1

F9

Description:

The contents of the register pair HL are loaded into thi

Stack Pointer SP.

M CYCLES: 1 T STATES: 6 4 MHZ E.T.! 1.50

Example:

If the register pair HL contains 442EH, after the

instruction

LD SP.HL

the Stack Pointer will also contain 442EH.

Condition Bits Affected:

None

66

LD SP. IX

Operation: SP<-IX

Format :

Opcode

Operands

SP, IX

— I 1 1 1 — I — I 1 —
110 1110 1
I I t I I L_JI

— I 1 1 1 1 1 1 —

111110 1
I — I — I I — I — I I —

DD
F9

Description:

The two byte contents of index Register IX are loaded

into the Stack Pointer SP.

M CYCLES: 2 T STATES: 10(4,6) A MHZ E.T.: 2.50

Condition Bits Affected : None
Example :

If the contents of the Index Register IX are 98I)AH,

after the instruction

LD SP.IX

the contents of the Stack Pointer will also be 98DAH.

67

LD SP

Operation: SP<-IY

Format :

Opcode

Operands

SP, lY

— I 1 1 1 1 1 1 —
1111110 1
I I 1 I I 1 I

— I 1 \ 1 1 1 1 —

111110 1
I I I I I l_J

FD

F9

Description:

The two byte contents of Index Register lY are loaded

into the Stack Pointer SP,

M CYCLES: 2 T STATES: 10(4,6) 4 MHZ E.T.: 2.50

Condition Bits Affected ; None
Example :

If Index Register lY contains the integer A227tt, after

the instruction
LD SP,IY

the Stack Pointer will also contain A227H,

68

PUSH qq

PUSH qq

Operation ; (SP-2) qpt , <SP-1 ) QQH

Format ;

Opcode Operands
PUSH qq

1 ' 1 ' q ' q ' ' 1 ' ' 1

I I I I L—l L I

Description :

The contents of the register pair qq are pushed Into the

external memory LIFO (last-In, flrst-out) Stack. The
Stack Pointer (SP) register pair holds the 16-blt
address of the current "top" of the Stack. This
Instruction first decrements the SP and loads the high
order byte of register pair qq Into the memory address
now specified by the SP; then decrements the SP again
and loads the low order byte of qq Into the memory
location corresponding to this new address In the SP.
The operand qq Identifies register pair BC, DE, HL, or
AF, assembled as follows In the object code:

Pair qq^

BC 00
DE 01
HL 10
AF 11

M CYCLES: 3 T STATES: 11(5,3,3) 4 MHZ E.T.: 2.75

Condition Bits Affected : None
Example :

If the AF register pair contains 2233H and the Stack

Pointer contains 1007H, after the instruction

PUSH AF

memory address 1006H will contain 22H, memory address

1005H will contain 33H, and the Stack Pointer will
contain 1005H.

69
PUSH

Operation; (SP-2)^IXl, (SP-1)-*-IXh

Format :

Opcode

Operands

PUSH

IX

110 1110 1
DD

1110 10 1

E5

Description:

The contents of the Index Register IX are pushed Into

the external memory LIFO (last-in, first-out) Stack.
The Stack Pointer (SP) register pair holds the 16-blt
address of the current "top" of the Stack. This
instruction first decrements the SP and loads the high
order byte of IX into the memory address now specified
by the SP; then decrements the SP again and loads the
low order byte into the memory location corresponding to
this new address in the SP,

M CYCLES: 3 T STATES: 15(4,5,3,3) 4 MHZ E.T.: 3.75

Example :

If the Index Register IX contains 2233H and the Stack

Pointer contains 1007H, after the Instruction

memory address 1006H will contain 22H, memory address

1005H will contain 33H, and the Stack Pointer will
contain 1005H.

Condition Bits Affected;

None

PUSH IX

70

PUSH lY
Operation; (SP-2) ^ I Yl , (SP-1) I Yh

Format :

Opcode

Operands

PUSH

lY

1111110 1

FD
1110 10 1

E5

Description:

The contents of the Index Register lY are pushed Into

the external nemory LIFO (last-In, flrst-out) Stack.
The Stack Pointer (SP) register pair holds the 16-blt
address of the current "top" of the Stack. This
Instruction first decrements the SP and loads the high
order byte of lY Into the memory address now specified
by the SP; then decrements the SP again and loads the
low order byte into the memory location corresponding to
this new address in the SP.

M CYCLES: 4 T STATES: 15(4,5,3,3) 4 MHZ E.T.: 3.75

Example:
If the Index Register lY contains 2233H and the Stack
Pointer contains 1007H, after the instruction

memory address 1006H will contain 22H, memory address

1005H will contain 33H, and the Stack Pointer will
contain 1005H.

Condition Bits Affected:

None

PUSH lY

71

POP qq

qPH^ISP+D, qqL^(SP)
Opcode Operands
POP qq

1 1 q q 1
_J I I I I I 1—

Desc r Ipt ion ;

The top two bytes of the external memory LIFO (last-in,

first-out) Stack are popped Into register pair qq. The
Stack Pointer (SP) register pair holds the 16-bit
address of the current "top" of the Stack. This
instruction first loads into the low order portion of
qq, the byte at the memory location corresponding to the
contents of SP; then SP is incremented and the contents
of the corresponding adjacent memory location are loaded
into the high order portion of qq and the SP is now
incremented again. The operand qq identifies register
pair BC, DE, HL, or AF, assembled as follows in the
object code:

Pair r

BC 00
DE 01
HL 10
AF 11

M CYCLES: 3 T STATES: 10(4,3,3) 4 MHZ E.T.: 2.50

Condition Bits Affected ; None

72

Example ;

If the Stack Pointer contains lOOOH, memory location

lOOOH contains 55H, and location lOOlH contains 33H,
instruction

POP HL

will result in register pair HL containing 3355H, and

the Stack Pointer containing 1002H.

73

POP
Operation; I Xh (SP+1 ) . IXl^(SP)

Format :

Opcode

Operands

POP

IX

110 1110 1

DD
1 1 1 1

El

Description:

The top two bytes of the external memory LIFO (last-In,

first-out) Stack are popped Into Index Register IX. The
Stack Pointer (SP) register pair holds the 16-blt
address of the current "top" of the Stack. This
Instruction first loads Into the low order portion of IX
the byte at the memory location corresponding to the
contents of SP; then SF Is Incremented and the contents
of the corresponding adjacent memory location are loaded
into the high order portion of IX. The SP is now
Incremented again.

M CYCLES: 4 T STATES: 14(4,4,3,3) 4 MHZ E.T.: 3.50

Example:
If the Stack Pointer contains lOOOH, memory location
lOOOH contains 55H, and location lOOlH contains 33H, the
instruction

will result in Index Register IX containing 3355H, and

the Stack Pointer containing 1002H.

Condition Bits Affected:

None

POP IX

74

POP lY

Operation; IYh^(SP+1), IYl^(SP)

Format :

Opcode

Operands

— I 1 1 1 —

11111.,
I I I I I I L

T 1

1 1

— I 1 1 1 1 1 1 —

1 1 1 1
I I I I I I I
FD
El

Description:

The top two bytes of the external memory LIFO (last-In,

flrst-out) Stack are popped Into Index Register lY, The
Stack Pointer (SP) register pair holds the 16-blt
address of the current "top" of the Stack. This
instruction first loads into the low order portion of lY
the byte at the memory location corresponding to the
contents of SP; then SP is incremented and the contents
of the corresponding adjacent memory location are loaded
into the high order portion of lY. The SP is now
Incremented again.

M CYCLES: 4 T STATES: 14(4,4,3,3) 4 MHZ E.T.: 3.50

Condition Bits Affected : None
Example :

If the Stack Pointer contains lOOOH, memory location

lOOOH contains 55H, and location lOOlH contains 33H, the
instruction

POP lY

will result in Index Register lY containing 3355H, and

the Stack Pointer containing 1002H.
75

-EXCHANGE. BLOCK TRANSFER AND SEARCH GROUP-

76

EX DE. HL

Operation: DE HL

Format :

Opcode

Operands
EX

DE.HL

1110 10 11

EB

Description:

The two-byte contents of register pairs DE and HL are

exchanged .

M CYCLES: 1 T STATES: 4 4 MHZ E.T.: 1.00

Condition Bits Affected: None
Example :

If the content of register pair DE is the number 2822H,

and the content of the register pair HL is number 499AH,
after the instruction

the content of register pair DE will be 499AH and the

content of register pair HL will be 2822H.
EX DE,HL

77

EX AF, AF'

Operation; AF AF*

Format :

Opcode

Operands

EX
AF.AF'

08

Description:

The two-byte contents of the register pairs AF and AF'

are exchanged. (Note: register pair AF' consists o£
registers A' and F' .)

Condition Bits Affected: None

Example :

If the content of register pair AF is number 9900H, and

the content of register pair AF' is number 5944H, after
the instruction

the contents of AF will be 5944H, and the contents of

AF' will be 9900H.

M CYCLES: 1 T STATES

4 MHZ E.T. : 1 .00

EX AF.AF'

78

EXX
Operation; (BO « (BC), (DE) « (DE'I, (HL) ^ (HL')
Format ;

Opcode Operands

EXX

I 1 1 1 1 1 1 1 —

110 110 1
I t I I I I '

Description:

Each two-byte value in register pairs BC, DE, and HL is

exchanged with the two-byte value in BC' , DE' , and HL' ,
respectively .

M CYCLES: 1 T STATES: 4 4 MHZ E.T.: 1.00

Condition Bits Affected: None

Example :

If the contents of register pairs BC, DE, and HL are the

numbers 445AH, 3DA2H, and 8859H, respectively, and the
contents of register pairs BC' , DE' , and HL' are 0988H,
9300H, and 00E7H, respectively, after the instruction

EXX

the contents of the register pairs will be as follows:

BC: 0988H; DE: 9300H; HL: 00E7H; BC' : 445AH; DE': 3DA2H;
and HL': 8859H.

79

EX CSPD. HL

Operation: H ^ (SP+1), L (SP)

Format :
Opcode

Operands

EX

(SP) ,HL

1 1 1 Q 1 1

E3

Description;

The low order byte contained in register pair HL is

exchanged with the contents of the memory address
specified by the contents of register pair SP (Stack
Pointer) , and the high order byte of HL is exchanged
with the next highest memory address (SP+1) .
M CYCLES: 5 T STATES: 19(4,3,4,3,5) 4 MHZ E.T.: 4.75

Condition Bits Affected: None

Example:

If the HL register pair contains 7012H, the SP register

pair contains 8856H, the memory location 8856H contains
the byte IIH, and the memory location 8857H contains the
byte 22H, then the instruction

will result in the HL register pair containing number

2211H, memory location 8856H containing the byte 12H,
the memory location 8857H containing the byte 70H and
the Stack Pointer containing 8856H.

EX (SP) ,HL
80

EX CSPD, IX

Operation ! IXh (SP+11 , IXl (SP)

Format ;

Opcode

EX

Operands
(SP) ,IX

— I 1 1 1 1 1 1 —

110 1110 1
I I I I ' ■ '
— I — I — I — I — I — I — I —
1 1 1 1 1
I I I I I I l_

DD
E3

Description:

The low order byte In Index Register IX Is exchanged

with the contents of the memory address specified by the
contents of register pair SF (Stack Pointer) , and the
high order byte of IX is exchanged with the next highest
memory address (SP+1),

M CYCLES: 6 T STATES: 23(4,4,3,4,3,5) 4 MHZ E.T.: 5.75

Condition Bits Affected: None

Example:
If the Index Register IX contains 3988H, the SP register
pair contains OlOOU, the memory location OlOOH contains
the byte 90H, and memory location OlOlH contains byte
48H, then the Instruction

EX (SP),IX

will result In the IX register pair containing number

4890H, memory location OlOOH containing 88H, memory
location OlOlH containing 39H and the Stack Pointer
containing OlOOH.

81

EX CSP3,

Operation; IYh (SP+1), I Yl (SP)

Opcode

EX
Operands
(SP) ,IY

— I — 1 — I — I — I — I — I —
1111110 1
I— —I I I I L—J

— I 1 1 1 1 1 1

1 1 1 1 1
— I — I — I I I — I — I

FD
E3

Description:

The low order byte In Index Register lY is exchanged

with the contents of the memory address specified by the
contents of register pair SP (Stack Pointer), and the
high order byte of lY Is exchanged with the next highest
memory address (SF+1) .
M CYCLES: 6 T STATES: 23(4,4,3,4,3,5) 4 MHZ E.T.: 5.75

Condition Bits Affected: None

Example;

If the Index Register lY contains 3988H, the SP register

pair contains OlOOII, the memory location OlOOH contains
the byte 90H, and memory location OlOlH contains byte
48H, then the instruction

EX (SP) ,IY

will result in the lY register pair containing number

4890H, memory location OlOOH containing 88H, memory
location OlOlH containing 39H, and the Stack Pointer
containing OlOOH.

82

LDI
Operation: (DE)^(HL), DE ^ DE+1 , HL ^ HL+1 , BC ^ BC-1

Operands

1110 11

1 1
I — I I I I 1 I

ED

AO

Description:

A byte of data is transferred from the memory location

addressed by the contents of the UL register pair to the
memory location addressed by the contents of the DE
register pair. Then both these register pairs are
incremented and the BC (Byte Counter) register pair is
d ecremented .

H CYCLES: 4 X STATES: 16(4,4,3,5) 4 MHZ E.T.: 4.00

Condition Bits Affected:

S: Not affected

Z: Not affected

H: Reset

P/V: Set if BC-lj^O;

reset otherwise

N: Reset

C: Not affected

83
Example ;

If the HL register pair contains llllH, memory location

llllH contains contains the byte 88H, the DE register
pair contains 2222H, the memory location 2222H contains
byte 66H, and the BC register pair contains 7H, then the
instruction

will result in the following contents in register pairs

and memory addresses:

LDI

HL
( 1 1 IIH)

DE
(2222H)

BC

1112H
88H
2223H

8 811
6H

84

LDIR

LDIR

Operation ; (DE) t- (HL), DE<-DE+1. HL-i-HL+1, BC-hBC-1

Format ;

Opcode
Operands

LDIR

1110 110 1

ED

1 1 1

BO

Descrlpt Ion ;

This two byte Instruction transfers a byte of data from

the memory location addressed by the contents of the HL
register pair to the memory location addressed by the DE
register pair. Then both these register pairs are
incremented and the BC (Byte Counter) register pair is
decremented. If decrementing causes the BC to go to
zero, the instruction is terminated. If BC is not zero
the program counter is decremented by 2 and the
instruction is repeated. Interrupts will be recognized
and two refresh eyeless will be executed after each data
transfer. Note that if BC is set to zero prior to
instruction execution, the instruction will loop through
64K bytes.

For BC-0:

M CYCLES: 5 T STATES: 21(4,4,3,5,5) 4 MHZ E.T.: 5.25

For BC=0:

M CYCLES: 4 T STATES: 16(4,4,3,5) 4 MHZ E.T.: 4.00

85

Condition Bits Affected;

S: Not affected

Z: Not affected

H: Reset

P/V: Reset
N: Reset

C: Not affected

Example :

If the HL register pair contains llllH, the DE register

pair contains 2222H, the BC register pair contains
0003H, and memory locations have these contents:

then after the execution of

LDIR

the contents of register pairs and memory locations will

be:

HL : HUH
DE : 2225H
BC : OOOOH

(HUH)
(1112H)
(1113H)
88H
36H
ASH

(2222H)
(2223H)
(2224H)

66H
59H
C5H

(lUlH) : 88H (2222H)

(1112H) : 36H (2223H)
(1113H) : ASH (2224H)

88H
36H
ASH

LDD
Operation: (DE)^{HL), DE ^ DE-1 , HL^HL-1, BC<-BC-1

Opcode

Operands

— I 1 1 1 1 1 1 —

1110 110 1
I I ■ I I l—J

— I — I — I — I — I — I — I —
10 10 10
I — I I I I I — I

ED
A8
Descripttion;

This two byte instruction transfers a byte of data from

the memory location addressed by the contents of the HL
register pair to the memory location addressed by the
contents of the DE register pair. Then both of these
register pairs including the BC (Byte Counter) register
pair are decremented.

M CYCLES: 4 T STATES: 16(4,4,3,5) 4 MHZ E.T.: 4.00

Condition Bits Affected:

S: Not affected

Z: Hot affected

H: Reset

P/V: Set if BC-l/O;

reset otherwise

N: Reset

C: Not affected
87

Example :

If the HL register pair contains llllH, memory location

llllH contains the byte 88H, the DE register pair
contains 2222H, memory location 2222H contains byte 66H,
and the BC register pair contains 7H, then the
inst ruction

will result in the following contents in register pairs

and memory addresses:

LDD

HL
(HUH)

DE
(2222H)

BC
11 lOH
88H
222 1H

8 8H
6H

88

LDDR

Operation ; (DE) ^ (HL)L DE^DE-1,. BC <- BC-1

Operands

— I 1 1 1 1 1 1 —

1110 110 1
I I ■ I I I 1 —
ED

— I 1 1 1 1 1 1 —

10 1110
I I 1 1 1 1 1 — .

Description ;

This two byte instruction transfers a byte of data from

the memory location addressed by the contents of the HL
register pair to the memory location addressed by the
contents of the DE register pair. Then both of these
registers as well as the BC (Byte Counter) are
decremented. If decrementing causes the BC to go to
zero, the instruction is terminated. If BC is not zero,
the program counter is decremented by 2 and the
instruction is repeated. Interrupts will be recognized
and two refresh eyeless will be executed after each data
transfer. Note that if BC is set to zero prior to
instruction execution, the instruction will loop through
6 4K bytes.

For BC-0:
M CYCLES: 5 T STATES: 21(4,4,3,5,5) 4 MHZ E.T.: 5.25
For BC=0:

M CYCLES: 4 T STATES: 16(4,4,3,5) 4 MHZ E.T.; 4.00

Condition Bits Affected ;

S: Not affected

Z: Not affected

H: Reset

P/V: Reset

N: Reset

89

Example :

If the HL register pair contains 1114H, the DE register

pair contains 2225H, the BC register pair contains
0003H, and memory locations have these contents:

(1114H) : ASH (2225H) : C5H

(1113H) : 36H (2224H) : 59H
(1112H) : 88H (2223H) : 66H

then after the execution of

LDDR

the contents of register pairs and memory locations will

be:

HL : llllH
DE : 2222H
BC : OOOOH

(1114H) : ASH (2225H) : ASH

(1113H) : 36H (2224H) : 36H
(1112H) : 88H (2223H) : 88H

90

CPI

Operation; A-{HL), HL^HL+1, BC BC-1

Opcode
Operands

— I 1 1 1 1 1 1 —

1110 110 1

1 1 1

I — I — I — I — I — I — I —

ED
Al

Desc r Ip tlon :

The contents of the memory location addressed by the HL

register pair is compared with the contents of the
Accumulator. In case of a true compare, a condition bit
is set. Then HL is incremented and the Byte Counter
(register pair BC) is decremented.
M CYCLES: 4

T STATES: 16(4,4,3,5)

4 MHZ E.T. : 4.00

Condition Bits Affected :

P/V:

N:
C :

Set if result is negative;

reset otherwise

Set if A=(HL);

reset otherwise

Set if borrow from

Bit 4; reset otherwise

Set if BC-1=0;

reset otherwise

Set

Not affected

Example ;

If the Al register pair contains llllH, memory location

llllH contains 3BH, the Accumulator contains 3BH, and
the Byte Counter contains OOOIH, then after the
execution of

91

CPI

the Byte Counter will contain OOOOH, the HL register

pair will contain 1112H, the Z flag in the F register
will be set, and the P/V flag In the F register will be
reset. There will be no effect on the contents of the
Accumulator or address llllH.

92

CPIR

Operation ; A-(HL) , HL^HL+1. BC ^ BC-1

Forma t ;

Opcode Operands
CPIR

1110 110 1 ED
' I I I I I I-

— I 1 1 1 1 1 1 —

1 1 1 1

I L.J 1 1 1 1
Bl

Description ;

The contents of the memory location addressed by the HL

register pair is compared with the contents of the
Accumulator. In case of a true compare, a condition bit
Is set. The HL Is Incremented and the Byte Counter
(register pair BC) Is decremented. If decrementing
causes the BC to go to zero or If A"(HL), the
instruction is terminated. If BC is not zero and
A"(HL), the program counter is decremented by 2 and the
Instruction is repeated. Interrupts will be recognized
and two refresh cycles will be executed after each data
transfer. Note that If BC is set to zero before
instruction execution, the instruction will loop through
64K bytes, if no match Is found.

For BC=0 and A-(HL) :

M CYCLES; 5 T STATES; 21(4,4,3,5,5) 4 MHZ E.T.; 5.25

For BC-0 or A-(HL>;

M CYCLES; 4 T STATES: 16(4,4,3,5) 4 MHZ E.T.: 4.00

93
Condition Bits Affected;

S:

Set If result Is negative;

reset otherwise

Z:

Set if A-(HL) ;

reset otherwise

H:

Set If borrow from

Bit 4; reset otherwise

P/V:

Set If BC-1-0;

reset otherwise

N:

Set

C:

Not affected

Example :

If the HL register pair contains HUH, the Accumulator

contains F3H, the Byte Counter contains 0007H, and
memory locations have these contents:

then after the execution of

the contents of register pair HL will be 1 11 4H , the

contents of the Byte Counter will be 0004H, the P/V flag

in the F register will be set and the Z flag in the F

register will be set.

(llllH)
(1112H)
(1113H)

52H
OOH
F3H

CPIR
94

CPD

Operation : A-(HL). BC BC-1

Opcode Operands
CPD

11101101
— I 1 1 I \ 1 I

10 10 10 1

ED

A9

Description ;
The contents of the memory location addressed by the HL
register pair Is compared with the contents of the
Accumulator. In case of a true compare, a condition bit
Is set. The HL and the Byte Counter (register pair BC)
are decremented.

M CYCLES: 4 T STATES: 16(4,4,3,5) 4 MHZ E.T.: 4.00

Condition Bits Affected ;

S: Set If result Is negative;

reset otherwise
Z: Set If A=(HL);

reset otherwise
H: Set If borrow from

Bit 4; reset otherwise

P/V; Set if BC-1=0;

reset otherwise
N: Set

C: Not Affected
Example :

If the HL register pair contains lUlH, memory location

llllH contains 3BH, the Accumulator contains 3BH, and
the Byte Counter contains OOOIH, then after the
execution of

95

CPD

the Byte Counter will contain OOOOH, the HL register

pair will contain IHOH, the Z flag In the F register
will be set, and the P/V flag in the F register will be
reset. There will be no effect on the contents of the
Accumulator or address llllH.

96

CPDR
Operation ; A - (HL) , HL ^ HL-1 , BC ^ BC-1

Format ;

Opcode

Operands

CPDR

1110 110 1

ED

10 1110 1
B9

Description :

The contents of the memory location addressed by the HL

register pair Is compared with the contents of the
Accumulator. In case of a true compare, a condition bit
is set. The HL and BC (Byte Counter) register pairs are
decremented. If decrementing causes the BC to go to
zero or if A=(HL), the instruction is terminated. If BC
is not zero and A"(HL), the program counter is
decremented by 2 and the instruction is repeated.
Interrupts will be recognized and two refresh eyeless
will be executed after each data transfer. Note that if
BC is set to zero prior to instruction execution, the
Instruction will loop through 64K bytes, if no match is
found .

For BC-0 and A-(HL):

M CYCLES: 5 T STATES: 21(4,4,3,5,5) 4 MHZ E.T.: 5.25

For BC=0 or A-(HL):

M CYCLES: 4 T STATES: 16(4,4,3,5) 4 MHZ E.T.: 4.00

97
Condition Bits Affected ;

S :

Set If result Is negative;

reset otherwise

Z :

%et if A=(HL);

reset otherwise

H:

Set if borrow from

Bit 4; reset otherwise

P/V:

Set if BC-1-0;

reset otherwise

N:

Set

C:

Not affected

Example ;
If the HL register pair contains 11 1 8H , the Accumulator
contains F3H, the Byte Counter contains 0007H, and
memory locations have these contents:

then after the execution of

the contents of register pair HL will be I115H, the

contents of the Byte Counter will be 0004H, the P/V flag
In the F register will be set, and the Z flag in the F
register will be set.

(1118H)
(1117H)
(1116H)

52H
OOH
F3H

CPDR
98

-8 BIT mmJK AND LOGICAL GROUP-

99

ADD A, p

Operation: A A + r

Fornat :

Opcode

Operands

ADD
A,r

1 -^ r-*

Description :

The contents of register r are added to the contents

the Accumulator, and the result is stored in the
Accumulator. The symbol r identifies the registers
A,B,C,D,E,H or L assembled as follows In the object
code :

M CYCLES: 1 T STATES: 4 4 MHZ E.T.: 1,00

Condition Bits Affected:

S:

Set if result is negative;

reset otherwise

Z:

Set if result is zero;

reset otherwise

H:

Set if carry from

Bit 3; reset otherwise

P/V:

Set if overflow;
reset otherwise

N:

Reset

C:

Set if carry from

Bit 7; reset otherwise

Register

A
B
C
D
E
H
L

111

000
001
010

oil

100
101

100

Ex am p 1 c :

If the contents of the Accumulator are 44H, and the

contents of register C are IIH, after the execution of
ADD A,C

the contents of the Accumulator will be 55H.

101

ADD A, n

Format :

Operation: A •<- A + n

Opcode
ADD

Operands

A,n
— I 1 1 1 1 1 1 —

1 1 1 1
— I — I — I — I I I — I —

-1 — I — I — I — r-

C6

Description:

The Integer n is added to the contents of the

Accumulator and the results are stored in the
Accumulator .

M CYCLES: 2 T STATES: 7(4,3)

Condition Bits Affected:

4 MHZ E.T. : 1. 75

P/V:
N:
C:

Set if result is negative;

reset otherwise

Set if result is zero;

reset otherwise

Set if carry from

Bit 3; reset otherwise

Set if overflow;

reset otherwise

Reset

Set if carry from

Bit 7; reset otherwise

Example :

If the contents of the Accumulator are 23H, after the

execution of

ADD A,33H

the contents of the Accumulator will be 56H,

102

ADD A. CHU

Operation; A^A + (HL)

Format :

Opcode

Operands

ADD
A, (HL)

1 1 1

86

Description:

The byte at the memory address specified by the contents

of the HL register pair Is added to the contents of the
Accumulator and the result is stored in the Accumulator.

M CYCLES: 2 T STATES: 7(4,3) 4 MHZ E,T.: 1.75

Condition Bits Affected:

S: Set if result is negative;

reset otherwise
Z: Set if result is zero;
reset otherwise
H: Set If carry from

Bit 3; reset otherwise

P/V: Set if overflow;

reset otherwise
N: Reset

C: Set if carry from

Example :

If the contents of the Accumulator are AOH, and the

content of the register pair HL is 2323n, and memory
location 2323H contains byte 08H, after the execution of

Bit 7;

reset otherwise

ADD A,(HL)
the Accumulator will contain ASH.

103

ADD A. CIX+dD

Operation! A-<-A + (IX+d)

Opcode
ADD

Operands
A, (IX+d)
1 1

DD

Description ;

The contents of the Index Register (register pair IX) is

added to a two's complement displacement d to point to
an address in memory. The contents of this address is
then added to the contents of the Accumulator and the
result is stored in the Accumulator.

M CYCLES: 5 T S^TATES : 19(4,4,3,5,3) 4 MHZ E.T.: 4.75

Condition Bits Affected :

S: Set If result is negative;

reset otherwise
Z: Set If result is zero;

reset otherwise
H: Set if carry from

Bit 3; reset otherwise

P/V: Set if overflow;
reset otherwise
N: Reset

C: Set if carry from

Bit 7; reset otherwise

Example :

If the Accumulator contents are IIH, the Index Register

IX contains lOOOH, and if the content of memory location

104

1005H is 22H, after the execution of

ADD A, (IX+5H)
the contents of the Accumulator will be 33H.

105

ADD A, ClY+d]
Operation ; A A+( I Y+d)
Format ;

Opcode
ADD

Operands
A, (lY+d)

— I 1 —

1 1
I I

1 1

FD

Description ;

The contents of the Index Register (register pair lY) is

added to a two's complement displacement d to point to
an address in memory. The contents of this address is
then added to the contents of the Accumulator and the
result is stored in the Accumulator.

M CYCLES: 5 T STATES: 19(4,4,3,5,3) 4 MHZ E.T.: 4.75

Condition Bits Affected :

S:

Set if result is negative;

reset otherwise

Z:

Set if result is zero;

reset otherwise

H:

Set if carry from

Bit 3; reset otherwise

P/V:

Set if overflow;

reset otherwise

N:

Reset

C:
Set if carry from bit 7;

reset otherwise

Example :

If the Accumulator contents

pair lY contains lOOOH, and

are llH , the Index Register

if the content of memory

106

location 1005H Is 22H, after the execution of

ADD A, (IY+5H)
the contents of the Accumulator will be 33H.
107

ADC A. s

Operation: A ^ A + s + CY

Format :

Opcode
ADC

Operands
A, s

The s operand is any of r ,n , ( HL) , ( IX+d) or (lY+d) as

defined for the analogous ADD instruction. These
various possible opcode-operand combinations are
assembled as follows in the object code:
ADC A,r
ADC A,n

ADC A,(HL)
ADC A, (IX+d)

ADC A,(IY+d)

*r identifies registers B,C,D,E

1 1

1 1
__l

1 1
I

1 1
1 1

1 1

CE

8E
DD
8E

FD
8E

follows in the object code field above:

H,L or A assembled as

108

Register r
B 000
C 001
D 010
E Oil
H 100
L 101
A 111

Description;

The s operand, along with the Carry Flag ("C" in the F

register) is added to the contents of the Accumulator,
and the result Is stored in the Accumulator.

INSTRUCTION M CYCLES T STATES 4 MHZ E.T.

ADC A,r 1 4 1.00

ADC A,n 2 7(4,3) 1.75

ADC A,(HL) 2 7(4,3) 1.75

ADC A,(IX+d) 5 19(4,4,3,5,3) 4.75

ADC A,(IY+d) 5 19(4,4,3,5,3) 4,75

Condition Bits Affected ;

S: Set if result is negative;

reset otherwise
Z; Set if result is zero;

reset otherwise
H: Set if carry from

Bit 3; reset otherwise

P/V: Set if overflow;

reset otherwise
N; Reset

C: Set if carry from

Bit 7; reset otherwise

Example :

If the Accumulator contains 16H, the Carry Flag is set,

the UL register pair contains 6666H, and address 6666H
contains lOH, after the execution of

ADC A,(HL)

the Accumulator will contain 27H.

109

SUB s
operation: A A - s

Format ;

Opcode

SUB

Operands

The s operand Is any of r ,n , ( HL ) , ( IX+d) or (lY+d) as

defined for the analogous ADD instruction. These
various possible opcode-operand combinations are
assembled as follows in the object code:

SUB (HL)
SUB (IX+d)
SUB (lY+d)

*r identifies registers B

D6

96

DD
96

FD
96

follows in the object code field above:

C,D,E,H,L or A assembled as
110

Register

000

001

010

Oil
H

100

101

111

Description ;

The s operand is subtracted from the contents of the

Accumulator, and the result is stored in the
Acc umu 1 a t o r .

INSTRUCTION
T STATES

4 MHZ E.T.

SUB r
SUB n
SUB (HL)
SUB (IX+d)
SUB (lY+d)

7(4,3)
7(4,3)

19(4, 4,3,5.3)
19(4,4,3,5,3)

1 . 00
1 .75
1 . 75
4. 75
4.75
Condition Bits Affected:

S: Set if result is negative;

reset otherwise
Z: Set if result is zero;

reset otherwise
H: Set if borrow from

Bit 4; reset otherwise

P/V: Set if overflow;

reset otherwise
N : Set

C: Set if borrow;

reset otherwise

Examp 1 e :

If the Accumulator contains 29H and register D contains

IIH, after the execution of

SUB D
the Accumulator will contain 18H.

Ill

SBC A, s

Operation: A ^ A - s - CY

Format :

Opcode

Operands
A,s

The s operand is any of r ,n , (HL) , ( IX+d) or (lY+d) as

defined for the analogous ADD instructions. These
various possible opcode-operand combinations are
assembled as follows in the object code:

SBC A,r
SBC A,n

SBC A,(HL)
SBC A, (IX+d)

SBC A,(IY+d)

DE

9E
DD
9E

FD
9E

*r identifies registers B,C,D,E,U,L or A assembled as

follows in the object code field above:
Register

000

001

010

Oil

100
L

101

111

Descr ipt ion :

The s operand, along with the Carry Flag ("C" In the F

register) is subtracted from the contents of the
Accumulator, and the result Is stored in the
Accumul a t or .

INSTRUCTION

SBC A,r
SBC A,n
SBC A, (HL)
SBC A, (IX+d)
SBC A, (lY+d)
M CYCLES

2
2
5
5

T STATES
4

7(4,3)
7(4,3)

19(4,4,3,5,3)
19(4,4,3,5,3)

Condition Bits Affected;

S: Set if result is negative;

reset otherwise
Z: Set If result is zero;

reset otherwise
H: Set if borrow from

Bit 4; reset otherwise

P/V: Set if overflow;

reset otherwise
N: Set

C: Set if borrow;

reset otherwise

4 MHZ E.T.

1.00
1 . 75
1.75
4. 75
4. 75

Examp 1 e :

If the Accumulator contains 16H, the carry flag is set,

the HL register pair contains 3433H, and address 3433H
contains 05H, after the execution of

SBC A, (HL)

the Accumulator will contain lOH.

113

AND s

Operation: A A A s

Opcode

AND

Operands

The s operand is any of r ,n , (HL) , ( IX+d) or (lY+d), as

defined for the analogous ADD instructions. These
various possible opcode-operand combinations are
assembled as follows in the object code:
AND r

AND n

AND (HL)
AND (IX+d)

AND (lY+d)

E6

A6

DD
A6

FD
A6

*r identifies registers B,C,D,E,U,L or A assembled as

follows in the object code field above:

114

Register £

000

001
D

010

Oil

100

101

111
Description :

A logical AND operation is

specified by the s operand
Accumulator; the result is

INSTRUCTION M CYCLES

performed between the byte

and the byte contained in the
stored in the Accumulator.

T STATES 4 MHZ E.T.

AND r 1 4 1.00

AND n 2 7(4,3) 1.75

AND (HL) 2 7(4,3) 1.75

AND (IX+d) 5 19(4,4,3,5,3) 4.75

AND (IX+d) 5 19(4,4,3,5,3) 4.75

Condition Bits Affected;

S: Set if result is negative;

reset otherwise
Z: Set if result is zero;

reset otherwise
H: Set
P/V: Set if parity even;

reset otherwise
N: Reset
C: Reset

Exampl e :

If the B register contains 7BH (0111 1011) and the

Accumulator contains C3H (1100 0011) after the execution
of

AND B

the Accumulator will contain 43H (01000011).

115

OR s

Operation ; A^AVs
Format ;

Opcode Operands

OR s

The s operand is any of r ,n , (HL) , ( IX+d) or (lY+d), as

defined for the analogous ADD instructions. These
various possible opcode-operand combinations are
assembled as follows in the object code;

OR n

OR (HL)
OR (IX+d)

OR (lY+d)
F6

DD
B6

FD

B6

*r identifies registers B,C,D,E,H,L or A assembled as

follows in the object code field above:

116

Register
000
001
010
Oil
100
101
111

Description ;

A logical OR operation Is performed between the byte

specified by the s operand and the byte contained In the

Accumulator; the result Is stored In the Accumulator.

INSTRUCTION

OR r
OR n
OR (HL)
OR (IX+d)
OR (lY+d)

M CYCLES

1
2
2
5
5

T STATES
4

7(4,3)
7(4,3)

19(4,4,3,5, 3)
19(4,4,3,5,3)

Condition Bits Affected:

S: Set if result Is negative;

reset otherwise
Z: Set if result Is zero;

reset otherwise
H: Reset
P/V: Set If parity even;

reset otherwise
N: Reset
C: Reset

4 MHZ E.T.

1.00
1 . 75
1.75
4.75
4.75

Example :

If the H register contains 48H (010001000) and the

Accumulator contains 1 2H (00010010) after the execution
of

the Accumulator will contain 5AH (01011010).

117

XOR s
Operation: A*-A®s

Format ;

Opcode

XOR

Operands

The s operand Is any of r,n, (HL),(IX+d) or (lY+d), as

defined for the analogous ADD instructions. These
various possible opcode-operand combinations are
assembled as follows in the object code:

XOR (HL)
XOR (IX+d)
XOR (lY+d)

EE

AE
DD
AE

FD
AE

*r identifies registers B,C,D,E,H,L or A assembled as

follows in the object code field above:

118

Register

000
001
010
Oil
100
101
111

Description :

A logical exclusive-OR operation is performed between

the byte specified by the s operand and the byte
contained in the Accumulator; the result is stored In
the Accumulator.

INSTRUCTION

XOR r
XOR n
XOR (HL)
XOR (IX+d)
XOR (lY+d)

M CYCLES

1
2
2
5
5
T STATES
4

7(4,3)
7(4,3)

19(4,4,3,5,3)
19(4,4,3,5,3)

4 MHZ E.T.

1 . 00
1.75
1. 75
4. 75
4. 75

Condition Bits Affected;

S: Set If result is negative;

reset otherwise
Z: Set if result is zero;
reset otherwise
H: Reset
P/V: Set if parity even;

reset otherwise
N: Reset
C: Reset

Example ;

If the Accumulator contains 96H (10010110), after the

execution of

XOR SDH (Note: SDH = 01011101)

the Accumulator will contain CBH (11001011).

119

CP s

Operation: A-s
Foraat ;

Opcode Operands

CP s

The s operand Is any of r ,n , (HL) , ( IX+d) or (lY+d), as

defined for the analogous ADD Instructions. These
various possible opcode-operand combinations are
assembled as follows In the object code:

CP n

CP (HL)
CP (IX+d)

CP (lY+d)

FE

BE

1 DD
"ol BE

1 FD

BE

*r Identifies registers B,C,D,E,H,L or A assembled as

follows In the object code field above:

120

Register

B 000
C 001
D 010
E Oil
H 100
L 101
A 111

Description ;
The contents of the s operand are compared with the
contents of the Accumulator. If there is a true
compare, the Z flag is set. The execution of this
Instruction does not affect the contents of the
Accumulator.

INSTRUCTION M CYCLES T STATES 4 MHZ

CP r 1 4 1.00

CP n 2 7(4,3) 1.75

CP (HL) 2 7(4,3) 1.75

CP (IX+d) 5 19(4,4,3,5,3) 4.75

CP (lY+d) 5 19(4,4,3,5,3) 4.75

Condition Bits Affected ;

S; Set if result is negative;

reset otherwise
Z; Set if result is zero;

reset otherwise
H; Set if borrow from

Bit 4; reset otherwise

P/V; Set if overflow;
reset otherwise
N; Set

C; Set if borrow;

reset otherwise

Example ;

If the Accumulator contains 63H, the HL register pair

contains 6000H and memory location 6000H contains 60H
the instruction

CP (HL)

will result in the P/V flag in the F register being

reset.

121

INC r

Operation; r r + 1

Format :
Opcode

Operands

INC

— ^1

Description:

Register r is incremented. r identifies any of the

registers A,B, C,D,E,H or L, assembled as follows in the
object code.
M CYCLES: 1 T STATES: 4 4 MHZ E.T.: 1.00
Condition Bits Affected:

S:

Set if result is negative;

reset otherwise

Z:

Set if result is zero;

reset otherwise

H:

Set if carry from

Bit 3; reset otherwise

P/V:

Set If r was 7FH before

operation; reset otherwise

N:

Reset

C:

Not affected

Register
r

A
B
C
D
E
H
L

111
000
001
010

oil

100
101

122

Ex am p 1 e :
If the contents of register D are 2811, after the
execution of

INC D

the contents of register D will be 29H.

123

INC CHU

Operation: (HL) ^ {HL)+1

Format :

Opcode

Operands
INC

(HL)

110 10

34

Description:

The byte contained in the address specified by the

contents of the HL register pair is incremented.

M CYCLES: 3 T STATES: 11(4,4,3) 4 MHZ E.T.: 2.75

Condition Bits Affected:

reset otherwise
Z:

Set if result is zero;

reset otherwise

H:

Set if carry from

Bit 3; reset otherwise

P/V:

Set if (HL) was 7FH before

operation; reset otherwise

N:

Reset

C:

Not Affected

Example :

If the contents of the HL register pair are 3434H, and

the contents of address 3434H are 82H, after the
execution of

memory location 3434H will contain 83H.

Set if result is negative;

INC (HL)

124

INC ClX+d]

Operation: (IX+d) (IX+d)+1

Format :

Opcode

INC

Operands
(IX+d)
DD

34

Description :

The contents of the Index Register IX (register pair IX)

are added to a two's complement displacement integer d
to point to an address in memory. The contents of this
address are then incremented.

M CYCLES: 6 T STATES: 23(4,4,3,5,4,3) 4 MHZ E.T.: 5.75

Condition Bits Affected:

P/V:

N:
C:

Set if result is negative;

reset otherwise
Set if result Is zero;

reset otherwise

Set if carry from

Bit 3; reset otherwise

Set if (IX+d) was 7FH before

operation; reset otherwise

Reset

Not affected

125

Example :

If the contents of the Index Register pair IX are 2020H,

and the memory location 2030H contains byte 3AH, after
the execution of

INC (IX+IOH)

the contents of memory location 2030H will be 35H.

INC ClY+d]

Operation: (lY+d)^ (IY+d)+1

Opcode

INC

Operands
(lY+d)

— I 1 1 —

1111

110 1
I I I
FD
34

Description;

The contents of the Index Register lY (register pair lY)

are added to a two's complement displacement integer d
to point to an address in memory. The contents of this
address are then incremented.

M CYCLES: 6 T STATES: 23(4,4,3,5,4,3) 4 MHZ E.T.: 5.75

Condition Bits Affected :

S: Set if result is negative;

reset otherwise
Z: Set if result is zero;

reset otherwise
H: Set if carry from

Bit 3; reset otherwise

P/V: Set if (lY+d) was 7FH before

operation; reset otherwise

N: Reset
C: Not Affected
127

Example;

If the contents of the Index Register pair lY are 2020H,

and the memory location 2030H contain byte 34H, after
the execution of

INC (lY+lOH)

the contents of memory location 2030H will be 35H.

-GENERAL PURPOSE ARmffJIC AND CPU CONTROL GROUPS-

131

Register r

B
000

001

010

Oil

100

101
A

111

Description :

The byte specified by the m operand Is decremented.

INSTRUCTION M CYCLES T STATES 4 MHZ E.T.

DEC r 1 4 1.00

DEC (HL) 3 11(4,4,3) 2.75

DEC (IX+d) 6 23(4,4,3,5,4,3) 5.75

DEC (lY+d) 6 23(4,4,3,5,4,3) 5.75

Condition Bits Affected;

S:

Set If result Is negative;

reset otherwise

Z:

Set If result is zero;

reset otherwise

H:

Set If borrow from

Bit 4, reset otherwise

P/V:

Set If m was 80H before

operation; reset otherwise

N:

Set

C:

Not affected

Example ;

If the D register contains byte 2AH, after the execution

of

DEC D

register D will contain 29H.

130
Condition Bits Affected;

S:

Set if most significant bit

of Acc. Is 1 after operation;

reset otherwise

Z:

Set If Acc, Is zero after operation

reset otherwise
U:

See Instruction

P/V:

Set if Acc. is even parity after

operation; reset otherwise

N:

Not affected

C:

See instruction

Ex anple ;

If an addition operation is performed between 15 (BCD)

and 27 (BCD), simple decimal arithmetic gives this
resul t :

15
+2 7
42

But when the binary representations are added in the

Accumulator according to standard binary arithmetic,

0001 0101
+0010 QUI
0011 1100 3C

the sum Is ambiguous. The DAA instruction adjusts this

result so that the correct BCD representation Is
obtained :

0011 1100
+0000 QUO
0100 0010 - 42

133

DAA

Operation ;
Format ;

Opcode
BAA

— I 1 1 1 1 1 1 —

1 1 1 1
I I I I I L— I

27

Description:

This instruction conditionally adjusts the Accumulator

for BCD addition and subtraction operations. For
addition (ADD, ADC, INC) or subtraction (SUB,
SBC.DEC.NEG) , the following table indicates the
operation performed:
HEX

HEX

VALUE

VALUE

NUMBER
C

IN

IN

ADDED

BEFORE

UPPER

BEFORE

LOWER

TO
AFTER

OPERATION

DAA

DIGIT

DAA

DIGIT

BYTE

DAA

(bit
(bit

7-4)

3-0)

0-9
0-9

00

0-8

A-F

06

ADD )
0-9

0-3

06

ADC >

A-F

0-9
60

INC )

9-F

A-F

66

1
A-F

0-3

66

0-2

0-9

60
1

0-2

A-F

66

0-3

1
0-3

66

SUB )

0-9

0-9

00

SBC (
0-8

6-F

FA

DEC (

7-F

0-9
AO

NEG ;

6-F

6-F

9A

M CYCLES: I T STATES: 4 4 MHZ E.T.: 1.00

132

Operation : A 0-A
Format ;

Opcode
NEG

— I 1 1 1 1 1 1 —

1110 110 1

— I 1 1 1 1 1 1 —

1 1
__l I I I I — I — I —

ED
44

Description ;

The contents of the Accumulator are negated (two's

complement). This is the same as subtracting the
contents of the Accumulator from zero. Note that 80H
left unchanged.

M CYCLES: 2 T STATES: 8(4,4) 4 MHZ E.T.: 2.00

Condition Bits Affected;

S:

Set If result Is negative;

reset otherwise

Z:

Set If result Is zero;

reset otherwise

H;

Set If borrow from

Bit 4; reset otherwise

P/V:

Set If Acc. was 80H before

operation; reset otherwise

N:

Set

C;
Set If Acc. was not OOH before

operation; reset otherwise

135

CPL

Operation ; A A
Format !

Opcode
CPL

— I 1 1 1 1 1 1 —

10 1111

2F
Description ;

The contents of the Accumulator (register A) are

Inverted (I'a complement).

M CYCLES: 1 T STATES: 4 4 MHZ E.T.: 1.00

Condition Bits Affected ;

S: Not affected

Z: Not affected

H: Set

P/V: Not affected

N; Set

C: Not affected

Example :

If the contents of the Accumulator are 1011 0100, after

the execution of

CPL
the Accumulator contents will be 0100 1011.

134

operation; CY-«-CY

Opcode
CCF

— I 1 1 1 1 1 1 —

00111111
I I I I I I — I —

3F

Description !

The Carry flag In the F register Is Inverted.

M CYCLES: 1 T STATES: 4 4 MHZ E.T.: 1.00
Condition Bits Affected :

S: Not affected

Z: Not affected

H: Previous carry will be copied

P/V: Not affected

N: Reset

C: Set If CY was before

operation; reset otherwise

137

Example :

If the contents of the Accumulator are

1
after the execution of
NEG

the Accumulator contents will be

1
136

NOP

Operation: —

Opcode
NOP

— 1 1 1 1 1 1 1 —

00000000
I I I I I I I

00

Description:

The CPU performs no operation during this machine cycle.

M CYCLES: 1 T STATES: 4 4 MHZ E.T.: 1.00
Condition Bits Affected: None

139

SCF

Operation ; CY 1
Format ;

Opcode
SCF

1 T 1 1 1 1 1

110 111

-t-

37
Desc rlpt Ion ;

The Carry flag in the F register Is set.

M CYCLES: 1 T STATES: 4 4 MHZ E.T.: 1.00

Condition Bits Affected:

S :
Z :
H:
P/V:
N:
C :

Not affected
Not affected
Reset

Not affected

Reset

Set
138

Operation: IFF-*-0

Format :

Opcode
DI

— I 1 1 1 1 1 1 —

11110 11
— I — I — I — I — I — |_l —

F3

Description:

DI disables the maskable Interrupt by resetting the

Interrupt enable f lip-f lopB< IFFl and IFF2) . Note that
this instruction disables the maskable interrupt during
its execution.

M CYCLES: 1 T STATES: 4 4 MUZ E.T. : 1.00

Condition Bits Affected: None

Example:

When the CPU executes the instruction

DI

the maskable interrupt is disabled until it IS

subsequently re-enabled by an EI Instruction. The CPU
will not respond to an Interrupt Request (INT) signal.

141

HALT
operation;

format ;

Opcode
HALT

— I 1 1 1 1 1 1 —

1110 110
I I 1 1 1 1 1 —

76

Description:

The HALT Instruction suspends CPU operation until a

subsequent interrupt or reset Is received. While In the
halt state, the processor will execute MOP's to maintain
memory refresh logic.

M CYCLES: 1 T STATES: 4 4 MHZ E.T.: 1.00

Condition Bits Affected: None
140

IM

Operation :

Format :

Opcode

Operands

IM
1110 110 1

ED

1 1 1

46

Description :

The IM instruction sets interrupt mode 0. In this

mode the interrupting device can insert any instruction
on the data bus for execution by the CPU. The first
byte of a multi-byte instruction is read during the
interrupt acknowledge cycle. Subsequent bytes are read
in by a normal memory read sequence.

M CYCLES: 2 T STATES: 8(4,4) 4 MHZ E.T.: 2.00

Condition Bits Affected:

None

143

Operation; IFF 1
Format ;

Opcode
EI

— I 1 1 1 1 1 1 —

1 1 1 1 1 Q 1 1
— I 1 1 1 1 1— I

FB

Description;
The enable interrupt Instruction will set both Interrupt
enable flip flops (IFFl and XFF2) to a logic '1'
allowing recognition of any maskable Interrupt. Note
that during the execution of this instruction and the
following instruction, maskable interrupts will be
disabled.

M CYCLES: 1 T STATES: A 4 MHZ E.T.: 1.00

Condition Bits Affected ; None
Example ;

When the CPU executes instruction

EI

RETT

the maskable interrupt will be enabled after the

execution of the RETI Instruction.

142

IM

Operation ; —
Format ;

Opcode

Operands

IM

1110 110 1

ED

—I — I — I — I — I — r — I —

10 11110
5E

Description :

The IM 2 instruction sets the vectoreed Interrupt mode

2. This mode allows an indirect call to any memory
location by an 8 bit vector supplied from the peripheral
device. This vector then becomes the least significant
8 bits of the indirect pointer while the I register In
the CPU provides the most significant 8 bits. This
address points to an addreess in a vector table which is
the starting address for the interrupt service routine.

M CYCLES: 2 T STATES: 8(4,4) 4 MHZ E.T.: 2.00

Condition Bits Affected ;

None

145
IM 1

Operation: —

Opcode
IM

Operands

1 1 1
I I

1 1
— I I —
1
I — I —

10 10 110
I I I I I

ED
56

Description:

The IM instruction sets interrupt mode 1. In this mode

the processor will respond to an Interrupt by executing
a restart to location 0038H.

M CYCLES: 2 T STATES: 8(4,4) 4 MHZ E.T.: 2.00

Condition Bits Affected: None

144

-16 BIT ARIWeiC GROUP-

146

Example :

If register pair HL contains the integer 424211 and

register pair DE contains llllH, after the execution of

ADD HL.DE

the HL register pair will contain 5353H.

148

ADD HL, ss

Operation: HL-^HL+ss

Format :
Opcode

Operands

ADD

HL, ss

OS, Si, 0. 0, 1

Description:

The contents of register pair ss (any of register pairs

BC,DE,HL or SP) are added to the contents of register
pair HL and the result is stored in HL. Operand ss is
specified as follows in the assembled object code.
M CYCLES: 3 T STATES: 11(4,4,3) 4 MHZ E.T.: 2.75
Condition Bits Affected:

S:

Not affected

Z:

Not affected

H:

Set if carry out of

Bit 11; reset otherwise

P/V:

Not affected
N:

Reset

C:

Set if carry from

Register
Pair

ss

BC
DE
HL
SP

00
01
10
11

Bit 15; reset otherwise

147

Example :

If the register pair BC contains 2222H, register pair HL

contains 5437H and the Carry Flag is set, after the
execution of

ADC HL.BC

the contents of HL will be 765AH.

150

ADC HL. ss
Operation: HL<-HL+ss+CY

Format :

Opcode

ADC

Operands
HL,ss

— I 1 1 1 1 1 \ —

1110 110 1
I I I — I — I — I — I —

— I — I — I — I — I — I — I —

1 s s 1 1
I I I I I I — I
ED

Description:

The contents of register pair ss (any of register pairs

BC.DE.HL or SP) are added with the Carry Flag (C flag In
the F register) to the contents of register pair HL, and
the result is stored in HL. Operand ss is specified as
follows in the assembled object code.

Register
Fair ss

BC
DE
HL
SP

00
01
10
11
M CYCLES: 4 T STATES: 15(4,4,4,3) 4 MHZ E.T.: 3.75

Condition Bits Affected ;

S: Set if result is negative;

reset otherwise
Z: Set if result is zero;

reset otherwise
H: Set if carry out of

Bit 11; reset otherwise

P/V: Set if overflow;

reset otherwise
N: Reset

C: Set if carry from

Bit 15; reset otherwise

149

Ex am p 1 e :
If the contents of the HL register pair are 9999H, the
contents of register pair DE are 111111, and the Carry
Flag is set, after the execution of

SBC UL.DE

the contents of HL will be 8887H.

152

SBC HL, ss

Operation : HL-<-HL-ss-CY
Format :

Opcode Operands
SBC HL.ss

I'l'i'o'i'i'o'i

ED
1 s s 1
1 I I 1 1 1 1 —

Description :

The contents of the register pair ss (any of register

pairs BC,DE,HL or SP) and the Carry Flag (C flag In the
F register) are subtracted from the contents of register
pair HL and the result is stored in HL . Operand ss is
specified as follows in the assembled object code.

EC
DE
HL
SP

00
01
10
11

H CYCLES: 4 T STATES: 15(4,4,4,3) 4 MHZ E.T.: 3.75

Condition Bits Affected ;

S: Set if result is negative;

reset otherwise
Z: Set if result is zero;

reset otherwise
H: Set if a borrow from

Bit 12;reset otherwise

P/V: Set if overflow;

reset otherwise
N: Set

C: Set if borrow;

reset otherwise

151

Example :

If the contents of Index Register IX are 333H and the

contents of register pair BC are 5555H, after the
execution of
ADD IX, BC

the contents of IX will be 8888H.

154

ADD IX. pp

Operation: IX-«-IX + pp

Opcode

Operands
IX, pp

I'l'o'i'i'i'o'i

I I 1 I I I I
DD

o'o'p'p'i'o'o'i

I I I I I I I

Description:

The contents of register pair pp (any of register pairs

BC.DE.IX or SP) are added to the contents of the Index
Register IX, and the results are stored in IX, Operand
pp is specified as follows in the assembled object code.

Register
Pair pp

BG
DE
IX
SP

00
01
10
11

M CYCLES: 4 T STATES: 15(4,4,4,3) 4 HHZ E.T.: 3.75

Condition Bits Affected:

S:

Not

affected

Z:

Not

affected

H:
Set

if carry out of

Bit

11; reset otherwise

P/V:

Not

affected

N:

Reset

C:
Set

if carry from

Bit

15; reset otherwise

153

Example ;

If the contents of Index Register lY are 333H and the

contents of register pair BC are 555H, after the
execution of

ADD lY.BC

the contents of lY will be 8888H.

156

ADD lY, rr

Operation: lY-^IY+rr

Opcode

Operands
lY.rr

— I 1 1 1 1 1 1 —

1111110 1
— I I I 1 I I I

--T \ 1 1 1 1 1 —

r r 1 1
— I I I — I I I I
FD

Description:

The contents of register pair rr (any of register pairs

BC,DE,IY or SP) are added to the contents of Index
Register lY, and the result Is stored in lY. Operand rr
is specified as follows in the assembled object code.

Register
Pair rr

BC
DE
lY
SP

00
01
10
11

M CYCLES:
T STATES: 15(4,4,4,3) 4 MHZ E.T.: 3.75

Condition Bits Affected:

S: Not affected
Z; Not affected
H: Set If carry out of

Bit 11; reset otherwise

P/V: Not affected
N: Reset

C: Set if carry from

Bit 15; reset otherwise

INC

Operation! IX <*- IX + 1
Format :

Opcode

Operands

IX

— I 1 1 1 1 1 1 —

110 1110 1
— I — I — I — I — I 1 I

— I — I — I — I — I — I — I —

1 1 1
I I I I ' I I

DD
23
Description:

The contents of the Index Register IX are Incremented.

M CYCLES: 2 T STATES: 10(4,6) 4 MHZ E.T.: 2.50
Condition Bits Affected: None

Example :

If the Index Register IX contains the Integer 3300H

after the execution of

INC IX

the contents of Index Register IX will be 3301H.

158

INC ss

Operation: ss*-ss+1
Format :

Opcodes

Operands

INC

ss

s s 1 1

Description:

The contents of register pair ss (any of register pairs

BC, DE.HL or SP) are incremented. Operand ss is
specified as follows in the assembled object code.
M CYCLES: 1 T STATES: 6 4 MHZ E.T. 1.50
Condition Bits Affected : None

Example :

If the register pair contains lOOOH, after the execution

of

INC HL
HL will contain lOOlH.

Register

ss

BC
DE
HL
SP

CO
01
10
11
157

DEC ss

Operation: ss-<-ss-1

Format :

Opcode

Operands

DEC

ss
s s 1 1 1

I I ■ I I I L

Description:

The contents of register pair ss (any of the register

pairs BC,DE,HL or SP) are decremented. Operand ss is
specified as follows in the assembled object code.

M CYCLES: 1 T STATES: 6 4 MHZ E.T.: 1,50

Condition Bits Affected ; None

Example:

If register pair HL contains lOOlH, after the execution

of

DEC HL

the contents of HL will be lOOOH.

Pair
ss

BC
DE
HL
SP

00
01
10
11

160

lY

Operation; IY-«-IY+1
Format :

Opcode

Operands

INC

lY

1111110 1
—I I I \ 1 I L_

FD

1 1 1
23

Description:

The contents of the Index Register lY are Incremented.

M CYCLES: 2 T STATES: 10(4,6) 4 MHZ E.T.: 2.50
Condition Bits Affected : None

Example:

If the contents of the Index Register are 2977H, after

the execution of

the contents of Index Register lY will be 2978H.

INC lY

159

DEC
Operation: IY-*-|Y-1

Opcode
DEC

Operands

lY

— I 1 1 1 1 1 1 —

1111110 1
— I — I — I I I I I

— I — I — 1 — I — I — I — I —
10 10 11
I I I I I ■ '

FD
2B
Description:

The contents of the Index Register lY are decremented.

M CYCLES: 2 T STATES: 10 (4,6) 4 MHZ E,T.: 2.50
Condition Bits Affected: None

Example :

If the contents of the Index Register lY are 7649H,

after the execution of

DEC lY

the contents of Index Register lY will be 7648H.

162

DEC IX

Operation: IX-«-IX-1
Fo rmat :

Opcode

Operands

DEC

IX

110 1110 1

DD

10 10 11

2B
Description:

The contents of Index Register IX are decremented.

M CYCLES: 2 T STATES: 10(4,6) 4 MHZ E,T.: 2.50

Condition Bits Affected ; None

Example:

If the contents of Index Register IX are 2006H, after

the execution of

DEC IX

the contents of Index Register IX will be 2005H.

161

-ROTATE AND SHIF GROUP-

163
Example :

If the contents of the Accumulator are

7 6 5 4 3 2 1

[i|o|o[o|i|o[o|o|

after the execution of

RLCA

the contents of the Accumulator and Carry Flag will be

C 7 6 5 4 3 2 1

IT] |o|o|o|i|o|oio|i|

165

RLCA

Ope r
Fo rma t ;

Opcode Operands
1 1 1

__l I I I I — I I —

07

Description :

The contents of the Accumulator (register A) are rotated

left one bit position. The sign bit (bit 7) is copied
into the Carry Flag and also into bit 0. Bit is the
least significant bit.

M CYCLES: 1 T STATES 4 4 MHZ E.T.: 1.00

Condition Bits Affected :

S: Not affected

Z: Not affected

H: Reset

P/V: Not affected

N: Reset
C: Data from Bit 7 of Acc.

164

Example :

If the contents of tlie Accumulator and the Carry Flag

are

C 7 6

10 1

2
1

after the execution of

RLA

the contents of the Accumulator and the Carry Flag will

be
C 7 6

II 1 1 1

1
1

167

RLA

Operation:

Format ;
Opcode

Operands

RLA

1 1 1 1

17

Desc ript ion :

The contents of the Accumulator (register A) are rotated

left one bit position through the Carry Flag. The
previous content of the Carry Flag is copied into bit 0.
Bit is the least significant bit.

M CYCLES: 1 T STATES: 4 4 MHZ E.T.: 1.00

Condition Bits Affected:

S
Z
H

Not affected
Not affected
Res e t

P/V
N
C

Not affected
Rese t

Data from Bit 7 of Acc.

166

Ex am pi e :
If the contents of the Accumulator are

1
1

After the execution of

RRCA

the contents of the Accumulator and the Carry Flag will

be

7 6 5
4

1 II 1

1
1

169

RRCA

Operation :

7—^0 -Mcv

Fo rma t :

Opc ode
Operands

RRCA

1 1 1 1

OF

Description :

The contents of the Accumulator (register A) are rotated

right one bit position. Bit is copied into the Carry
Flag and also into bit 7. Bit is the least
significant bit.

M CYCLES: 1 T STATES; 4 4 MHZ E . T . : 1.00

Condition Bits Affected:

S
Z
H

Not affected
Not affected
Reset

P/V

Not affected
Reset

N
C

Data from Bit of Acc.

168

Example :

If the contents of the Accumulator and the Carry Flag

are

1
1

10

after the execution of

RRA

the contents of the Accumulator and the Carry Flag will

be
7

1
1

oil.

171

RRA

Ope ration

Format ;
Opcode

Operands

RRA

1 1 1 1 1

IF

Description:

The contents of the Accumulator (register A) are rotated

right one bit position through the Carry Flag. The
previous content of the Carry Flag is copied into bit 7.
Bit is the least significant bit.

M CYCLES: 1 T STATES: 4 4 MHZ E.T.: 1.00

Condition Bits Affected:

S
Z
H

Not affected
Not affected
Reset

P/V

Not affected
Reset

N
C

Data fron Bit of Acc.

170

Condition Bits Affected:

S:

Set if result is negative;

reset otherwise

Z :

Set if result is zero;

reset otherwise

11:
Reset

P/V:

Set if parity even;

reset otherwise

N:

Reset

C:

Data from Bit 7 of

source register

Example :
If the contents of register r are

1
1

after the execution of

RLC r

the contents of register r and the Carry Flag will be

6
5

1
1

173

RLC p

Operation

Fo rmat :

Opcode

Operands
RLC

110 10 11

CB

-« r— *►

Description:

The contents of register r are rotated left one bit

position. The content of bit 7 Is copied into the Carry
Flag and also into bit 0. Operand r is specified as
follows in the assembled object code:

M CYCLES: 2 T STATES: 8(4,4) 4 MHZ E.T.: 2.00

Register

B
C
D
E
H
L
A

000
001
010
Oil
100
101

111

172
Example :

If the contents of the IIL register pair are 2828H, and

the contents of memory location 2828H are

1
1

after the execution of

RLC (HL)

the contents of memory location 2828H and the Carry Flag

will be
C 76543210

rri ioioioiiioioioii

175

RLC CHLD

Operation

(HL)

Format :

Opcode

Operands
RLC

(HL)

110 10 11

CB

1 1

06

Description ;

The contents of the memory address specified by the

contents of register pair HL are rotated left one bit
position. The content of bit 7 is copied into the Carry
Flag and also into bit 0. Bit is the least
significant bit.

M CYCLES: 4 T STATES: 15(4,4,4,3) 4 MHZ E.T.: 3.75

Condition Bits Affected;

S:

Set if result is negative

reset otherwise

Z :

Set if result is zero;

reset otherwise

H:

Reset

P/V:

Set if parity even;

reset otherwise
N:

Reset

C:

Data from Bit 7 of

source register

174

Example :

If the contents o£ the Index Register IX are lOOOH, and

the contents of memory location 1022K are

7
6

1
1

after the execution of

RLC (IX+2H)

the contents of memory location 1002H and the Carry Flag

will be

C 76543210

nn io|oioiiioio{oii

177

RLC CIX+dD
Operation
Format :

. Jcvj-J-?-*—

(IX+d)

Opcode

RLC

Operands
(IX+d)

1 1

1
1 DD
CB

06

Description;

The contents of the memory address specified by the sum

of the contents of the Index Register IX and a two's
complement displacement Integer d, are rotated left one
bit position. The content of bit 7 is copied into the
Carry Flag and also Into bit 0. Bit is the least
significant bit.

M CYCLES: 6 T STATES: 2 3(4,4,3,5,4,3) 4 MHZ E.T.: 5.75

Condition Bits Affected:

S:

Set if result is negative

reset otherwise

Z:

Set if result is zero;

reset otherwise

H:

Reset
P/V:

Set if parity even;

reset otherwise

N:

Reset

C:

Data from Bit 7 of

source register

176
Example :

If the contents of the Index Register lY are lOOOH, and

the contents of memory location 1002H are

1
1

after the execution of

RLC (IY+2H)

the contents of memory location 1002H and the Carry Flag

will be
□

1
1

179

RLC CIY+d3

Operation !
Format :
. jcvlX?-*— ^

(lY+d)

Opcode

Operands
(lY+d)

FD

CB
06

Description ;

The contents of the memory address specified by the sum

of the contents of the Index Register lY and a two's
complement displacement Integer d are rotated left one
bit position. The content of bit 7 Is copied Into the
Carry Flag and also Into bit 0. Bit Is the least
significant bit.

M CYCLES: 6 T STATES: 2 3(4,4,3,5,4,3) 4 MHZ E.T.: 5.75

Condition Bits Affected;

S ;

Set if result is negative;

reset otherwise
Z;

Set if result is zero;

reset otherwise

H;

Reset

P/V:

Set If parity even;

reset otherwise

N:

Reset
C:

Data from Bit 7 of

source register

178

RL (lY+d)

1 FD
CB

16

*r identifies registers B,C,D,E,H,L or A specified as

follows in the assembled object code above:
Register

B
C
D
E
H
L
A

000
001
010
Oil
Oil
101
111

Description:

The contents of the m operand are rotated left one bit

position. The content of bit 7 is copied into the Carry

Flag and the previous content of the Carry Flag is
copied into bit 0.

INSTRUCTION

M CYCLES T STATES

4 MHZ E.T.

RL r 2 8(4,4) 2.00

RL (HL) 4 15(4,4,4,3) 3.75

RL (IX+d) 6 23(4,4,3,5,4,3) 5.75

RL (lY+d) 6 23(4,4,3,5,4,3) 5.75

181

RL m
Operation
Format :

opcode

Operands

RL m

The m operand is any of r,(HL), (IX+d) or (lY+d), as

defined for the analogous RLC instructions. These
various possible opcode-operand combinations are
specified as follows in the assembled object code:

RL r

RL (HL)

RL (IX+d)
t

1
I

CB

CB

16
DD
CB

180

RRC
Operation

Format :

Opcode
RRC

Operands

The m operand Is any of r,(HL), (IX+d) or (lY+d), as

defined for the analogous RLC instructions. These
various possible opcode-operand combinations are
specified as follows in the assembled object code:

CB

RRC (HL)
RRC (IX+d)

CB
OE
DD
CB

OE

183

Condition Bits Affected:

s *

Set if result is negative

reset otlierwise
Z:

Set if result is zero;

reset otherwise

H:

Reset

P/V:

Set if parity even;

reset otherwise

N:
Reset

C:

Data from Bit 7 of

source register

Example ;

If the contents of register D and the Carry Flag are

5
4

1
1

after the execution of

RL D

the contents of register D and the Carry Flag will be

C 76543210

182

Condition Bits Affected:

S:

Set if result is negative

reset otherwise

Z:

Set if result is zero;

reset otherwise

H:

Reset

P/V:

Set if parity even;

reset otherwise

N:
Reset

C:

Data from Bit of

source register

Example :

If the contents of register A are

5
A 3

1 j

1
after the execution of
RRC A

the contents of register A and the Carry Flag will be

76543210 C

1 1 1 1

185

RRC (lY+d)

1 FD
CB

OE

*r identifies registers B,C,D,E,H,L or A specified as

follows in the assembled object code above:

Register

Description;

000
001
010
Oil
100
101
111

The contents of operand m are rotated right one bit

position. The content of bit is copied into the Carry
Flag and also into bit 7. Bit is the least significant
bit.

INSTRUCTION

RRC r
RRC (HL)

RRC (IX+d)

RRC (lY+d)

M CYCLES T STATES

8(4,4)
15(4,4,4,3)
23(4,4,3,5,4,3)
23(4,4,3,5,4,3)

4 MHZ E.T.

2.00
3.75
5.75
5. 75

184

RR (lY+d)
1 1

1 1

0.1 FD
CB

*r identifies registers B,C,D,E,H,L or A specified as

follows in the assembled object code above:

Register

B
C
D
E
H
L
A
000
001
010
Oil
100
101
111

Description;

The contents of operand m are rotated right one bit

position through the Carry flag. The content of bit is
copied into the Carry Flag and the previous content of
the Carry Flag is copied into bit 7. Bit is the least
significant bit.

INSTRUCTION

RR r

RR (HL)

RR (IX+d)

RR (lY+d)
M CYCLES T STATES

4 MHZ E.T.

8(4,4) 2.00

15(4,4,4,3) 3.75

23(4,4,3,5,4,3) 5.75

23(4,4,3,5,4,3) 5.75

187

RR m

Operation

Opcode
Operand

The m operand is any of r, (HL), (IX+d), or (lY+d), as

defined for the analogous RLC Instructions. These
various possible opcode-operand combinations are
specified as follows in the assembled object code:

RR r

CB

RR (HL)
RR (IX+d)

CB
IE
DD
CB

IE

SLA

Operation :

Format :

Opcode Operands
SLA m

The m operand is any of r, (HL), (IX+d) or (lY+d), as

defined for the analogous RLC instructions. These
various possible opcode-operand conbinations are
specified as follows in the assembled object code:

SLA (IIL)

SLA (IX+d)

1 CB

CB
26
DD

1 CB

26
189

Condition Bits Affected:

S:

Set if result is negative;

reset otherwise

Z :

Set If result Is zero;

reset otherwise
H:

Reset

P/V:

Set if parity is even;

reset otherwise

N:

Reset

C:

Data from Bit of

source register
Exampl e :

If the contents of the HL register pair are 4343H, and

the contents of memory location 4343H and the Carry Flag
are

1
1

10

after the execution of

RR (HL)

the contents of location 4343H and the Carry Flag will

be
7

C
1

1 1

188

Condition Bits Affected:

S:

Set if result is
reset otherwise

negative

Z :

Set If result Is
reset otherwise

zero ;

II:

Reset

P/V:

Set if parity Is
reset otherwise
even ;

N:

Reset

C:

Data from Bit 7

Example :

If the contents of register L are

6
5

3 2

1
1

after the execution of

SLA L

the contents of register L and the Carry Flag will be

C 76543210

1 1 1 1

191

SLA (lY+d)

1 1

26
*r Identifies registers B,C,D,E,H,L or A specified as
follows in the assembled object code field above:

1 1 1

FD
CB

Register

000

C
001

010

oil

100

101

ill
Description :

An arithmetic shift

left

on the contents of operand m. The content of bit 7

copied into the Carry Flag. Bit is the least
significant bit.

INSTRUCTION

SLA r

SLA (HL)

SLA (IX+d)

SLA (lY+d)

M CYCLES T STATES
8(A.4)
15(4,4,4,3)
23(4,4,3,5,4,3)
23(4,4,3,5,4,3)

4 MHZ E.T.

2.00
3.75
5. 75
5.75

SRA(I Y+d)

*r identifies registers

1
I

1
_J
1 1
1

FD
CB

2E

C,D,E,H,L or A specified as

follows in the assembled object code field above:-

Register r

000
C

001

010

Oil

100

101

A
111

An arithmetic shift right one bit position is performed

on the contents of operand m. The content of bit is
copied into the Carry Flag and the previous content of
bit 7 is unchanged. Bit is the least significant bit.

INSTRUCTION M CYCLES T STATES 4 MHZ E.T.

BRA r 2 8(4,4) 2.00

SRA (HL) 4 15(4,4,4,3) 3.75

SRA (IX+d) 6 23(4,4,3,5,4,3) 5.75

SRA (lY+d) 6 23(4,4,3,5,4,3) 5.75

193

SRA m
Operation:

Format ;

Opcode Operands

SRA n

The m operand is any of r, (HL), (IX+d) or (IY+d),as

defined for the analogous RLC instructions. These
various possible opcode-operand conblnations are
specified as follows in the assembled object code:

SRA r

SRA(HL)

SRA(IX+d)
1

1
I

1 1
I —

1 1
-J

1 1

1 CB

2E
192

SRL

Operation

0-*> | 7— »o| -|cy]

Opcode

Operands

SRL m

The operand m is any of r, (HL), (IX+d) or (lY+d), as

defined for the analogous RLC instructions. These
various possible opcode-operand combinations are
specified as follows in the assenbled object code:
SRL (HL)

SRL (IX+d)

1111
I I I

CB

CB
3E
DD
CB

3E

195
Condition Bits Affected:

S:

Set If result Is negative

reset otherwise

Z:

Set if result Is zero;

reset otherwise

H:

Reset
P/V:

Set If parity Is even;

reset otherwise

N:

Reset

C:

Data from Bit of

source register

Example :

If the contents of the Index Register IX are lOOOH, and

the contents of memory location 1003H are
7

1
1

after the execution of

S&A (IX+3H)

the contents of memory location 1003H and the Carry Flag

will be

6
5

1
1

194

Condition Bits Affected;

S :

Rese t

Z :
Set if result is zero

reset otherwise

H:

Reset

P/V:

Set if parity is even

reset otherwise

N:

Reset

C:
Data from Bit of

source register

Example :

If the contents of register B are

5 4

2
1

after the execution of

SRL B

the contents of register B and the Carry Flag will be

7 6 5 4 3 2 1 c

'll'l

197
SRL (lY+d)

1 1

1
_J

1
I

1
I

1 1

FD
CB
3E

*r identifies registers B,C,D,E,H,L or A specified as

follows in the assembled object code fields above:

Register

B
C
D
E
H
L
A

000
001
010
Oil
100
101
111
Description!

The contents of operand m are shifted right one bit

position. The content of bit is copied into the Carry
Flag, and bit 7 is reset. Bit is the least significant
bit .

INSTRUCTION

SRL r

SRL (HL)

SRL (IX+d)

SRL (lY+d)

M CYCLES T STATES

8(4,4)
15(4,4,4,3)
23(4,4,3,5,4,3)
23(4,4,3,5,4,3)
4 MHZ E.T.

2. 00
3.75
5.75
5.75

196

Example :

If the contents of the HL register pair are 5000H, and

the contents of the Accumulator and memory location
5000H are

5
4

1
1

Accumulator

7 6 5 4 3 2 1

(5000H)

after the execution of

RLD

the contents of the Accumulator and memory location

5000H will be

6
5

1
1

Accumulator

7 6 5 4 3 2 1

1
1

(5000H)

199

RLD

Operation:

. a |7 4|3|o| [tTIyI iHL)

Opcode
Operands

RLD

1110 110 1
I I I I I I I

— I 1 1 1 1 1 1 —

110 1111

— I — I I I I I I

ED

6F

Description:
The contents of the low order four bits (bits 3,2,1 and
0) of the memory location (HL) are copied into the high
order four bits (7,6,5 and 4) of that same memory
location; the previous contents of those high order four
bits are copied Into the low order four bits of the
Accumulator (register A); and the previous contents of
the low order four bits of the Accumulator are copied
into the low order four bits of memory location (HL).
The contents of the high order bits of the Accumulator
are unaffected. Note: (HL) means the memory location
specified by the contents of the HL register pair.

M CYCLES: 5 T STATES: 18(4,4,3,4,3) 4 MHZ E.T.: 4.50

Condition Bits Affected:

S:

Set if Acc. Is negative after

operation; reset otherwise

Z :

Set if Acc. is zero after

operation; reset otherwise

H:

Reset

P/V:

Set if parity of Acc. is even

after operation; reset otherwise

N:

Reset

C:

Not affected

198
Example :

If the contents o£ the HL register pair are 5000H, and

the contents of the Accumulator and memory location
5000H are

1
1

Accumulator

7 6 5 4 3 2 1
1

(5000H)

after the execution of

RRD
the contents of the Accumulator and memory location
5000H will be

I
Accumulator

7 6 5 4 3 2 1
10 10 (5000H)

201
RRD

Operation ; *Q^^^]<"U
Format ;

Opcode

RRD

Operands

1110 110 1
— I — I — I — I I I I

— r— T — I — I — I — I — I —
110 111
— I 1 1 1 1 U_l

ED
67
Description:

The contents of the low order four bits (bits 3,2,1 and
0) of memory location (HL) are copied Into the low order
four bits of the Accumulator (register A) ; the previous
contents of the low order four bits of the Accumulator
are copied Into the high order four bits (7,6,5 and A)
of location (HL) ; and the previous contents of the high
order four bits of (HL) are copied into the low order
four bits of (HL) . The contents of the high order bits
of the Accumulator are unaffected. Note: (HL) means
the memory location specified by the contents of the HL
register pair.

U CYCLES: 5 T STATES: 18(4,4,3,4,3) 4 MHZ E.T.: 4.50

Condition Bits Affected :

S:

H:
P/V:

N:
C:
Set If Acc. is negative after
operation; reset otherwise
Set if Acc. is zero after
operation; reset otherwise
Reset

Set if parity of Acc. is even after

operation; reset otherwise

Reset

Not affected

200

-BIT SET, RESET AND TEST GROUP-

202

Exampl e :

If bit 2 in register B contains 0, after the execution

of
BIT 2,B

the Z flag in the F register will contain 1, and bit 2

in register B will remain 0. Bit in register B is the
least significant bit.

204

BIT b, r

Operation: Z r jj
Fo rmat !

Opcode

Operands

BIT

b ,r
— I 1 1 1 1 ! 1 —

110 10 11
■ I I I I I I —

J 1 L.

CB

Description:

This instruction tests Bit b in register r and sets the

Z flag accordingly. Operands b and r are specified as
follows in the assembled object code:

Bit Tested

Register
r

000

000

001

001

010
D

010

Oil

oil

100

100

5
101

101

110

111

111
M CYCLES: 2 T STATES: 8(4,4) 4 MHZ E.T.: 2.00
Condition Bits Affected :
S: Unknown

Z: Set if specified Bit is

0; reset otherwise
H: Set
P/V: Unknown
N: Reset
C: Not affected

203

Example :

If the HL register pair contains 4444H, and bit 4 in the

memory location 444H contains 1, after the execution of

BIT 4, (HL)

the Z flag In the F register will contain 0, and bit 4

in memory location 4444H will still contain 1. (Bit in
memory location 4444H is the least significant bit.)
206

BIT b, CHLD

Operation ; Z-«-(HL)j,

Format :

Opcode

Operands

BIT

b,(HL)
110 10 11

CB

1-1 — b ^1 1

Description ;

This Instruction tests bit b In the memory location

specified by the contents of the HL register pair and
sets the Z flag accordingly. Operand b Is specified as
follows In the assembled object code:

M CYCLES: 3 T STATES: 12(4,4,4) 4 MHZ E.T.: 3.00

Condition Bits Affected ;

Bit Tested

b
1
2
3
4
5
6
7

000
001
010
Oil
100
101
110
111

S;
Z :

Unknown

Set If specified Bit is

0; reset otherwise
Set
Unknown
Reset

Not affected

P/V

H
C

205

Condition Bits Affected:

S: Unknown

Z: Set if specified Bit is

0; reset otherwise
H: Set

P/V: Unknown

N: Reset

C: Not affected

Example :

If the contents of Index Register IX are 2000H, and bit

6 in memory location 2004H contains 1, after the
execution of

BIT 6, (IX+4H)

the Z flag in the F register will contain 0, and bit 6

in memory location 2004H will still contain 1. (Bit
in memory location 2004H is the least significant bit.)

208
BIT b. CIX+dD

Operation ; Z-«-{IX+d)jj
Fo rmat ;

Opcode
BIT

Operands
b , (IX+d)

1 1

DD
CB

Description ;
This instruction tests bit b in the memory location
specified by the contents of register pair IX combined
with the two's complement displacement d and sets the Z
flag accordingly. Operand b is specified as follows in
the assembled object code.

Tested

000

001

010

3
on

100

101

110

111

M CYCLES: 5 T STATES: 20(4,4,3,5,4)

Condition Bits Affected:
4 MHZ E.T. : 5.00

S : Unknown

Z: Set if specified Bit is

0; reset otherwise

207

Condition Bits Affected:

S; Unknown

Z: Set If specified Bit is

0; reset otherwise

H: Set

P/V: Unknown

N: Reset
C: Not affected

Example :

If the contents of Index Register are 2000H, and bit 6

in memory location 2004H contains 1, after the execution
of

BIT 6, (IY+4H)

the Z flag in the F register sill contain 0, and bit 6

in memory location 2004H will still contain 1. (Bit
in memory location 2004H is the least significant bit.)

210

BIT b, ClY+d]

BIT b,(IY+d)
Operation ! Z (I Y+tl)b
Format ;

Opcode
BIT

Operands
b , (lY+d)

1 1

1 FD
CB

Description ;

This Instruction tests bit b In the memory location

specified by the contents of register pair lY combined
with the two's complement displacement d and sets the Z
flag accordingly. Operand b Is specified as follows In
the assembled object code:

Bit Tested

1
2
3
4
5
6
7

000
001
010
Oil
100
101
110
111

M CYCLES: 5 T STATES: 20 ( A , 4 , 3 , 5 , 4 ) 4 MHZ E.T.: 5.00

209

SET b. CHL3

Operation : (HLlj,"*-!
Format ;

Opcode
SET

Operands
b , (HL)

I'l'o'o'
•1

I L.

1 — I — I —

-b — .-1

1 1

CB

Descr ipt Ion :

Bit b in the memory location addressed by the contents

of register pair HL is set. Operand b is specified as
follows in the assembled object code:
Bit Tested

1
2
3
4
5
6
7

M CYCLES: 4 T STATES:
Condition Bits Affected :
Example :

000
001
010
Oil
100
101
110
111

15(4,4,4,3)
None
4 MHZ E.T. : 3.75

If the contents of the HL register pair are 3000H, after

the execution of

SET 4,(HL)

bit 4 in memory location 3000H will be 1. (Bit in

memory location 3000H is the least significant bit.)

212

SET b, r

Operation ; rjj 1
Forma t ;

Opcode Operands

SET b,r
1 'l 'O 'O 'l 'O 'l 'l I CB
I I I 1 I 1 I

1 ' 1 ' . ' b ' . ' . '

— I — 1 — I — 1 — I — 1 — I —

Description ;

Bit b In register r (any of registers B,C,D,E,H,L or A)

is set. Operands b and r are specified as follows in
the assembled object code;

Bit

Register

000
B

000

001

001

010

010

3
Oil

Oil

100

100

101

101
6

110

111

ill

M CYCLES; 2 T STATES; 8(4,4) 4 MHZ E.T.: 2.00

Condition Bits Affected ; None
Example ;

After the execution of

SET 4, A

bit 4 In register A will be set. (Bit is the least

significant bit.)
211

Example :

If the contents of Index Register are 2000H, after the

execution of

SET 0,(IX+3H)

bit in memory location 2003H will be 1. (Bit in

memory location 2003H Is the least significant bit.)

214

SET b. ClX+d]

Operation ; (IX+dlj,-*-!
Format ;

Opcode
SET
Operands
b, (IX+d)

1 DD

1 CB

Description ;

Bit b In the memory location addressed by the sum of the

contents of the IX register pair and the two's
complement Integer d Is set. Operand b Is specified as
follows In the assembled object code:
Bit Tested

1
2
3
4
5
6
7

000
001
010
Oil
100
101

no
111

M CYCLES: 6
5.75

T STATES; 23(4,4,3,5,4,3) 4 MHZ E.T.:

Condition Bits Affected;

213

the execution of

SET 0,(IY+3H)

bit in memory location 2003H will be 1. (Bit in

memory location 2003H is the least significant bit.)

216

SET b. ClY+d]

Operation ; (I Y+d)b 1
Format ;

Opcode
SET
Operands
b , (lY+d)

1 1

FD
CB

Description !

Bit b In the memory location addressed by the sum of the

contents of the lY register pair and the two's
complement displacement d Is set. Operand b Is
specified as follows In the assembled object code:

Bit Tested

1
2
3
4
5
6
7

000
001
010
Oil
100
101
110
111

M CYCLES: 6
5.75

T STATES: 23(4,4,3,5,4,3) 4 MHZ E.T.

Condition Bits Affected ; None

Example ;

If the contents of Index Register lY are 2000H, after

215

Reset

Reg Is t er

nnn
u uu

000

1
001

001

010

010

on

oil
4

100

100

101

101

no

A
111

111

Description:

Bit b In operand m Is reset.

INSTRUCTION M CYCLES T STATES 4 MHZ

RES r 4

RES (HL) 4

RES (IX+d) 6

RES (lY+d) 6
8/(4,4) 2.00

15(4,4,4,3) 3.75

23(4,4,3,5,4,3) 5.75

23(4,4,3,5,4,3) 5.75

Condition Bits Affected: None

Example:

After the execution of

RES 6,D

bit 6 In register D will be reset. (Bit In register D

Is the least significant bit.)

RES b. m
Operation; Sjj *"

Opcode

RES

Operands

Operand b is any bit (7 through 0) of the contents of

the m operand, (any of r, (HL) , (IX+d) or (IY+d))as
defined for the analogous SET Instructions. These
various possible opcode-operand combinations are
assembled as follows in the object code:

RES b,r
1

CB

RES b,(HL)

CB
RES b,(IX+d)

DD
CB

RES b,(iy+d)

FD
CB

-JlfP GROUP-

219

JP cc, nn

Operation; IF cc TRUE, PC nn
Opcode
JP

Operands

cc ,nn

Note: The first n operand in this assembled object code

is the low order byte of a 2-byte memory address.

Description:

If condition cc is true, the instruction loads operand

nn into register pair PC (Program Counter) , and the
program continues with the instruction beginning at
address nn. If condition cc is false, the Program
Counter is incremented as usual, and the program
continues with the next sequential instruction.
Condition cc is programmed as one of eight status which
corresponds to condition bits in the Flag Register
(register F) , These eight status are defined in the
table below which also specifies the corresponding cc
bit fields in the assembled object code.

CONDITION

RELEVANT
FLAG

000
001
010

on

100
101
110
111

NZ non zero

Z zero

NC no carry
C carry

PO parity odd

PE parity even

P sign positive

M sign negative

Z
Z
C
C

P/V
P/V
S
S

221

JP nn

Operation ; PC nn
Format ;

Opcode
JP

Ope rands

1 1

C3

Note: The first operand in this assembled object code

is the low order byte of a 2-byte address.

Description ;

Operand nn is loaded into register pair PC (Program

Counter). The next instruction is fetched from the
location designated by the new contents of the PC.
M CYCLES: 3 T STATES: 10(4,3,3)
Condition Bits Affected; None

4 MHZ E.T. : 2.5

220

JR

Operation: PC PC + e

Format :

Opcode

Operand
— I 1 1 1 1 1 1 —

1 1
I 1 I I I I I

18

-e-2-

-J — I I I I I i_

Description:

This instruction provides for unconditional branching to

other segments of a program. The value of the
displacement e is added to the Program Counter (PC) and
the next instruction is fetched from the location
designated by the new contents of the PC. This jump is
measured from the address of the Instruction opcode and
has a range of -126 to +129 bytes. The assembler
automatically adjusts for the twice incremented PC.

M CYCLES: 3 T STATES: 12(4,3,5) 4 MHZ E.T.: 3.00

Condition Bits Affected: None

Example :

To Jump forward 5 locations from address 480, the

following assembly language statement is used:

JR $+5

The resulting object code and final PC value is shown

below:

480
481
482
483
484
485

Instruction
03

PC after jump
223

M CYCLES: 3 T STATES: 10(4,3,3) 4 MHZ E.T.: 2.50

Condition Bits Affected : None
Example ;

If the Carry Flag (C flag in the F register) is set and

the contents of address 1520 are 3H , after the
execution of

JP C,1520H

the Program Counter will contain 1520H, and on the next

machine cycle the CPU will fetch from address 1520H the
byte 03H.

222

JR C,$-4

The resulting object code and final PC value is shown

below:

Location Instruction
47C •* — PC after jump

47D

47E

47F

480 38

481 FA (2'8 complement- 6)

225

JR C, e

Operation: If C = 0, continue

If C= 1, PC^PC + e
Format :

Opcode

Operands

JR

C,e

1 1 1

38

e-2

Description:
This instruction provides for conditional branching to
other segments of a program depending on the results of
a test on the Carry Flag. If the flag is equal to a
' 1 ' , the value of the displacement e is added to the
Program Counter (PC) and the next instruction is fetched
from the location designated by the new contents of the
PC. The jump is measured from the address of the
instruction opcode and has a range of -126 to +129
bytes. The assembler automatically adjusts for the
twice incremented PC.

If the flag is equal to a '0', the next Instruction to

be executed is taken from the location following this
instruction .

If condition is met:

M CYCLES: 3 T STATES: 12(4,3,5) 4 MHZ E.T.:3.00

If condition is not met:

M CYCLES: 2 T STATES: 7(4,3) 4 MHZ E.T.: 1.75

Condition Bits Affected : None
Example :

The Carry Flag is set and it is required to jump back 4

locations from 480. The assembly language statement is:

224
JR NC , $

The resulting object code and PC after the jump are

shown below:

Location Instruction

480 30 ■*— PC after jump

481 00

227

JR NC. e

Operation: If C = 1 , continue

lfC = 0, PC*-PC + e

Fo rmat :
Opcode

Operands

JR

NC,e

1 1

30

e-2

Description:
This instruction provides for conditional branching to
other segments of a program depending on the results of
a test on the Carry Flag. If the flag is equal to '0',
the value of the displacement e is added to the Program
Counter (PC) and the next instruction is fetched from
the location designated by the new contents of the PC.
The Jump Is measured from the address of the instruction
opcode and has a range of -126 to +129 bytes. The
assembler automatically adjusts for the twice
incremented PC.

If the flag is equal to a '1', the next instruction to

be executed is taken from the location following this
instruction.

If the condition is met:

II CYCLES: 3 T STATES: 12(4,3,5) 4 MHZ E.T.: 3.00

If the condition is not net;

M CYCLES: 7

T STATES: 7(4,3)

4 MHZ E.T. : 1 . 75
Condition Bits Affected:

None

Example :

The Carry Flag is reset and it is required to repeat the

jump instruction. The assembly language statement is:

JR Z,$ +5

The resulting object code and final PC value Is shown

below:

Location Instruction

300 28

301 03
302

303

304

305 ■* — PC after jump

229

JR Z. e

Operation: If Z = 0, continue

lfZ = 1, PC^PC + e

Opcode

Operands

JR
Z,e

— I 1 1 1 1 1 1 —

1 1
I I I I I I I

28

-e-2-

Description :

This instruction provides for conditional branching to

other segments of a program depending on the results of
a test on the Zero Flag. If the flag is equal to a '1',
the value of the displacement e is added to the Program
Counter (PC) and the next instruction is fetched from
the location designated by the new contents of the PC.
The Jump is measured from the address of the instruction
opcode and has a range of -126 to +129 bytes. The
assembler automatically adjusts for the twice
incremented PC.

If the Zero Flag is equal to a '0', the next instruction

to be executed is taken from the location following this
instruction.

If the condition is met:

M CYCLES: 3 T STATES: 12(4,3,5) 4 MHZ E.T.: 3.00

If the condition is not net:

M CYCLES: 2 T STATES: 7(4,3) 4 MHZ E.T.: 1.75

Condition Bits Affected ; None
Example :

The Zero Flag is set and it is required to jump forward

5 locations from address 300. The following assembly
language statement is used:

228

JR NZ,$-4
The resulting object code and final PC value is shown
below:

Location Instruction

47C -« — PC after jump

4 7D

A7E

47F

480 20

481 FA (2' coinplement-6)

231

JR NZ, e

Operation ; If Z = 1, continue
lfZ = 0, PC^PC + e

Format:

Opcode

Operands

NZ,e

1 1 1 1 1 1 1 1 1

I I I I L__

20

-e-2-
Description:

This Instruction provides for conditional branching to

other segments of a program depending on the results of
a test on the Zero Flag. If the flag is equal to a '0',
the value of the displacement e is added to the Program
Counter (PC) and the next instruction is fetched from
the location designated by the new contents of the PC.
The jump is measured from the address of the Instruction
opcode and has a range of -126 to +129 bytes. The
assembler automatically adjusts for the twice
incremented PC.

If the Zero Flag is equal to a '1', the next instruction

to be executed is taken from the location following this
instruc tion .

If the condition is met:

M CYCLES: 3 T STATES: 12(4,3,5) 4 MHZ E.T.: 3.00

If the condition is not met;

M CYCLES: 2 T STATES: 7(4,3) 4 MHZ E.T.: 1.75

Condition Bits Affected ; None

Example:
The Zero Flag is reset and it is required to jump back 4
locations from 480. The assembly language statement is;

230

JP CIXD

Operation ; PC-«-IX

Format !

Opcode

Operands

JP
(IX)

110 1110 1

DD

1110 10 1

E9

Description ;

The Program Counter (register pair PC) Is loaded with

the contents of the IX Register Pair. The next
Instruction is fetched from the location designated by
the new contents of the PC.

M CYCLES: 2 T STATES: 8(4,4) 4 MHZ E.T.: 2.00

If the contents of the Program Counter are lOOOH, and
the contents of the IX Register Pair are 4800H, after
the execution of

the contents of the Program Counter will be 4800H.

Condition Bits Affected;

None

Example ;

JP (IX)

233

JP CHLD
Operation: PC-<-HL

Format :

Opcode

Operands

JP

(HL)

1110 10 1

E9
L-j I I I I I L

Description:

The Program Counter (register pair PC) is loaded with

the contents of the HL register pair. The next
instruction is fetched from the location designated by
the new contents of the PC,

M CYCLES: 1 T STATES: 4 4 MHZ E.T.: 1.00

Condition Bits Affected: None

Example:

If the contents of the Program Counter are lOOOH and the

contents of the HL register pair are 4800U, after the
execution of

JP (HL)

the contents of the Program Counter will be 4800H.

232
DJNZ

Operation:

Format :

Opcode

Operand

— I 1 1 1 1 1 1 —

1
— I 1 I 1 1 I I

10

Description:
This instruction is similar to the conditional jump
instructions except that a register value is used to
determine branching. The B register Is decremented and
if a non zero value remains, the value of the
displacement e is added to the Program Counter (FC).
The next instruction is fetched from the location
designated by the new contents of the PC. The jump is
measured from the address of the Instruction opcode and
has a range of -126 to +129 bytes. The assembler
automatically adjusts for the twice Incremented PC.

If the result of decrementing leaves B with a zero

value, the next instruction to be executed is taken from
the location following this instruction.

If B/0:

M CYCLES: 3 T STATES: 13(5,3,5) 4 MHZ E.T.: 3.25

If B-0:

M CYCLES: 2 T STATES: 8(5,3) 4 MHZ E.T.: 2.00

Condition Bits Affected ; None
Example :

A typical software routine is used to demonstrate the

use of the DJNZ instruction. This routine moves a line
from an input buffer (INBUF) to an output buffer

235
JP CIY]

Operation ! PC-«-IY

Format :

Opcode

Operands

JP

(lY)

1111110 1
FD

1110 10 1

E9

Description:

The Program Counter (register pair PC) is loaded with

the contents of the lY Register Pair. The next
instruction is fetched from the location designated by
the new contents of the PC.

M CYCLES: 2 T STATES: 8(4,4) 4 MHZ E.T.: 2.00

Example ;

If the contents of the Program Counter are lOOOH and the

contents of the lY Register Pair are 4800H, after the
execution of
the contents of the Program Counter will be 4800H.

Condition Bits Affected:

None

JP (lY)

234

-CALL m RETURN GROUP-

237

(OUTBUF). It moves the bytes until it finds a CR, or

until it has moved 80 bytes, whichever occurs first.

LD B,80 ;Set up counter

LD HL.Inbuf ;Set up pointers

LD DE.Outbuf

LD

A, (HL)

LD

CP

JR

INC

INC

DJNZ

(DE) ,A
ODH

Z.DONE
HL

DE

LOOP

;Get next byte from

;input buffer

;Store in output buffer

;Is it a CR?

;Yes finished

;Increment pointers

;Loop back if 80
;byte8 have not
;been moved

236

Exampl e ;
If the contents of the Program Counter are 1A47H, the
contents of the Stack Pointer are 3002H, and memory
locations have the contents:

then if an instruction fetch sequence begins, the

three-byte instruction CD3521H will be fetched to the
CPU for execution. The mnemonic equivalent of this is

After the execution of this instruction, the contents of

memory address 3001H will be lAH, the contents of
address 3000H will be 4AH, the contents of the Stack
Pointer will be 3000H, and the contents of the Program
Counter will be 2135H, pointing to the address of the
first opcode of the subroutine now to be executed.

Location

Con tents

1A47H
1A48H
1A49H

CDH
35H
21H

CALL 2135H

239

CALL nn

Operation ; (SP-D^PCh, {SP-2) «- PCl , PC^ nn

Format ;

Opcode Operands

CALL nn
1 1

CD

Note: The first of the two n operands in the assembled

object code above is the least significant byte of a
two-byte memory address.

Description :

The current contents of the Program Counter (PC) are

pushed onto the top of the external memory stack. The
operands nn are then loaded into the PC to point to the
address in memory where the first opcode of a subroutine
is to be fetched. (At the end of the subroutine, a
RETurn instruction can be used to return to the original
program flow by popping the top of the stack back Into
the PC.) The push is accomplished by first decrementing
the current contents of the Stack Pointer (register pair
SP), loading the high-order byte of the PC contents into
the memory address now pointed to by the SP; then
decrementing SP again, and loading the low-order byte of
the PC contents into the top of stack. Note: Because
this is a 3-byte instruction, the Program Counter will
have been incremented by 3 before the push is executed.

M CYCLES: 5 T STATES: 17(4,3,4,3,3) 4 MHZ E.T.: 4.25

Condition Bits Affected:

238

the push Is executed. Condition cc Is programmed as one

of eight status which corresponds to condition bits in
the Flag Register (register F) . These eight status are
defined In the table below, which also specifies the
corresponding cc bit fields In the assembled object
code :

cc

Condition

Relevant

Flag
000

NZ non zero

001

Z zero

010

NO non carry

Oil

C carry
C

100

PO parity odd

P/V

101

PE parity even

P/V

no

P sign positive

111
M sign negative

If cc is true:

M CYCLES: 5 T STATES: 17(4,3,4,3,3) 4 MHZ E.T.: 4.25

If cc is false:

M CYCLES: 3 T STATES: 10(4,3,3) 4 MHZ E.T.: 2.50

Condition Bits Affected : None

Example:

If the C Flag In the F register is reset, the contents

of the Program Counter are 1A47H, the contents of the
Stack Pointer are 3002H, and memory locations have the
contents :

Location

1A47H
1A48U
1A49H
Contents

D4H
35H
21H

then if an instruction fetch sequence begins, the

three-byte instruction D43521H will be fetched to the
CPU for execution. The mnemonic equivalent of this is

CALL NC,2135H

241

CALL cc, nn

Operation ; IF cc TRUE: (SP-I)-«-PCh

(SP-2) ^ PC, , PC ^ nn

Opcode
CALL
Operands

Note: The first of the two n operands in the assembled

object code above is the least significant byte of the
two-byte memory address.

Description:

If condition cc is true, this instruction pushes the

current contents of the Program Counter (PC) onto the
top of the external memory stack, then loads the
operands nn into PC to point to the address in memory
where the first opcode of a subroutine is to be fetched.

(At the end of the subroutine, a RETurn instruction can

be used to return to the original program flow by
popping the top of the stack back into PC.) If
condition cc is false, the Program Counter is
incremented as usual, and the program continues with the
next sequential instruction. The stack push is
accomplished by first decrementing the current contents
of the Stack Pointer (SP), loading the high-order byte
of the PC contents into the memory address now pointed
to by SP; then decrementing SP again, and loading the
low-order byte of the PC contents into the top of the
stack. Note: Because this is a 3-byte instruction, the
Program Counter will have been incremented by 3 before
240

RET

Operation : PCl^ (sp) . PCH-^-tSP+D

Fo rmat :

Opcode

RET

1 1 1 1

C9
Description:

The byte at the memory location specified by the

contents of the Stack Pointer (SP) register pair are
moved to the low order eight bits of the Program Counter
(PC). The SP is now incremented and the byte at the
memory location specified by the new contents of the SP
are moved to the high order eight bits of the PC. The
SP is now incremented again. The next op code following
this instruction will be fetched from the memory
location specified by the PC. This instruction is
normally used to return to the main line program at the
completion of a routine entered by a CALL instruction.

M CYCLES: 3 T STATES: 10(4,3,3) 4 MHZ E.T.: 2.50

Example :

If the contents of the Program Counter are 3535H, the

contents of the Stack Pointer are 2000H, the contents of

memory location 2000H are B5H, and the contents of

memory location 2001H are 18H, then after the execution

of
the contetns of the Stack Pointer will be 2002H and the
contents of the Program Counter will be 18B5H, pointing
to the address of the next program opcode to be fetched

Condition Bits Affected;

None

RET

243

After the execution of this instruction, the contents of

memory address 3001H will be lAH, the contents of
address 3000H will be 4AH, the contents of the Stack
Pointer will be 3000H, and the contents of the Program
Counter will be 2135H, pointing to the address of the
first opcode of the subroutine now to be executed.

242
M CYCLES: 3 T STATES: 11(5,3,3) 4 MHZ E.T.: 2.75
If cc is false:

M CYCLES: 1 T STATES: 5 4 MHZ E.T.: 1.25

Condition Bits Affected ; None
Example ;

If the S flag In the F register Is set, the contents of

the Program Counter are 3535H, the contents of the Stack
Pointer are 2000H, the contents of memory location 2000H
are B5H, and the contents of memory location 2001H are
18H, then after the execution of

RET M

the contents of the Stack Pointer will be 2002H and the

contents of the Program Counter will be 18B5H, pointing
to the address of the next program opcode to be fetched.

245

RET cc

Operation : I F CC TRUE: PCl (SP), PCh"*- (SP+I)

Format ;

Opc ode Operand

RET cc

I I I 1 1 1 1 1 1

1 1 — CC — ^0

L__l 1 1 1— I 1 1

Description ;

If condition cc Is true, the byte at the memory location

specified by the contents of the Stack Pointer (SP)
register pair are moved to the low order eight bits of
the Program Counter (PC). The SP is now Incremented and
the byte at the memory location specified by the new
contents of the SP are moved to the high order eight
bits of the PC. The SP is now incremented again. The
next op code following this Instruction will be fetched
from the memory location specified by the PC. This
Instruction is normally used to return to the main line
program at the completion of a routine entered by a CALL
instruction. If condition cc is false, the PC is simply
Incremented as usual, and the program continues with the
next sequential instruction. Condition cc is programmed
as one of eight status which correspond to condition
bits in the Flag Register (register F) . These eight
status are defined in the table below, which also
specifies the corresponding cc bit fields in the
assembled object code.
cc

Condition

Relevant

Flag

000

NZ non zero

001

Z zero
Z

010

NC non carry

Oil

C carry

100

PO parity odd

P/V

101
PE parity even

P/V

110

P sign positive

111

M sign negative

If cc is true:

244
B generates an interrupt and is acknowledged. (The
interrupt enable out, lEO, of B goes low, blocking any
lower priority devices from interrupting while B is
being serviced). Then A generates an interrupt,
suspending service of B. (The lEO of A goes 'low'
indicating that a higher priority device is being
serviced.) The A routine is completed and a RETI Is
issued resetting the lEO of A, allowing the B routine to
continue. A second RETI is issued on completion of the
B rou-tine and the lEO of B is reset (high) allowing
lower priority devices interrupt access.

RETI

Operation : Return from interrupt

Format ;

Opcode
RETI

— I \ 1 1 1 \ 1 —

1110 110 1
I — I — I — I — 1 —

— I — I — I — I — \ — I — I —

10 110 1

ED
40

Description:

This instruction is used at the end of a maskable

interrupt service routine to:

1. Restore the contents of the Program Counter (PC)

(analogous to the RET instruction)

2. To signal an I/O device that the interrupt routine

has been completed. The RETI instruction also
facilitates the nesting of Interrupts allowing higher
priority devicess to temporarily suspend service of
lower priority service routines. Note: This
Instruction does not enable interrupts which were
disabled when the interrupt routine was entered.
Before doing the RETI instruction, the enable
Interrupt instruction (EI) should be executed to
allow recognition of interrupts after completion of
the current service routine.

M CYCLES: 4 T STATES: 14(4,4,3,3) 4 MHZ E.T.: 3.50

Condition Bits Affected : None

Examp 1 e :

Given: Two interrupting devices, A and B connected in a

daisy chain configuration with A having a higher
priority than B.

lEI lEO

lEI lEO
*

order-byte first, and 0066H will be loaded onto the

Program Counter. That address begins an interrupt
service routine v/hlch ends with RETN instruction. Upon
the execution of RETN, the former Program Counter
contents are popped off the external memory stack,
low-order first, resulting in a Stack Pointer contents
again of lOOOH. The program flow continues where it
left off with an opcode fetch to address 1A45H.

249

RETN

Operation ; Return from non maskable interrupt

Format :

Opcode
RETN

1110 110 1

ED

1 1 1

45

Description ;

This Instruction Is used at the end of a non-maskable

Interrupt service routine to restore the contents of the
Program Counter (PC) (analogous to the RET instruction).

The state of IFF2 is copied back into IFFl so that

maskable Interrupts are enabled immediately following
the RETN if they were enabled before the non-maskable
interrupt .
M CYCLES: 4 T STATES: 14(4,4,3,3) 4 MHZ E.T.: 3.50

Example :

If the contents of the Stack Pointer are lOOOH and the

contents of the Program Counter are 1A45H when a non
maskable interrupt (NMI) signal is received, the CPU
will ignore the next instruction and will Instead
restart to memory address 0066H. That is, the current
Program Counter contents of 1A45H will be pushed onto
the external stack address of OFFFH and OFFER, high
order-byte first, and 0066H will be loaded onto the
Program Counter. That address begins an Interrupt
service routine which ends with RETK instruction. Upon
the execution of RETN, the former Program Counter
contents are popped off the external memory stack,
low-order first, resulting in a Stack Pointer contents
again of lOOOH. The program flow continues where it
left off with an opcode fetch to address 1A45H.

Condition Bits Affected;

None
248

Example :

If the contents of the Prog

the execution of

RST 18H (Object

the PC will contain 0018H,

opcode to be fetched.

ram Counter are 15B3H, after

code IIOIIII)
as the address of the next

RST p

Operation ; (SP-I)^PCh, (SP-2) ^ PCl , PCh^O, PCl ^ P

Format ;
Opcode Operand

RST p

I 1 1 1 1 1 1 1 —

1 1 ^1 1 1

1 I 1 1 1 1 I —

Description:

The current Program Counter (PC) contents are pushed

onto the external memory stack, and the page zero memory
location given by operand p Is loaded into the PC.
Program execution then begins with the opcode in the
address now pointed to by PC. The push is performed by
first decrementing the contents of the Stack Pointer
(SP), loading the high-order byte of PC into the memory
address now pointed to by SP, decrementing SP again, and
loading the low-order byte of PC into the address now
pointed to by SP. The ReSXart Instruction allows for a
Jump to one of eight addresses as shown in the table
below. The operand p is assembled into the object code
using the corresponding T state. Note: Since all
addresses are in page zero of memory, the high order
byte of PC is loaded with OOH. The number selected
from the "p" column of the table is loaded into the
low-order byte of PC.

P t

OOH 000

08H 001

lOH 010

18H Oil

20H 100

2 on 101

30H 110

38H 111

II CYCLES: 3 T STATES: 11(5,3,3) 4 MHZ E.T,: 2.75

250

-INPUT m OUTPUT GROUP-

252

IN p. CCD

Operation: r <- (C)

Format :

Opcode

Operands
r,(C)

1110 110 1

ED
1 — r — ^0
I I i I I I I

Description:

The contents of register C are placed on the bottom half

(AO through A7) of the address bus to select the I/O
device at one of 256 possible ports. The contents of
Register B are placed on the top half (A8 through A15)
of the address bus at this time. Then one byte from the
selected port is placed on the data bus and written into
register r in the CPU. Register r identifies any of the
CPU registers shown in the following table, which also
shows the corresponding 3-bit "r" field for each. The
flags will be affected, checking the input data.

Reg .

000
C

001

010

oil

100

101

A
111

M CYCLES: 3 T STATES: 12(4,4,4) 4 MHZ E.T.: 3.00

254

A, Cn]

Operation: A ^ (n)

Format :

Opcode

Operands

IN
A,(n)

110 110 11

DB

Description:

The operand n is placed on the bottom half (AO through

A7) of the address bus to select the I/O device at one
of 256 possible ports. The contents of the Accumulator
also appear on the top half ( A8 through A15) of the
address bus at this time. Then one byte from the
selected port is placed on the data bus and written into
the Accumulator (register A) in the CPU.

M CYCLES: 3 T STATES: 11(4,3,4) 4 MHZ E.T.: 2.75

Condition Bits Affected: None

Example :
If the contents of the Accumulator are 23H and the byte
7BH is available at the peripheral device napped to I/O
port address OIH, then after the execution of

IN A, (OIH)

the Accumulator will contain 7BH.

253

Operation ; (HL) <- (C) , B ^ B-1 , HL^HL + 1

Format :

Opcode

1110 110 1
I — \ I I I I I
1 1 1
__J — I — I — I — I — I — 1__

ED
A2

Description:

The contents of register C are placed on the bottom half

(AO through A7) of the address bus to select the I/O
device at one of 256 possible ports. Register B may be
used as a byte counter, and its contents are placed on
the top half (A8 through A15) of the address bus at this
time. Then one byte from the selected port is placed on
the data bus and written to the CPU. The contents of
the HL register pair are then placed on the address bus
and the input byte is written into the corresponding
location of memory. Finally the byte counter is
decremented and register pair UL is incremented.

M CYCLES: 4 T STATES: 16(4,5,3,4) 4 MHZ E.T.: 4.00

Condition Bits Affected:

S: Unknown

Z: Set if B-1-0;

reset otherwise

H: Unknown

P/V: Unknown

M: Set

C: Not affected

Example :

If the contents of register C are 07H, the contents of

register B are lOH, the contents of the HL register pair
are lOOOH, and the byte 7BH is available at the
peripheral device mapped to I/O port address 07H, then

256

Condition Bits Affected:

S:

Set if input data is negative;

reset otherwise

Z:

Set if input data is zero;

reset otherwise

H:

Reset

P/V:

Set if parity is even;

reset otherwise

N:

Reset
C:

Not affected

Example :

If the contents of register C are 07H, the contents of

register B are 1 OH , and the byte 7BH is available at the
peripheral device mapped to I/O port address 0711, then
after the execution of

IN D, (C)

255

INIR

Operation ; (HL) ^ (C) , B ^ B-1 , HL ^ HL + 1

Fo rmat :

Opcode
INIR
— I 1 r— I 1 1 1

ED

— I 1 1 1 1 1 1 —

1110 110 1
■ I I I I I I —

— I 1 1 1 1 1 1 —

10 110 10

I I I I I I I

B2

Desc r ipt ion :

The contents of register C are placed on the bottom half

(AO through A7) of the address bus to select the I/O
device at one of 256 possible ports. Register B is used
as a byte counter, and its contents are placed on the
top half (A8 through A15) of the address bus at this
time. Then one byte from the selected port is placed on
the data bus and written to the CPU. The contents of
the HL register pair are placed on the address bus and
the input byte is written into the corresponding
location of memory. Then register pair HL is
incremented, the byte counter is decremented. If
decrementing causes B to go to zero, the instruction is
terminated. If B is not zero, the PC is decremented by
two and the instruction repeated. Interrupts will be
recognized and two refresh cycles will be executed after
each data transfer. Note that if B is set to zero prior
to instruction execution, 256 bytes of data will be
input .

If B=0:

M CYCLES: 5 T STATES: 21(4,5,3,4,5) 4 MHZ E.T.: 5.25

If B=0:

M CYCLES: 4 T STATES: 16(4,5,3,4) 4 MHZ E.T.: 4.00

258

after tha execution of

INI

memory location lOOOH will contain 7BH, the HL register

pair will contain lOOlH, and register B will contain
OFH.

IND

Operation; (HL)^(C), B ^ B-1 , HL <- HL-1

Opcode

1110 110 1 ED
_l I — I — I — I — I — I-

— I — I — I — I — 1 — I — I —

10 10 10 10

[ 1 I I I — I I
AA

Description :

The contents of register C are placed on the bottom half

(AO through A7) of the address bus to select the I/O
device at one of 256 possible ports. Register B may be
used as a byte counter, and Its contents are placed on
the top half (A8 through A15) of the address bus at this
time. Then one byte from the selected port Is placed on
the data bus and written to the CPU. The contents of
the HL register pair are placed on the address bus and
the Input byte Is written Into the corresponding
location of memory. Finally the byte counter and
register pair HL are decremented.

M CYCLES: 4 T STATES: 16(4,5,3,4) 4 MHZ E.T.: 4.00

Condition Bits Affected:

S: Unknown

Z: Set if B-1-0;

reset otherwise
H: Unknown

P/V: Unknown

K: Set

C: Not affected

Example :

If the contents of register C are 07H, the contents of

register B are lOH, the contents of the HL register pair
are lOOOH, and the byte 7BH is available at the

260

Condition Bits Affected;

S: Unknown

Zs Set

H: Unknown
P/V: Unknown

N: Set

C: Hot affected

Example :

If the contents of register C are 07H, the contents of

register B are 03H, the contents of the HL register pair
are lOOOH, and the following sequence of bytes are
available at the peripheral device mapped to I/O port of
address 07H:

the HL register pair will contain 1003H, register B will

contain zero, and memory locations will have contents as
follows :

51H
A9H
03H

then after the execution of

INIR

Location

Contents

lOOOH
lOOIH
1002H

51H
A9H
03H

259

INDR
Operation ; (HL)*-(C). B ^ B-1 - HL^HL-1
Format ;

Opcode
INDR

— I 1 1 1 1 1 1 —

1110 110 1
I I I i 1 1 1 —

— I 1 1 1 1— 1 1 —

10 1110 10
' ■ I I I \ I

ED
BA

Desc ription :

The contents of register C are placed on the bottom half

(AO through A7) of the address bus to select the I/O
device at one of 256 possible ports. Register B is used
as a byte counter, and its contents are placed on the
top half (A8 through A15) of the address, bus at this
time. Then one byte from the selected port is placed on
the data bus and written to the CPU. The contents of
the HL register pair are placed on the address bus and
the input byte is written into the corresponding
location of memory. Then HL and the byte counter are
decremented. If decrementing causes B to go to zero, the
instruction is terminated. If B is not zero, the PC is
decremented by two and the instruction repeated.
Interrupts will be recognized and two refresh cycles
will be executed after each data transfer. Note that if
B Is set to zero prior to instruction execution, 256
bytes of data will be input.

If B=0:

M CYCLES: 5 T S TATE S : 2 1 ( 4 , 5 , 3 , 4 , 5 ) 4 MHZ E,T.: 5.25

If B=0:

M CYCLES: 4 T STATES: 16(4,5,3,4) 4 MHZ E.T.: 4.00

262

peripheral device mapped to I/O port address 07H, then

after the execution of

IND
memory location lOOOH will contain 7BH, the HL register
pair will contain OFFFH, and register B will contain
OFH.

261

OUT CnD

Operation ; (n) A

Format ;

Opcode

Operands

OUT
(n) ,A

110 10 11

D3

Description ;

The operand n Is placed on the bottom half (AO through

A7) of the address bus to select the 1/0 device at one
of 256 possible ports. The contents of the Accumulator
(register A) also appear on the top half (A8 through
A15) of the address bus at this time. Then the byte
contained in the Accumulator is placed on the data bus
and written into the selected peripheral device.

M CYCLES: 3 T STATES: 11(4, 3, A) 4 MHZ E.T.: 2.75

Condition Bits Affected : None

Example :

If the contents of the Accumulator are 23H, then after

the execution of

the byte 23H will have been written to the peripheral

device mapped to I/O port address OIH.

OUT (OIH), A

264

Condition Bits Affected:

S: Unknown

Z: Set

H: Unknown

P/V: Unknown

N: Set
Example :

If the contents of register C are 07H, the contents of

register B are 03H, the contents of the HL register pair
are lOOOH, and the following sequence of bytes are
available at the peripheral device napped to I/O port
address 07H:

51H
A9H
03H

then after the execution of

INDR

the HL register pair will contain OFFDH, register B will

contain zero, and memory locations will have contents as
follows :

Location Contents
OFFEH 03H

OFFFH A9H

lOOOH 51H

263

Condition Bits Affected: None

Example:

If the contents of register C are OIH and the contents

of register D are 5AH, after the execution of

OUT (C) ,D

the byte 5AH will have been written to the peripheral

device mapped to I/O port address OIH.

266
□ UT CCD. n

Operation: (C) <- r

Opcode

OUT

Operands

(C) .r

— I 1 1 1 1 1 1 —

1110 110 1

— I — I — I — I — I — I — I —

1 -« — r -0 1
■ I I L_-I I I—

ED

Description:

The contents of register C are placed on the bottom half

(AO through A7) of the address bus to select the I/O
device at one of 256 possible ports. The contents of
Register B are placed on the top half (A8 through A15)
of the address bus at this time. Then the byte
contained in register r is placed on the data bus and
written into the selected peripheral device. Register r
Identifies any of the CPU registers shown in the
following table, which also shows the corresponding
3-bit "r" field for each which appears in the assembled
object code:

Register

B
000

001

010

Oil

100

101
A

111

M CYCLES: 3 T STATES: 12(4,4,4) 4 MHZ E.T.: 3.00

265

59H, then after the execution of

OUTI

register B will contain OFH, the HL register pair will

contain lOOlH, and the byte 59H will have been written
to the peripheral device mapped to I/O port address 07H.

268

OUTI
Operation: (C) ^ (HL) , B ^ B-1 , HL HL + 1

Format :

Opcode

OUTI

— I 1 1 1 1 1 1 —

1110 110 1
I I — I — I — I — I — I —

1 1 1 1

■ ■ I I L— I I

ED
A3

Description:

The contents of the HL register pair are placed on the

address bus to select a location In memory. The byte
contained In this memory location Is temporarily stored
In the CPU, Then, after the byte counter (B) Is
decremented, the contents of register C are placed on
the bottom half (AO through A7) of the address bus to
select the I/O device at one of 256 possible ports.
Register B may be used as a byte counter, and Its
decremiented value Is placed on the top half (A8 through
A15) of the address bus. The byte to be output Is
placed on the data bus and written Into selected
peripheral device. Finally the register pair HL Is
Incremented .

M CYCLES: 4 T STATES: 16(4,5,3,4) 4 MHZ E.T.: 4.00

Condition Bits Affected:

S: Unknown

Z: Set If B-1-0;
reset otherwise

H; Unknown

P/V: Unknown

N: Set

C: Not affected

Example:

If the contents of register C are 07H, the contents of

register B are lOH, the contents of the HL register pair

are lOOOH, and the contents of memory address lOOOH are

267

Condition Bits Affected:

S: Unknown
Z: Set

H: Unknown

P/V: Unknown

N: Set

C: Not affected

Example :

If the contents of register C are 07H, the contents of

register B are 03H, the contents of the HL register pair
are lOOOH, and memory locations have the following
contents:

Location Contents

the HL register pair will contain 1003H, register B will

contain zero, and a group of bytes will have been
written to the peripheral device mapped to I/O port
address 07H in the following sequence:

lOOOH
lOOlH
1002H

51H
A9H
03H

then after the execution of

OTIR

51H
A9H
03H

270

OTIR
Operation : (C) (HL) , B ^ B-U HL^HL + 1
Format ;

Opcode

—1 1 1 1 1 1 1 —

1110 110 1
I I I I I I I

— I — I — I — I — I — I — I —
10 110 11
I — I I — I I — I I —

ED
B3

Description:

The contents of the HL register pair are placed on the

address bus to select a location In memory. The byte
contained in this memory location is temporarily stored
in the CPU. Then, after the byte counter (B) is
decremented, the contents of register C are placed on
the bottom half (AO through A7) of the address bus to
select the I/O device at one of 256 possible ports.
Register B may be used as a byte counter, and its
decremented value Is placed on the top half (A8 through
A15) of the address bus at this time. Next the byte to
be output is placed on the data bus and written into the
selected peripheral device. Then register pair HL is
incremented. If the decremented B register is not zero,
the Program Counter (PC) is decremented by 2 and the
Instruction is repeated. If B has gone to zero, the
instruction Is terminated. Interrupts will be recognized
and two refresh cycles will be executed after each data
transfer. Note that if B is set to zero prior to
instruction execution, the Instruction will output 256
bytes of data.

If B-0:

M CYCLES: 5 T STATES: 21(4,5,3,4,5) 4 MHZ E.T.: 5.25

If B-0:

M CYCLES: 4 T STATES: 16(4,5,3,4) 4 MHZ E.T.: 4.00

269

register B are lOH, the contents of the HL register pair

are lOOOH, and the contents of memory location lOOOH are
59H, after the execution of
OUTD

register B will contain OFH, the HL register pair will

contain OFFFH, and the byte 59H will have been written
to the peripheral device mapped to I/O port address 07H.

272

OUTD

Operation ; (C) <- (HL) , B B-1 , HL-^HL-1

Format :

Opcode
OUTD.

I'l'i'o'i'i'o'i

I'o' I'o' I'o' l' 1

■ ■ ■ ■ ■ l_l
ED
AB

Description ;

The contents of the HL register pair are placed on the

address bus to select a location in memory. The byte
contained in this memory location is temporarily stored
in the CPU. Then, after the byte counter (B) Is
decremented, the contents of register C are placed on
the bottom half (AO through A7) of the address bus to
select the I/O device at one of 256 possible ports.
Register B may be used as a byte counter, and its
decremented value is placed on the top half (A8 through
A15) of the address bus at this time. Next the byte to
be output is placed on the data bus and written into the
selected peripheral device. Finally the register pair
HL is decremented.

M CYCLES: A T STATES: 16(4,5,3,4) 4 MHZ E.T.: 4.00

Condition Bits Affected;

S:

Unknown

Z:

Set If B-l-O;

reset otherwise

H:

Unknown

P/V:

Unknown

N:

Set
C:

Not affected

Example ;

If the contents of register C are 07H, the contents of

271

Condition Bits Affected;

S: Unknown
Z : Set
H: Unknown
P/V: Unknown
N: Set

C: Not affected

Example :
If the contents of register C are 07H, the contents of
register B are 03H, the contents of the HL register pair
are lOOOH, and memory locations have the following
contents :

Location Contents

OFFEH 51H
OFFFH A9H
lOOOH 03H

then after the execution of

OTDR

the HL register pair will contain OFFDH, register B will

contain zero, and a group of bytes will have been
written to the peripheral device mapped to I/O port
addres 07H In the following sequence:

03H
A9H
51H

274

OTDR
Operation ; (C) ^ (HL) . B ^ B-1 , HL^HL-1
Format ;

Opcode
OTDR

— I 1 1 1 1 1 1 —

1110 110 1
I I I I \ I I

10 1110 11
I I I I I I

ED

BB

Description ;

The contents of the HL register pair are placed on the

address bus to select a location In memory. The byte
contained In this memory location Is temporarily stored
In the CPU. Then, after the byte counter (B) Is
decremented, the contents of register C are placed on
the bottom half (AO through A7) of the address bus to
select the I/O device at one of 256 possible ports.
Register B may be used as a byte counter, and Its
decremented value Is placed on the top half (A8 through
A15) of the address bus at this time. Next the byte to
be output Is placed on the data bus and written into the
selected peripheral device. Then register pair HL Is
decremented and If the decremented B register Is not
zero, the Program Counter (PC) Is decremented by 2 and
the Instruction Is repeated. If B has gone to zero, the
instruction is terminated. Interrupts will be
recognized and two refresh cycles will be executed after
each data transfer. Note that if B is set to zero prior
to instruction execution, the Instruction will output
256 bytes of data.

If B-0:

M CYCLES: 5 T STATES: 21(4,5,3,4,5) 4 MHZ E.T.: 5.25

If B-0:

M CYCLES: 4 T STATES: 16(4,5,3,4) 4 MHZ E.T.: 4.00

273

EX (SP),IX Exchange the location (SP)

and IX 81

EX (SP),IY Exchange the location (SP)

and lY 82

EX AF,AF' Exchange the contents of AF and AF' 78

EX DE.HL Exchange the contents of DE and HL 77

EXX Exchange the contents of

BC,DE,HL with contents of

BC'.DE'.HL' respectively 79

HALT HALT (wait for Interrupt or reset) 140

XM Set Interrupt mode 14|3

IM 1 Set interrupt mode 1 144

IM 2 Set interrupt mode 2 MB

IN A,(n) Load the Acc. with

input from device n 253

IN r,(C) Load the Reg. r with

input from device (C) 254

INC (HL) Increment location (HL) 124

INC IX Increment IX 158

INC (IX+d) Increment location (IX+d) 125

INC lY Increment lY 159

INC (lY+d) Increment location (lY+d) 127

INC r Increment Reg. r 122

INC ss Increment Reg. pair ss 157

IND Load location (HL) with

input from port (C) ,

decrement HL and B 260

INDR Load location (HL) with

Input from port (C) ,

decrement HL and decrement B,

repeat until B-0 262

INI Load location (HL) with

input from port (C) ;

and increment HL and decrement B 256

INIR Load location (HL) with

input from port (C) ,

increment HL and decrement B,

repeat until B-0 258

JP (HL) Unconditional Jump to (HL) 232

JP (IX) Unconditional Jump to (IX) 233

JP (lY) Unconditional Jump to (lY) 234

JP cc.nn Jump to location nn

If condition cc is true 221

JP nn Unconditional jump to location nn 220

JR C,e Jump relative to

PC+e If carry-1 224

JR e Unconditional Jump

relative to PC+e „ 223

JR NC,e Jump relative to

PC+e if carry-0 226

276
Z80-CPU INSTRUCTION SET

ALPHABETICAL

ASSEMBLY MNEMONIC OPERATION PAGE

ADC HL.ss Add with Carry Reg. pair ss to HL 149

ADC A,s Add with carry operand s to Acc...> 108

ADD A,n Add value n to Acc 102

ADD A,r Add Reg. r to Acc 100

ADD A,(HL) Add location (HL) to Acc 103

ADD A,(IX+d) Add location (IX+d) to Acc 104

ADD A,(IY+d) Add location (lY+d) to Acc 106

ADD HL.ss Add Reg. pair ss to HL 147

ADD IX, pp Add Reg. pair pp to IX 153

ADD lY.rr Add Reg. pair rr to lY 155

AND s Logical 'AND' of operand s and Acc 114

BIT b,(HL) Test BIT b of location (HL) 205

BIT b,(IX+d) Test BIT b of location (IX+d) 207

BIT b,(IY+d) Test BIT b of location (lY+d) ^.209

BIT b.r Test BIT b of Reg. r 203

CALL cc.nn Call subroutine at location nn if

condition cc is true 240

CALL nn Unconditional call subroutine

at location nn 238

CCF Complement carry flag 137

CP s Compare operand s with Acc 120

CPD Compare location (HL) and Acc.

decrement HL and EC 95

CPDR Compare location (HL) and Acc.

decrement HL and BC,

repeat until BC-0 97

CPI Compare location (HL) and Acc.

increment HL and decrement BC 91

CPIR Compare location (HL) and Acc.

increment HL, decrement BC

repeat until BC-0 93

CPL Complement Acc. (I's comp) 134

DAA Decimal adjust Acc 132

DEC m Decrement operand m 129

DEC IX Decrement IX 161

DEC lY Decrement lY ..162

DEC ss Decrement Reg. pair ss .160

DI Disable interrupts 141

DJNZ e Decrement B and Jump

relative if B"0 235

EI Enable interrupts 142

EX (SP),HL Exchange the location (SP)

and HL 80

275
LDI Load location (DE) with location (HL),

increment DE,HL, decrement BC «... 83

LDIR Load location (DE) with location (HL),

Increment DE.HL, decrement

BC and repeat until BC-0 83

NEG Negate Acc. (2's complement) 135

NOP No operation 139

OR s Logical 'OR' of operand s and Acc 116

OTDR Load output port (C) with location (HL)

decrement HL and B,

repeat until B = 273

OTIR Load output port (C) with location (HL),

increment HL, decrement B,

repeat until B = 269

OUT (C),r Load output port (C) with Reg. r 265

OUT (n),A Load output port (n) with Acc 264

OUTD Load output port (C) with location (HL) ,

decrement HL and B 271

OUTI Load output port (C) with location (HL),

increment HL and decrement B 267

POP IX Load IX with top of stack 74

POP lY Load lY with top of stack 75

POP qq Load Reg. pair qq with top of stack 72

PUSH IX Load IX onto stack 70

PUSH lY Load lY onto stack 71

PUSH qq Load Reg. pair qq onto stack 69

RES b,m Reset Bit b of operand m 217

RET Return from subroutine 243

RET cc Return from subroutine if condition

cc is true 244

RETI Return from interrupt 246

RETN Return from non maskable interrupt 248

RL m Rotate left through carry operand ra 180

RLA Rotate left Acc. through carry ^. 166

RLC (HL) Rotate location (HL) left circular 174

RLC (IX+d) Rotate location (IX+d) left circclar ...176

RLC (lY+d) Rotate location (lY+d) left circular 178

RLC r Rotate Reg. r left circular 172

RLCA Rotate left circular Acc. i. 164

RLD Rotate digit left and right

between Acc. and location (HL) 198

RR m Rotate right through carry operand m 186

RRA Rotate right Acc. through carry 170

RRC m Rotate operand m right circular 183

278

JR NZ,e Jump relative to

PC+e If non zero (Z-0) 230

JR Z,e Jump relative to

PC+e If zero (Z=l) 228

LD A,(BC) Load Acc. with location (BC) 42

LD A,(DE) Load Acc. with location (DE) 43

LD A, I Load Acc. with I 48

LD A,(nn) Load Acc. with location nn 44

LD A,R Load Acc. with Reg. R 49

LD (BC),A Load location (BC) with Acc 45

LD (DE),A Load location (DE) with Acc. 46

LD (HL),n Load location (HL) with value n 39

LD dd,nn Load Reg. pair dd with value nn 53

LD dd,(nn) Load Reg. pair dd with location (nn) 57

LD HL,(nn) Load HL with location (nn) 56

LD (HL),r Load location (HL) with Reg. r 34

LD I, A Load I with Acc 50

LF IX, nn Load IX with value nn 54

LD IX, (nn) Load IX with location (nn) 59

LD (IX+d),n Load location (IX+d) with value n 40

LD (IX+d),r Load location (IX+d) with Reg. r 35

LD IY,nn Load lY with value nn 55

LD IY,(nn) Load lY with location (nn) 60

LD (IY+d),n Load location (lY+d) with value n 41

LD (IY+d),r Load location (lY+d) with Reg. r 37

LD (nn) ,A Load location (nn) with Acc. 47

LD (nn),dd Load location (nn) with Reg. pair dd 62

LD (nn),HL Load location (nn) with HL 6t

LD (nn),IX Load location (nn) with IX 64

LD (nn),IY Load location (nn) with lY 65

LD R,A Load R with Acc 51

LD r,(HL) Load Reg. r with location (HL) 29

LD r,(IX+d) Load Reg. r with location (IX+d) 30

LD r,(IY+d) Load Reg. r with location (lY+d) 32

LD r,n Load Reg. r with value n 28

LD r,r' Load Reg. r with Reg. r' 27

LD SP,HL Load SP with HL '. 66

LD SP,IX Load SP with IX 67

LD SP.IY Load SP with lY 68

LDD Load location (DE) with location (HL),

decrement DE,HL and BC 87

LDDR Load location (DE) with' locat'lon" "(HL) ,

decrement DE.HL and BC ;

repeat until BC=0 89

277

APPENDIX A
ERROR MESSAGES AND EXPLANATIONS

1) WARNING - OPCODE REDEFINED

Indicates that an opcode has been redefined by
a macro so that future uses of the opcode will
result in the appropriate macro call. This
message may be suppressed by the NOW option.

2) NAME CONTAINS INVALID CHARACTERS

Indicates that a name (either a label or an

operand) contains Illegal characters. Names
must start with an alphabetic character and
any following characters must be either
alphanumeric (A...Z or 0...9), a question mark
(?) or an underbar ( ).

3) INVALID OPCODE

Indicates that the opcode was not recognized.

Occurs when the opcode contains an illegal
character (including non-printing control
characters), when the opcode Is not either all
upper case or all lower case, or when macros
are used and the M option is not specified.

4) INVALID NUMBER

Indicates an invalid character in a number.

Occurs when a number contains an Illegal
character (including non-printing control
characters) or a number contains a digit not
allowed in the specified base (e.g., 8 or 9 in
an octal number or a letter in a hexadecimal
number where the trailing H was omitted.)
5) INVALID OPERATOR

Indicates use of an invalid operator in an

expression. Occurs when an operator such as
AND or XOR is misspelled or contains illegal
characters .

6) SYNTAX ERROR

Indicates the syntax of the statement is

invalid. Occurs when an expression is
incorrectly formed, unmatched parenthesis are
found in an operand field, or a DEFM string is
either too long (greater than 63 characters)
or contains unbalanced quotes.

7) ASSEMBLER ERROR

Indicates that the assembler has failed to

process this instruction. Usually occurs when
an expression is incorrectly formed.

8) UNDEFINED SYMBOL

Indicates that a symbol In an operand field

280

RRCA Rotate right circular Acc 168

RRD Rotate digit right and left

between Acc. and location (HL) 200

RST p Restart to location p 250

SBC A,s Subtract operand s

from Acc. with carry 112

SBC HL,ss Subtract Reg. pair ss from

HL with carry 151

SCF Set carry flag (C-I) 138

SETb.CHL) Set Bit b of location (HL) 212

SET b,(IX+d) Set Bit b of location (IX+d) 213

SET b,(IY+d) Set Bit b of location (lY+d) 215

SET b,r Set Bit b of Reg. r 211

SLA m Shift operand m left arithmetic 189

SRA m Shift operand m right arithmetic 192

SRL m Shift operand m right logical 195

SUB s Subtract operand s from Acc. 110

XOR s Exclusive 'OR' operand s and Acc 118

279

bytes). The line will be truncated.

16) MACRO STACK OVERFLOW

Indicates that the depth of nesting of macro

calls has exceeded the macro parameter stack
buffer capacity. Occurs when the sum of the
parameter string lengths (plus some additional
information for each macro call) is longer
than the buffer (currently 256 bytes), which
often happens if infinitely recursive macro
calls are used. The macro call which caused
the error will be ignored.

17) INCLUDE NESTED TOO DEEP

Indicates that a *Include command was found

which would have caused a nesting of included
source files to a depth greater than four,
where the original source file is considered
to be level one. The command will be ignored.

18) GLOBAL DEFINITION ERROR

Indicates that either a label was present on a

GLOBAL pseudo-op statement, or there was an
attempt to give an absolute value to a GLOBAL
symbol in a relocatable module. The latter
case is not allowed since all GLOBALs in a
relocatable module will be relocated by the
Linker. May occur either after a GLOBAL
pseudo-op or after an EQU or DEFL statement
which is attempting to absolutize a
relocatable GLOBAL symbol.

19) EXTERNAL DEFINITION ERROR

Indicates that either a label was present on

an EXTERNAL pseudo-op statement, or there was
an attempt to declare a symbol to be EXTERNAL
which had previously been defined within the
module to have an absolute value. May occur
due to a misspelling or other oversight.

20) NAME DECLARED GLOBAL AND EXTERNAL

Indicates that the name was found in both a

GLOBAL pseudo-op and an EXTERNAL pseudo-op
which is contradictory. May occur due to a
misspelling or other oversight.

21) LABEL DECLARED AS EXTERNAL

Indicates that a name has been declared in

both an EXTERNAL pseudo-op and as a label in
this module. May occur due to a misspelling
or other oversight.
22) INVALID EXTERNAL EXPRESSION

Indicates that a symbol name which has been

declared in an EXTERNAL pseudo-op is
Improperly used in an expression. May occur
when invalid arithmetic operators are applied
to an external expression or when the mode of

282

was never defined. Occurs when a name Is

misspelled or not declared as a label for an
instruction or pseudo-op.
9) INVALID OPERAND COMBINATION

Indicates that the operand combination for

this opcode is invalid. Occurs when a register
name or condition code is missspelled or
incorrectly used with the particular opcode.

10) EXPRESSION OUT OF RANGE

Indicates that the value of an expression is

either too large or too small for the
appropriate quantity. Occurs on 16-bit
arithmetic overflow or division by zero in an
expression, incrementing the reference counter
beyond a 16-bit value, or trying to use a
value which will not fit into a particular
bit-field - typically a byte.

11) MULTIPLE DECLARATION

Indicates that an attempt was made to redefine

a label. Occurs when a label is misspelled,
or mistakenly used several times. The
pseudo-op DEFL can be used to assign a value
to a label which can then be redefined by
another DEFL.

12) MACRO DEFINITION ERROR

Indicates that a macro is incorrectly defined.

Occurs when the M option is not specified but

macros are used, when a macro is defined
within another macro definition, when the
parameters are not correctly specified, or an
unrecognized parameter is found in the macro
body .

13) UNBALANCED QUOTES

Indicates that a string is not properly

bounded by single quote marks or quote marks
inside a string are not properly matched in
pairs .

14) ASSEMBLER COMMAND ERROR

Indicates that an assembler command is not

recognized or is incorrectly formed. The
command must begin with an asterisk (*) in
column one, the first letter identifies the
command, and any parameters such as 'ON', 'OFF'
or a filename must be properly delimited. The
command will be ignored.

15) MACRO EXPANSION ERROR

Indicates that the expansion of a single line

in a macro has overflowed the expansion
buffer. Occurs when substitution of parameter
causes the line to increase in length beyond
the capacity of the buffer (currently 128

281

APPENDIX B
INSTRUCTION SET ALPHABETICAL ORDER
2-80 CROSS ASSEMBLER VERSION 1.06 OF 06/18/76

U//UV/IO 1U>££>

LOC OBJ coot

STMT
SOURCE STATEMENT

LOC

08J CODE

STMT

SOURCE STATEMENT

0000

8E

AOC

Al (HLi

007C
CB56

70

BIT

2.(HL)

inni

0D8E05

AOC

A> ( IX + INO)

007E

DDCB0556
71

BIT

2. ( tX«^IN0)

0004

FDBE05

AOC

A, ( lY-flNOI

U082

F0CB0556

72
BIT

2.(lY+IN0)

0007

AOC

Af A

0086

CB57

73

BIT

2.A
0008

68

AOC

AfB

U088

CB50

74

BIT

2.B
89

AOC

AtC

008A

CB51

75

BIT

2,C

OOOA

8A
7

AOC

AtO

008C

CB52

76

8IT

2,0

OOOB

88

g
AOC

A.E

008E

CB53

77

BIT

2.E

OOOC

ac

AOC
A,H

009Q

CB54

78

BIT

2|H

80

10

ADC

AtL

0092
Ca55

79

BIT

2.L

OOOE

CE20

AOC

A(N

0094

CB5E
80

BIT

3. IHL)

0010

E04A

12

AOC

HL.BC

0096

0DCB055E

61
BIT

3t( tXt-INO)

0012

E05A

13

AOC

HL.DE

009A

FDCB055E

62

BIT
StllY^-INO)

E06A

14

AOC

HLfHL

009E

CB5F

83

BIT

3. A
0016

ED7A

15

AOC

HL.SP

00 AO

CB58

84

BIT

3,B
86

ADD

A , ( HL )

O0A2

CBS9

85

BIT

3tC

0019

008605

17
ADU

At ( IX+IND)

00A4

CB5A

86

BIT

3.0

OOlC

FD8605

18

ADO
A, ( lYt-INO)

00A6

CB5B

87

BIT

3.E

OOIF

87

19

ADD

A, A
O0A8

CB5C

88

BIT

3.H

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an operand must be either absolute or

relocatable.

23) INVALID RELOCATABLE EXPRESSION

Indicates than an expression which contains a

relocatable value (either a label or the
reference counter sumbol $ In a relocatable
module) is improperly formed or used. May
occur when invalid arithmetic operators are
applied to a relocatable expression or when
the mode of an operand must be absolute.
Remember that all relocatable values
(addresses) must be represented in 16 bits.

24) EXPRESSION MUST BE ABSOLUTE

Indicates that the mode of an expression is

not absolute when it should be. May occur
when a relocatable or external expression is
used to specify a quantity that must be either
constant or representable in less than 16
bits.

25) UNDEFINED GLOBAL(S)

Indicates that one or more sumbols which were

declared in a GLOBAL pseudo-op were never
actually defined as a label In this module.
May occur due to a misspelling or other
oversight .

26) WARNING - ORG IS RELOCATABLE

Indicates that an ORG statement was

encountered in a relocatable module. This
warning is Issued to remind the user that the
reference counter is set to a relocatable
value, not an absolute one. May occur when
the Absolute option is not specified for an
absolute module. This warning may be
suppressed by the NOW option.
283

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Z-SO CROSS ASSEMBLER VERSION 1.06 OF 06/18/76

U7/04/76 10:22:
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07/09/76 10:22:4 7

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563

SET
0.(HLJ

0502

CBF5

632

SET

6rL

045E

0DCB05C6

564

SET

OtdX^-IND)
0504

CBFE

633

SET

7 ff (HLl

0462

F0CB05C6

565

SET

0t( IV«^INO)

0506
00CB05FE

634

SET

7ff t IX^INO)

0466

CBC7

S66

SET

O.A

05 OA

F0CB05FE
635

SET

7t ( lY^IND)

0468

CBCO

567

SET

OiB

050E

C8FF

636
SET

7tA

046A

CBCl

568

SET

0,C

CBF8

637

SET
7tB

046C

CBC2

569

SET

OfD

0512

CBF9

638

SET

7tC
046E

CBC3

570

SET

O.E

05 14

CBFA

639

SET

7f

0470
C6C4

57i

SET

OfH

0516

CBFB

640

SET

7f E

0472

CBC5
572

SET

O.L

0518

CBFC

641

SET

7tH

0474

CBCE

573
SET

lilHL)

CBFD

642

SET

7iL

0476

0DCB05CE

574

SET

1,(IX+IN0I
05 IC

CB26

643

SLA

(HL)

04 7 A

F0Cd05Cc

575

SET

1,( lYtlNO)

05 IE
00CB0526

644

SLA

{ IX'flNOI

04 7E

CBCF

5 76

SET

IfA

0522

FDCB0526
645

SLA

( lY't'IND)

0480

CBC8

577

SET

IfB

0526

CB27

646
SLA

0482

578

SET

ItC

647

SLA
0484

rSfA
CBCA

579

SET

ItO

052A

CB2X

648

SLA

0486
CBCB

580

SET

1>E

052C

C822

649

SLA

0488

CBCC
581

SET

l.H

052E

CB23

650

SLA

048A

CBCD

582
SET

ItL

0530

CB24

651

SLA

04 8C

CB06

583

SET
2.(HL)

0532

CB25

652

SLA

048E

0OCBO506

584

SET

2f (IX«^IND)
0534

CB2E

653

SRA

(HL 1

0492

FOCB0506

585

SET

2t(IY<'IND)

0536
OOCB052E

654

SRA

( IX4-IN0)

0496

C807

586

SET

2, A

053A

FDCB052E
655

SRA

( lYf-INO)

0498

CBDO

587

SET

2.B

053E

CB2F

656
SRA

049A

CBOl

588

SET

2.C

CB28

657

SRA
B

04 9C

CB02

589

SET

2i0

0542

CB29

658

SRA

C
049E

CB03

590

SET

2.E

0544

CB2A

659

SRA

04 AO
C804

591

SET

2..H

0546

CB26

660

SRA

04A2

CB05
592

SET

2tL

C62C

661

SRA

04A4

CB08

593
SET

3 8

054A

CB2D

662

SRA

04A6

C6DE

594

SET
3tlHL»

054C

CB3E

663

SRL

04 A 8

595

SET

3«<IX*IN0)

054E
0DCB053E

664

SRL

1 IX-*-lNOI

04AC

F0CB050E

596

SET

3f lIYt-INO)

0552

F0CB053E
665

( 1 Y ^iMO 1

0480

597

SET

3tA

0556

CB3F

666
*

04B2

CB09

598

SET

3»C

0558

CB38

«B1
599

SET

3>0

055A

CB39

QBl

Ihi

rnoB

600
SET

3tE

055C

CB3A

669

n oa

rnnr

601

SET
3,H

055E

CB3B

A7i*

«i

n^RA

f Run

602

SET

3f L

0560
CB3C

671

SRL

nlar

C6E6

603

SET

4t (HL)

0562

CB3D
672

SRL

n^BC

604

SET

4<( IXtlNOI

0564

96

673
SUB

(HL)

n^rj

605

SET

4t ( lY+INO)

0565

009605

674

SUB

( IX>I^O)
606

SET

4t A

0568

FD9605

675

SUB

( IY«^INO)

□tea
cbIo

607

SET

4fB

0568

97

676

SUB

n^r A

608
SET

4iC

056C

90

677

SUB

nVrr

r ?

609

SET
4tD

0560

91

678

SUB

7^

rRF3

610

SET

4tE
056E

92

679

SUB

0400

CBc4

611

SET

4f H

056F
93

680

SUB

0402

CBE5

612

0570

94
0404

CBEE

613

SET

5> (HLi

0571

95

682

SUB
L

0406

DDCBOSEE

614

SET

S.(IXtlNO)

0572

D620

683

SUB

H
040A

FDCB05EE

615

SET

5f (IY*INDI

0574

AE

684

XOR

(HL)

04UE
CBEF

616

SET

5, A

0575

00AE05

685

XOR

(IXtlNOI

04 EO

CBE8
617

SET

5,B

0578

F0AE05

686

XOR

(lYl-IND)

04E2

CBE9

618
SET

5,C

057B

AF

687

XOR

04E4

CBEA

619

SET
SfO

057C

A8

688

XOK

04E6

CBEB

620

SET

5,E
05 70

A9

689

XOR

04EB

CBEC

621

SET

5,H

057E
AA

690

XOR

2-eO CKOSS ASSEMBLER VERSION 1.

07/09/76 10:22J47 OPCODt LISTING

LOC OBJ coot STMT SOURCE STATEMENT

0328

CB8F

416

RES

1 1
|A

032A

ceaa

416

RES

li

iB

03 2 C

ceev

417

RES
li

rC

032E

CB8A

418

RES

1<

>0

0330

CB8B

419
RES

li

lE

0332

CB8C

420

RES

1,

>H

0334

CBBD
421

RES

1<

>L

0336

CB96

422

RES

2,

>(HLI

033B
DDCB0596

423

RES

2.

r ( IX+IND)

33C

F0CB0596

424

RES

2i

,( lYI-INDI
03«0

€697

425

RES

2i

rA

0342

CB90

426

RES

2i
rB

0344

CB91

42 7

RES

2i

>C

0346

CB92

428

RES
2.

.0

0348

CB93

429

RES

2,

,E

034A

CB94

430
RES

2i

iH

034C

C695

431

RES

2,

rL

034E

CB9E
432

RES

3,

, IHL)

0350

D0CB059E

433

RES

3,

,(IXtINDI

03S4
F0CB059E

434

RES

3,

, ( lY + IND)

0358

CB9F

435

RES

3,

>A
035A

C698

436

RES

3i

rB

035C

CB99

43 7

RES

3i
rC

035E

CB9A

438

RES

3,

rO

0360

CB9B

439

RES
3,

,E

0362

CB9C

440

KES

3,

rH

0364

CB90

441
RES

3,

,L

0366

CBA6

442

RES

4,

, (HL)

0368

0UCB05A6
443

RES

4,

,( IX+INDl

036C

F0CB05A6

444

RES

4,

,( lY+INOl

0370
CBA7

445

RES

4,

.A

0372

CBAO

446

RES

4,

>B
0374

CBAl

447

RES

4,

rC

0376

CBA2

448

RES

4,
rO

0378

CBA3

449

RES

4,

,E

037A

CBA4

450

RES
4,

.H

037C

CBA5

451

RES

4i

,L

03 7E

CBAE

452
RES

5i

r (HLI

U380

0OCBO5AE

453

RES

5,

0384

FDCBOSAE
454

RES

5,

, { lY + INDJ

0388

CBAF

455

RES

5f

>A

038A
CBA8

456

RES

5,

rB

038C

CBA9

457

RES

5,

,C
038E

CBAA

458

RES

5,

rD

0390

CBAB

459

RES

5,
,E

0392

C8AC

460

RES

5,

.H

0394

CBAO

461

RES
5,

>L

0396

CBB6

462

RES

6i

, (HL)

0398

00CB05B6

463
RES

6,

i(IX«^INU)

039C

FDCB05B6

464

RES

6,

r ( IY*IND)

03 AO

CBB7
465

RES

6,

>A

03A2

CBBO

466

RES

6i

tB

03 A4
CBBl

467

RES

6i

iC

03A6

CBB2

468

RES

6i

rO
3A8

CBB3

469

RES

6,

lE

03AA

C6B4

470

RES

6i
iH

03 AC

CBB5

471

RES

6,

iL

03AE

CBBE

472

RES
7.

> ( HL )

03 BO

DDCB05BE

473

RES

7,

, ( IX+INO)

03B4

FDCB05BE

474
RES

7,

, ( lYi-INO)

03B8

CBBF

475

RES

7i

lA

03BA

CBB8
476

RES

7,

rB

03BC

CBB9

477

RES

7,

>c

03BE
CBBA

478

RES

7,

>D

03C0

CBBB

479

RES

7,

>E
03C2

CBBC

480

RES

7,

iH

03C4

CBBD

481

RES

7,
iL

03C6

C9

482

RET

03C/

08

483

RET

C
OF 06/18/76

LOC OBJ coot STMT SOURCE STATEMENT

03C8

F8

484

03C9

485
RPT

03CA

CO

486

OCT

U7

03CB

FO

487

RET

D
03CC

,E8

488

PC

03CD

EO

489

HPT

on

03CE
C8

490

OCT

03CF

E040

491

DCTI

03DI

ED45
492

OCTN

RETN

0303

CB16

493

d*^

(HL )

03DS

OOCB0516

494
03 D9

F0CB0516

495

Dl

I 1 T* IMU 1

03 OD

CB17

496

RL

*
03DF

CBIO

497

RL

OiEl

CBll

498

RL

03E3
CB12

Ri*^

J"

03E5

CB13

sin
500

03E7

CB14

501
D

03 E9

CB15

502

RL

03EB

1 7

503

RLA
03EC

CB06

504

RLC

IHLJ

03EE

DOCB0506

505

RLC

( IX-*-lND)

03f 2
FDC6U506

506

RLC

1 1 T * 1 nu 1

03F6

CB07

507

RLC

03F8

CBOO
508

RLC

03FA

CBOl

509

RLC

03FC

CB02

510
RLC

03FE

CB03

511

RLC

0400

CB04

512

RLC
H

0402

CB05

513

RLC

*-

0404

07

514

RLCA
0405

ED6F

515

RLD

0407

CBIE

516

RR

IHL I

0409

ODCBOSlt
517

( I X+ INO )

040D

FDCBU51t

5 18

RR

111*1 nui

0411

CBIF

519
*

0413

CB 16

520

DO

RR

0415

CB19

521
C

0417

CBIA

522

RR

0419

CBIB

523

E
041B

CBIC

524

DD

RR

0410

CBIO

525

RR

041F
IF

525

RRA

0420

Cboe

527

RRC

( HL 1

0422

0DCB050E
528

RRC

1 IX4-IND)

0426

FDCB050E

529

II Y+IND)

042A

CBOF

530

Dor
*

042C

CB08

531

RRC

042E

CB09

532

RRC

C
0430

CBOA

533

0432

CBOB

534

aor

0434

CBOC
Dor

0436

CBOD

BRf

0438

RHf A
0439

ED6 7

DBn

04 3 B

C7

tin

OCT

043C

07
OCT

0430

OF

541

R^T

in

04 3 E

E7

542

RST
f «H

043F

EF

544

RST

30H

0441
FF

545

RST

38H

0442

CF

546

RST

0443

9E
547

SBC

A.(HL)

0444

DD9E05

548

SBC

A.IIXi^INOi

0447

Fl)9E05

549
SBC

A,( lY^INOI

044A

9F

550

SBC

At A

044B

98

551

SBC
A,B

04 4C

99

552

SBC

A,C

287

APPENDIX C
INSTRUCTION SET NUMERICAL ORDER

Z-eO CROSS ASSEMBLER VERSION 1.06 OF 06/18/76

LOC
OBJ CODE

STMT

SOURCE STATEMENT

LOC

OBJ CODE

STMT

SOURCE STATgMENT

0000

00

NOP
0063

45

70

LO B.L

0001

018405

LO BC.NN

0064

46

71
LO B.(HL)

0004

02

LO (BC).A

0065

47

72

LO B.A

0005

03
4

INC BC

0066

48

73

LD C.B

0006

04

INC B

0067
49

74

LO C.C

0007

05

DEC B

0068

4A

75

LO CD
0008

0620

LO B,N

0069

4B

76

LO C.E

OOOA

07

8
RLCA

006A

4C

77

LO C.H

oooa

08

EX AFfAF*

006B

40
78

LO C.L

oooc

09

10

AOO HLfBC

006C

4E

79

LD C.IHL)

0000
OA

11

LO A.IBC)

0060

4F

80

LD C.A

UOOE

OB

12

DEC BC
006E

50

81

LO O.B

OOOF

OC

13

INC C

006F

51

82
LO D.C

0010

00

14

DEC C

0070

52

S3

LD 0.0

0011

0E20
15

LO C.N

0071

53

84

LO O.E

0013

OF

16

RRCA

0072
54

85

LO D.H

0014

102 E

17

OJNZ DIS

0073

55

86

LD D.L
0016

118405

18

LO OE.NN

0074

56

87

LD O.(HL)

0019

12

19
LO (OEI.A

0075

57

88

LO O.A

OOIA

13

20

INC OE

0076

58
89

LD E.a

0018

14

21

INC

0077

59

90

LO E.C

OOlC
15

22

DEC

0078

5A

91

LO E.O

0010

1620

23

LO O.N
0079

SB

92

LO E.E

00 IF

17

24

RLA

007A

5C

93
LO E.H

0020

182E

25

JR OIS

007B

50

94

LO E.L

0022

19
26

AOD HL.OE

007C

SE

95

LO E.lHLt

0023

lA

27

LO A.(OE)

0070
5F

96

LO E.A

0024

IB

28

DEC DE

007E

60

97

LO H.B
0025

IC

29

INC E

007F

61

98

LO H.C

0026

10

30
DEC E

0080

62

99

LD H.D

0027

1E20

31

LO E.N

0081

63
100

LO H.E

0029

IF

32

RRA

0082

64

101

LO H.H

002A
202E

33

JR NZ.DIS

0083

65

102

LO H.L

002C

218405

34

LO HL.NN
0084

66

103

LD H.IHLi

002 F

228405

35

LO INNI.HL

0085

67

104
LO H.A

0032

23

36

INC HL

0086

68

105

LD L.B

0033

24
37

INC H

0087

69

106

LO L.C

0034

25

38

OEC H

0088
6A

107

LO L.O

0035

262 U

39

LO H.N

0089

6B

108

LD L.E
0037

27

40

DAA

008A

6C

109

LD L.H

0038

282E

41
JR Z.OIS

008B

60

110

LO L.L

003A

29

42

AOO HL.HL

OOSC

6E
111

LO LtiHLI

003B

2A8405

43

LO HL.INNl

0080

6F

112

LO L.A

003E
2B

44

DEC HL

008E

70

113

LO (HL).B

003F

2C

45

INC L
008F

71

114

LD (HLI.C

U040

20

46

OEC L

0090

72

115
LO (HL).O

0041

2E20

47

LO L.N

0091

73

116

LO (HLt.E

0043

2F
48

CPL

0092

74

117

LO (HL)iH

0044

302 E

49

JR NC.OIS

0093
75

118

LO (HL).L

0046

318405

50

LO SP.NN

0094

76

119

HALT
0049

328405

51

LO (NNi.A

0095

77

120

LD IHD.A

004C

33

52
INC SP

0096

78

121

LO A.B

0040

34

53

INC (HL)

009 7

79
122

LO AtC

004E

35

54

OEC (HLt

0098

7 A

123

LO A.O

004F
3620

55

L0>' (HD.N

0099

7B

124

LO A.E

0051

37

56

SCF
009A

7C

125

LD A.H

0052

3e2E

57

JR C.OIS

009B

70

126
LD A.L

0054

39

58

AOD HL.SP

009C

7E

127

LO A.(HL)

0055

3A840S
59

LO A. INN)

0090

7F

128

LD A.A

U05S

3B

60

OEC SP

009E
80

129

AOO A.B

0059

3C

61

INC A

009F

81

130

AOD AtC
OOSA

30

62

OEC A

OOAO

82

131

ADO A.O

00 SB

3E20

63
LO A.N

OOAl

83

132

AOO A.E

0050

3F

64

CCF

00A2

84
133

AOO A.H

005E

40

65

LO B.B

00A3

65

134

ADD A.L

OOSF
41

66

LO B.C

00A4

86

135

AOD A.IHLi

0060

42

67

LD B.D
OOAS

87

136

AOO A.A

0061

43

68

LO B.E

00A6

88

137
ADC A.B

0062

44

69

LO B.H.NN

00A7

S9

138

AOC A.C

290
Z-80 CROSS ASSEMBLER VERSION 1.06 OF 06/18/76
07/09/76 I0!2<i:*7 OPCODE LISTING

LOC OUJ CODE STMT SOURCE STATEMENT

057F AB

0580 AC

0581 AO

0582 ££20
0584

691

XOR

692
XOR

693

XOR

694

XOR

695
NN

DEFS

696

I NO

Ego

697

EUU

lOH
698

EOU

20H

699

OIS

EQU

30H

700

END
289

Z-80 CROSS ASSEMBLER VERSION 1.06 OF 06/18/76

07/09/76 10:20*50 .OPCODE LISTING

1 nr
LOC

STMT

SOURCE STATEMENT

LOC

OBJ COOk

STMT

SOURCE STATEMENT
0178

CB18

277

RR B

0202

CB65

346

BIT

4.L

017A

CB19
278

RR C

0204

CB66

347

BIT

4. (HLi

017C

CBIA

279

RR
0206

C867

348

BIT

4. A

017E

CBIB

280

RR

0208
CB68

349

BIT

5.B

0180

CBIC

281

RR H

020A

CB69

350
dIT

5.C

0182

CBIO

282

RR 1

02 OC

CB6A

351

BIT
5,0

0184

CBIE

283

RR

HL)

020E

Ca6B

352

BIT

5.E
0186

CBIF

284

RR /

0210

CB6C

353

BIT

5.H

0188
CB20

285

SLA

0212

CB60

354

BIT

5.L

018A

C621
286

SLA

0214

CB6E

355

BIT

5. (ML)

018C

CB22

287
SLA

0216

CB6F

356

BIT

5. A

018E

CB23

288

SLA
E

0218

CB70

357

BIT

6iB

0190

CB24

289

SLA

H
02 lA

CBTl

358

BIT

6iC

0192

CB25

290

SLA

02 IC
CB72

359

BIT

6.0

0194

CB26

291

SLA

IHL)

02 IE

Ca73
360

BIT

6.E

0196

CB27

292

SLA

0220

CB74

361
BIT

6.H

0198

CB2S

293

SRA

0222

CB75

362

BIT
6.L

019A

CB29

294

SRA

0224

CB76

363

BIT

6. (HLI
019C

CB2A

295

SRA

0226

CB77

364

BIT

6. A

019E
C82B

296

SRA

0228

CB78

365

BIT

7.B

OlAO

CB2C
297

SRA

022A

CB79

366

BIT

7.C

01A2

CB2D

298
SRA

022C

CB7A

367

BIT

7.0

01A4

CB2E

299

SRA
(HL)

022E

CB7B

368

BIT

7.E

01A6

CB2F

300

SRA

A
0230

CB7C

369

BIT

7.H

OlAS

CB36

301

SRL

0232
CB7D

370

BIT

7.L

OlAA

CB39

302

SRL

0234

CB7E
371

BIT

7.(HL)

OlAC

CB3A

303

SRL

0236

CB7F

372
BIT

7. A

OlAE

CB3B

304

SRL

0238

CBSO

373

RES
O.B

01 BO

CB3C

305

SRL

023A

CB81

374

RES

O.C
6lB2

CB3D

306

SRL

023C

CB82

375

RES

0.0

0184
CB3E

307

SRL

(HLi

023E

CB83

376

RES

O.E

0186

CB3F
308

SRL

0240

CB84

377

RES

O.H

01B8

CB40

309
BIT

O.B

0242

CB85

378

RES

O.L

OIBA

CB41

310

BIT
OtC

0244

CB86

379

RES

0. (HLi

OIBC

CB42

3U

BIT

OtO
0246

CB87

380

RES

O.A

OIBE

CB43

312

BIT

OiE

0248
CB88

381

RES

l.B

OICO

CB44

313

BIT

O.H

024A

CB89
382

RES

l.C

01C2

CB45

314

BIT

OtL

024C

CB8A

383
RES

1.0

01C4

CB46

315

BIT

OflHL)

024E

CB8B

384

RES
I.E

01C6

C847

316

BIT

OtA

0250

CB8C

385

RES

l.H
01C8

CB4B

317

BIT

i.e

0252

CBttD

386

RES

l.L

OICA
CB49

318

BIT

l.C

0254

CB8E

387

RES

1 . ( HL )

OICC

CB4A
319

BIT

liO

0256

CB8F

388

RES

l.A

OICE

CB4B

320
BIT

I.E

0258

CB90

389

RES

2.B

0100

CB4C

321

BIT
ItH

025A

CB91

390

RES

2.0

0102

CB4U

322

BIT

ItL
025C

CB92

391

RES

2.0

0104

CB4E

323

BIT

I.IHLI

025E
CB93

392

0106

C84F

324

BIT

ItA

0260

CB94

393
oe«

»'u

0108

CBSO

325

BIT

2.B

0262

CB9S

394

RES
» 1

OlOA

CB51

326

BIT

2.C

0264

CB96

395

RES

2)1 HLI
OlDC

CB52

327

BIT

2.0

0266

CB97

396

RES

2. A

OlOE
CBS3

328

BIT

2.E

0268

CB98

397

RES

3.8

01 EO

CB54
329

BIT

2.H

026A

CB99

398

RES

3.0

01E2

cess

330
BIT

2.L

026C

CB9A

399

RES

3.0

01E4

CB56

331

BIT
2. (HLI

026E

CB9B

400

RES

3.E

01E6

CB57

332

BIT

2. A
0270

CB9C

401

RES

01E8

CBS8

333

BIT

3.B

0272
CB90

402

s'l

OlEA

CBS9

334

BIT

3.C

0274

CB9E

403
RES

3ff(HL)

OlEC

CBSA

335

BIT

3.0

0276

CB9F

404
OlEE

CB5B

336

BIT

3iE

0278

CBAO

405

RES

4tB
OlFO

case

337

BIT

3.H

027A

CBAl

406

RES

4.0

01F2
CBSO

338

BIT

3tL

02 7C

CBA2

407

RES

4.0

01 F4

CSSE
339

BIT

3. (HL)

02 7E

CBA3

408

RES

4.E

01F6

cesF

340
BIT

3.A

0280

CBA4

409

RES

4.H

01F8

CB60

341

BIT
4.B

0282

CBAS

410

RES

4.L

01 FA

CB61

342

BIT

4.C
0284

CBA6

411

RES

4. (HLI

OlFC

CB62

343

BIT

4.D

0286
CBA7

412

RES

4.A

OlFE

CB63

344

BIT

4.E

0288

CBAB
413

RES

5,B

0200

0664

345

BIT

4,H

02eA

CBA9

414
RES

S.C

292

Z-BO CROSS ASSEMBLER VERSION 1.06 OF 06/18/76

07/09/76 10:20:&0 .OPCODE LISTING

LOC

OBJ CODE

STMT

SOURCE STATEMENT

LOC

OBJ CODE
STMT

00 AS

8A

139

AOC AtO

OOFB

00

208

00A9

8B
140

ADC AffE

OOFC

POP DE

OOAA

BC

141

ADC AfH

n?nn
111

JP NCtNN

OOAB

80

142

AOC AtL

0320

OUT N»A

OOAC
8E

143

AOC Af 1 HL 1

D484 05

712

CALL NC t NN

OOAQ

SF

144

AOC ArA

0105
5^

PUSH OE

OOAE

90

145

SUB B

0106

0620

D^T I'nu
OOAF

91

146

SUB C

01 08

07

lis

OOBO

92

147

SUB
0109

08

OOBl

93

148

SUB E

OlOA

09
00B2

94

149

SUB H

01 OB

0A8405

218

ID r uu

00B3

95

150
sue L

lOE

0B20

IM AW

j! A. r '/•

00B4

96

151

SUB (HLJ

01 10

DC 8405
CALL CffNN

00B5

97

152

SUB A

0113

DE20

221

OCT ?ou

00B6
98

153

SBC AtB

0115

OF

W\

00B7

99

154

SBC AtC
0116

EO

ncT on

00B8

9A

155

SBC A>0

0117

El

?P%

POP HL
00B9

9B

156

SBC AtE

01 18

E 28405

OOBA

9C

157
SBC AfH

3 3A

jIt

pv f CP 1 . Ul

OOBB

90

158

SBC AfL

ni ir

E48405
r Al 1 pn. isjM

OOBC

9E

159

SBC At(HL)

OllF

£5

AMn*^*!^*^

OOBO

9F
160

SBC AfA

120

E620

229

OOBE

AO

161

AND B

0122
DCT »nu

OOBF

Al

162

AND C

0123

E6

231

OCT PC

OOCO
A2

163

AND

0124

E9 .

232

JP I HL 1

OOCl

A3

164

AND E
0125

E A8405

233

c» nc'ui*

00C2

A4

165

AND H

0128

^.1 P oe ....
00C3

A5

166

AND L

0129

EC 8405

235

CALL PEtNN

OOC*

A6

167
AND (HLl

012C

EE20

00C5

A7

168

AND A

012E

£F
237

RST 28H

00C6

A8

169

XOR B

012F

FO

238

RET P

00C7
A9

170

XOR C

0130

F 1

239

POP AF

O0C8

AA

171

XOR D
JP PtNN

00C9

AB

172

XOR E

0134

F3

241

01
OOCA

AC

173

XOR H

0135

F48405

242

CALL PffNN

OOCB

AU

174
XOR L

0138

F5

243

PUSH AF

OOCC

AE

175

XOR (HL)

0139

F62
244

OOCU

AF

176

XOR A

013B

F 7

245

RST 30H

OOCE

BO
177

OR B

2}f ^

?n^^p HI

OOCF

Bl

178

OR C

0130
Ji7

OOUO

B2

179

OR

FA8405

248

IP M NN

JP HfNN

0001
83

180

OR E

0141

249

f }

U0D2

B4

181

OR H
0142

FC8405

250

CALL MfNN

0003

B5

182

OR L

0145

FE20

251
CP N

0004

86

183

OR ( HL )

0147

OOOS

87

184
OR A

0148

' CBOO

253

RLC B

0006

B6

185

CP 8

014A

CBOl
254

RLC C

0007

B9

186

CP C

014C

CB02

255

RLC

0008
8A

187

CP D

014E

CB03

256

?|-^ f

0009

BB

188

CP E
01 50

CB04

257

RLC H

OODA

BC

189

CP H

0152

CB05
OOOB

BO

190

CP L

0154

CB06

259

RLC iHLi

OODC

BE

191
CP ( HL I

0156

CB07

260

OOOD

BF

192

CP A

01 58

CB08
Bor B

OOOE

CO

193

RET NZ

JA^

opr r

OOOF

Ci
194

POP BC

015C

jaI

KHr n

OOEO

C28405

195

JP NZfNN

OlSE
CBOB

ppr c

00E3

C38405

196

JP NN

0160

CBOC

J s

Dpr u

00E6
C48405

19 7

ni^i

5AA
5a5

RRC L

Q0E9

C5

198
rnnp

opr fui \

OOEA

C620

199

ADD AtN

ni

r Bnc

268
OOEC

C7

200

ni fc«

TBI n

JAQ

OOED

C8

201

RET Z
016A

CBll

270

RL C

202

RET

016C

CB12

271

RL D
OOEF

CA8405

203

JP Z.NN

016E

CB13

272

RL E

00F2

CC8405

204
CALL Z.NN

0170

CB14

273

RL H

OOFS

C08405

205

CALL NN

0172

CB15
274

RL L

00F8

CE20

206

ADC A,N

0174

CB16

275

RL (HL)

OOFA
CF

207

RST 8

0176

CB17

276

RL A

291

Z-eO CROSS ASSEMBLER VERSION i.06 OF 06/1S/76

07/09/76 10«20«50 .OPCODE LISTING

LOC OBJ CODE STNT SOURCE STATEMENT

030A
OBOE
03EZ
03 E6
03EA
03EE
03F2
U3F6
03FA
03FE
0402
0406
060 A
060E
0612
0616
061A
061 E
0622
0626
0426

042 8
042C
062 E
0630
0632
0634
0436
0436
043A
043 E
0440
0442
0444
0446
044A
044C

044 E
0450
0452
0454
0458
045A
045C
0456
0460
0462
0464
0666
0668
066A
066C
0670
0672
0674
0476
047A
047C
047E
0480
0482
0484
0486
0488
048A
048C
048 E
0490
0492

0DCB0576

DDCB0S7E

OOCB0586

DOC BOS 8 E

00CB0596

0DCB0S9E

DDCB0SA6

OOCBOSAE

00CB0SB6

00CB05BE

0DCB09C6
0OCB05CE

00CB0506

OOCBOSOE

OOC805E6

OOCBOSEE

0DCB05F6

OOCBOSFE

ED60

ED41

ED62

ED6384a5

E044

E045

E046

E047

E068

E049
E06A

E06B8405

E040

ED50

E051

EDS2

E0S38405

E056

E0S7

EDS8

E059

ED5A

EOS 88405

E05E

E060

E061
ED62

ED67

E068

ED69

E06A

E06F

E072

E0738405
E078
E079
ED7A

ED 7B 8405

EDAO

EOAl

EDA2

EDA3

EDA8

E0A9
EOAA

EDAB

EDBO

EOBl

E0a2

EDB3

E088

553
556
555
556
557
558
559
560
561
S62
563
566
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
S90
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621

BIT 6.( tX+INO)

BIT 7,(IX4'IND)
RES OtIIX+INO)
RES l.dX+INDi
RES 2>IIX+IN0i
RES 3,«IX*IND)
RES 4t(IX4lNOI
RES 5,(IX+IN0I
RES 6.(IX»INDI
RES 7.IIX«INDI
SET OtUXf-IND)
SET l.(IX«INDi
SET ZidXtIND)
SET 3,UX*INDI
SET 6.(IX*IN0)
SET S.dXi^INOI
SET 6i(IX+IND)
SET T.dXl-IND)
IN B.ICI
OUT IC)>B
SBC HL.BC
LO INN)>BC
NEG
RETN
IN
LO ItA
IN C.(C>
OUT IC),C
ADC HL.aC
LO BCtCNN)
RETI

IN Dt(C)
OUT lO.D
sac HLfOE
LO (NNt,DE
IM 1
LD All
IN EtCCI
OUT IC),E
AOC HL.OE
LO OE.INNI
IM 2
IN HtICi
OUT tC)>H
sec HL.HL
RRD

IN Lt(C)
OUT (C).L
AOC HL.HL
RLO

SBC HLtSP

LO (NN),SP

IN A.(C)

OUT ICt,A

AOC HL.SP

LD SPt(NN)

LDI

CPI

INI

OUTI

LOO

CPO
IND

OUTD

LOIR

CPIR

INIR

OTIR

LDDR

LOC

OBJ CODE

STMT

0494

E0B9

622
0496

EDBA

623

0498

EDBB

624

049A

F009

625

049C

FD19
626

049E

F 02 18405

627

04A2

F0228405

628

04A6

FD23

629

04AB
F029

630

04AA

FD2A8405

631

04AE

F02B

632

0480

FD3405

633
0483

FD3505

634

04B6

FD3 60520

635

04 B A

F039

636

04BC

F04605
637

04BF

FD4E05

638

04C2

FD5605

639

04CS

FOSE 05

640

04C8
FD6605

641

04CB

FD6E05

642

04CE

FDT005

643

04D1

F07105

644
0404

F07205

645

04D7

F07305

646

040A

FD7405

647

0400

F07505
648

04E0

F07705

649

04E3

F07E05

650

04E6

FDa60S

651

04fc9
F08E05

652

04EC

F 096 05

653

04EF

FD9E05

654

04 F2

FDA605

655
04F5

F0AE05

656

04F8

FDB605

657

04Fa

F0BE05

658

04FE

FDEl
659

0500

F0E3

660

0502

FOES

661

0504

FDE9

662

0506
F0F9

663

0508

FDCB0506

664

050C

FOCB050E

665

0510

F0CB0516

666
0514

F0C8051E

667

0518

FOCB0526

668

05 10

F0CB052E

669

0520

FaCB0S3E
670

0524

F0CB0546

671

0S2e

FDCB054E

672

052C

FOCB0556

673

0530
FOCB05SE

t}t

0534

FOCB0566

675

0538

F0CB056E

676

053C

F0CB0576

677
0540

F0CB057E

678

0544

FOCB0586

679

0548

FOCB058E

680

054C

FDCB0596
681

0550

FDCB059E

682

0554

FOCB05A6

0558

FDCB05AE

684

055C
FDCB05B6

685

0560

FDCBOSBE

686

0564

FDCB0SC6

687

0568

FDCBOSCE

688
056C

FDCB0SD6

689

0570

FDCB050E

690

STMT SOURCE STATEMENT

CPOR
I NOR
OTDR

ADD lY.BC

ADO iY«oe

LO lY.NN
LO (NN),IY
INC lY
ADD lYtlY
LO IY,<NN)
DEC lY
INC dY-^INDI
DEC

: (lYI^INO)
LO (lY+INOl.N
ADO lY.SP
LO B.(iy«^INO)
LO C,dy«INOI
LO 0.(IY«INOI
LO EtdYtlNO)
LO H.dY + INO>
LO L.dYVINOI
LD (lYtlNbt.B
LO (IY4lNbJ,C
LD dYflNbi.O
LO dY«INpt,E
LD (lY+INDItH
LD dY4-INpt,L
LO dY«'INp),A
LO A.dY + INO)
ADO A.ilYjflND)
ADC A,dY»INOI
SUB dY+INOl
SBC A.CIY^tNO)
AND ( IY»l|«Oi
XOR CIY+INOl
OR (lY^INb)
CP (IY*INOi
POP IV
EX iSPt.IY
PUSH lY
JP (lYI
LO SP.IY
RLC IIY+INO)
RRC dV+iNO)
RL (lY+INp)
RR dY+INp)
SLA (IY4-IN0i
SRA (lYl-lNO)
SRL IIY+llHD)
BIT O.dYl-INDI
BIT ItdYflND)
BIT Z.dYflNDi
BIT 3,(IY*IN0»
BIT 4.dY4^IND)
BIT S.dY+INO)
BIT 6.(tYllNDi
BIT T.dY+INOi
RES O.dYtINO)
RES l.dYtIND)
RES 2«dY|IND)
RES 3.dV|lND)
RES 4,IIY^IN0)
RES S.dY^-INO)
RES 6.IIYVlNDt
RES T.dYflNOi
SET a,dY4IN0l
SET l.dYtlND)
SET 2tdY4INDi
SET 3,dY«IND)

294

Z-80 CROSS ASSEMBLER VERSION 1.06 OF 06/18/76

07/09/76 10:20;50 .OPCODE LISTING

LOG OBJ CODE STMT SOURCE STATEMENT LOG OBJ CODE

STMT SOURCE STATEMENT

028G

CbAA

415

RES

5.0
028E

CBA8

416

RES

5,E

0290

CBAC

417

RES

5,H

0292
CBAO

418

RES

5,L

0294

CBAE

419

RES

5,(HL)

02 96

CBAF
420

RES

5, A

0298

CB80

421

RES

6iB

029A

CBBl

422
RES

6,C

029C

CBB2

423

RES

6,0

029E

CB83

424

RES
6.E

O2A0

CBB4

425

RES

6tH

02A2

CBB5

426

RES

6.L
02A4

CBB6

427

RES

6«(HLI

02A6

CBB7

428

RES

6, A

02A8
C&B8

429

RES

7,B

02AA

CB89

430

RES

7,C

02AC

CB8A
431

RES

7,0

02 AE

CBBB

432

RES

7,E

0280

C8BC

433
RES

7,H

0282

CB8D

434

RES

7,L

028*

C88E

435

RES
7,(HLI

0286

CB8F

436

RES

7, A

0288

CBCO

437

SET

O.B
028A

CBCl

438

SET

O.C

02BC

CBC2

439

SET

0,0

02BE
CBC3

440

SET

O.E

02G0

CBC4

441

SET

0,H

02C2

CBC5
442

SET

0,L

02C*

CBC6

443

SET

0,(HLJ

02C6

CBC7

444
SET

0,A

02C8

CBC8

445

SET

1,B

02CA

CBC9

446

SET
1,C

02CC

CBCA

447

SET

1,0

02Ce

CBCB

448

SET

l.E
02 DO

CBCC

449

SET

l,H

0202

CBCD

450

SET

1,L

0204
CBCE

451

SET

1,(HL)

0206

CBCF

452

SET

1,A

02DB

CBOD
453

SET

2,8

020A

CBUl

454

SET

2,C

U2DC

CBD2

455
SET

2,0

02DE

CB03

456

SET

2.E

02E0

CBU4

457

SET
2,H

02E2

CBD5

458

SET

2,L

02E4

CBt)6

459

SET

2,(HL)
02E6

CBD7

460

SET

2, A

02E8

CBD8

461

SET

3 8

02tA
CBD9

462

SET

3,C

02EC

CBOA

463

SET

3,0

02EE

CBDB
464

SET

3,E

O2F0

CBOC

465

SET

3,H

02F2

CBOO

466
SET

3,L

02F4

CBDE

467

SET

3,(HL)

02F6

CBOF

468

SET
3, A

02F8

CBEO

469

SET

4,8

02FA

CBEl

470

SET

4,C
02FC

CBE2

471

SET

4,0

02FE

C8E3

472

SET

4,E

0300
C8E4

473

SET

4,H

0302

CBES

474

SET

4,L

U304

CBE6
475

SET

4, (HL)

0306

CBE7

476

SET

4, A

0308

C8E8

477
SET

5,B

030A

CBE9

478

SET

5,C

030C

CBEA

479

SET
5,0

030E

CBEB

480

SET

5.E

U310

CBEC

481

SET

5,H
0312

CBEO

482

SET

5,L

0314

CBEE

483

SET

5,(HLI

0316
CBEF

484

SET 5, A

0318

CBFO

485

SET 6,B

03 I A

CBFl

486

SET 6,C
031C

CBF2

487

SET 6,0

031E

CBF3

488

SET 6,E

0320

CBF4

489
SET 6,H

0322

CBF5

490

SET 6,L

0324

CBF6

491

SET 6,(HL)

0326

CBF7
492

SET 6, A

0328

CBF8

493

SET 7,B

032A

CBF9

494

SET 7,C

032C
CBFA

495

SET 7,0

032E

CBFB

496

SET 7,E

0330

CBFC

497

SET 7,H
0332

CBFO

498

SET 7,L

0334

CBFE

499

SET 7,(HL)

0336

CBFF

500
SET 7, A

0338

U009

501

ADO IX,BC

033A

0019

502

ADO IX, OE

033C

00218405
503

LO IX,NN

0340

DD228405

504

LO INNI,IX

0344

0023

505

INC IX

0346
0029

506

ADD IX, IX

0348

0D2A8405

507

LO IX, INN)

034C

0028

508

DEC IX
034E

0D3405

509

INC ( 1X4- IND)

0351

003505

510

DEC IIX+INO>

0354

00360520

511
LO ( I Xi-I NO) ,N

0358

DD39

512

ADO IX, SP

035A

0D4605

513

LO BtllX-t-INO)

0350

0D4E05
514

LD C, ( IX+INO)

0360

005605

515

LD 0, 1 IX+INO)

0363

005E05

516

LO E, (IX+INO)

0366
006605

517

LO H,( IX+INO)

0369

DO6E05

518

LO L, ( IX + INO)

036C

007005

519

LD (IX+INO), B
036F

DD7105

520

LD (IX+INO). G

0372

007205

521

LD (IX+INO),

0375

007305

522
LO ( IX+IND) ,E

0378

007405

523

LO ( IX+INO), H

037B

007505

524

LO (IX+INO), L

037E

007705
525

LO IIX+INO),A

0381

0D7E05

526

LD A, ( IX+IND)

0384

DD8605

527

ADD A, (IX+INO)

0387
D08E05

528

ADC A, (IX+INO)

03 8 A

009605

529

SUB ( IX+ INO )

0380

009E05

530

SBC A, (IX+INO)
0390

0DA605

531

AND ( IX+ INO )

0393

0DAE05

532

XOR (IX+INO)

0396

00B605

533
OR ( IX+I NO)

0399

00BE05

534

CP ( IX+INO)

039G

ODE 1

535

POP IX

039E

0DE3
536

EX ( SPI , t X

03A0

D0E5

537

PUSH IX

03A2

0DE9

538

JP ( IXI

03 A4
0DF9

539

LD SP, IX

03 A6

D0C80506

540

RLC (IX+INO)

03AA

ODC8050E

541

RRC (IX+INO)
03AE

0DCB0516

542

RL ( IX+INO)

03 82

0DCB051E

543

RR ( IX + IND)

03B6

0OCB0526

544
SLA (IX + 1 NO )

03BA

00CB052E

545

SRA ( IX + INO)

03BE

00CB053E

546

SRL (IX+IND)

03C2

ODCB0546
547

BIT 0, (IX+IND)

03C6

DDCB054E

548

BIT 1, (IX+IND)

03CA

0DCe0556

549

BIT 2, (IX+INO)

03CE
00CB055E

550

BIT 3, ( IX+INO)

0302

0DCB0566

551

BIT 4, (IX+INO)

0306

D0CB056E

552

BIT 5, (IX+IND)
293

ACCUMULATOR

Z80-CPU REGISTER CONFIGURATION

HEXADECIMAL COLUMNS™

ASCir CHARACTER SET (7-BIT CODE)

HEX ' DEC HEX -DEC

1 6S.53e

2 131,072

3 I96,<0a
2 2,097,1S

4,1M,304

5 5,242.Ma

6 6.291.4S6
7,340,032
8,388,608

9 9,437,184
« 10,485,760
B 11,534,336
C 12,582,912
O 13,631,488
14,680,0*4
15,728,640

4 262,14

5 327,680

6 393.216

7 468,762

8 524,288
g 589,824
A 665,360
B 720,896
C 786.432
D 851.968
E 917.504
F 983.040

4567

HEX -DEC HEX - DEC

4,096
8,192
3 12,288
■ 16,384

5 20,480

6 24,576

7 28,672

8 32,768

9 36,864
A 40,960
B 45,056
C «9,1S2
D 53,248
E 57,344
HEX-DEC HEX- DEC

0123

2 612

3 768
1.024

5 1.280

6 1.536

7 1,792

8 2.048

9 2.304
A 2.500

2.816
C 3.072
D 3.328
E 3«>4
f 3.840
4567

0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110

1111

0C2
DC3
DC4
NAK
SYN
ETB
CAN
26S
512
1024
2 04S
4 096
a 192
16 384
32 768
65 536
131 072
262144
524 288
1048 576
2 097152
4194 304
8 388 608
16 777 216

232.188
2»-16«
2". 16"
244 . ,jll

2" - 16"
2« - 16"
2» - 16"
2" - 16«

POWERS OF 16
16
256
4096
66 536
1048S76
18 777 216
2664354B6
4294 967 296
68 71*476 736
1099 511627 776
17 592 186 044 416
261 474 976 710 666
4 503 599 627 370 496
72 057 594 037 927 936
152 921 504 608 846 976

296

LOC

OBJ CODE

STMT
SOURCE STATEMENT

0574

FDCB05E6

691

SET 4.1 lY+INO)

F0CB05EE

692

SET SidY+IND)

057C
F0CB05F6

693

SET 6t( lY+INO)

05B0

FOCB05FE

694

SET TilIYtIND)

0584

695
NN

OEFS 2

696

IND

EQU 5

697

EQU lOH
698

EQU 20H

699

OIS

EQU 30H

700
END

295