a Low Drift, Low Power

Instrumentation Amplifier
AD621
FEATURES CONNECTION DIAGRAM
EASY TO USE 8-Pin Plastic Mini-DIP (N), Cerdip (Q)
Pin-Strappable Gains of 10 & 100 and SOIC (R) Packages
All Errors Specified for Total System Performance
Higher Performance than Discrete In-Amp Designs
Available in 8-Pin DIP and SOIC G=10/100 1 AD621 8 G=10/100
Low Power, 1.3 mA max Supply Current
Wide Power Supply Range (62.3 V to 618 V) –IN 2 7 +VS

EXCELLENT DC PERFORMANCE +IN 3 6 OUTPUT

0.15% max, Total Gain Error

–VS 4 5 REF
65 ppm/8C, Total Gain Drift
TOP VIEW
125 mV max, Total Offset Voltage
1.0 mV/8C max, Offset Voltage Drift pin strapping. The AD621 is fully specified as a total system,
LOW NOISE therefore, simplifying the design process.
9 nV/√Hz, @ 1 kHz, Input Voltage Noise For portable or remote applications, where power dissipation,
0.28 mV p-p Noise (0.1 Hz to 10 Hz} size and weight are critical, the AD621 features a very low sup-
EXCELLENT AC SPECIFICATIONS ply current of 1.3 mA max and is packaged in a compact 8-pin
800 kHz Bandwidth (G = 10}, 200 kHz (G = 100} SOIC, 8-pin plastic DIP or 8-pin cerdip. The AD621 also
12 ms Settling Time to 0.01% excels in applications requiring high total accuracy, such as pre-
cision data acquisition systems used in weigh scales and trans-
APPLICATIONS
ducer interface circuits. Low maximum error specifications
Weigh Scales
including nonlinearity of 10 ppm, gain drift of 5 ppm/°C, 50 µV
Transducer Interface & Data Acquisition Systems
offset voltage and 0.6 µV/°C offset drift (“B” grade), make pos-
Industrial Process Controls
sible total system performance at a lower cost than has been pre-
Battery Powered and Portable Equipment
viously achieved with discrete designs or with other monolithic
PRODUCT DESCRIPTION instrumentation amplifiers.
The AD621 is an easy to use, low cost, low power, high accu- When operating from high source impedances, as in ECG and
racy instrumentation amplifier which is ideally suited for a wide blood pressure monitors, the AD621 features the ideal combina-
range of applications. Its unique combination of high perfor- tion of low noise and low input bias currents. Voltage noise is
mance, small size and low power, outperforms discrete in amp specified as 9 nV/√Hz at 1 kHz and 0.28 µV p-p from 0.1 Hz to
implementations. High functionality, low gain errors and low 10 Hz. Input current noise is also extremely low at 0.1 pA/√Hz.
gain drift errors are achieved by the use of internal gain setting The AD621 outperforms FET input devices with an input bias
resistors. Fixed gains of 10 and 100 can be easily set via external current specification of 1.5 nA max over the full industrial tem-
30,000
perature range.
10,000
TOTAL ERROR, ppm OF FULL SCALE

25,000
TOTAL INPUT VOLTAGE NOISE, G = 100 – µVp-p

3 - OP AMP
TYPICAL STANDARD
IN-AMPS 1,000
20,000 BIPOLAR INPUT
(3 OP 07'S)
IN-AMP

15,000 100
(0.1 – 10Hz)

AD621A
10,000
10

5,000 AD621 SUPERßETA

1 BIPOLAR INPUT
IN-AMP
0
5 10 15 20
SUPPLY CURRENT – mA 0.1
1k 10k 100k 1M 10M 100M
SOURCE RESISTANCE – Ω
Three Op Amp IA Designs vs. AD621
Total Voltage Noise vs. Source Resistance
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
otherwise under any patent or patent rights of Analog Devices. Tel: 617/329-4700 Fax: 617/326-8703
AD621–SPECIFICATIONS
Gain = 10 (typical @ +258C, V = 615 V, and R = 2 kV, unless otherwise noted)
S L

AD621A AD621B AD620S1

Model Conditions Min Typ Max Min Typ Max Min Typ Max Units

GAIN
Gain Error VOUT = ± 10 V 0.15 0.05 0.15 %
Nonlinearity,
VOUT = –10 V to +10 V RL = 2 kΩ 2 10 2 10 2 10 ppm of FS
Gain vs. Temperature –1.5 ±5 –1.5 ±5 –1 ±5 ppm/°C
TOTAL VOLTAGE OFFSET
Offset (RTI) VS = ± 15 V 75 250 50 125 75 250 µV
Over Temperature VS = ± 5 V to ± 15 V 400 215 500 µV
Average TC VS = ± 5 V to ± 15 V 1.0 2.5 0.6 1.5 1.0 2.5 µV/°C
Offset Referred to the
Input vs. Supply (PSR)2 VS = ± 2.3 V to ± 18 V 95 120 100 120 95 120 dB
Total NOISE
Voltage Noise (RTI) 1 kHz 13 17 13 17 13 17 nV/√Hz
RTI 0.1 Hz to 10 Hz 0.55 0.55 0.8 0.55 0.8 µV p-p
Current Noise f = 1 kHz 100 100 100 fA/√Hz
0.1 Hz–10 Hz 10 10 10 pA p-p
INPUT CURRENT VS = ± 15 V
Input Bias Current 0.5 2.0 0.5 1.0 0.5 2 nA
Over Temperature 2.5 1.5 4 nA
Average TC 3.0 3.0 8.0 pA/°C
Input Offset Current 0.3 1.0 0.3 0.5 0.3 1.0 nA
Over Temperature 1.5 0.75 2.0 nA
Average TC 1.5 1.5 8.0 pA/°C
INPUT
Input Impedance
Differential 10i2 10i2 10i2 GΩipF
Common-Mode 10i2 10i2 10i2 GΩipF
Input Voltage Range3 VS = ± 2.3 V to ± 5 V –VS + 1.9 +VS – 1.2 –VS + 1.9 +VS – 1.2 –VS + 1.9 +VS – 1.2 V
Over Temperature –VS + 2.1 +VS – 1.3 –VS + 2.1 +VS – 1.3 –VS + 2.1 +VS – 1.3 V
VS = ± 5 V to ± l8 V –VS + 1.9 +VS – 1.4 –VS + 1.9 +VS – 1.4 –VS + 1.9 +VS – 1.4 V
Over Temperature –VS + 2.1 +VS – 1.4 –VS + 2.1 +VS – 1.4 –VS + 2.3 +VS – 1.4 V
Common-Mode Rejection
Ratio DC to 60 Hz with
1 kΩ Source Imbalance VCM = 0 V to ± 10 V 93 110 100 110 93 110 dB
OUTPUT
Output Swing RL = 10 kΩ,
VS = ± 2.3 V to ± 5 V –VS + 1.1 +VS – 1.2 –VS + 1.1 +VS – 1.2 –VS + 1.1 +VS – 1.2 V
Over Temperature –VS + 1.4 +VS – 1.3 –VS + 1.4 +VS – 1.3 –VS + 1.6 +VS – 1.3 V
VS = ± 5 V to ± 18 V –VS + 1.2 +VS – 1.4 –VS + 1.2 +VS – 1.4 –VS + 1.2 +VS – 1.4 V
Over Temperature –VS + 1.6 +VS – 1.5 –VS + 1.6 +VS – 1.5 –VS + 2.3 +VS – 1.5 V
Short Current Circuit ± 18 ± 18 ± 18 mA
DYNAMIC RESPONSE
Small Signal,
–3 dB Bandwidth 800 800 800 kHz
Slew Rate 0.75 1.2 0.75 1.2 0.75 1.2 V/µs
Settling Time to 0.01% 10 V Step 12 12 12 µs
REFERENCE INPUT
RIN 20 20 20 kΩ
IIN VIN +, VREF = 0 +50 +60 +50 +60 +50 +60 µA
Voltage Range –VS + 1.6 +VS – 1.6 –VS + 1.6 +VS – 1.6 VS + 1.6 +VS – 1.6 V
Gain to Output 1 ± 0.0001 1 ± 0.0001 1 ± 0.0001
POWER SUPPLY
Operating Range ± 2.3 ± 18 ± 2.3 ± 18 ± 2.3 ± 18 V
Quiescent Current VS = ± 2.3 V to ± 18 V 0.9 1.3 0.9 1.3 0.9 1.3 mA
Over Temperature 1.1 1.6 1.1 1.6 1.1 1.6 mA
TEMPERATURE RANGE
For Specified Performance –40 to +85 –40 to +85 –55 to +125 °C
NOTES
1
See Analog Devices military data sheet for 883B tested specifications.
2
This is defined as the supply range over which PSRR is defined.
3
Input Voltage Range = CMV + (Gain × VDIFF).
Specifications subject to change without notice.

–2– REV. A
 AD621
Gain = 100 (typical @ +258C, VS = 615 V, and RL = 2 kV, unless otherwise noted)

AD621A AD621B AD620S1

Model Conditions Min Typ Max Min Typ Max Min Typ Max Units

GAIN
Gain Error VOUT = ± 10 V 0.15 0.05 0.15 %
Nonlinearity,
VOUT = –10 V to +10 V RL = 2 kΩ 2 10 2 10 2 10 ppm of FS
Gain vs. Temperature –1 ±5 –1 ±5 –1 ±5 ppm/°C
TOTAL VOLTAGE OFFSET
Offset (RTI) VS = ± 15 V 35 125 25 50 35 125 µV
Over Temperature VS = ± 5 V to ± 15 V 185 215 225 µV
Average TC VS = ± 5 V to ± 15 V 0.3 1.0 0.1 0.6 0.3 1.0 µV/°C
Offset Referred to the
Input vs. Supply (PSR)2 VS = ± 2.3 V to ± 18 V 110 140 120 140 110 140 dB
Total NOISE
Voltage Noise (RTI) 1 kHz 9 13 9 13 9 13 nV/√Hz
RTI 0.1 Hz to 10 Hz 0.28 0.28 0.4 0.28 0.4 µV p-p
Current Noise f = 1 kHz 100 100 100 fA/√Hz
0.1 Hz–10 Hz 10 10 10 pA p-p
INPUT CURRENT VS = ± 15 V
Input Bias Current 0.5 2.0 0.5 1.0 0.5 2 nA
Over Temperature 2.5 1.5 4 nA
Average TC 3.0 3.0 8.0 pA/°C
Input Offset Current 0.3 1.0 0.3 0.5 0.3 1.0 nA
Over Temperature 1.5 0.75 2.0 nA
Average TC 1.5 1.5 8.0 pA/°C
INPUT
Input Impedance
Differential 10i2 10i2 10i2 GΩipF
Common-Mode 10i2 10i2 10i2 GΩipF
Input Voltage Range3 VS = ± 2.3 V to ± 5 V –VS + 1.9 +VS – 1.2 –VS + 1.9 +VS – 1.2 –VS + 1.9 +VS – 1.2 V
Over Temperature –VS + 2.1 +VS – 1.3 –VS + 2.1 +VS – 1.3 –VS + 2.1 +VS – 1.3 V
VS = ± 5 V to ± l8 V –VS + 1.9 +VS – 1.4 –VS + 1.9 +VS – 1.4 –VS + 1.9 +VS – 1.4 V
Over Temperature –VS + 2.1 +VS – 1.4 –VS + 2.1 +VS – 1.4 –VS + 2.3 +VS – 1.4 V
Common-Mode Rejection
Ratio DC to 60 Hz with
1 kΩ Source Imbalance VCM = 0 V to ± 10 V 110 130 120 130 110 130 dB
OUTPUT
Output Swing RL = 10 kΩ,
VS = ± 2.3 V to ± 5 V –VS + 1.1 +VS – 1.2 –VS + 1.1 +VS – 1.2 –VS + 1.1 +VS – 1.2 V
Over Temperature –VS + 1.4 +VS – 1.3 –VS + 1.4 +VS – 1.3 –VS + 1.6 +VS – 1.3 V
VS = ± 5 V to ± 18 V –VS + 1.2 +VS – 1.4 –VS + 1.2 +VS – 1.4 –VS + 1.2 +VS – 1.4 V
Over Temperature –VS + 1.6 +VS – 1.5 –VS + 1.6 +VS – 1.5 –VS + 2.3 +VS – 1.5 V
Short Current Circuit ± 18 ± 18 ± 18 mA
DYNAMIC RESPONSE
Small Signal,
–3 dB Bandwidth 200 200 200 kHz
Slew Rate 0.75 1.2 0.75 1.2 0.75 1.2 V/µs
Settling Time to 0.01% 10 V Step 12 12 12 µs
REFERENCE INPUT
RIN 20 20 20 kΩ
IIN VIN +, VREF = 0 +50 +60 +50 +60 +50 +60 µA
Voltage Range –VS + 1.6 +VS – 1.6 –VS + 1.6 +VS – 1.6 VS + 1.6 +VS – 1.6 V
Gain to Output 1 ± 0.0001 1 ± 0.0001 1 ± 0.0001
POWER SUPPLY
Operating Range ± 2.3 ± 18 ± 2.3 ± 18 ± 2.3 ± 18 V
Quiescent Current VS = ± 2.3 V to ± 18 V 0.9 1.3 0.9 1.3 0.9 1.3 mA
Over Temperature 1.1 1.6 1.1 1.6 1.1 1.6 mA
TEMPERATURE RANGE
For Specified Performance –40 to +85 –40 to +85 –55 to +125 °C
NOTES
1
See Analog Devices military data sheet for 883B tested specifications.
2
This is defined as the supply range over which PSEE is defined.
3
Input Voltage Range = CMV + (Gain × VDIFF).
Specifications subject to change without notice.

REV. A –3–
AD621
ABSOLUTE MAXIMUM RATINGS 1 ESD SUSCEPTIBILITY
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 18 V ESD (electrostatic discharge) sensitive device. Electrostatic
Internal Power Dissipation2 . . . . . . . . . . . . . . . . . . . . . 650 mW charges as high as 4000 volts, which readily accumulate on the
Input Voltage (Common Mode) . . . . . . . . . . . . . . . . . . . . ± VS human body and on test equipment, can discharge without de-
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . ± 25 V tection. Although the AD621 features proprietary ESD protec-
Output Short Circuit Duration . . . . . . . . . . . . . . . . . Indefinite tion circuitry, permanent damage may still occur on these
Storage Temperature Range (Q) . . . . . . . . . . –65°C to +150°C devices if they are subjected to high energy electrostatic dis-
Storage Temperature Range (N, R) . . . . . . . . –65°C to +125°C charges. Therefore, proper ESD precautions are recommended
Operating Temperature Range to avoid any performance degradation or loss of functionality.
AD621 (A, B) . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C
AD621 (S) . . . . . . . . . . . . . . . . . . . . . . . . –55°C to +125°C ORDERING GUIDE
Lead Temperature Range
Temperature Package Package
(Soldering 10 seconds) . . . . . . . . . . . . . . . . . . . . . . . +300°C
Model Range Description Option1
NOTES
1
Stresses above those listed under “Absolute Maximum Ratings” may cause perma- AD621AN – 40°C to +85°C 8-Pin Plastic DIP N-8
nent damage to the device. This is a stress rating only and functional operation of AD621BN – 40°C to +85°C 8-Pin Plastic DIP N-8
the device at these or any other conditions above those indicated in the operational
AD621AR – 40°C to +85°C 8-Pin Plastic SOIC R-8
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability. AD621BR – 40°C to +85°C 8-Pin Plastic SOIC R-8
2
Specification is for device in free air: AD621SQ/883B2 – 55°C to +125°C 8-Pin Cerdip Q-8
8-Pin Plastic Package: θJA = 95°C/Watt AD621ACHIPS –40°C to +85°C Die
8-Pin Cerdip Package: θJA = 110°C/Watt
8-Pin SOIC Package: θJA = 155°C/Watt NOTES
1
N = Plastic DIP; Q = Cerdip; R = SOIC.
2
See Analog Devices' military data sheet for 883B specifications.

METALIZATION PHOTOGRAPH
Dimensions shown in inches and (mm).
Contact factory for latest dimensions.

–4– REV. A
 Typical Characteristics–AD621
50 50

SAMPLE SIZE = 90 SAMPLE SIZE = 90

40 40

PERCENTAGE OF UNITS
PERCENTAGE OF UNITS

30 30

20 20

10 10

0 0
–200 –100 0 +100 +200 –800 –400 0 +400 +800
INPUT OFFSET VOLTAGE – µV INPUT BIAS CURRENT – pA

Figure 1. Typical Distribution of VOS, Gain = 10 Figure 4. Typical Distribution of Input Bias Current

50 2

SAMPLE SIZE = 90

CHANGE IN OFFSET VOLTAGE – µV

40
1.5
PERCENTAGE OF UNITS

30

20

0.5
10

0 0
–80 –40 0 +40 +80 0 1 2 3 4 5
INPUT OFFSET VOLTAGE – µV WARM-UP TIME – Minutes

Figure 2. Typical Distribution of VOS, Gain = 100 Figure 5. Change in Input Offset Voltage vs. Warm-Up Time

50 1000

SAMPLE SIZE = 90

40
VOLTAGE NOISE – nV/√ Hz
PERCENTAGE OF UNITS

100
30
GAIN = 10

20
10

10
GAIN = 100

0 1
–400 –200 0 +200 +400 1 10 100 1k 10k 100k
INPUT OFFSET CURRENT – pA FREQUENCY – Hz

Figure 3. Typical Distribution of Input Offset Current Figure 6. Voltage Noise Spectral Density

REV. A –5–
AD621
1000
100mV 1s

100
90
Hz
CURRENT NOISE – fA/

100

10
0%

10
1 10 100 1000
FREQUENCY – Hz

Figure 7. Current Noise Spectral Density vs. Frequency Figure 9. 0.1 Hz to 10 Hz Current Noise, 5 pA per Vertical
Div, 1 Second per Horizontal Div

100,000

TOTAL DRIFT FROM 25°C TO 85°C, RTI – µV

RTI NOISE – 0.2 µV/div

10,000
FET INPUT
IN-AMP

1000

100

AD621A

TIME – 1 sec/div
10
1k 10k 100k 1M 10M
SOURCE RESISTANCE – Ω

Figure 8a. 0.1 Hz to 10 Hz RTI Voltage Noise, Gain = 10 Figure 10. Total Drift vs. Source Resistance

+160

+140 GAIN = 100

+120
RTI NOISE – 0.1 µV/div

+100 GAIN = 10
CMR – dB

+80

+60

+40

+20

0
TIME – 1 sec/div 0.1 1 10 100 1k 10k 100k 1M
FREQUENCY – Hz

Figure 8b. 0.1 Hz to 10 Hz RTI Voltage Noise, G = 100 Figure 11. CMR vs. Frequency, RTI, for a Zero to 1 kΩ
Source Imbalance

–6– REV. A
 AD621
180 35
G = 10 & 100
160 30
G = 100
140

OUTPUT VOLTAGE – Volts p-p

25

120
G = 10
PSR – dB

20
100
15
80

10
60

40 5

20 0
0.1 1 10 100 1k 10k 100k 1M 1k 10k 100k 1M
FREQUENCY – Hz FREQUENCY – Hz

Figure 12. Positive PSR vs. Frequency Figure 15. Large Signal Frequency Response

180 +Vs –0.0

160 –0.5

(REFERRED TO SUPPLY VOLTAGES)

G = 100

INPUT VOLTAGE LIMIT – Volts

140 –1.0

120 –1.5
G = 10
PSR – dB

100

80 +1.5

60 +1.0

40 +0.5

20 –Vs +0.0
0.1 1 10 100 1k 10k 100k 1M 0 5 10 15 20
FREQUENCY – Hz SUPPLY VOLTAGE ± Volts

Figure 13. Negative PSR vs. Frequency Figure 16. Input Voltage Range vs. Supply Voltage

1000 +Vs –0.0

–0.5
(REFERRED TO SUPPLY VOLTAGES)

R L= 10kΩ
OUTPUT VOLTAGE SWING – Volts

–1.0
CLOSED-LOOP GAIN – V/V

100

–1.5 R L= 2kΩ

10

+1.5 R L= 2kΩ

1 +1.0

+0.5 R L= 10kΩ

0.1 –Vs +0.0

100 1k 10k 100k 1M 10M 0 5 10 15 20
FREQUENCY – Hz SUPPLY VOLTAGE ± Volts

Figure 14. Closed-Loop Gain vs. Frequency Figure 17. Output Voltage Swing vs. Supply Voltage,
G = 10

REV. A –7–
AD621
30
5V 1mV 10µs
OUTPUT VOLTAGE SWING – Volts p-p

100
VS = ± 15V
90
G = 10
20

10
10
0%

0
0 100 1k 10k
LOAD RESISTANCE – Ω

Figure 18. Output Voltage Swing vs. Resistive Load Figure 21. Large Signal Pulse Response and Settling
Time, G = 100 (0.5 mV = 0.1%), RL = 2 kΩ, CL = 100 pF

5V 1mV 10µs 20mV 10µs

100 100

90 90

10 10

0% 0%

Figure 19. Large Signal Pulse Response and Settling Figure 22. Small Signal Pulse Response, G = 100,
Time Gain, G = 10 (0.5 mV = 0.01%), RL = 1 k Ω, RL = 2 kΩ, CL = 100 pF
CL = 100 pF

20

20mV 10µs
TO 0.01%
100

90 15
SETTLING TIME – µs

TO 0.1%

10

10
5
0%

0
0 5 10 15 20
OUTPUT STEP SIZE – Volts

Figure 20. Small Signal Pulse Response, G = 10, Figure 23. Settling Time vs. Step Size, G = 10
RL = 1 k Ω, CL = 100 pF

–8– REV. A
 AD621
20
100µV 2V
TO 0.01%
100

15 90
SETTLING TIME – µs

TO 0.1%
10

10
5 0%

0
0 5 10 15 20
OUTPUT STEP SIZE – Volts

Figure 24. Settling Time vs. Step Size, Gain = 100 Figure 27. Gain Nonlinearity, G = 10, RL = 10 kΩ, Vertical
Scale: 100 µ V/Div = 100 ppm/Div, Horizontal Scale:
2 Volts/Div

2.0
10kΩ 1kΩ 10kΩ
1% 10T 1%
1.5
INPUT
+I B 20V p-p
100kΩ VOUT
0.1%
1.0
INPUT CURRENT – nA

0.5 G=10 +VS

G=100 2
–I B 11kΩ 1kΩ 1
0 0.1% 0.1% 7

G=100
–0.5 G=10
AD621 6

5
–1.0
8 4

–1.5 3
–VS
–2.0
–125 –75 –25 25 75 125 175
TEMPERATURE – °C

Figure 25. Input Bias Current vs. Temperature Figure 28. Settling Time Test Circuit

0PW 0 VZR 0 100µV 2V

100

90

10

0%

0 WFM 20 WFM AQR WARNING

Figure 26. Gain Nonlinearity, G = 100, RL = 10 kΩ,

CL = 0 pF. Vertical Scale: 100 µ V/Div = 100 ppm/Div
Horizontal Scale: 2 Volts/Div

REV. A –9–
AD621
+VS input voltage across the gain-setting resistor, RG, which equals
7 R5 at a gain of 10 or the parallel combination of R5 and R6 at a
gain of 100.
I1 20µA VB 20µA I2
This creates a differential gain from the inputs to the A1/A2
outputs given by G = (R1 + R2) / RG + 1. The unity-gain sub-
A1 A2 10kΩ tracter A3 removes any common-mode signal, yielding a single-
C1 C2 ended output referred to the REF pin potential.
10kΩ
A3
OUTPUT The value of RG also determines the transconductance of the
6 preamp stage. As RG is reduced for larger gains, the transcon-
25k R2 25k 10kΩ 10kΩ
R3 R1 ductance increases asymptotically to that of the input transis-
REF
400Ω R5 5
– IN Q1 5555.6Ω Q2 +IN tors. This has three important advantages: (a) Open-loop gain is
2 R4 3
R6 400Ω boosted for increasing programmed gain, thus reducing gain-re-
555.6Ω
1 8 lated errors. (b) The gain-bandwidth product (determined by
G=100 G=100 C1, C2 and the preamp transconductance) increases with pro-
grammed gain, thus optimizing frequency response. (c) The in-
4 put voltage noise is reduced to a value of 9 nV/√Hz, determined
–VS
mainly by the collector current and base resistance of the input
devices.
Figure 29. Simplified Schematic of AD621
Make vs. Buy: A Typical Bridge Application Error Budget
THEORY OF OPERATION The AD621 offers improved performance over discrete three op
The AD621 is a monolithic instrumentation amplifier based on amp IA designs, along with smaller size, fewer components and
a modification of the classic three op amp circuit. Careful layout 10 times lower supply current. In the typical application, shown
of the chip, with particular attention to thermal symmetry builds in Figure 30, a gain of 100 is required to amplify a bridge out-
in tight matching and tracking of critical components, thus pre- put of 20 mV full scale over the industrial temperature range
serving the high level of performance inherent in this circuit, at a of –40°C to +85°C. The error budget table below shows how
low price. to calculate the effect various error sources have on circuit
accuracy.
On chip gain resistors are pretrimmed for gains of 10 and 100.
The AD621 is preset to a gain of 10. A single external jumper Regardless of the system it is being used in, the AD621 provides
(between Pins 1 and 8) is all that is needed to select a gain of greater accuracy, and at low power and price. In simple systems,
100. Special design techniques assure a low gain TC of 5 ppm/°C absolute accuracy and drift errors are by far the most significant
max, even at a gain of 100. contributors to error. In more complex systems with an intelli-
gent processor, an auto-gain/auto-zero cycle will remove all ab-
Figure 29 is a simplified schematic of the AD621. The input solute accuracy and drift errors leaving only the resolution errors
transistors Q1 and Q2 provide a single differential-pair bipolar of gain nonlinearity and noise, thus allowing full 14-bit accuracy.
input for high precision, yet offer 10× lower Input Bias Current,
thanks to Superβeta processing. Feedback through the Q1-A1-R1 Note that for the discrete circuit, the OP07 specifications for in-
loop and the Q2-A2-R2 loop maintains constant collector cur- put voltage offset and noise have been multiplied by 2. This is
rent of the input devices Q1 and Q2, thereby impressing the because a three op amp type in amp has two op amps at its in-
puts, both contributing to the overall input error.
+10V
10kΩ* 10kΩ*
OP07D
R = 350Ω R = 350Ω
10kΩ**

AD621A 100Ω** 10kΩ** OP07D

R = 350Ω R = 350Ω

REFERENCE
OP07D
10kΩ* 10kΩ*

AD621A MONOLITHIC
PRECISION BRIDGE TRANSDUCER 3 OP-AMP IN-AMP, G=100
INSTRUMENTATION
*0.02% RESISTOR MATCH, 3PPM/°C TRACKING
AMPLIFIER, G=100
**DISCRETE 1% RESISTOR, 100PPM/°C TRACKING
SUPPLY CURRENT = 15mA MAX
SUPPLY CURRENT = 1.3mA MAX

Figure 30. Make vs. Buy

–10– REV. A
 AD621
+5V

7 20kΩ
3
3kΩ 3kΩ
8 REF
AD621B 6 IN
DIGITAL
3kΩ 3kΩ 1 5 10kΩ ADC DATA
OUTPUT
2 4
AD705 AGND
20kΩ

1.3mA 0.6mA
1.7mA 0.10mA
MAX MAX

Figure 31. A Pressure Monitor Circuit which Operates on a +5 V Power Supply

Pressure Measurement presence of large, unwanted common-mode signals or offsets.

Although useful in many bridge applications such as weigh- Many monolithic in amps achieve low total input drift and noise
scales, the AD621 is especially suited for higher resistance pres- errors only at relatively high gains (~100). In contrast the
sure sensors powered at lower voltages where small size and low AD621’s low output errors allow such performance at a gain of
power become more even significant. 10, thus allowing larger input signals and therefore greater
Figure 31 shows a 3 kΩ pressure transducer bridge powered dynamic range. The circuit of Figure 32 (± 15 V supply, G = 10)
from +5 V. In such a circuit, the bridge consumes only 1.7 mA. has only 2.5 µV/°C max. VOS drift and 0.55 µ/V p-p typical
Adding the AD621 and a buffered voltage divider allows the sig- 0.1 Hz to 10 Hz noise, yet will amplify a ± 0.5 V differential sig-
nal to be conditioned for only 3.8 mA of total supply current. nal while suppressing a ± 10 V common-mode signal, or it will
amplify a ± 1.25 V differential signal while suppressing a 1 V
Small size and low cost make the AD621 especially attractive for offset by use of the DAC driving the reference pin of the
voltage output pressure transducers. Since it delivers low noise AD621. An added benefit, the offsetting DAC connected to the
and drift, it will also serve applications such as diagnostic reference pin allows removal of a dc signal without the associ-
noninvasion blood pressure measurement. ated time-constant of ac coupling. Note the representations of a
Wide Dynamic Range Gain Block Suppresses Large Common- differential and common-mode signal shown in Figure 32 such
Mode and Offset Signals that a single-ended (or normal mode) signal of +1 V would be
The AD621 is especially useful in wide dynamic range applica- composed of a +0.5 V common-mode component and a +1 V
tions such as those requiring the amplification of signals in the differential component.

Table I. Make vs. Buy Error Budget

AD621 Circuit Discrete Circuit Error, ppm of Full Scale

Error Source Calculation Calculation AD621 Discrete

ABSOLUTE ACCURACY at TA = +25°C

Input Offset Voltage, µV 125 µV/20 mV (150 µV × 2/20 mV 16,250 15,000
Output Offset Voltage, µV N/A ((150 µV × 2)/100)/20 mV N/A 12,150
Input Offset Current, nA 2 nA × 350 Ω/20 mV (6 nA × 350 Ω)/20 mV 12,118 121,53
CMR, dB 110 dB→3.16 ppm, × 5 V/20 mV (0.02% Match × 5 V)/20 mV 12,791 14,988

Total Absolute Error 17,558 20,191

DRIFT TO +85°C
Gain Drift, ppm/°C 5 ppm × 60°C 100 ppm/°C Track × 60°C 13,300 12,600
Input Offset Voltage Drift, µV/°C 1 µV/°C × 60°C/20 mV (2.5 µV/°C × 2 × 60°C)/20 mV 13,000 15,000
Output Offset Voltage Drift, µV/°C N/A (2.5 µV/°C × 2 × 60°C)/100/20 mV N/A 12,150

Total Drift Error 13,690 15,750

RESOLUTION
Gain Nonlinearity, ppm of Full Scale 40 ppm 40 ppm 12,140 12,140
Typ 0.1 Hz–10 Hz Voltage Noise, µV p-p 0.28 µV p-p/20 mV (0.38 µV p-p × √2)120 mV 121,14 12,127

Total Resolution Error 121,54 121,67

Grand Total Error 11,472 36,008
G = 100, VS = ± 15 V.
(All errors are min/max and referred to input.)

REV. A –11–
AD621
INPUT A:
+
±10V CM
VDIFF
±0.5V
–
+
VCOM Optional
±10V– 2

1 x10 VOUT1 10kΩ

6 2
AD621 G = 10
8
5 1 x10 VOUT2
3 6
AD621
8 TOTAL GAIN = 100
10kΩ 5
INPUT B: DAC
3
±1V + 0 TO ±10V
OFFSET
VDIFF + V OFFSET
±(1.25V + 1V)
– Use this in place of the DAC for zero suppression function.

TO TO
REF C VOUT1

R
2

6 AD548
3

Figure 32. Suppressing a Large Common-Mode or Offset Voltage in Order to Measure a Small Differential Signal
(VS = ± 15 V)

The AD621, as well as many other monolithic instrumentation The AD621’s input amplifiers can provide output voltage within
amplifiers, is based on the “three op amp” in amp circuit (Fig- 2.5 V of the supplies. To avoid saturation of the input amplifier
ure 33) amplifier. Since the input amplifiers (A1 and A2) have a the input voltage must therefore obey the equations:
common-mode gain of unity and a differential gain equal to the VCM + G × VDIFF/2 ≤ (Upper Supply – 2.5 V)
set gain of the overall in amp, the voltages V1 and V2 are de-
fined by the equations VCM – G × VDIFF/2 ≥ (Lower Supply + 2.5 V)
V1 = VCM + G × VDIFF/2 Figure 34 shows the trade-off between common-mode and
differential-mode input for ± 15 V supplies and G = 10.
V2 = VCM – G × VDIFF/2
By cascading with use of the optional AD621, the circuit of Fig-
The common-mode voltage will drive the outputs of amplifiers ure 32 will provide ± 1 V of zero suppression at gains of 10 and
A1 and A2 to the differential-signal voltage, multiplied by the 100 (at VOUT1 and VOUT2 respectively) with maximum TCs of
gain, spreads them apart. For a +10 V common-mode +0.1 V ± 4 ppm/°C and ± 8 ppm/°C, respectively. Therefore, depending
differential input, V1 would be at +10.5 V and V2 at +9.5 V. on the magnitude of the differential input signal, either VOUT1 or
INPUT AMPLIFIER OUTPUT AMPLIFIER VOUT2 may be used as the output.
DIFFERENTIAL GAIN = 10 DIFFERENTIAL GAIN = 1
COMMON MODE GAIN = 1 COMMON MODE GAIN = 1/1000 ±1.2

V1 10kΩ ±1.0
A1
10kΩ

20kΩ ±0.8
VDIFF – Volts

4.44kΩ A3 ±0.6
20kΩ

±0.4
10kΩ
A2
V2 10kΩ
±0.2

Figure 33. Typical Three Op Amp Instrumentation 0

0 ±2 ±4 ±6 ±8 ±10 ±12
Amplifier, Differential Gain = 10 VCM – Volts

Figure 34. Trade-Off Between VCM and VDIFF Range (VS =

± 15 V, G = 10), for Reference Pin at Ground

–12– REV. A
 AD621
Precision V-I Converter INPUT OVERLOAD CONSIDERATIONS
The AD621 along with another op amp and two resistors make Failure of a transducer, faults on input lines, or power supply
a precision current source (Figure 35). The op amp buffers the sequencing can subject the inputs of an instrumentation ampli-
reference terminal to maintain good CMR. The output voltage fier to voltages well beyond their linear range, or even the supply
VX of the AD621 appears across R1 which converts it to a cur- voltage, so it is essential that the amplifier handle these over-
rent. This current less only the input bias current of the op amp loads without being damaged.
then flows out to the load. The AD621 will safely withstand continuous input overloads of
+VS ± 3.0 volts (± 6.0 mA). This is true for gains of 10 and 100, with
power on or off.
VIN+ 7
3 The inputs of the AD621 are protected by high current capacity
+ Vx – dielectrically isolated 400 Ω thin-film resistors R3 and R4 (Fig-
AD621 6 ure 29) and by diodes which protect the input transistors Q1
R1
5 and Q2 from reverse breakdown. If reverse breakdown occurred,
VIN– 2 4 there would be a permanent increase in the amplifier’s input
IL
current.
–VS
AD705 The input overload capability of the AD621 can be easily in-
(VIN+ ) – (VIN– ) G
creased while only slightly degrading the noise, common-mode
Vx
I L=
R1
=
R1
rejection and offset drift of the device by adding external resis-
LOAD
tors in series with the amplifier’s inputs as shown in Figure 36.
Table II summarizes the overload voltages and total input noise
for a range of range of r values. Note that a 2 kΩ resistor in se-
Figure 35. Precision Voltage to Current Converter ries with each input will protect the AD621 from a ± 15 volt
(Operates on 1.8 mA, ± 3 V) continuous overload, while only increasing input noise to
13 nV√Hz—about the same level as would be expected from a
INPUT AND OUTPUT OFFSET VOLTAGE typical unprotected 3 op amp in amp.
The AD621 is fully specified for total input errors at gains of 10
and 100. That is, effects of all error sources within the AD621 Table II. Input Overload Protection vs. Value of Resistor RP
are properly included in the guaranteed input error specs, elimi-
nating the need for separate error calculation. Total Input Noise Maximum Continuous
Value of in nV√Hz @ 1 kHz Overload Voltage, VOL
Total Error RTI = Input Error + (Output Error/G) Resistor RP G = 10 G = 100 In Volts
Total Error RTO = (Input Error × G) + Output Error
0 14 9 3
REFERENCE TERMINAL 499 Ω 14 10 6
Although usually grounded, the reference terminal may be used 1.00 kΩ 14 11 9
to offset the output of the AD621. This is useful when the load 2.00 kΩ 15 13 15
is “floating” or does not share a ground with the rest of the sys- 3.01 kΩ* 16 14 21
tem. It also provides a direct means of injecting a precise offset. 4.99 kΩ* 17 16 33
Another benefit of having a reference terminal is that it can be *1/4 watt, 1% metal-film resistor. All others are 1/8 watt, 1% RN55
quite effective in eliminating ground loops and noise in a circuit or equivalent.
or system.
+VS

RP
2 7
VOL VOUT
AD621 6
VOL RP
5
3
4
GAIN = 10 OR 100

–VS

Figure 36. Input Overload Protection

REV. A –13–
AD621
Gain Selection +VS
+VS
The AD621 has accurate, low temperature coefficient (TC),
0.1µF
gains of 10 and 100 available. The gain of the AD621 is nomi- – 0.1µF
2 7
nally set at 10; this is easily changed to a gain of 100 by simply
10
connecting a jumper between Pins 1 and 8. INPUTS
AD621 6 3

+ 5
8 OUTPUT
3
4
AD526 9
4
2 5
2
G = 10 6
555.5Ω 0.1µF 7 20kΩ
...
–VS
REXT 5,555.5Ω AD621 6 OFFSET
0.1µF
... –VS NULL
(OPTIONAL)
3 5
Figure 38. A High Performance Programmable Gain
Amplifier
Figure 37. Programming the AD621 for Gains Between
10 and 100 COMMON-MODE REJECTION
Instrumentation amplifiers like the AD621 offer high CMR
As shown in Figure 37, the device can be programmed for any which is a measure of the change in output voltage when both
gain between 10 and 100 by connecting a single external resistor inputs arc changed by equal amounts. These specifications are
between Pins 1 and 8. Note that adding the external resistor will usually given for a full-range input voltage change and a speci-
degrade both the gain accuracy and gain TC. Since the gain fied source imbalance.
equation of the AD621 yields:
For optimal CMR the reference terminal should be tied to a low
9 (RX + 6,111.111) impedance point, and differences in capacitance and resistance
G = 1+
(RX + 555.555) should be kept to a minimum between the two inputs. In many
applications shielded cables are used to minimize noise, and for
This can be solved for the nominal value of external resistor for best CMR over frequency the shield should he properly driven.
gains between 10 and 100: Figures 39 and 40 show active data guards which are configured
(G – 1) 555.555 – 55,000 to improve ac common-mode rejections by “bootstrapping” the
RX = capacitances of input cable shields, thus minimizing the capaci-
(10 – G )
tance mismatch between the inputs.
Table III gives practical 1% resistor values for several common +VS
gains. – INPUT
2
7
Table III. Practical 1% External Resistor AD648
100Ω 1
Values for Gains Between 10 and 100
100kΩ VOUT
Desired Recommended Gain Error Temperature AD621 6
Gain 1% Resistor Value Coefficient (TC) 100Ω
100kΩ
–VS 5
10 ∞ (Pins 1 and 8 Open) * *5 ppm/°C max 8
REFERENCE
4
20 4.42 k ≈± 10% ≈0.4 (50 ppm/°C
3
+ Resistor TC) + INPUT

50 698 Ω ≈± 10% ≈0.4 (50 ppm/°C –VS

+ Resistor TC)
100 0 (Pins 1 and 8 Shorted)* *5 ppm/°C max Figure 39. Differential Shield Driver, G = 10
+VS
A High Performance Programmable Gain Amplifier – INPUT
2
The excellent performance of the AD621 at a gain of 10 make it 7
1
a good choice to team up with the AD526 programmable gain VOUT
100Ω
amplifier (PGA) to yield a differential input PGA with gains of AD548 AD621 6
10, 20, 40, 80, 160. As shown in Figure 38, the low offset of the 5
8
AD621 allows total circuit offset to be trimmed using the offset 4 REFERENCE
3
null of the AD526, with only a negligible increase in total drift + INPUT
error. The total gain TC will be 9 ppm/°C max, with 2 µV/°C –VS
typical input offset drift. Bandwidth is 600 kHz to gains of 10 to
80, and 350 kHz at G = 160. Settling time is 13 µs to 0.01% Figure 40. Common-Mode Shield Driver, G = 100
for a 10 V output step for all gains.

–14– REV. A
 AD621
GROUNDING +VS

Since the AD621 output voltage is developed with respect to the – INPUT
2
potential on the reference terminal, it can solve many grounding 7
problems by simply tying the REF pin to the appropriate “local
ground.” VOUT
AD621 6
In order to isolate low level analog signals from a noisy digital
5
environment, many data-acquisition components have separate LOAD
4
analog and digital ground pins (Figure 41). It would be conve-
nient to use a single ground line; however, current through 3
+ INPUT REFERENCE
ground wires and PC runs of the circuit card can cause hun- –VS
dreds of millivolts of error. Therefore, separate ground returns
should be provided to minimize the current flow from the sensi-
TO POWER
tive points to the system ground. These ground returns must be SUPPLY
tied together at some point, usually best at the ADC package as GROUND
shown.
Figure 42b. Ground Returns for Bias Currents when Using
ANALOG P.S. DIGITAL P.S. a Thermocouple Input
+15V C –15V C +5V
+VS
– INPUT
0.1µF 0.1µF 2
1µF 1µF 1µF
7
7
VOUT
2 4 11 4 +
7 9 11 15 1 AD621 6
AD621 6 AD585 DIGITAL
6 S/H AD574A DATA 5
3 5
ADC OUTPUT 4 LOAD

3
+ INPUT REFERENCE
Figure 41. Basic Grounding Practice 100kΩ 100kΩ –VS

GROUND RETURNS FOR INPUT BIAS CURRENTS

TO POWER
Input bias currents are those currents necessary to bias the input SUPPLY
transistors of an amplifier. There must be a direct return path GROUND
for these currents; therefore when amplifying “floating” input
sources such as transformers, or ac-coupled sources, there must Figure 42c. Ground Returns for Bias Currents when Using
be a dc path from each input to ground as shown in Figures 42a AC Input Coupling
through 42c. Refer to the Instrumentation Amplifier Application
Guide (free from Analog Devices) for more information regard-
ing in amp applications.
+VS
– INPUT
2

VOUT
AD621 6

5
4 LOAD

3
+ INPUT REFERENCE
–VS

TO POWER
SUPPLY
GROUND

Figure 42a. Ground Returns for Bias Currents when Using

Transformer Input Coupling

REV. A –15–
AD621
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).

Plastic DIP (N-8) Package

8 5

0.25 0.31

C1673–24–6/92
(6.35) (7.87)

1 4

0.30 (7.62)
0.39 (9.91)
REF
MAX
0.035 ± 0.01
0.165 ± 0.01 (0.89 ± 0.25)
(4.19 ± 0.25)
SEATING PLANE
0.011 ± 0.003
0.125 (3.18)
(4.57 ± 0.76)
MIN

0.18 ± 0.03
0.018 ± 0.003 0.10 (4.57 ± 0.76) 0 - 15
(0.46 ± 0.08) (2.54)
TYP
0.033
(0.84)
NOM

Cerdip (Q-8) Package

0.005 (0.13) MIN 0.055 (1.4) MAX

8 5

0.310 (7.87)
0.220 (5.59)

1 4
0.070 (1.78)
0.030 (0.76)
0.320 (8.13)
0.405 (10.29) MAX 0.290 (7.37)

0.200 0.060 (1.52)

(5.08) 0.015 (0.38)
MAX

0.150
0.200 (5.08) 0.015 (0.38)
(3.81)
0.125 (3.18) 0.008 (0.20)
MIN

0.023 (0.58) 0.100 (2.54) 0 - 15

0.014 (0.36) BSC
SEATING PLANE

SOIC (R-8) Package

0.198 (5.03)
0.188 (4.77)

8 5

0.158 (4.00)
0.150 (3.80)

0.244 (6.200) PRINTED IN U.S.A.

1 4 0.228 (5.80)

0.018 (0.46)
0.050 (1.27) 0.014 (0.36) 0.205 (5.20)
TYP 0.181 (4.60)

0.094(2.39)
0.010 (0.25) 0.100 (2.59) 0.015 (0.38) 0.045 (1.15)
0.004 (0.10) 0.007 (0.18) 0.020 (0.50)

–16– REV. A