RT1720

60V Hot Swap Controller with Fault Timer

General Description
The RT1720 is an over-voltage and over-current The RT1720 features include, open-drain fault and
protection circuit. It monitors a circuit’s input voltage power-good outputs, and a shutdown input.
and current with its adjustable over-voltage and The RT1720 is available in the MSOP-10 package.
over-current thresholds and drives an external
N-MOSFET switch to connect the input to the output Features
voltage only when it is safe. Its wide input voltage  Wide Input Operation Range : 5V to 80V
range makes it useful for high-voltage applications and  Negative Input Voltage Rating to −60V
in systems that experience large transient voltages and  Adjustable Output Clamp Voltage
currents, such as automotive, telecom, and industrial  Adjustable Over-Current Protection
applications.  Programmable Timer for Fault Protection
During over-voltage events, the RT1720 quickly  Low Shut Down Current
reduces the gate drive of the external MOSFET to  Internal Charge Pump N-MOSFET Drive
regulate the output voltage at the level chosen by its  Fast 80mA MOSFET Shut-off for Overvoltage
external FB resistors. During over-current events, when  Fault Output Indication
the load draws excessive current, the RT1720 reduces
Applications
the gate drive to regulate the output current at the level
 Automotive/Avionic Surge Protection
set by its external current sense resistor. In both cases
 Hot Swap/Live Insertion
the output voltage or current is linearly regulated,
 High-Side Switch for Battery Powered Systems
thermally stressing the MOSFET load switch. However,
 Intrinsic Safety Applications
an externally-adjustable timer limits the duration of
MOSFET stress, eventually signaling a fault and then
turning off the MOSFET. The RT1720 then periodically
restarts operation to test if the fault has cleared. The
timer protects the MOSFET while allowing the load
circuit to temporarily operate normally through voltage
and current surges, such as load dump in automobiles
or spinning up disk drives.

Simplified Application Circuit

VIN RSNS Q1 VOUT
5V to 80V VOUT_Max = 60V
R3 VCC SNS COUT
SHDN GATE
VOUT
RT1720 R2
FB
TMR FLT FAULT R1
CTMR PGOOD POWER
GND GOOD

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RT1720
Ordering Information Marking Information
RT1720 01= : Product Code
Package Type YMDNN : Date Code
01=YM
F : MSOP-10
DNN
Lead Plating System
G : Green (Halogen Free and Pb Free)

Note : Pin Configurations

Richtek products are : (TOP VIEW)

 RoHS compliant and compatible with the current FB 10 TMR

requirements of IPC/JEDEC J-STD-020. VOUT 2 9 GND
GATE 3 8 PGOOD
 Suitable for use in SnPb or Pb-free soldering SNS 4 7 FLT
VCC 5 6 SHDN
processes.

MSOP-10

Functional Pin Description

Pin No. Pin Name Pin Function
Voltage Regulator Feedback Input. Connect a resistive divider from output to FB to
1 FB
GND to set the maximum output voltage and voltage regulation set-point.
Output Voltage Connection. VOUT is the lower reference voltage for the GATE
2 VOUT
charge pump.
3 GATE N-MOSFET Gate Drive Output.
Current Sense Input. Connect a sense resistor from VCC to SNS to monitor the
4 SNS
current through the external N-MOSFET.
5 VCC Positive Supply Voltage Input.
6 ̅̅̅̅̅̅̅̅
SHDN Shutdown Control Input.
7 ̅̅̅̅̅̅̅
FLT Open-Collector Fault Output.
8 PGOOD Open-Collector Power Good Indicator.
9 GND Ground.
Fault Timer Input. Connect a capacitor from TMR to GND to program the maximum
10 TMR time the part is allowed to remain in voltage regulation or current regulation mode.
TMR capacitor with value greater than 0.47F is recommended.

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 RT1720
Function Block Diagram

VCC SNS GATE VOUT

50mV +
- + FB
Charge - 1.25V

+
-
Pump
FLT

Control Logic
PGOOD
VCC
28.5μA
1.4V -
+ SHDN
+
1.2V -
GND
-
3.5μA
0.5V +

TMR

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RT1720
Operation
The RT1720 is an over-voltage and over-current charged by a 25A pull-up current and at 1.2V the ̅̅̅̅̅̅̅
FLT
protection regulator that drives an external N-MOSFET output goes low, signaling a fault. The load switch
load switch. If the input voltage rises above the voltage MOSFET remains on until VTMR reaches 1.4V, giving
set-point (set by the voltage divider at FB) the RT1720 time for any system housekeeping to occur before the
linear-regulates the load voltage using the external MOSFET turns off.
load switch MOSFET, until the adjustable fault timer If the fault condition ends or the MOSFET switch is
trips and turns the MOSFET off to prevent overheating. turned off (eliminating the fault), the capacitor at TMR is
If the load draws more than the current set-point (set by slowly discharged by a 3.5A pull-down current. When
the external sense resistor connected between SNS VTMR reaches 0.5V, GATE begins charging up and
and VCC) the IC controls the load switch MOSFET as a turns on the load switch, restarting the load
current source to limit the output current, until the fault automatically. The slower TMR discharge rate allows a
timer trips and turns off the MOSFET. These functions low duty factor of operation, to prevent overheating the
protect the load and system from faults and surges MOSFET or the load.
while potentially allowing the load to operate through The RT1720 open-drain PGOOD output rises when the
short-term voltage or current overloads. load switch turns on fully and the MOSFET’s source
The RT1720 operates over a wide supply voltage approaches its drain voltage. This output signal can be
range of 5V to 80V and can withstand reverse supply used to enable downstream devices or to signal a
voltages up to 60V below ground without damage. system that normal operation can begin.
Whenever it is enabled and no fault is detected, its The IC’s ̅̅̅̅̅̅̅̅̅
SHDN input disables all functions and
internal charge pump generates a gate-source voltage reduces the VCC quiescent current down to 7A.
of about 12V, fully enhancing the load switch MOSFET
to minimize dissipation and voltage loss. During a fault
condition, an external capacitor (at TMR) is slowly

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 RT1720
Absolute Maximum Ratings (Note 1)
 VCC, SNS --------------------------------------------------------------------------------------------------------------- 60V to 90V
 ̅̅̅̅̅̅̅̅̅ -------------------------------------------------------------------------------------------------------------------- 0.3V to 45V
SHDN
 ̅̅̅̅̅̅̅̅̅
SHDN Input Current --------------------------------------------------------------------------------------------------- 1mA
 VOUT--------------------------------------------------------------------------------------------------------------------- 0.3V to 65V
 GATE ------------------------------------------------------------------------------------- 0.3V to VOUT + AMR (GATE to VOUT)
 GATE to VOUT -------------------------------------------------------------------------------------------------------- (Note 5)
 FB, TMR ----------------------------------------------------------------------------------------------------------------- 0.3V to 10V

̅̅̅̅̅̅̅, PGOOD ----------------------------------------------------------------------------------------------------------- 0.3V to 12V
FLT
 TMR, FB, VOUT, GATE, PGOOD, FLT (Note 6) --------------------------------------------------------- 10mA
 Power Dissipation, PD @ TA = 25C
MSOP-10 ---------------------------------------------------------------------------------------------------------------- 0.27W
 Package Thermal Resistance (Note 2)
MSOP-10, JA ---------------------------------------------------------------------------------------------------------- 365C/W
 Lead Temperature (Soldering, 10 sec.) -------------------------------------------------------------------------- 260C
 Junction Temperature ------------------------------------------------------------------------------------------------ 150C
 Storage Temperature Range --------------------------------------------------------------------------------------- 65C to 150C
 ESD Susceptibility (Note 3)
HBM (Human Body Model) ----------------------------------------------------------------------------------------- 2kV
MM (Machine Model) ------------------------------------------------------------------------------------------------- 200V

Recommended Operating Conditions (Note 4)

 Supply Input Voltage, VCC ------------------------------------------------------------------------------------------ 5V to 80V
 Output Voltage, VOUT ------------------------------------------------------------------------------------------------ 5V to 60V
 Ambient Temperature Range--------------------------------------------------------------------------------------- 40C to 85C
 Junction Temperature Range -------------------------------------------------------------------------------------- 40C to 125C

Electrical Characteristics
(VCC = 12V, TA = 25C, unless otherwise specified)
Parameter Symbol Test Conditions Min Typ Max Unit
̅̅̅̅̅̅̅̅̅ unconnected
SHDN -- 2.3 5 mA
VCC Supply Current ICC
̅̅̅̅̅̅̅̅̅ = GND
SHDN -- 7 25 A
VSNS = VCC = 30V,
Reverse Input Current IR ̅̅̅̅̅̅̅̅̅ -- 0.3 1 mA
SHDN unconnected
VCC = 5V ; (VGATE  VOUT) -- 9 12
GATE Output High Voltage
VGATE 80V ≥ VCC ≥ 8V ; (VGATE  V
(Note 5) -- 12 16
VOUT)
VGATE = 12V 15 40 60
GATE Pull-Up Current IGATE_UP A
VGATE = 48V, VCC = 48V 30 70 120

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RT1720
Parameter Symbol Test Conditions Min Typ Max Unit
Over Voltage, VFB = 1.4V,
55 80 --
VGATE = 12V
Over Current, VCC  VSNS =
GATE Pull-Down Current IGATE_ON -- 3 -- mA
120mV, VGATE = 12V
̅̅̅̅̅̅̅̅̅ =
Shutdown Mode, SHDN
55 80 --
GND, VGATE = 12V
FB Servo Voltage VFB VOUT = 12V 1.2 1.25 1.3 V
FB Input Current IFB VFB = 1.25V -- 0.3 1 A
Over Current Fault VCC = 12V 45 50 55
VSNS (VCC VSNS) mV
Threshold VCC = 48V 43 48 53
SNS Input Current ISNS VSNS = VCC = 12V to 48V -- 120 -- A
̅̅̅̅̅, PGOOD Leakage
FLT VPGOOD = VFLT = 10V,
ILEAK ̅̅̅̅̅̅̅̅̅ -- -- 2 A
Current SHDN = GND
VTMR = 1V, VFB = 1.5V, or
TMR Pull-Up Current ITMR_UP -- 25 -- A
VSNS = 60mV
VTMR = 1V, VFB = 1V, or
TMR Pull-Down Current ITMR_DOWN 2.5 3.5 5 A
VSNS = 0V
TMR Fault Threshold
VTMR_F FLT changes state 1.14 1.2 1.26 V
Voltage
TMR GATE Off Threshold VTMR_L GATE turns off -- 1.4 -- V
TMR GATE On Threshold VTMR_UL GATE turns on -- 0.5 -- V
̅̅̅̅̅, PGOOD Output Low
FLT ISINK = 2mA -- 300 500
VOL mV
Voltage ISINK = 0.1mA -- 120 300
VOUT = VCC = 12V -- 200 500 A
VOUT Pin Input Current IOUT VOUT = VCC = 12V,
̅̅̅̅̅̅̅̅̅ -- -- 2 mA
SHDN = GND
VOUT = VCC VOUT ;
VOUT High Threshold VOUT 0.4 0.8 1.1 V
PGOOD from Low to High
̅̅̅̅̅̅̅̅̅
SHDN Logic-High VCC = 12V to 48V 2.5 -- -- V
Input
Voltage Logic-Low VCC = 12V to 48V -- -- 0.5 V
̅̅̅̅̅̅̅̅̅ Input Current
SHDN I̅̅̅̅̅̅̅̅̅
SHDN V̅̅̅̅̅̅̅̅̅
SHDN = 3V -- 0.4 -- A

Note 1. Stresses beyond those listed “Absolute Maximum Ratings” may cause permanent damage to the device. These are
stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions may affect
device reliability.
Note 2. JA is measured at TA = 25C on a high effective thermal conductivity four-layer test board per JEDEC 51-7.
Note 3. Devices are ESD sensitive. Handling precaution recommended.
Note 4. The device is not guaranteed to function outside its operating conditions.
Note 5. GATE to VOUT voltage is internally generated and clamped with specification shown in the electrical characteristics
table. External driving at GATE pin is forbidden because it may damage the device.
Note 6. All currents into device pins are positive, all currents out of device pins are negative. All voltages are referenced to GND
unless otherwise specified.

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 RT1720
Typical Application Circuit
RSNS
10m Q1
VIN VOUT
R3
VCC SNS COUT
100k
1μF
SHDN GATE
VOUT
RT1720 R2
VCC
102k
TMR FB DC/DC
CTMR R1 Converter
0.47μF 4.99k

FAULT FLT PGOOD

GND SHDN GND

Figure 1. 4.5A, 27V Over-voltage Regulator

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RT1720
Typical Operating Characteristics

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 RT1720

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RT1720

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 RT1720
Application Information
The RT1720 over-voltage and over-current protection while CTMR is slowly discharged. The discharge is
controller directly drives an external N-MOSFET load slower than the charge rate to reduce the overall duty
switch to limit the voltage and current delivered to a factor for faults that last multiple TMR cycles. Once
load and to protect the load. If the supply voltage VTMR reaches 0.5V, FLT̅̅̅̅̅̅ is released and the MOSFET
surges or the load draws excessive current, the turns on again in a controlled soft-start.
RT1720 controls the MOSFET gate to regulate the The duration of a fault before the MOSFET turns off is :
voltage or current, keeping both below their adjustable
CTMR  1.4V
thresholds. If any fault condition continues long enough tFAULT =
25μA
to for the adjustable-length fault timer to time out, the
MOSFET is turned off for some time and then the The interval between ̅̅̅̅̅̅
FLT asserting low and the
MOSFET automatically turns on again. MOSFET MOSFET turning off is given by :
turn-on is slow and controlled, to prevent surge CTMR  1.4V - 1.2V 
currents, making the circuit useful for soft-start and hot t WARNING =
25μA
insertion applications.
The MOSFET cool down period is given by :
Fault Timer CTMR  1.4V - 0.5V 
tCOOLOFF =
The RT1720’s fault timer is activated during any 3μA
over-voltage or over-current event. During an event,
Over-Voltage Protection
the capacitor at TMR (CTMR) is slowly charged. When
the voltage at TMR reaches 1.2V, the open-drain The RT1720’s adjustable over-voltage protection
̅̅̅̅̅̅
FLT output goes low and when VTMR reaches 1.4V the function uses an external voltage divider at FB, from
MOSFET switch is turned off disconnecting the load. the output voltage to GND, to set the protection
The time delay while VTMR charges from 1.2V to 1.4V threshold voltage. When the voltage at FB exceeds
gives system software an opportunity to perform any 1.25V (typical), GATE is discharged sharply and the
required housekeeping functions. The fault timing is set MOSFET begins turning off. As the MOSFET turns off
by the external capacitor at TMR. and the voltage at FB drops, GATE begins charging up
During an over-voltage fault, the MOSFET load switch again. In this way, GATE reaches an equilibrium point
is used to regulate the output voltage at the voltage and the output voltage is linear-regulated with FB at
level set by the FB resistive divider. During an 1.25V.
over-current fault the current is regulated at the current During an over-voltage event, TMR begins charging
level set by the current sense resistor at SNS. In both while the over-voltage remains and GATE continues to
of these events, regulating the output voltage or current linear-regulate the output voltage. Eventually, VTMR
causes power dissipation in the external MOSFET load may reach 1.2V (where the FLT ̅̅̅̅̅̅ output goes low,
switch. The fault timer sets the maximum duration of signaling a fault) and then 1.4V (where GATE will turn
the power dissipation stress. Select CTMR to keep the completely off). If VTMR does not reach 1.4V and the
MOSFET power dissipation acceptable for the selected input voltage drops (allowing GATE to turn on fully),
external MOSFET. If the MOSFET can withstand TMR will slowly discharge. The capacitor at TMR
continuous dissipation for any possible fault, you can determines how long an over-voltage event may last
disable the timer by connecting TMR to ground. without causing GATE to turn off and the output voltage
When the fault timer reaches 1.4V and turns off the to collapse completely.
MOSFET, or if the fault ends before VTMR reaches The system operates normally while TMR charges
1.4V, TMR slowly discharges the capacitor (CTMR). If during an over-voltage event but the excess input
the fault timer reaches 1.4V, the MOSFET load switch voltage is dropped across the external MOSFET and
is turned off to allow the switch and the load to cool heat is dissipated. The capacitor at TMR should be

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RT1720
chosen carefully to allow the system to operate through The current limit is set by the following equation :
expected over-voltage events without interruption, but
to prevent prolonged excessive dissipation that might ILIM = 50mV
RSNS
damage the external MOSFET or load.
The OVP voltage is set by the following equation : MOSEFT Selection

VOUT_OVP = 1.25V  1+ R2
R1   The N-MOSFET load switch is the critical component
for the protection circuit. Choosing an appropriate
device is not difficult but there are many important
where R1 and R2 are the FB voltage divider from VOUT
requirements. The most important are :
to GND.
 on-resistance (RDS(ON))
Over-Current Protection  maximum current rating
The RT1720’s adjustable over-current protection  maximum drain-source voltage
function uses a current-sense resistor between SNS  maximum gate-source voltage
and VCC to set the protection threshold voltage.  power dissipation and safe operating area (SOA)
When the voltage between these two pins exceeds  gate threshold (for lower VIN applications)
50mV (typical), GATE is discharged and the MOSFET For most of the time the MOSFET will be fully on. In
begins turning off. As the MOSFET turns off and the that state, the voltage loss and power dissipation are a
output voltage drops, the load current decreases and simple matter of RDS(ON) and current. Choose a device
the current sense voltage drop below the threshold. that doesn’t drop more voltage than is acceptable
GATE begins charging up again and reaches an considering the minimum value of the intended input
equilibrium point regulating the load current at the voltage and the voltage requirements of the load, and
threshold. one that can handle the required continuous current.
During an over-current event, TMR begins charging Avoid logic-level MOSFETs with their low VGS
while the over-current remains and GATE continues to maximum ratings, or add a GATE-VOUT clamp to
regulate the load current. Eventually, VTMR will reach avoid damaging. The RT1720 GATE drive voltage may
̅̅̅̅̅̅ output goes low, signaling a fault)
1.2V (where the FLT be as high as 14V so standard-threshold MOSFETs
and then 1.4V (where GATE will turn completely off). If with 20V VGS ratings is recommended.
VTMR does not reach 1.4V and the excessive load When the MOSFET is turned off (whether in shutdown
current decreases (allowing GATE to turn on fully), or in OVP or OCP) the full input voltage appears across
TMR will slowly discharge. The capacitor at TMR the MOSFET. Choose a MOSFET with a maximum
determines how long an over-current event may last drain-source voltage exceeding your maximum input
without causing GATE to turn off and the output voltage surge voltage.
to collapse completely. During an over-voltage (OV) event, the MOSFET will
The system continues to operate somewhat normally linear regulate the output voltage delivered to the load.
(with reduced output voltage) while TMR charges According to the timing determined by the capacitor
during an over-current event but the voltage dropped connected at the TMR pin, the circuit will turn the load
across the external MOSFET during the high load on and off periodically until the over-voltage ends.
current causes high dissipation in the external While linear-regulating, the MOSFET will dissipate
MOSFET and possibly the load. The capacitor at TMR power and heat up. Since TMR charges around seven
should be chosen carefully to allow the system to times the rate that it discharges, the MOSFET will
operate through expected over-current events without linear regulate with a duty cycle of about 12% during a
interruption, but to prevent prolonged excessive long continuous OV event.
dissipation that might damage the external MOSFET or
load.

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 RT1720
If the OV event is shorter than the TMR charge timing use one of the longer timed areas of the SOA graph
then examine the MOSFET’s safe operating area (SOA) (perhaps the DC area) but adjust the IOC_THRESHOLD
graph, using VIN – VOUT for MOSFET drain to source value by the 12% duty cycle of the MOSFET on periods
voltage and ILOAD(VOUT) for the drain current, to to determine if the MOSFET will work. For thermal
determine if the over-voltage event will cause MOSFET management, the MOSFET dissipation during long
damage. It may be helpful to adjust CTMR to meet the over-current events is :
MOSFET’s SOA limits. PDMOSFET(OV) = DC   VIN - VOUT   IOC_THRESHOLD
If the OV event lasts more than one TMR cycle then the where DC is the duty cycle of current regulation,
MOSFET will turn on and off, dissipating power each typically about 12%.
time it is on and linear regulating and cooling down
Parallel MOSFETs
when it is off. In this case, use one of the longer-timed
Select a single MOSFET for most applications. If the
areas of the SOA graph but adjust the drain current
RDS(ON) target is very low and difficult to achieve at the
value by the 12% duty cycle of the MOSFET on periods
necessary voltage rating, multiple devices may be used
to determine if the MOSFET will work. For thermal
in parallel. Parallel devices can decrease the voltage
management, the MOSFET dissipation during long
drop in normal operation and reduce dissipation.
over-voltage events is :
However, SOA requirements must generally be met by
PDMOSFET(OV) = DC   VIN - VOUT   ILOAD(VOUT)
a single device.
where DC is the duty cycle of linear regulation, typically In OV and OC conditions, GATE will decrease until the
about 12%. programmed output voltage or current is maintained. In
During an over-current (OC) event the MOSFET will that state, the MOSFET with the lowest threshold will
regulate the output current delivered to the load and carry more current than other parallel MOSFETs with
the output voltage will collapse to whatever voltage is higher thresholds, perhaps dramatically more. It’s
needed to sustain the OC threshold current. According generally best to assume that one device will be
to the timing determined by the capacitor connected at subjected to the entire SOA stress.
the TMR pin, the circuit will turn the load on and off
Shutdown
periodically until the over-current event ends. While
regulating the load current, the MOSFET will dissipate The RT1720 enters a low current (7A typical)
power and heat up. Unlike an OV event, the output ̅̅̅̅̅̅̅̅̅ pin
shutdown mode when the voltage at the SHDN
voltage and the MOSFET’s drain-source voltage may goes below its 0.5V logic-low level. In shutdown all
not be easily predicted. If the output is shorted the functions are turned off.
voltage may collapse nearly to zero, placing the entire For automatic start-up, it’s recommended to connect
input voltage across the MOSFET. Further, this type of SHDN pin to
event is likely to continue for long periods. If the output (1) A voltage between 3V and 45V through a 100k
voltage during the OC event is not easily determined, resistor.
use zero for VOUT.
(2) A voltage higher than 45V through a resistor with
For the rare OC event that is short compared to the minimum value of the following formula,
TMR timing, examine the MOSFET’s safe operating
RSHDN = [ VSHDN_max – 45V ] / 0.25mA
area (SOA) graph, using VIN – VOUT for MOSFET drain
No external voltage clamp is needed since the pin
to source voltage and your IOC_THRESHOLD for drain
clamps the input voltage. If external board leakage is
current, to determine if the over-current event will
cause MOSFET damage. kept below 1A, the pin can be left open and an
internal current source will pull the pin voltage to about
If the OC event lasts more than one TMR cycle then the
2.5V. ̅̅̅̅̅̅̅̅̅
SHDN may also be driven by a logic output to
MOSFET will turn on and off, dissipating power each
turn the IC on and off.
time it is on and cooling down when it is off. In this case,

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RT1720
̅̅̅̅̅̅
FLT Output VIN, PGOOD rises when VOUT is within the VOUT
high threshold (VIN-1V typical). Once high, PGOOD
The RT1720 includes an open-drain fault output that
stays high even if GATE turns off and VOUT falls, until
indicates the state of the TMR pin voltage. Typically,
̅̅̅̅̅̅ is externally pulled up to some positive voltage VOUT discharges to about 2V (typical). Once low,
FLT
PGOOD only rises again when GATE turns on and
(such as VIN or a system logic supply) through a
VOUT again approaches VIN. PGOOD is always high
resistor such as 100k.
when SHDN is low and the IC is in its low-power
When an over-voltage or over-current condition occurs,
shutdown state, unless PGOOD is pulled up to a
the TMR pin begins charging CTMR. When VTMR is less
voltage (like VOUT) that turns off in shutdown. PGOOD
than the fault threshold (1.2V typical) the ̅̅̅̅̅̅
FLT output
is not designed as a traditional power-good indicator. A
remains unconnected allowing the external resistor to
traditional power-good indicator usually has a fixed
pull it high. When VTMR exceeds the threshold, the
threshold voltage and indicates if VOUT is above or
̅̅̅̅̅̅
FLT output is internally pulled to GND, signaling that
below that threshold. The RT1720’s PGOOD output is
VTMR is nearing the GATE latch threshold (1.4V typical)
intended to indicate to downstream load devices that
where the external MOSFET is turned completely off.
GATE has fully turned on the external MOSFET load
When GATE turns off or the fault ends, the ̅̅̅̅̅̅
FLT output switch and full output current is available. Enabling the
remains low while GATE is off, until VTMR reaches the load before GATE has fully turned on is poor practice
GATE unlatch threshold (0.5V typical) and GATE turns because the load current causes high dissipation in a
the external MOSFET back on. The FLT ̅̅̅̅̅̅ output rises
partially-enhanced MOSFET. Also, drawing a large
when TMR reaches the threshold, indicating that GATE load current through the partially-on MOSFET might
is beginning to turn on. cause the output voltage to collapse, possibly leaving
system components in an unreliable logic state.
PGOOD Output
PGOOD goes high (open-circuit) only when VOUT is
The RT1720’s includes an open-drain PGOOD output. reaching VIN and the MOSFET switch is nearly fully on.
The PGOOD output’s state relates to the VOUT voltage
On MOSFET turn off (if SHDN falls or if there is a
relative to VIN, rather than the absolute level of VOUT.
voltage or current fault) PGOOD stays high, allowing
Since it is open drain, PGOOD only shows a voltage
the load to operate as long as possible, until VOUT falls
level if it is externally pulled up to some positive voltage
to about 2V (typical). Once PGOOD falls, it only rises
(such as VIN, VOUT, or a system logic supply) through
again if the output voltage nears VIN.
a resistor such as 100k.
When GATE begins charging and VOUT rises toward

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 RT1720
Application Design Example
Using the typical application circuit as a design During an over-voltage or over-current event, GATE
example with the following specifications : will regulate the output voltage or current while CTMR
 Automotive Application charges. When the voltage on the timing capacitor
 VIN = 8V to 14V DC with transients up to 80V. (VTMR) reaches the fault threshold ( VTMR_F , 1.2V
̅̅̅̅̅̅ will go low, signaling that GATE will turn
typical) FLT
 Output Voltage : VOUT 16V
 Current Limit (ILIM) : 10A off the external MOSFET soon. The “housekeeping”
 Overvoltage Duration : 25ms timing from ̅̅̅̅̅̅
FLT low ( VTMR_F ) to GATE turn-off
(VTMR_L) is :
Output Over-voltage Protection Setting :
To set the OVP threshold at 16V, choose R1 as 4.99k CTMR   VTMR_L - VTMR_F 
tHOUSEKEEPING =
(giving a very robust 250A divider current) and iTMR_UP

0.47μF  1.40V - 1.2V 

calculate R2 according to the following equation :

 1.25V - 1 = 58.9k
tHOUSEKEEPING = = 3.76ms
V 25μA
R2 = R1 OVP

In the event of a long fault, GATE will turn on an off

Select R2 as a standard 1% value of 59k or use 56k repeatedly. The on and off timings (tGATE_ON and
and calculate the resulting threshold as : tGATE_OFF) are controlled by the TMR charge and

 
discharge currents (iTMR_UP and iTMR_DOWN) and the
VOVP = 1.25V  R2 + 1 = 15.3V voltage difference between the TMR latch and unlatch
R1
thresholds (VTMR_L - VTMR_UL) :
Current Limit Setting :
CTMR   VTMR_L - VTMR_UL 
Calculate the sense resistor, RSNS, according to the tGATE_ON =
iTMR_UP
following formula :

RSNS =
VSNS
= 50mV = 5mΩ 0.47μF  1.40V - 0.5V 
ILIM 10A tGATE_ON = = 16.9ms
25μA

Calculate the power dissipation of RSNS to avoid

overheating the sense resistor : CTMR   VTMR_L - VTMR_UL 
tGATE_OFF =
iTMR_DOWN
PDRSNS  = ILIM2  RSNS = 1.2  (10A)2  5mΩ = 0.6W
Select a 1W sense resistor or consider a parallel
0.47μF  1.40V - 0.5V 
combination of lower-wattage resistors. tGATE_OFF = = 141ms
3μA
Over-Voltage/Over-Current Timer Setting :
Choose the MOSFET :
Calculate the value of fault timing capacitor (CTMR)
using the typical TMR pull-up current and TMR latch Select the Q1 MOSFET VDS rating, allowing for your
threshold with the following formula : maximum input voltage and transients. Then select an
operating RDS(ON) to meet any voltage drop
tLATCH  iTMR_UP 25ms  25μA
CTMR = = = 0.45μF specifications and your on-state dissipation allowance.
VTMR_L 1.4V
Finally, its package must be able to handle that
Select the standard value of 0.47F and calculate the dissipation and control its operating temperature.
resulting fault timing: Most manufacturers list a maximum RDS(ON) at 25C
CTMR  VTMR_L 0.47μF  1.4V and provide a typical characteristics curve from which
tLATCH = = = 26.3ms
iTMR_UP 25μA values at other temperatures can be estimated. You
can also use the below equation to estimate maximum
RDS(ON) from the 25C specification :
RDS(ON)_MAX =  TJ(MAX) - 25C  0.5%/C
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RT1720
Given the 8V minimum input and the 10A output Higher-Voltage Transients
current, the RDS(ON) must be very low to avoid dropping
If voltage transients above 80V are expected, there is
a large percentage of the input voltage. To limit the
one possible approach (shown in Figure 3). The input
drop to 1% of 8V (80mV) requires an 8m maximum.
voltage can simply be clamped at less than 80V using a
Therefore, the 25°C specification should be about 5m.
Zener diode, transient voltage suppressor, or metal
The package needs to dissipate about (10A)2 x 8m =
oxide varistor. Noted that the voltage clamping device
800mW into a hot automotive ambient temperature.
D1 must be able to absorb the entire energy of the
Something like the Vishay SQM120M10-3m8, with its
input voltage transient.
100V VDS rating, 6.4m maximum at 125°C, and its
40°C/W (on a copper PCB) D2Pak package should be +24V Typical RSNS
10m
Q1
+120V Transients Si4190DY VOUT
more than adequate.
VIN D1
3.0SMCJ58A 1µF
Diodes Inc.
Reverse Input Voltage Blocking
Some applications have to withstand reverse input R5
100k VCC SNS

voltages such as a battery connected backwards or SHDN GATE

VOUT
negative-voltage transients. Typically such applications RT1720 R3
use a blocking diode in series with the input voltage. In FB

applications where the diode’s voltage drop or power GND R4

dissipation is unacceptable, back-to-back N-MOSFETs

may be an acceptable cost.
Figure 3. Withstanding Higher-Voltage Transients
Figure 2 shows one possible application. In normal
operation, GATE charges both MOSFET gates. In case TMR Ratio Setting
of reverse input voltage, Q3 turns on and pulls Q2’s
The turn on time represents the time takes the circuit to
gate below ground and keeps its VGS near zero, while
charge up the output capacitance and load. The turn on
GATE’s internal protection diode clamps its voltage at
time is a function of the type of control; current limit,
ground, keeping Q1 off. The RT1720 IC’s VCC pin is
power limit, or dV/dt control for MOSFET. To reduce
designed to withstand reverse voltage and needs no
heat dissipation of the MOSFET during OC/OV
additional protection.
protection, the lower ratio of tGATE_ON to tGATE_OFF can
RSNS Q2 Q1 be achieved by adding D1 and Q2 as shown in Figure 4
VIN 10mohm Si4190DY Si4190DY VOUT

+24V Typical 4.5A

below.
-60V to +80V Transients Q3 1µF
2N3904

R6 VIN RSNS Q1 VOUT

R5 D1
100k 100k
1N4148 R7
C2 C3
100k

VCC SNS R1 R2
SHDN GATE
0.1µF
VOUT
TMR
R3
RT1720 VCC SNS
102K
SHDN GATE
FB
R4 Q2 VOUT
TMR
4.99K D1 RT1720 R3

FAULT FLT PGOOD

CTMR FB
GND
R4

FLT PGOOD
GND

Figure 2. Reverse-Voltage Application

Figure 4. Gate On and Gate Off Time Setting Design

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 RT1720
Thermal Considerations operating ambient temperature for fixed TJ(MAX) and
Since this device dissipates little power in operation, thermal resistance, JA. The derating curve in Figure 5
even the 270mW MSOP-10 package is unlikely to allows the designer to see the effect of rising ambient
overheat due to its own operation. Its 1mA supply temperature on the maximum power dissipation.
current, even with an 80V input voltage range, makes a
discussion of thermal resistance, package dissipation, 0.4

Maximum Power Dissipation (W)1

Four-Layer PCB
and thermal layout almost unnecessary.
However, carefully consider the placement of the 0.3

RT1720 in the overall layout with nearby components,

particularly for high-temperature applications (such as 0.2

automotive) and in conjunction with high-temperature

rated MOSFETs that can operate with junction 0.1
temperatures well above this IC’s 125°C maximum
recommended operating range. Do not allow the
0.0
combination of internal dissipation, ambient 0 25 50 75 100 125

temperature, and dissipation from surrounding Ambient Temperature (°C)

components (MOSFETs, sense resistors, DC/DC

Figure 5. Derating Curve of Power Dissipation
converter components) to raise the IC’s junction
temperature above its 125°C maximum. The RT1720 Layout Considerations
includes a thermal shutdown state (typically activated The RT1720 has relatively simple layout requirements.
at 150°C) that pulls GATE low and turns off the external
Place the VCC, VOUT, and TMR capacitors close to
MOSFET.
their respective pins, to avoid noise issues.
For continuous operation, do not exceed absolute
Place FB voltage divider resistors close to their
maximum junction temperature. The maximum power
respective pins to avoid threshold detection problems.
dissipation depends on the thermal resistance of the IC
Don’t route these connections next to noisy traces such
package, PCB layout, rate of surrounding airflow, and
as high-speed digital lines or DC/DC switching nodes.
difference between junction and ambient temperature.
Avoid current sensing errors by using Kelvin sensing in
The maximum power dissipation can be calculated by
the RSNS layout (Figure 6). Connect VCC and SNS to
the following formula :
RSNS avoiding any high current-carrying copper.
PD(MAX) = (TJ(MAX)  TA) / JA
Connecting to the inside of RSNS is recommended.
where TJ(MAX) is the maximum junction temperature,
Connect GND and the package’s backside pad (if any)
TA is the ambient temperature, and JA is the junction to
to the bypass and timing capacitor grounds and voltage
ambient thermal resistance.
divider grounds with a wide solid copper ground area,
For recommended operating condition specifications, to avoid noise issues.
the maximum junction temperature is 125C. The
The recommended PCB layout guide lines are listed as
junction to ambient thermal resistance, JA, is layout
follows :
dependent. For MSOP-10 package, the thermal
 The current sense resistor RSNS is recommended
resistance, JA, is 365C/W on a standard JEDEC 51-7
to achieve accurate current Kelvin sensing
four-layer thermal test board. The maximum power
connection.
dissipation at TA = 25C can be calculated by the
 The input capacitors CIN must be placed as close
following formula :
to the VCC pin as possible.
PD(MAX) = (125C  25C) / (365C/W) = 0.27W for  Connect the GND pin and exposed pad to a large
MSOP-10 package ground plane for maximum power dissipation and
The maximum power dissipation depends on the noise reduction.
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RT1720
RSNS

POWER PATH
CIN

VCC SNS

GND
RT1720

Figure 6. Current Sense Resistor Kelvin Connection.

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 RT1720
Outline Dimension

Dimensions In Millimeters Dimensions In Inches

Symbol
Min Max Min Max
A 0.810 1.100 0.032 0.043
A1 0.000 0.150 0.000 0.006
A2 0.750 0.950 0.030 0.037
b 0.170 0.270 0.007 0.011
D 2.900 3.100 0.114 0.122
e 0.500 0.020
E 4.800 5.000 0.189 0.197
E1 2.900 3.100 0.114 0.122
L 0.400 0.800 0.016 0.031
10-Lead MSOP Plastic Package

Richtek Technology Corporation

14F, No. 8, Tai Yuen 1st Street, Chupei City
Hsinchu, Taiwan, R.O.C.
Tel: (8863)5526789
Richtek products are sold by description only. Richtek reserves the right to change the circuitry and/or specifications without notice at any time. Customers should
obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. Richtek cannot assume
responsibility for use of any circuitry other than circuitry entirely embodied in a Richtek product. Information furnished by Richtek is believed to be accurate and
reliable. However, no responsibility is assumed by Richtek or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may
result from its use. No license is granted by implication or otherwise under any patent or patent rights of Richtek or its subsidiaries.
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