CuHaPTER 2 g086 System Bus Structure 8086 SIGNALS _~ 1 The SOS6 pins and signals are shown in Figs, 2.1 and 2.2. The 8086 is a 40-pin IC and all the $085 pins are Tra to M1 will be different for mini to an a Transistor Logic (TTL) compatible. The signals assigned to pins 24 ind maximuin modes of operation. The signals assigned to all cect pins are common for minimum and maximum modes of operation. AD, u 30 HLDA (RQ/GT,) AD.12 29> WR (COCR) AD 113, 2F>Mi0 GS) AD. ya 27> DTR G) AD His 26> DEN) AD, 2SPALE (QS) NMI [> INTA (QS) INTR TEST ck READY GND RESET Fig. 2.1 : 8086 pin assignments. 2.1.1 COMMON SIGNALS Note: Signals shown in parenthesis are maximum mode signals. The common signals for minimum and maximum modes are listed in Table 2.1. The lower 16 lines of the address are multiplexed with data and the upper four lines of the address ae multiplexed with status signals. During the first clock period of a bus cycle, the entire 20-bit address is available on these lines. During all other clock periods of'a bus cycle, the data and status signals will be available on these lines.Microprocessors and Microcon AD AD. D>} ma . LC MNMXN=Vic A HOLD Es [> HLDA [> Lock ps. BTR a satenom | 7 TE TR spstimum f>S NMI—4} mode FO DEN NMI—} mode 145, cux [> ALE cK | sas, [2 Tx L» os, <— TEST uo <— READY Voc ox <— RESET one {a) : 8086-Minimum mode. (b) : 8086—Maximum mode. Fig. 2.2 : 8086 pins and signals. TABLE 2.1: COMMON SIGNALS Name Description/Function Type AD,,- AD, Address/Data Bidirectional, Tristate A Ad/SeAdS, | Address/Status Output, Tristate BHE/S, Bus high enable/Status Output, Tristate MNIMX Minimum/Maximum mode control Input RD Read control Output, Tristate TEST Wait on test contro! Input READY Wait state control Input RESET System reset Input Non-maskable interrupt request Input Interrupt request Input ‘System clock Input +5V Power supply, input | Ground Power supply, ground _|Chapter 2 - 8086 System Bus Structure Joo 2.2: MINIMUM MODE SIGNALS [MN/MIX = Veg (Logic high)] : Description/Function x HOLD Hold request Input ‘| HLDA Hold acknowledge Output . WR Write control Output, Tristate 7 Mio Memory/IO control Output, Tristate 7 OUR Data transmit/Receive Output, Tristate DEN Data enable Output, Tristate y ALE Address latch enable Output s iNTA Interrupt acknowledge Output 4 (fast 2.3: MAXIMUM MODE SIGNALS [MN/MX = Ground(Logic low)] Name Description/Function Type = RO GT, RQ GT Request/Grant bus access control Bidirectional tock Bus priority lock control Output, Tristate $2,550 Bus cycle status Output, Tristate - Qs,, as, Instruction queue status Output STATUS SIGNAL DURING MEMORY-SEGMENT ACCESS 2 val Status signal Segment register S, Ss o ° Extra segment 0 1 Stack segment 1 0 Code or no segment 4 1 Data segment The status lines S, and S, are used to indicate which segment is accessed during the current bus cycle. The status line S, indicates the status of the 8086 interrupt enable flag. A low on the line S, indicates that the 8086 is on the bus (i ae! ., itindicates that 8086 is the bus master) and during hold acknowledge, this pin is driven to high impedance state. The output signal BHE on the first T-state of a bus cycle is maintained as status signal S, during all other T states of the bus cycles. ofa bus cycle is maintained as status Signal S,. Fire 8086 outputs. low on thi 1 When the data is to be transferred to the with address bit A,(AD,) to select memory banks. pin. read, write and interrupt acknowledge cycles the high order data bus,)The BHE can be used in conjunction D combined with addreuw lauoF Microprocessors and Microcontolly When the processor reads from the memory or an 10 location, itasserts RD as low. The este by the WAIT instruction, The 8086 will en instruction and it will resume execution only when TEST is made low by an external hardware) This is used to synchronize an extemal activity to the processor's intemal operation, TEST inp is synchronized internally during each clock cycle on the leading edge of the clock signal. ST await state after execution of the WAIT NTR is the maskable interrupt and INTR must be held high until itis recognized to generat aan interrupt signal. NMI is the non-maskable interrupt input activated by a leading edge signa tem reset input signal. For power-ON reset, it is held high for microstconds, For reset while working, it is held high for at least four clock eyeles. When is reset, the DS, SS, ES, IP and flag register are cleared, Code Segment (CS) register} ‘4 And queue is emptied. After reset, the processor will start fetching instruct trom the 20-bit physical address FFFFO,.. al to the processor, used by the memory or 10 devices to get time tor data traister or to introduce wait states in the bus cycles. Normally, READY is tied ) Ifthe READY is tied low, the S086 introduces wait states after the second T:state of a bus and it will complete the bus cycle only when READY is made high again. f CLK inpatis the clock signal that provides the basic timing for the S086 and bus contr The S086 does not have an on-chip clock Bgneration cireuit. Hence, the 8284 clock g chip is used to generate the required clock. A Quan? “tystal whose frequency is thrice that internal clock of an S086 must be connected to the 8284. The 8284 generates the clock at frequency, The S284 divides the generated clock by three and modifies the duty ¢ ‘output on the CLK pin of $284, This CLK output of $284 must be connected to the 8 Pin. The $284 also provides the RESET and READY signals to the 8086, The clock ft different versions of $086 can vary from 5-10 MHz. 2.1.2 MINIMUM MODE SIGNALS ~~ The minimum mode signals of an S086 are listed in Table 2.2. For minimum operation, the MN/MX pinis tied to V (logic high). In minimum mode, the S086 itself, all the bus control signals. The minimum mode signals are explained as follows: DT/R = (Data Transmit Receive) — It is an output signal from the processor to | direction of data flow through the data transceivers. DEN == (Data Enable) — It is an output signal from the processor used as ou! the data transceivers. ALE - (Acdéress Latch Enable) — Itis used to demultiplex the address and extemal latches, MIO _ tis used to differentiate memory access and 10 access, For IN and O itis low. For memory reference instructions, itis high.\Chaprer 2 - 8086 System Bus Structure + Itisa write control signal and is asserted low whenever the processor writes data the memory or 10 port. Ls INTA - (Interrupt Acknowledge) — The 8086 outputs low on this line to acknowledge whe t the interrupt request is accepted by the processor. HOLD - Itis.an input signal to the Processor from other bus masters as a Tequest to grant th Control of the bus. It is usually used by the DMA controller to get the control of the bus 'HLDA - (Hold Acknowledge) ~ It is an acknowledge signal by the processor to the master Fequesting the control of the bus through HOLD. The HLDA is asserted high when the processor accepts the HOLD. [On accepting the hold, the processor drives all the tristate pins to high impedance state and sends an acknowledge to the device which requested HOLD. On receiving the acknowledge, the other master will take control of the bus.) MAXIMUM MODE SIGNALS = SUM MODE SIGNALS The maximum mode signals of 8086 are listed in Table 2.3. The 8086-based system can be made to work in maximum mode by grounding the MN/MX pin (i.e., MN/MX is tied to logic low). In maximum mode, the pins 24 to 31 are redefined as follows: Se5,,52 - These are status signals and they are used by the 8288 bus controller to generate the bus timing and control signals. The status signals are decoded as shown in Table 2 L TABLE 2.5: STATUS SIGNALS DURING VARIOUS MACHINE CYCLES Status signal S. Machine cycle a i Interrupt acknowledge Read IO port Write 10 port Halt Code access Read memory Write memory Passive/inactive aanscoos as004400 +Osr04040 ~RQIGT., - (Bus RequesvBus Grant) - These requests are used by the other local bus masters ROIGT, 10 force the processor to release the local bus at the end of the processor's current bus cycle. These pins are bidirectional. The request on GT, will have higher priority than GT...)Microprocessars and Mictocy The bus request to 8086 works as follows: 1, When a bocal bus master requires system bus control, it sends a low pudse to the 6086. | 2. At the end of the current bus cycle, the processor (2026) drives its pins to high impedance state ‘tends an acknowledge signal a1 a low pulte on the same pin to the device which requested the bus contral 3. On receiving the acknurwledge tral, the local master wil take contol of the system tees. After completing ig ‘1 the ond, the local bus master sends a low signal on the same pin to the 2026 to inform the end of contra. 8026 regan the control ofthe bus. + Lu tyaa wos, Wee “ernain rg love + Wis an output signal, activated by the LOCK prefix iristriction and remains 2 until the completion of the instruction prefixed by LOCK. The 8086 outputs lo the LOCK pin while executing an instruction prefixed by LOCK to prevent other masters from gaining control of the system bus. Q5,.QS, - (Queue Status) ~The processor provides the status of queue on these lines. The qe status can be used by the external device to track the internal status of the o: the 4046, The QS, and QS, are valid during the clock period following 2: operation. The output on QS, and QS, can be interpreted as shown in Tab! TABI Queue operation No operation First byte of an opcode from queue Empty the queue Subsequent byte from queue 2.2 BASIC CONFIGURATIONS The basic configurations of the 8086 micro, and maximum mode systems, The mode is decided system, the pin MN/MX is permanently tied high, is permanently low. Processor-based system are minimunt| by the signal MN/MX pin. In minis In maximum mode system, the pin 2.2.1 MINIMUM MODE 8086 MICROPROCESSOR SvsTeM 2.2.1 MINIMUM S086 MICROPROCESSOR SYSTEM Jn minimum mode, the 8086 processor itself is no need for an external bus controller. The 8086 and address/status pins. In a system, multiplexing is lines has to be demultiplexed by using external latc! signal ALE supplied by the processor. In an 8086-1 generates all bus control signals and s Processor has multiplexed ad: not allowed and so the multiplexed! hes and the latches are enabled based system, the data bus should be pr with data transceivers to drive the data on the bus, The signal DEN is used as enable an DT/R is used as direction control for data transceivers.2.23 e the corresponding status bits from the 8086 “processor Sor rectly connected to the CLK input of the 8288 in order peynshronize the activity of the bus controller with that of the processor. The signal output oa ALE, DTR and DEN are similar to that of 8086 minimum mode signals for various bus gyeles in order to enable the address latch and data transceivers. The bus controller issues the appropiate intr acknow edge signal through the INTA pin when the status signals are all zer0 (ie. whenSs= 5: ). a, era ] iner The [ORCand TOWCean be used as normal 10 read and write control signals. respectively: The AIOWCwill provide xtended 10 ite time, ‘which can be used for writing 10 de ment Risher write time, The MINTCcan be used as normal memory read and write control signals, respectively. will provide extended memory write ume, W hich can be used ee or writing memory devices requiring higher write time. The AEN, IOB and CEN are provided to configure the bus controller either for the AEN and [OB are tied to the eniprocessor oF the multiprocessor system. Ina uniprocessor system, Al ground (OV) and CEN is tied to V.(45 V)- Ina multiprocessor system, the AEN cam be asserted tor ‘high (by a bus arbiter such as INTEL 8289) to Tnable disable the command outputs of 8288. Fora multiprocessor system, [OB is ticd 10 Vc(5 V). The signal output 8 MCE/PDEN depends tied to IOB. In a uniprocessor mode, 1OB is ca the mode, which is determined by the signal applied 072 ended and so the output of MCE/PDEN will be high and itis used to control the cascaded £2596 (cascaded interrupt controllers). In multiprocessor mode, IB is tied to Ve an this mode, the MCE/PDEN is asserted low during the IO read/write operati used to enable 1O bus data transceivers. | Note: In multiprocessor mode, when an 10! transfer is made, PDEN is active and DEN is: inactive. is active and PDEN is inactive. | For a memory transfer, DEN. 75 10 PROGRAMMING 0 devices in a microprocessoi dara transfer schemes are employed. The data-transfer schemes berween the processor and peripheral devices. Ina typical microcomputer data transfer takes place between any two devices: microprocessor snd memory. microprocessor and IO devices, memory and IO devices. For effective data transfer between these devices, the timing parameters of the devices should be matched. But most of the devices have incompatible timings. For example, an 10 device may be slower than the processor due to which it cannot send data to the processor at the expected time. memories are available with compatible timings. Moreover, slow onal hardware to introduce wait states in machine cycles. ften faces difficulties while interfacing 10 devices and r-based system, various types of For programming the I refer to the method of data transfer The semiconductor memories can be interfaced using additi The microprocessor system designer o|Sécupmesses TegEne meme ‘lite fimee or int st) hie te Gee ose mer tp cmoupmcssn Siewml demtamsie schemes Gere bee develirmed op solve the imrs, Paiions with 10 deress Ge Gepmamnic ethene Sve te bay chhotied in dhe ilowine 1. FogommetD 2 ferries 2 Grom Weary domes (i) Fig. 246200 coe terse steces ny, is progemmed 10. Bite Redes Giles mets of ds mci sees Figce 214 shows nes of 10 trader uchemes in 2 miccocomces, - 7 2.5.1 PROGRAMMED 10 DATA-TRANSPER SCHEME In programmed 10 dete trstix, a memory resi : Sor a trecotes to or fora one of te processor regime OS Progpecamed 10 daratrecsfer a 8 to be transferred. In these schemes, escally one-byis oy crepe Sea ema of fae i DAC, Hex-keyboord. 7-50 The progpemimed data-transter scheme cen be fumber clase ified into the following two} 1, Synchronous Cata-trentfer scheme. 2. Asynchronses datetrensier scheme,\ chapter 2 BORG System Bus Structure 2.25 ‘A TRANSFER SCHEME, [AU May’15, 2 marks] ‘The synchronous data-transfer scheme is the simplest of all data-transfer schemes. In this scheme, the processor oes not check the readiness of the device. The IO device or peripheral should have matched timing parameters, Whenever data is to be obtained from the device or transferred to the device, the user program can issue a suitable instruction for the device, At the end of the execution of this instruction, the transfer would have been completed. SYNCHRONOUS: DA’ The synchronous data transfer scheme can also be implemented with small delay (if the delay is tolerable) after the request has been made, The sequence of operations for synchronous data-transfer scheme is shown in Fig, 2.15, The mode-0 input/output in 8255 is an example of synchronous data transfer, Request Device Request Deviee to to Get Ready Get Ready Perform Any Other “Task Until the Device is Ready Wait (Execute a Delay} Routine) or Perform “Another Task Check Whether the Device is Ready —t Execute Inpul/Output Instruction ar Fig, 2.15 : Synchronous data- transfer scheme, Fig 2.4 +: Asynchronous data-transfer scheme. ASYNCHRONOUS DATA TRANSFER SCHEME The asynchronous data-transfer scheme is employed when the speeds of the processor and 10 device do not match. In this scheme, the processor sends a request to the device for read/write operation, Then the processor keeps on polling the status of the device. Once the device is ready, the processor executes a data-transfer instruction to complete the process. To implement this scheme, the device should provide a signal which may be tested by the processor to ascertain Whether it is ready or not, ‘The sequence of operations for asynchronous data transfer is shown in Fig. 2.16. The mode-1 and mode-2 handshake data transfer of 8255 without interrupt is an example of asynchronous data transfer, 2.8.2 INTERRU! RIVEN 10 DATA-TRANSFER SCHEME The interrupt-driven data transfer scheme is the best method of data transfer for efficient Utilization of processor time. In this scheme, the processor first initiates the 10 device foroe Microprocessors and Microconta 2 a data transfer, After initiating the device, the processor will continue the execution of Instructions in the program, Also at the end of every instruction, the processor will check for valid inter signal. If there is no interrupt then the processor will continue the execution. Note: The user/system designer need not write any subroutine/procedure to check jor al interrupt. The logic of checking interrupt signals while executing each instruction i incorporated in the processor itself by the manufacturer of the processor. j When the 10 device is ready, it will interrupt the processor. On receiving an interrupt, signal, the processor will complete the current instruction execution and save the processor status in stack. Then the processor calls an Interrupt Service Subroutine (ISS) to service the interrupting device. At the end of ISS, the Processor status is retrieved from the stack and the processor starts executing its main Program. The sequence of operations for an interrupt-driven data-transfer scheme is shown in Fig. 2.17. (For detailed discussion on interrupt driven-data transfer scheme, please refer Chapter 1.) Request Deviee to Get Ready Save Processor Status Fetch Next Instruction] Execute Data Transfer and Execute Instructions L Restore Processor Status Enable Interrupt System] Call ISS Associated With This Interrupt Retum to Main Program) (a): Main program —_(b) : ISS execution execution sequence. sequence. Fig. 2.17 : Interrupt-driven data-transfer schem 2.5.3 DIRECT MEMORY ACCESS DATA-TRANSFER SCHEME 2.5.5 DIRECT MEMORY ACCESS DATA.TRANSFER SCHEME [AU May’15, 6 marks] In Direct Memory Access (DMA) data transfer, the processor is forced to HOLD state (high impedance state) by an IO device until the data transfer between the device and the memo! is complete. The processor does not execute any instructions during the HOLD period. The DMA data transfer is used for a large block of data transfer between the 10 devi and memory. Typical examples of devices using DMA are CRT controller, floppy disk, hard ds high-speed line printer, ete, The different types of DMA data transfer schemes are 1, Cycle stealing DMA or Single transfer mode DMA. 2. Block or Burst mode DMA. 3. Demand transfer mode DMA, Normally, the data transfer from memory to 10 device or 10 device to memory can be achel only through the microprocessor, When data has to be transferred from memory to 10 device. the processor sends address and control signals to memory to read the data from memory: the processor sends address and control signals to the 1 device to write data to the 10 devihupeer2- 8086 System Bus Structure 2.27 Similarly, when the data has to be transferred from the IO device to memory, first the processor sends the address and control signals to the IO device to read data from the 10 device. Then the processor sends address and control signals to the memory device to write data to memory. In the data-transfer method described above, the data cannot be directly transferred between the memory and IO device, even though they are connected to a common bus. The above process is inevitable because the processor cannot simultaneously select two devices. Hence, a scheme called Direct Memory Access (DMA) has been developed in which the IO device can gecess the memory directly for data transfer. The DMA data transfer will be useful to transfer iarge amounts of data between the memory and 10 device in a short time. For direct data transfer between the IO device and memory, a dedicated hardware device called Direct Memory Access controller (DMA controller) is used. ADMA controller temporarily data bus and control bus from the microprocessor, and transfers borrows the address bus, f memory locations or vice versa. Some the data bytes directly from the IO ports to a series of DMA controllers can also perform memory-to-memory transfer. licrocomputer System with a DMA Controller ‘The simplified diagram of a microcomputer system with a DMA controller is shown in Fig. 2.18. In the system shown in Fig. 2.18, the DMA controller has one channel, which serves for one IO device. In an actual DMA controller, we may have more than one channel and each channel may service an IO device independently. Each channel contains an address register, a control register and a count register. For simplicity, let us consider @ one-channel DMA controller. ‘The DMA controller can work as a slave or as a master. In the slave mode, the microprocessor loads the address register with the starting address of the memory, loads the count register with the number of bytes to be transferred and loads the control register with the control information. For performing DMA operation, the processor has to initialize or program the IO device snd DMA controller, Consider an example of transferring a bulk data froma floppy to the memory byDMA. In this case, the processor initializes both the DMA controller and floppy controller, so that the DMA controller is informed about the address, type of DMA and number of bytes to be transferred, and the floppy controller is informed to go for a DMA. eds a DMA transfer, it sends a DMA request signal (DREQ) to the .ceives a DMA request, it sends a HOLD request to the processor. At the end of the current instruction execution, the processor relieves the bus by assening all its data, address and control pins to high impedanee state. Then the processor sends an acknowledge (HLDA) signal to the DMA controller. ‘ves an acknowledge signal, it takes control of the system bus and er sends a DMA acknowledge signal (DACK) to the device to get ready for DMA transfer. When the IO device ni DMA controller, When the DMA controller re When the controller recei begins to work as a master. The DMA controll lO device, The DACK signal will inform thea Microprocessors and Microcontrg le 2.2 les System Bus Latches and Buffers Microprocessor 8086 cru Bus Controller 8237 or 8257 ‘System Bus Fig. 2.18 : Block diagram of a microcomputer ‘system with a DMA controller. Enable (Such as Floppy Disk [external or Disk Controller) Device For a read operation, the DMA controller outputs the memory address on the address and asserts MEMR and JOW signals. The DMA read refers to reading memory locations. for a read operation, the memory outputs the data on the data bus and this data will be written the IO port. For a write operation, the DMA controller outputs the memory address on the addi and asserts MEMW and IOR signals. The DMA write refers to writing data to the memory. for a write operation, the IO device outputs the data on the data bus and this data will be into memory. When the data transfer is complete, the DMA controller unasserts its HOLD signal to the processor and the processor takes control of the system bus. The DMA transfer may be performed to transfer a byte at a time or in blocks. In cycle: DMA or single-transfer mode, the DMA controller will perform one-byte transfer in instruction cycles. In burst mode or block transfer mode, the DMA controller will transfer of data. 2.6 INTRODUCTION TO MULTIPROGRAMMING (Ina microprocessor system, the various tasks ofa program will be executed one by: sequence of occurrence in the program and this method of execution is called uniprogi When the various tasks of program are executed concurrently or simultaneously then th of execution is called multiprogramming:)Chaprer 2- $086 System Bus Structure 3 In the 8086 microprocessor based system, for uniprogram execution, the program codes for various tasks are written sequencially in the order of execution as a single program and stored in asingle memory block/segment. But for multiprogram execution, the program codes for various tasks are written separately as modules and stored in separate memory blocks/segments, and a main program can call and execute these modules in a time-sliced fashionThe main program can be designed to switch from one task to the other in a predefined priority in predefined time slots depending on the importance of the tasK)In this method, all the program task will be executed Sq simultaneously in a time-sliced fashion, (in the 8086 microprocessor-based system, the memory is organized in segments, and this segmeptation of memory helps the program execution to switch from one task to the oth Consider a program with two independent tasks running in multiprogram environment. The program codes for two tasks will be stored in two different memory blocks/segments. In order to run the first task, the segment registers are loaded with the base and offset address associated with the memory segment in which the first task is stored. Then after a predefined time (time slice for a task) or when an interrupt of the second task is initiated the content of segment registers and other , intermediate results of the first task can be pushed to the stack and the segment registers are filled ” with base and offset address of the second ta Then after a predefined time or interrupt of the first task is initiated, the content of segment registers and other intermediate results of the second task can be pushed to the stack and the segment TS) tet reistesare filled with base and offset address of the firs task. In this manner, the program control switch between two tasks until the program execution is completed. Similarly, a program with syust?- multiple tasks can be executed in a multiprogramming environment’) (the advantages of multiprogramming are as follows: 1. Processor idle time can be minimized. 2. Efficient memory management. 3. Execution of real-time events is possible. 4, Improves system performance by overlapping IO operations and CPU operations. 5. Allows multiprocessing. 6. Allows multiusers at a tine.) - 2.7 SYSTEM BUS STRUCTURE a, ‘A microprocessor is a semiconductor device (or Integrated Circuit) manufactured by the i ?, VLSI (Very Large Scale Integration) techniquejit includes the ALU, register arrays and control “gf Sitcuit ona single chip, To performa function or useful task, we have to form a system by using the . microprocessor as a CPU (Central Processing Unit) and interfacing memory, the input and output ir ocomputer or, devices to it. A system designed using a microprocessor as its CPU is called a m single-board microcomputer. A microprocessor-based system consists-of a microprocessor as the CPU, semiconductor memories like EPROM and RAM, an input device, an output device and ibterfacing devices. The memories, input device, output device and interfacing devices are called J d Peripherals),Microprocesors an Mieco, | memory is used to store permanent programs and data. The RAM. Memory i, The input device is used to enter the program, thy s used Tor examining the results, Since the speedo of ‘stem, th CPU Dus - MD anal wo operate iets we i = Master cru Interface System Bus 10 Interface AD - Address/Data Bus EPROM A -Address Bus. [noe] flourrn ey ome s a Device | | Device Ss Fig. 2.19 : 8086 Microprocessor-based system bus structure. AU May’15, 2 marks) 10 devices does not match with the speed of the microprocessor, an interface device is provided between the system bus and the 10 devices. Generally, IO devices are slow devices.A set of conductors used for communicating information between the components of a system is called bus A bus is a group of conducting lines that carries data, address and control signals. Buses canbe classified into data bus, address bus and control bus, The group of conducting lines that carries dais called data bus.The group of conducting lines that carries address is called address bus.The r0 of conducting lines that carries control signals is called control bus.The group of conducting li that are directly connected to the microprocessor is called CPU bus, Ina CPU bus, the signals multiplexed, i.c., more than one signal is passed through'the same line but at different timings. group of conducting lines that carries data, address and control signals in a microcomputer system called system bus. Multiplexing is not allowed in a system bus. The CPU bus has multiplexed lin i.e., the same line i used to carry different signals. The CPU interface is provided to demultil the multiplexed lines, to generate chip select signals and additional control signals. The st bus has separate lines for each signal, The block diagram of an 8086 microprocessor-based system bus structure is show" Fig. 2.19. In this system, the microprocessor is the master and all other peripherals are slaves master controls all the peripherals and initiates all the operations. (AIL the slaves in the system are connected to the same system bus. At any time, ins communication takes place betwcen the masterand one of the slaves Allthe staves state and hence normally remain ina high impedance state. The processor selects a slave by sending address, When a slave is selected, I'comes to the normal logic and communicates with the proceCnagper Wit press toes arcrone 2 2-1, WORKING OF 2056 MICROPROCESSOR BASED SYSTEM The wotk dune by the processor can be classified into the following three groups N “SS 1, Work tea ieterat to the srocesuen, ~ 1. Wot tana wrtarvel to the prveagser, Ny 1. Gpatations lariat by the saves 7 peripherals, ~ te mons done internal to the processor are addition, subtraction, logical operations oy data tranafer within registers, etc, The works, done external to the processor are reading/writin, the memory and reading/wsiting, the JO devices on the peripherals. Ifthe peripheral requires th scention of the snaster then it an interrupt the master and initiate an operation. | ~ 7 the microprocessor is the snaster which contsols all the activities of the system. To perform: ‘or. a specific job of task, the microprocessor has to execute a program stored in the py The re program consists of a set of instructions stored in consecutive memory locations. In order 16 execute |, the program, the microprocessor issues address and control signals to fetch the instruction and. data cL. trom merneny one by one. After fetching, each instruction, the processor decodes the instruction ‘|im and carrion out the task specified by the instruction. ) 4 297% CONCEPT OF MULTIPLEXING IN A MICROPROCESSOR BUS __ (Bfultiplexing is transferring different information at different well-defined times through the Ws anne lines. A group of such lines is called a multiplexed bus2The result of multiplexing is that_ « fewer pinis are required for microprocessors to communicate with the outside world. ost microprocessors cannot provide simultaneously similar etc.). Hence multiplexing of one or more of these buses is performed, Most often data lines are multiplexed with some or all address lines to form an sddress/data bus (€.4., in #086, the Jower 16-address lines are multiplexed with data lines). The - atus signals emitted by the microprocessor are sometimes multiplexed either with the data lines Cee eIn INTE AO4A) or with some of the address lines (as done in INTEL 8086). Whenever multiplexing, is used, hardware to demultiplex those lines to i = Due to pin-number limitations, lines (such as address, data, status signals, the CPU interface of the system must include the necessary produce separate address, data and control buses required {onthe system, Demultiplexing, of a multiplexed bus can be handled either at the CPU interface or Jucally at appropriate points in the system. Besides a slower system operation, a multiplexed bus alup results in additional interface hardware requirements. 1G. OF ADDRESS/DATA IN AN 8086 SYSTEM BUS ‘ddress/data lines (of the processor), the processor provides a :nable), The ALE is asserted high and then low by the processor same time, the address is given out through AD,-AD,, Ey Siprahcalled ALA (Address Latch atthe heyinning of every bus cycle, At the ‘Demulliplexing of address/data lines and address/status lines using in Fig, 2.20. 27/8 DEMULTIPLEX! tn order to demultiplex the " 4 Fines and A, fsa lines) fy, Pit Detatch 741.8373 is shown Ad she AL Jvisconnected othe Enable Pin (EN) of the extemal 8-bit latches. When ALE is asserted wed weMicroprocessors and Microconty high and then low, the addresses are latched into the output lines of the latch. It holds the ‘Addy until the nest bus cycle. After latching the address, the AD,-AD,, lines are free for data transfer, A, status lines are free for carrying status information, The first T-state of every bus yee} used foraddress latching in 8086 and the remaining T states are used for reading or writing operat D,-Dy Lanits of AD--AD, 7ALS373 2Nos. of (bit 748245 D-Latch) Bidirectional] 8086 Buffer) ALE EN BR AwcAg/Status sl 74L8373 (bit D-Latch) EN Fig. 2.20 : Demultiplexing of address and data lines in an 8086-based system bus. The data bus is provided with a bidirectional but in the bus. The 8086 provides two control signals, DTIR is used to decide the direction of data flo ffer in order to drive the data to a longer distat DT/R and DEN, for controlling the data buffe w and DEN is used to enable the data buffer. 2.8 MULTIPROCESSOR CONFIGURATIONS 7 4 muttiprocessor system will have two or more processors that can execute instructions Perform operations) simultaneously. In multiprocessor systems, be special-purpose processors which are specifically designed to can be other general-purpose processors. For example, a multip using an 8086 microprocessor and an 8087 coprocessor in ord arithmetic capability to the 8086-based system) the extra or added processors! perform certain tasks efficient, rocessor system can be formet ler to impart efficient floating-P ‘The multiprocessor systems offers the following advantages over single-processot és 1. Several low-cost processors may bo combined to fit the needs of an application while =¥¢ ‘he expense of the unneeded capailitias ofa centralized system, 2. The multiprocessor system provides room for expansion because it is easy to ald processors as the need arises. 3. Ina multiprocessor system, implementation of modular processing of tasks can be achieved: 4. When a failure occurs, itis easier to replace only the faulty patiprocessor.hayes) NING Nhe Hy Stata — porn ho We mnttoy tanto - Paar ie Seas rc an sr bela erp a. WNL, Wot Thai nie procossar Will hate the system memory ag Wo afev ove through a vounmnon ayaten fs ane so ey Hoyle mst be feted fa ensure that only cwvo piven The one te the ay ston vat any’ ane tne, Also there shoud be an unambiguous Ary OF AHTOH PEC ONROT COMMITTIOATION aa Thal ote pracensor ean alispateh a task or return a result jr another piuvesrar unaMbiqnonsly, (Mio movin mote KOKO mieraprovessir has foatres fhe designing a multipracessor jyvtein. Nu typex of nmaltipmncessor contiqurations ean be farmed using NOK processor: closely oonptedd (at tightly: coupled) contxuration and loosely eoupted configuintion), 28,1 COPROCKSHOR {ivy eopwwersor has been ypevtally: desuned! 0 take cate cuprocessor is also called math coprocessor oF to work in parallel with a microprocessor, x86 family of microprocessors. sor, the 80287 L has started of mathematical calculations involving tnteger and Moating-point data, The Numerte Data Prncersar (NDP), A coprocessor indlesigned The INTHE has developed SOS87 series of eaprocessons fr the ANEBE, has loveloped the 8087 coprocessor for the 8086 proce: SO4NHDX onwards, INTEL Dbricating micropracessors with Vor examples cogeessor fr the RO28O processor, and so on, Prom copnocessor With the mvleropnacessor and started fal integrating the anonschip eopmacessot, S01 +> sou oN "sow "sa AQT UNt OVINDEANT OWULYANIVANT WN shyly ar “ayy ‘sour SOA gy Saks 8 i } Lease |NN SSNS haute, poe de fived ° upls Cchapect 2- 8086 System Bus Structure fut a The internal interrupts of 80186 includes INTEL predefined interrupts, software interrupts and interrupts from internal timers and DMA channels. ‘The IN predefined interrupts of s0186 includes the five INTEL predefined interrupts of 8086 (Divide error, Single step, NMI, Rreak-point-and Interrupt on overflow) and in addition has three predefined interrupts: Atray BOUNDS Interrupt, Unused opcode interrupt and ESC opegde nte ypt. 4 The array BOUNDS interrupt oe Gui ‘ota inl regi itth Boundary ot a inl registers outside the values set up in the memory. The unused opcode interrupt occurs whenever the Processor executes any undefined opcode. The ESC opeode interrupt occurs if ESC opcodes are executed Each interrupt of 80186 has been allotted a type number and a vector addfess like that of 8086. The interrupt vector table of 80186 occupies the first Ik memory space like that of 8086, The type number, vector address and priority of the internal and extemal interrupts of 80186 arc listed in Table 2.10. oo ou ‘ . ‘ rk Vv The chip select unit generates the chip select{ighalyfor . unit provides 6 memory chip select outputs, namelyUCS, LCS, MCSo, MCS, nd MCS), The UCSis used to select the upper/top memory space of size I kiB to 256K1 ending with address FFFFF,,. The LCSis used to select the lower/bottom memory space of size 1 kB to 256 KD starting with address 00000,,, The MCSo to MCSscan be used to select four address spaces of size 8 kB to Y. yond a Ws SO we MATEY “ ~ $12 kB within 1MB address space, excluding the address space defined by UCS and LCS, The chip select unit provides seven peripheral chip select signals. Each peripheral chip select signal addresses a 128-byte block of 1O address space. The programmable IO address space starts at a base IO (or memory) address programmed by the user. The seven consecutive blocks of 128 bytes starting from this base address will be the IO address space addressed by the seven peripheral chip select signals respectively. The chip select signals are active for all memory and 10 cycles in their programmed arcas, whether they are generated by the BIU or the DMA unit. The 80186 is completely object-code compatible with 8086, The instruction set of 80186 « Consists of the instructions of 8086 and of 10 new instructions, which are as follows: (1. ENTER - Enter a procedure 2. LEAVE = Leave a procedure 3. BOUND = — Check if'an array index ina register is in range of array 4. INS - Input string byte or string word 5. OUTS = Output string byte or string word 6. PUSHA - Push all registers to stack 7. POPA = Pop all registers from stack 8. PUSH imm = Push immediate (imm) data to stack 9. IMUL reg,sou,imm - Multiply the immediate (imm) data and source (sou) data, and store the result in register(reg) 10, SHIFT desimm Shift the destination (des) register/memory contents specified immediate (im) number of times“. “= tdi Microprocessors and Microcontrolter, TABLE 2.10: TYPE NUMBER AND PRIORITIES OF INTERRUPTS OF 80186 Type | Vector address Priority number level 0 Divide error 00000 - 00003 Single step 1 00004 - 00007 NMI 00008 - 0000B Broak-point 0000C - 0000F Interrupt on overflow 00010 - 00013 Array BOUNDS, 00014 - 00017 Unused opcode 00018 - 00018 ESC opcode 0001C - 0001F Timer-0 Timor-1 ‘Timer-2 Reserved 00020 - 00023 00048 - 0004B 0004 - O004F 00024 - 00027 00028 - 00028 0002c - oo02F 00030 - 00033 00034 - 00037 00038 - 00038 0003C - 0003F 00040 - 00043 [Note : Interrupt priority level 1 is the highest andl 9s the lowest. Some interrupts have the same priority. 2.9.2 INTEL 80286 MICROPROCESSOR vw Ccuctng2d 1983 and improved version o¢ £0(gt The INTEL 80286 is a I &-bit microprocessor with on-chip memory protection capabilities. The 80286 is an integration of 8086 and the memory management unit on a single chip. Itis Primarily designed for multiuser/multitasking systems. The 80826 is used as a CPU in IBM's Personal computers PC/AT and its clones. Che 80826 has two operating modes: real address mode and protected virtual address mode) Inthe real address mode, the 80286 can address upto 1 MB (Megabyte) of physical memory address space like 8086. In protected virtual address mode, it can address up to 16 MB of physical memory address space and 1GB (Gigabyte) of virtual memory address space) Ghe instruction sct of 80286 includes the instructions of 8086 and 80186} and has some extra instructions to support the operating system and memory management. In the real address mode, the{80286 is object-code compatible with 8086) In the Protected virtual address mode /t is sourt code compatible with 8086and the software May re to i quire some modifications to incorporate te Virtual address features. fhe performance of 80286 is five times faster than that of astandard 8086) Cthe 80286 is available with maximum internal clock frequency ratings of 4, 6 and 8 Miz) Operating fugues Nor & tere SiigChapter 2- 8086 System Bus Structure 2. I5 41312, 1D 918 76s ee 10 Fig. 2.28 : Flag register of 80286. Note: The 80286 has a 13-bit index for descriptor and allows two descriptor tables (Global Descriptor Table [GDT] and Local Deseriptor Table [LDT]). Therefore, the processor allows, 2'2@ 2 = J6 kdescriptors. Each descriptor can define a segment of IKB size to 64 KB. Hence, total virtual space is 16k * 64 KB = 2! x 2! byte: "9 x 2" bytes = 1024 * IMB = 1GB. 2.9.3 INTEL 80386 MICROPROCESSOR eduled 2. 17ee Tr The 80386 is a 32-bit microprocessor and it is an improved version of 80286 with software compatibility with 8086, 80186 and 80286/The major improvements in 80386 over 80286 are the following: 1, The processor registers and ALU are 32-bit wide and the instruction set is extended to support 32-bit addresses and data. The main memory and the data path to memory can be 32- bit wide, so instructions and data ‘ead/write operations will be two times faster. The maximum size of physical memory is extended from 16 MB (2* bytes) to 46B (2 bytes). ‘Since 80386 runs at higher clock frequency, faster execution speed is obtzined and most instructions take fewer clock cycles to execute. The on-chip memory management supports paging. (-The 80386 is available in two versions: 80386DX and 80386SXThe internal architecture of both the versions of 80386 are same, but they differ only in external address and data bus)The “346DX has a separate external 32-bit data bus and address bus. The 80386SX has an external 16-4 address bus. The 80386DX is called the full version of 80386 and 80386SX is called the reduced | bus version of $0386. The 80386SX was developed after the 80386DX for applications that did not require an external 32-bit bus and at the same time had the advantage of x ae internal 32-bit computation.———oa_— 086 System Bus Structure - a BL EBX cL ECX DL EDX ESI EDI General Purpose Registers EBP ESP cs ss Ds ES FS Segment Registers Gs a 16 15 0 [1 31 1615 oi FLAGS JEFLAG Fig. 2.30 : Base architecture registers of an 80386. 2.9.4 THE INTEL 80486 MICROPROCESSOR The INTEL 80486 is a 32-bit processor with higher performance than 80386, It is an integration of the improved 80386 processor, 80387 coprocessor and 8 kB RAM memory (called cache memory) on a single chip. The INTEL 80486 family of processors includes 80486SX, £0486DX, SX2, DX2, Write-back enhanced DX2, DX4 and Write-back enhanced DX4 processors. The base architecture for the entire family of the 80486 processor is same except for the minor differences. The 80486SX and SX2 processors do not have an internal coprocessor unit. The DX2 sad DX¢ are double clock versions of 80486, Also, the DX¢4 processor has a 16 KB internal cache ‘memory. The concepts discussed in this section refer to the 80486DX processor. The 80486 has 1.2 million transistors and works three times faster than the combined operation of 80386 and 80387. The 80486 has five stages of instruction pipeline execution and allows simultaneous execution of two consecutive instructions if resources used by one instruction tenot used by the other instruction. Due to extensive pipelining, the execution time of most of the "istructions is one clock cycle and the average execution time of an instruction is 1.6 clock cycles.Microprocessors and Microcontrale p wn % The base architecture, memory address capability, memory management unit and operating modes are identical to that of 80386, The 80486 processor is software compatible with 80386, Ty instruction set of 80486 includes the instructions of 80386 and a few new instructions to suppor the new applications and increase performance. The 80486DX is available with maximum clock speed ratings of 33, 66 and 100 MHz ARCHITECTURE OF 80486 MICROPROCESSOR The INTEL 80486 is a 32-bit processor with on-chip memory management, floating poist and cache memory units. The architecture (or functional block diagram) of the 80486 processcr is shown in Fig. 2.31. The various functional units of the 80486 processor are as following: Data-processing unit consisting of ALU, barrel shifter and an array of registers Bus interface unit consisting of drivers and various control logic unit 32-byte instruction prefetch queue Instruction decode unit Floating-point unit Memory-management unit consisting of segmentation and paging units 7. 8kB cache memory unit The data processing unit consists of a 32-bit ALU, a 64-bit barrel shifter and eight general-purpose registers. The functions of the ALU and barrel shifter are same as that of the processor. The general purpose registers of 80486 are also same as that of the 80386 proces" ‘The general-purpose registers are EAX, EBX, ECX, EDX, EBP, EDI, ESI and ESP. Part of tie 32-bit registers can be accessed as 16 or 8-bit registers like that of 80386. The Instruction Pois* and Flag register of 80486 are identical to that of the 80386 processor. Pe Pen a tit : ee se ‘The bus interface unit consists of drivers for address and data bus and various control “te which j 1 units, which includes bus cycle control, burst bus cycle control, bus size control and cache com logic units. The contro! signals necessary for memory, IO and interrupt bus cycles are gen° by this unit. It also takes care of managing the control signals for cache memory control- The bus interface unit also has a parity generation and control unit. The parity unite a parity bit (for even parity) for each byte of data during write operation, and output 00 DP,” fines. These parity bits can be stored in the memory along with data when parity is empl0% the system. During a read operation, the parity unit checks for even parity and if it finds 29% then it generates a parity check error signal, etch The 80486 processor has five-stage instruction pipeline execution, which includes pe a first decode, second decode, execute and write back. Due to five-stage pipeline, several ins will be in the pipeline at a time, Hence, the 80486 processor can execute two inst™™ i i si simultaneously if exe inshaci Cee ously if execution of one instruction does not depend on the other instructio®: sf decoding jump instructions, the proce: i 1 ‘Ssor automatically prefetches the instructions from destination, which improves the processor Performance greatly. ance greatly. 063 io!called status register, control register and tag v et and 10 numbers of registers called instruction pointer and data pointer. The floating-point unit sy data poit Ports 39,5 8 Aoaing point da ps, 1632.64 is (sine) integer data pesand Oi packegnes Init ang The Memory Management Unit (MMU) consists of a segmentation w, The MMU of 80486 is almost identical to that of 80386. Segmentation allons Manage 2S the logical address space. The paging mechanism operates beneath segmentstos Tk is optional and ean be disabled by system software, Memory is orgenized igge1* PS variable length segments, each up to 4 GB in size. Each segment can be divided into omen Re 4KB pages. The segment registers and descriptors of 80486 are identical to that of $0: The cache memory contains static RAMs which are very RAMS. The cache memory address is a small part of total memory adress. The cache memory can be used to store both code and data. The cache memory, a5 a four-way set associative cache with LRU (Least Recenlly Used) replacement ‘The SKB cache is divided into 128 sets, Each set has 64 bytes (8 kB = 2" bytes = 128 64 bytes) and organized as 4 lines with 16 bytes per line (4«16 bytes = 64 bytes) fie organization is a 4-way set-associative cache. 2.9.5 PENTIUM PROCESSOR (The Pentium processor is an advanced A2chit superscalar processor with 64-bit and 3: address bus to address up to.4 GB of physical memory space. It was released in 1988 and consists of 3.1 million transistors. The Pentium employs two genera-purps. pipelines, branch prediction, highly pipelined floating-point unit and separate code and da toachieve the highest performance level while preserving the binary code compatibility wit ‘Processors. The Pentium processor can execute two integer instructions simultaneot is available with maximum clock speed ratings of 60-233, MHZ) ma B86, fast as compared tthe space which bol ace which the proces ces ith Soxi¢ ThePesix ‘The features of Pentium processor are 1. Supersealar architecture 11. Dynamic branch prediction 2. Pipelined floating-point unit 12. Improved instruction execution time 3. Separate code and data caches 13. 64-bit data bus 4. Bus cycle pipelining 5. Internal party checking 6. Execution tracing 7. IEEE 1149.1 boundary scan 8. Virtual mode extensions 9. 14, Address parity 15. Functional redundancy checking and lock-step operat 16. Performance monitoring 17. System management mode 18. Dual processing support . Advanced power management feature 19. Fractional bus operation) * 0. On-chip local APIC (Advanced Programmable Interrupt Controller) deviceThe Pentium pro is a 32-bit processor with a 64 to address up to 64 GB of physical memory space. It was released in 1995 ons 5 million transistors. It isa 387-pin IC and available in PGA (Pin Grig Array) et ‘vailable with maximum intemal clock ratings of 150/166/180/200 Mity, Re The features of pentium pro processor are the follow! it data bus and 36-bit ing: 1, Three-way superscalar architecture Five parallel execution units and 12:stage super pipeline Uuakcavity PGA ceramic packages wth a CPU die anda secondary cache fie " Out-ot-order execution and speculative execution - DIB (Dual Independent Bus) architecture Register renaming Error checking and correcting codes {mroved power management with two extra modes (Stop Grant and Auto HALT modes} {Internal micro-ops similar to RISC-like instructions 1. Transactional 10 bus gees ee een |. Scalable up to four processors = Fault anaysistecovery Integrated level two (secondary) cache of 256 k/512kI1MB 14, Internal thermal protection 18. Automatic selection of power-supply voltage PENTIUM IT ‘Tbe Petia Ti was reicased ia 1997, ard consists of7-5 mllion wansstoteR ee im Pro processor with on-chip MMX (Multi Media Extension). Itis also a 32-i 64-bit data bus and 36-bit address bus to address up to 64 GB of physical memory 7 Its available with maximum intemal clock ratings of 233-450 MHz and in SEC (Sine E° Connector) caridge packaging or as a boxed processor along with fan/heat sink. The features of Pentium IL Processor are as follows: 1 Pentiur with Supports the INTEL architecture with dynamic execution Integrated primary (L1) 16 KB instruction cache ‘and 16 kB write-back data cache 2 4. Integrated 256 kB secondlevel(L2) cache 4, Fully compatible with previous microprocessorsBus Structure 2.59 sage System F_ Soprts MMK eeholgy fsck strand Dep sleep mads provide extremely lw power sipation 4. lew power GTL + processor system bus inter (GTL: Gunning Transceiver Logie) 4. tegrated math co processor (eating point unit compatible with IEEE std 754) a. berated thermal diode for measuring processor temperature the Pentium III was released in 1999 and consists of 9.5 million transistors. The higher gro etiam M1 consists of 28 million transistors. The Pentium III is a 32-bit processor “a6+bit data bus and a 36-bit address bus to address up to 64 GB of physical memory space. tsmalsble with maximum intemal ratings of $00 MHz to 1 GHz. Inte IC form, it is available as 370-pin IC in PGA (Pin Grid Array) package. The zal isan advanced version of Pentium II with improved MMX technology and processor ‘caiumnber. The INTEL has incorporated a processor serial number in Pentium III which supports szcsaxeptof processor identification. Each Pentium III processor has a 96-bit processor number ssasile by software (of various applications) to identify a system. Some of the applications that =yttliz processor serial number are membership authentication, data backup/restore protection, sonable storage data protection, managed access to files, etc. ‘The features of Pentium III processor are as follows: 1. Dynamic execution microarchitecture 2 Optimized for 32-bit applications running on advanced 32-bit operating systems Fully compatible with previous microprocessors Integrated high performance 16 kB instruction and 16 kB data, nonblocking level one cache Integrated 512 kB full speed level two cache allows for low latency on readistore operation 256+it cache data bus provides extremely high throughput on readlstore operation Eight-way cache associativity provides improved cache hit rate on readlstore operations. Error corecting code for system bus data Data prefetch logic Internet streaming SIMD (Single Instruction Multiple Data) Extensions for enhanced Video, Sound and 30 performance System management mode and multiple low-power states 12 Flip Chip Pin Grid Array (FC-PGA2) packaging technology which offers improved handling Protection and socketabilty 13. Intel processor serial numberON Microprocessors and Mig Ont The Pentium 4 processor was released in 2000 and consists of 42 million transis, ble wth aximum intemal clock ratings of 14 ~2.8 GHz, The Pentium 4 processor i : pe Threading) Technology was released inthe year 2002 and consists of $5 milion itis available with maximum intemal clock ratings of 2.4 GHz - 3.3 GHz, Itis avai 478-pin IC in the PGA (Pin Grid Array) package. Sis, lable as, The features of the Pentium 4 processor are as follows: 1. INTEL NetBurst microarchitecture 2. Hyper Threading (HT) technology Hyperpipelined technology which supports advanced dynamic execution and very deep Out fr execution Rapid execution engine-ALUs run at twice the processor core frequency System-bus frequency at 400/533/800 MHz Binary compatible with applications running on previous members of INTEL processors BKB level 1 data cache oe Level 1 execution trace cache stores 12k micro-ops and remaves decoder latency from main een loops 9, 512 kB advanced transfer cache with 8-way associativity and error correcting code 10. 144 streaming SIMD Extensions 2(SSE2) instructions, (SIMD : Single Instruction Multiple Data 11, System management mode and mulitple low power states ‘The features of INTEL NetBurst microarchitecture are hyper-pipelined technology,# rapid execution engine, 400/533/800 MHz system bus, execution trace cache, advanced dynat execution, advanced transfer cache, enhanced floating-point and multimedia unit and streamitt SIMD Extensions 2 (SSE2). ‘The hyper-pipelined technology doubles the pipeline depth in the Pentium 4 proce” with a $12 kB L2 cache, allowing the processor to reach much higher core frequencies. The ropid execution engine allows the two integer ALUs in the processor to run at twice the core fieale™ Which allows many integer instructions to execute in a 1/2 clock tick, : iy _ The Hyper Threading (HT) technology allows a single physical Pentium 4 proees* function as two logical processors, Each logical processor has its own architecture stat" of general-purpose registers and contol reg ra el mance eneral ; isters to provide increased system perfo™ multitasking environments,MicROCONTROLLE 41_ INTRODUCTION TO MICROCONTROLLERS Since the invention of microprocessory, diferent companies have started manutioturing jae an more sophisticated processors with improved foanunes sttel ay ange data bus, lange ratios NA Sophisticated memory management techniques and instetion set, capability of dandling a Wide range of integer and floating-point data, parallel processing of instructions, ete, gates sophisticata processors ate not nevessany fir sina appli axscmonitoring controlling temperaturg, swvitehing ON-OFF fi ations such as controlling a mrllit mafic Tights, ete, In the 1980s, the gaaticturers of microprocessors realized pragrammadte that there is a need tor Low cos compact single-chip pagrammable ICs called microcontrollers stems for small dedicated applications and so started mamutacturing another clase 43.1 BASIC FUNCTIONAL BLOCK DIAGRAM OF A MICROCONT! ¢ The microcontroller is a programmable IC manufactured by VEST (Very Lange Seale {exgfration) technique, and c of performing arithmetic and logical operations, The various fextonal blocks of a typical microcontroller are shown in Fig, 4.1, Sorrvnnsoo==------$----- i RAM EPROM Paral 3 ' Memary Memony in ! \ ' 1 1 ' \ \ Tnstruction | [Program t ims ff EH || rogram t Cont) a ing |} Counter ! ' Unit ’ ne Fig Raaer \ Fig. 4.1 : Functional block diagram of a microcontroller. The basic functional blocks of a microcontroller are the ALU, Flag register, Register i: Program Counter (PC), Instruction decoding Unit, Timing and control unit, RAM memory, Ey ROM/EEPROM memory, Parallel 10 port, Ser “microcontrollers may not have all the bloc! “own in Fig. 4.1, may not be available in certa inl 10 port, Programmable timer, ADC and DAC. hown in Fig, 4.1, Some of the functional blocks microcontrollers, The ALU is the computational unit of the microcontroller Ww! -8l operations. The various conditions of the result are stored ch performs arithmetic and status bits called flags in the “e register. The register array and intemal RAM memory are used as a temporary storage device “Tsoring temporary data during execution of a program. =<ADC Paul c\ineck ACCUM DAC > cig ob civack aco 42 Microprocessors and Microcontroller “The program codes and permanent data are stored in EPROM/EEPROM. In microcontroler based systems, an external memory is provided only when the internal memory is not sufficien and so in most of the microcontroller-based systems, the program and data are stored in the interna memory of the microcontroller itself. The program counter generates the address of the instructions to be fetched from the memon, and sends it through the intemal bus to the memory. (If the instruction to be fetched is stored ir the extemal memory then the address is sent through IO ports to the external memory. Becausy the microcontrollers communicate with the external world only through 10 ports.) The memon will send the instruction codes, which are decoded by the instruction decoding unit and send th. information to the timing and control unit. The timing and control unit will generate the necessary control signals for internal and extemal operation of the microcontroller. The parallel and serial IO ports are used for interfacing IO devices like switches, keyboard LCD/LED, ADC, DAC, etc., and also for any other input/output operations. Microcontrollers do not have a dedicated external address and data bus. Therefore, for interfacing any additional peripheral devices, the external address and data buses are formed only by using port lines. Microcontrollers with intemal ADC can directly accept analog signals for; processing. Likewise, microcontrollers with intemal DAC can directly generate analog signals for ‘controlling analog devices. ‘A programmable timer can be used for time-based operations and it can also be used as a counter. 4.2/ INTRODUCTION TO THE INTEL 8051 MICROCONTROLLER The 8051 family of microcontrollers was originally released by INTEL and later on licensed to many semiconductor companies like PHILIPS, ATMEL, SIEMENS, HARRIS, These companies have developed a family of 8X5X microcontrollers with the same base architecture but with different internal memory capacity and intemal devices. Some of the popular members of X5X family of microcontrollers are listed in Table 4.1. 4.2.1__PINS AND SIGNALS OF 8051 (The INTEL8051 isan8-bitmicrocontroller with 128 byte internal RAM and kB intemal ROM. The 8051 is.40-pin IC available in Dual In-line Package (DIP) and itrequires a single power supply of +5 V. Its maximum internal clock frequency rating is 12 MHz. The 8X5X family members listed in Table 4.2 are pin-to-pin compatible with 8051. The pin configuration of 8051 microcontroller is shown in Fig. 4.2 and the signals of the controller are listed in Table 4.2. Some of the port pins of 2 8051 microcontroller have alternate functions and they are listed in Table 4.3. The 8051 microcontroller has 32 10 pins and they are organized as four numbers ofan 8 parallel port. The ports are denoted as port-0, port-I, port-2 and port-3. Each port can be used eithet as an &-bit parallel port or 8 numbers of I-bit port (ice, individual pins of each port can be used 2s 1-bit 10 line independently). When used as 1-bit port, the port pins are denoted as PX.Y, where X can take values 0 to 3 and Y can take values 0 to 7. For example, the bit-0 of port-I Is denoted as PIO. The ports behave as latel#éf'during output operation and as buffers during input operation- Except port-0 all other ports are provided with internal pull up. Hence, while using port-0 for 10 operation, external pull up should be provided. =~ Jotun ~ Switutt ~ (op, orF) oogntcrocoarrollet s “4: SOME MEMBERS OF THE 8X5X FAMILY OF MICROCONTROLLERS P2.7(A15) PL&ALS) The signals shown Fig. 4.2 : Pin configuration of an INTEL 8051 microcontroller. CRONEKOD PO.7-PO0 (AD7- ADO) P27-P20 (ls-A9 FAV, [> ALEPROS |» PSENsidiceen | 44 Microprocessors and Microcontlen TABLE 4.2: SIGNALS OF A 8051 MICROCONTROLLER dl Pins/Signal Description PO.7 - PO.0 Port-0 input/output pins. P1.7-P1.0 Port-1 input/output pins. P2.7-P2.0 Port-2 input/output pins. P37 -P3.0 Port-3 input/output pins. RST Reset input x1, x2 Pins for crystal connection. The signal at X2 can be used as clock signal for peripherals, PSEN Program store enable. Used as read control or enable for extemal program memory. ALE/PROG Address Latch Enable or program pulse input during EPROM/ ROM programming, EAN, External Access or Programming voltage. Vee Power supply (+5 V) Ves Power supply ground (0 V) x TABLE 4.3: ALTERNATE FUNCTIONS OF PORT PINS Port pins Alternate signal Description PO0.7-P0.0 AD7-ADO Multiplexed low byte address/data. P2.7-P2.0 A15-A8 High byte address P37 RD External memory read control signal P3.6 WR External memory write contro! signal P35 " External input to timer 1 P34 To External input to timer 0 P33 int? External interrupt 1 P32 iNTO External interrupt 0 P34 TxD Serial data output P3.0 RxD Serial data input . y for Except port-1, all other ports have alternate functions, (Port-1 can be used only wy byt? = x OTT pons Mave Stemate functions. ° 10 operation.) When external memory 1s employed, port-0 functions as multiplexed 10 i i . . ssid address or data lines, and_port-2 functions as high byte address lines. Therefore, for acce address or data lines, and port-2 f ms 05 en Ta by extemal memory the microcontroller uses a 16-bit address and accesses the memoryages 4 Microcontroller 4.5 she addressable memory space is 64 KB (2'*= 64k). The 8051 allows the external memory to anized as two banks of 64 KB. one for the progranv/code and the other for the data. The signal isused as read control/enable for program memo rt pin P3.6 functions as swrite y. The port pin P3.7 functions as read control )s = = ‘ontrol (WR) for data memory. When two extemal pesory banks are not desirable, the PSENand RD should be externally ANDed to ledasingle__ ‘rol signal. In such cases, the controller will access a common memory space (of maximum kB) for program and data. pAddrets lati Euable Insystems with external memory, the signal ALE is used to demultiplex the low! address gr data using an extemal latch. The output signal on the ALE pin is the clock signal with a frequency goe-sixth of a crystal or internal clock frequency. The controller will output the ALE signal at a scastant rate (i.¢., at one-sixth of internal clock) even when there is no external memory. Therefore, Se ALE can also be used for external timing and clock source for peripherals or IO devices. In EPROM ROM version of 8051 family controllers, the programming pulse can be input through ALE during programming of EPROM/ROM. Signal EAis used as an extemal program memory access control, The microcontroller. will access the pro; ym external memory if EA pin is grounded. During programming node of internal EPROM/ROM, this pin is used to supply the programming voltage (+12 V). Note: For programming the internal EPROM/ROM of 8051 family of microcontroller, a separate programmer should be employed. The controllers listed in Table 4.1, do not have ISP (In-System Programmable) facility. ) 2) The X1 and X2 pins are provided for external quartz crystal connection, in order to generate the required clack for the microcontroller. The maximum frequency ofa quartz crystal that can be secected to an 8051 microcontroller is 12 MHA\(There are higher clock versions of the 8051 family ofrmicrocontrollers. For details please refer to manufacturers data sheet.) Alternatively, the external clock can be supplied through an X1 pin. The intemal clock frequency of an 8051 microcontroller is same as a crystal frequency or externally supplied clock frequency. When a crystal is connected berween XI and X2, the controller will output a clock signal through X2 whose frequency is same as crystal frequency and this clock signal can be used for peripheral or IO devices The RST signal is used to reset the microcontroller in order to bring the controller to a ksowa staté, For proper reset, the RST pin should be held low for at least two machine eyeles. When the £051 controller is reset, all the internal registers are cleared except the port latches, ack pointer and SBUF register. The internal RAM is not affected by reset. The content Ofte various registers of 8051 after a reset arc listed in Table 4.4,Microprocessors and Microcony Sere Register Pc Content after reset ¥x00000, 0xx00000,, Indeterminate 00, xxx00000, Q ‘The 8051 has five interrupts, In this, two interrupts are external interrupts and. the remaining Ahree are internal interrupts, The {wo external interrupts are interrupts initiated by applying appropriate signals through the pins INTO and INTI, and they are called extemal interrupt-0 and external interrupt-1, respectively. The intemal interrupts are initiated by timef-0, timer-1 and the internal interrupts Aimer), timer-I and the serial port} All the interrupts of 8051 are maskable and vectored interrupts. The vector address and the priorities of the interrupts of 8051 are listed in Table 4.5. (The priorities of the interrupts can also be altered by programming the IP register.) TABLE 4.5: VECTOR ADDRESS AND PRIORITY OF AN 8051 SEM ADDRESS AND PRIORITY OF AN 8051, Interrupt Vector address] Normal priority External interrupt-O 0003,, Highest Timer-0 interrupt 0008, External interrupt-1 0013, Timer-1 interrupt 0018, Serial port interrupt 0023, Lowest 4.3/ARCHITECTURE OF 8051 The architecture of 8051 is shown in Fig, 4.3. The various functional blocks of 8051 are he ALU, Special Function Registers (SFRs) listed in Table 4.6, Instruction Register (IR), Proeey Counter (PC), 128 bytes RAM, 4kB ROM, Port latches and drivers, Oscillator, Timing and Com Unit. [AU May’15, 8 marks & 16 marks) ices | The 8051 has Harvard architecture in which the same address in different memory dev'* ' ted or banks is used for program (or code) and data. Therefore, the architecture has tvo eet 16-bit address pointers, namely, Program Counter (PC) and Data Pointer (DPTR). The PC ne as the address pointer to access program instructions and it is automatically incremented afte!