UNIT-II

8086 SYSTEM BUS STRUCTURE

Title Contents
Unit-II Contents 8086 signals
Basic configurations
System bus timing
System design using
8086 IO programming
Introduction to
Multiprogramming System Bus
Structure Multiprocessor
configurations
Coprocessor, Closely coupled and
loosely Coupled configurations
Introduction to advanced processors
Text books: 1. Yu-Cheng Liu, Glenn
A.Gibson,
―Microcomputer Systems: The 8086
/ 8088 Family - Architecture,
Programming and Design‖, Second
Edition, Prentice Hall of India, 2007.
2. Mohamed Ali Mazidi, Janice
GillispieMazidi, RolinMcKinlay, ―The
8051 Microcontroller and Embedded
Systems:
Using Assembly and C‖, Second
Reference books: 1. DoughlasV.Hall, ―Microprocessors
and Interfacing, Programming and
Hardware‖, TMH,2012
2. A.PGodse and D.A
Godse
―Microprocessorand
Micrcontrollers‖,
Technical Publications.

Prepared By Verified By
Mr.B.Ramesh Asso.Prof/ ECE
Mrs.C.Rajani Assit.Prof/ ECE

1
 UNIT II
8086 SYSTEM BUS STRUCTURE
Syllabus:
8086 signals – Basic configurations – System bus timing –System design
using 8086 – IOprogramming – Introduction to Multiprogramming – System Bus
Structure - Multiprocessor configurations – Coprocessor, Closely coupled and loosely
Coupled configurations – Introduction to advanced processors.

2.1 8086
SIGNALS PIN OUT SIGNALS AND FUNCTIONS OF
8086
8086 is available in three clock rates, i.e. 5, 8 and 10 MHz, packaged as a 40 pin
chip. The 8086 operates in single processor or multiprocessor configurations to
achieve high performance.

The following signal descriptions are common for both the minimum and maximum
modes. AD15-- AD0 These are the time multiplexed memory I/O address and data lines.
Address remains on the lines during T 1 state, while the data is available on the data
bus duringT2, T3, Tw andT4. Here T2, T3, T4 and Tw are the clock states of a machine
2
cycle. Tw is a wait state. These lines are active high and float to a tristate during
interrupt acknowledge and local bus hold acknowledge cycles.

3
A19/S6,A18/S5,A17/S4, A16/S3 These are the time multiplexed address and status lines.
During T1, these are the most significant address lines for memory operations.
During I/O operations, these lines are low. During memory or I/O operations, status
information is available on those lines for T 2, T3, Tw andT4. The status of the interrupt
enable flag bit (displayed on S 5) is updated at the beginning of each clock cycle. The
S4 and S3 combinedly indicate which segment register is presently being used for
memory accesses as shown in Table 1.1. These lines float to tri-state off (tristated)
during the local bus hold acknowledge. The status line S 6 is always low (logical). The
address bits are separated from the status bits using latches controlled by the ALE
signal.
Table 1.1
S4 S3 Indications
0 0 Alternate Data
0 1 Stack
1 0 Code or none
1 1 Data

BHE / S7-Bus High Enable/Status The bus high enable signal is used to indicate the
transfer of data over the higher order (D 15—D8) data bus as shown in Table 1.2. It
goes low for the data transfers over D 15—D8 and is used to derive chip selects of odd
address memory bank or peripherals. BHE is low during T 1 for read, write and
interrupt acknowledge cycles, whenever a byte is to be transferred on the higher
byte of the data bus. The status information is available during T 2, T3 andT4. The
signal is active low and is tristated during ‗hold‘. It is low during T 1 for the first pulse
of the interrupt acknowledge cycle.
Table 1 .2 Bus High Enable/Status
BHE A0 Indications
0 0 Whole Word
0 1 Upper byte from or to odd address
1 0 Lower byte from or to even address
1 1 None

RD-Read Read signal, when low, indicates the peripherals that the processor is
performing a memory or I/O read operation. RD is active low and shows the state for
T2, T3, Tw of any read cycle. The signal remains tristated during the ‗hold
4
acknowledge‘.
READY This is the acknowledgement from the slow devices or memory that they
have completed the data transfer. The signal made available by the devices is
synchronized by the 8284A clock generator to provide ready input to the 8086. The
signal is active high.

5
INTR- Interrupt Request This is a level triggered input. This is sampled during the last
clock cycle of each instruction to determine the availability of the request. If any
interrupt request is pending, the processor enters the interrupt acknowledge cycle.
This can be internally masked by resetting the interrupt enable flag. This signal is
active high and internally synchronized.
TEST This input is examined by a ‗WAIT‘ instruction. If the TEST input goes low,
execution will continue, else, the processor remains in an idle state. The input is
synchronized internally during each clock cycle on leading edge of clock.
NMI-Non-maskable Interrupt This is an edge-triggered input which causes a Type2
interrupt. The NMI is not maskable internally by software. A transition from low to
high initiates the interrupt response at the end of the current instruction. This input
is internally synchronized.
RESET This input causes the processor to terminate the current activity and start
execution from FFFF0H. The signal is active high and must be active for at least four
clock cycles. It restarts execution when the RESET returns low. RESET is also
internally synchronised.
CLK-Clock Input The clock input provides the basic timing for processor operation
and bus control activity. Its an asymmetric square wave with 33% duty cycle. The
range of frequency for different 8086 versions is from 5MHz to 10MHz.
Vcc +5V power supply for the operation of the internal circuit.
GND ground for the internal circuit.

MN/MX The logic level at this pin decides whether the processor is to operate in
either minimum (single processor) or maximum (multiprocessor) mode.
MINIMUM MODE
The following pin functions are for the minimum mode operation of 8086.

M / I/O -Memory/IO This is a status line logically equivalent to S2 in maximum mode.

When it is low, it indicates the CPU is having an I/O operation, and when it is high, it
indicates that the CPU is having a memory operation. This line becomes, active in
the previous T4 and remains active till final T4 of the current cycle. It is tristated
during local bus ―hold acknowledge‖.
INTA -Interrupt Acknowledge This signal is used as a read strobe for interrupt
acknowledge cycles. In other words, when it goes low, it means that the processor
has accepted the interrupt. It is active low during T2, T3,and Tw of each interrupt
acknowledge cycle.
ALE-Address Latch Enable This output signal indicates the availability of the valid
address on the address/data lines, and is connected to latch enable input of latches.
6
This signal is active high and is never tristated.
DT / R-Data Transmit/Receive This output is used to decide the direction of data flow
through the transreceivers (bidirectional buffers). When the processor sends out
data, this signal is high and when the processor is receiving data, this signal is low.
Logically, this is equivalent to S 1 in maximum mode. Its timing is the same as M/ I/O.
This is tristated during ‗hold ack nowledge‘.

7
DEN-Data Enable This signal indicates the availability of valid data over the
address/data lines. It is used to enable the transreceivers (bidirectional buffers) to
separate the data from the multiplexed address/data signal. It is active from the
middle of T2 until the middle of T4. DEN is tristated during ‗hold acknowledge‘ cycle.
HOLD, HLDA-Hold /Hold Acknowledge When the HOLD line goes high, it indicates to
the processor that another master is requesting the bus access. The processor, after
receiving the HOLD request, issues the hold acknowledge signal on HLDA pin, in the
middle of the next clock cycle after completing the current bus (instruction) cycle. At
the same time, the processor floats the local bus and control lines. When the
processor detects the HOLD line low, it lowers the HLDA signal. HOLD is an
asynchronous input, and it should be externally synchronized.
If the DMA request is made while the CPU is performing a memory or I/O cycle, it will
release the local bus during T4 provided:
1. The request occurs on or before T2 state of the current cycle.
2. The current cycle is not operating over the lower byte of a word (or operating
on an odd address).
3. The current cycle is not the first acknowledge of an interrupt acknowledge
sequence. A Lock instruction is not being executed
MAXIMUM MODE SIGNALS
The following pin functions are applicable for maximum mode operation of 8086.

S2, S1, S0-Status Lines These are the status lines which reflect the type of operation,
being carried out by the processor. These become active during T 4 of the previous
cycle and remain active during T1 and T2 of the current bus cycle. The status lines
return to passive state during T 3 of the current bus cycle so that they may again
become active for the next bus cycle during T 4. Any change in these lines during T 3
indicates the starting of a new cycle, and return to passive state indicates end of the
bus cycle. These status lines are encoded in Table 1.3.
Table 1 .3

S 2 S1 S0 INDICATIONS

8
0 0 0 Interrupt Acknowledge
0 0 1 Read I/O port
0 1 0 Write I/O port
0 1 1 Halt
1 0 0 Code Access
1 0 1 Read Memory
1 1 0 Write memory
1 1 1 Passive

9
 LOCK This output pin indicates that other system bus masters will be prevented
from the

system bus, while the LOCK signal is low. The LOCK signal is activated by the LOCK
prefix instruction and remains active until the completion of the next instruction.
This floats to tri-state off during ―hold acknowledge‖. When the CPU is executing a
critical instruction which requires the system bus, the LOCK prefix instruction
ensures that other processors connected in the system will not gain the control of
the bus. The 8086, while executing the prefixed instruction, asserts the bus lock
signal output, which may be connected to an external bus controller.

QS1, QS0-Queue Status These lines give information about the status of the code
prefetch queue. These are active during the CLK cycle after which the queue
operation is performed. These are encoded as shown in Table 1.4.

Table 1 .4
QS1 QS2 Indications
0 0 No operation
0 1 First byte of Opcode from the
queue
1 0 Empty queue
1 1 Subsequent byte from the
queue

RQ / GT0 , RQ / GT1 -Request/Grant These pins are used by other local bus masters,
in maximum mode, to force the processor to release the local bus at the end of the

processor‘s currentbus cycle. Each of the pins is bidirectional with RQ / GT0 having

higher priority than RQ /

GT1 . RQ / GT pins have internal pull-up resistors and may be left

unconnected. The

request/grant sequence is as follows:

1. A pulse one clock wide from another bus master requests the bus access to
8086.
2. During T4 (current) or T1 (next) clock cycle, a pulse one clock wide from 8086
to the requesting master, indicates that the 8086 has allowed the local bus to

10
 float and that it will enter the ―hold acknowledge‖ state at next clock cycle.
The CPU‘s bus interface unit is likely to be disconnected from the local bus of
the system.
3. A one clock wide pulse from another master indicates to 8086 that the ‗hold‘
requestis about to end and the 8086 may regain control of the local bus at the
next clock cycle.

Thus each master to master exchange of the local bus is a sequence of 3 pulses.
Theremust be at least one dead clock cycle after each bus exchange. The request
and grant pulses are active

11
low. For the bus requests those are received while 8086 is performing memory or I/O
cycle, the granting of the bus is governed by the rules as discussed in case of HOLD
and HLDA in minimum mode.

2.2 Basic configurations

Minimum Mode 8086 System And Timings

The microprocessor 8086 is operated in minimum mode by strapping its

MN/ MX pin to logic 1. In this mode, all the control signals are given out by the
microprocessor chip itself. There is a single microprocessor in the minimum mode
system. The remaining components in the system are latches, transceivers, clock
generator, memory and I/O devices. Some type of chip selection logic may be
required for selecting memory or I/O devices, depending upon the address map of
the system.
The latches are generally buffered output D-type flip-flops, like, 74LS373 or
8282. They are used for separating the valid address from the multiplexed
address/data signals and are controlled by the ALE signal generated by 8086.
Transceivers are bidirectional buffers and are called as data amplifiers. They are
required to separate the valid data from the time multiplexed
address/data signal. They are controlled by twosignals, namely, DEN and DT/ R .
The DEN

signal indicates that the valid data is available on the data bus, while DT/ R
indicates the direction of data, i.e. from or to the processor. The system contains
memory for the monitor and users program storage. Usually, EPROMS are used for
monitor storage, while RAMs for users program storage. A system may contain I/O
devices for communication with the processor as well as some special purpose I/O
devices. The clock generator generates the clock from the crystal oscillator and then
shapes it and divides to make it more precise so that it can be used as an accurate
timing reference for the system. The clock generator also synchronizes some
external signals with the system clock. Since it has 20 address lines and 16 data
lines, the 8086 CPU requires three octal address latches and two octal data buffers
for the complete address and data separation. The system configuration is shown
below

12
The read cycle begins in T1 with the assertion of address latch enable (ALE) signal
and also M / IO signal. During the negative going edge of this signal, the valid
address is latched on the local bus.

The BHE and A0 signals address low, high or both bytes. From T1 to T4, the M/IO
signal indicates a memory or I/O operation.

At T2, the address is removed from the local bus and is sent to the output. The bus is
then tri- stated. The read (RD) control signal is also activated in T2.The read (RD)
signal causes the address device to enable its data bus drivers. After RDthe valid
data is available on the data bus.When the processor returns the read signal to high
level, the addressed device will again tristate its bus drivers.

A write cycle also begins with the assertion of ALE and the emission of the address.
The M/ IO signal is again asserted to indicate a memory or I/O operation. In T2, after
sending the address in T1, the processor sends data to be written to the addressed
location. The data remains on the

bus until middle ofT4 state. WR becomes active at the beginning ofT 2 . BHE and A0
are used to select the proper byte or bytes of memory or I/O word to be read or
written.

13
14
 M/ IO RD WR Indications
0 0 1 I/O Read
0 1 0 I/O Write
1 0 1 Memory Read
1 1 0 Memory Write

MAXIMUM MODE 8086 SYSTEM AND TIMINGS

In the maximum mode, the 8086 is operated by strapping the MN/ MX

pin to ground. In this mode, the processor derives the status signals S2 , S1 and S0 .

Another chip called

bus controller derives the control signals using this status information. In the
maximum mode, there may be more than one microprocessor in the system
configuration. The other components in the system are the same as in the minimum
mode system.

The basic functions of the bus controller chip 1C8288, is to derive

control signals

like RD andWR (for memory and I/O devices), DEN , DT/ R , ALE, etc. using the
information made available by the processor on the status lines. The bus controller
chip has input lines and

S2 , S1 and S0 CLK. These inputs to 8288 are driven by the CPU. It derives the
outputs ALE,

DEN , DT/ R , MRDC , MWTC , AMWC , IORC , IOWC and AIOWC . The AEN , IOB
and

CEN pins are specially useful for multiprocessor systems. AEN and IOB are
generally

grounded. CEN pin is usually tied to +5V. The significance of the MCE/ PDEN output
depends upon the status of the IOB pin. If IOB is grounded, it acts as master cascade
enable to control cascaded 8259A, else it acts as peripheral data enable used in the
multiple bus configurations.

INTA pin is used to issue two interrupt acknowledge pulses to the interrupt
controller or to an interrupting device.

15
IORC , IOWC are I/O read command and I/O write command signals respectively.
These signals enable an IO interface to read or write the data from or to the

addressed port. The MRDC ,

MWTC are memory read command and memory write command signals respectively
and may be used as memory read and write signals. All these command signals
instruct the memory to accept or send data from or to the bus. For both of these
write command signals, the advanced
signals namely AMWC and AIOWC are available. They also serve the same purpose,

but are activated one clock cycle earlier than the IOWC and MWTC signals,

respectively. The

16
maximum mode system is shown in Fig. 1.10.The maximum mode system timing
diagrams are also divided in two portions as read (input) and write (output) timing
diagrams. The address/data and address/status timings are similar to the minimum
mode. ALE is asserted in T1, just like minimum mode.

S0, S1, S2 are set at the beginning of bus cycle.8288 bus controller will output a
pulse as on the ALE and apply a required signal to its DT / R pin during T1.

In T2, 8288 will set DEN=1 thus enabling transceivers, and for an input it will
activate MRDC or IORC. These signals are activated until T4. For an output, the
AMWC or AIOWC is activated from T2 to T4 and MWTC or IOWC is activated from
T3 to T4.

The status bit S0 to S2 remains active until T3 and become passive during

T3 and T4. If reader input is not activated before T3, wait state will be

inserted between T3 and T4. Memory Read Timing Diagram for Maximum

Mode Operation of 8086: -

17
Memory Write Timing Diagram for Maximum Mode Operation of 8086: -

2.4 System design using 8086

2.4.1 Minimum Mode 8086 System

The Fig. 2.12 shows the typical minimum mode 8086 system.
For interfacing memory module to 8086, it is necessary to have odd
and even memorybanks. This is implemented by using two EPROMs and two
RAMs.
Data lines DI5-D8 areconnected to odd bank of EPROM and RAM,, and data
lines DrD0 are connected to evenbank of EPROM and RAM.
18
Address lines are connected to EPROM and RAM as per theircapacities.

19
 RD signal is connected to the output enable (0E) signals of EPROMs
andRAMs. WR signal is connected to WR signal of RAMs.
Two separate decoders are used toGenerate chip select signals for memory
and I/O devices. These chip select signals are logically ORed with either BHE
or to generate final chip select signals.
RD and WR signals are connected tothe RD and WR signals of I/O
device. Data lines D15-D0 are connected to the data lines ofI/O
device

Figure 2.12 Minimum Mode 8086 system

2.4.2 Maximum Mode 8086 System

The Fig. 2.13 shows the typical maximum mode 8086 system.
Here interfacing of memory and I/O devices are shown with the basic
maximum mode configuration.
The connections for memory and I/O devices are similar to that of minimum
modeconfiguration. The generation of control signals from 8086 is done by
external bus controller 8288.

20
 Figure 2.13 Maximum Mode 8086 system

2.5 IO programming
The transfer of data between keyboard and microprocessor, and
microprocessor and display device is called input /output data transfer or I/O
data transfer.
This data transfer is done by using I/O ports.
2.5.1 Input port:
It is used to read data from the input device such as
keyboard. The simplest form of input port is a buffer.
The input device is connected to the microprocessor through buffer as shown
Data bus Fig 2.14.

Figure 2.11 Input Port

This buffer is a tri-state buffer and its output is available only Enable when
enable signal is active.
When microprocessor wants to read data from the input device (keyboard), the
control signals from the microprocessor activates the buffer by asserting
enable Input of the buffer,
Once the buffer is enabled, data train the Input device is available on
the data bus. Microprocessor reeds this data by Initiating reed
command.
2.5.2 Output port:
It is used to send data to the output device such as display from the
microprocessor.
The simplest formof output port is a latch.The output device is
21
connected to the microprocessor through latch, as shown In the Fig. 2.15.
When microprocessor wants to send data to the output device, it puts the
data on the data bus and activates the clock signalof the latch.

22
 Figure 2.12 Output Port

2.5.3 Programmed I/O:

I/O operations will mean a data transfer between an I/O device and memory or
between an I/O device and the CPU.
If in any computer system I/O operations are completely controlled by the
CPU, then that system is said to be using ‗programmed I/O‘.
When such a technique is used,CPU executes programs that initiate, direct
and terminate the I/O operations, including sensingdevice status, sending a
read or write command and transferring the data.
It is the responsibility of the processor to periodically check the status of the

I/O system until it finds that the operation is complete. This process is
illustrated in below figure 2.16.
Figure 2.13 Flowchart for I/O service routine
2.5.4 Interrupt Driven I/O
The moat common method of servicing such device is the polled
approach. This is where the processor must test each device in
sequence.
It needs communication with the processor.

23
It is easy to see that a large portion of the main program is looping
through this continuous polling cycle.
Allows the processor to execute its main program and only stop to service
peripheral devices when it is told to do so by the device itself.

24
 The methodwould provide an external asynchronous input tothe processor.
Instruction that is currently being executed and fetch a new routine that will
service the requesting device.
Once this servicing iscompleted, the processor would resume exactly where
It left off. This method of servicing I/O request is called Interrupt driven I/O.
When a processor is interrupted, Itstops. Executingits current program and calls
a special routine which services the Interrupt thisis illustrated in fig.2.17.
Interruptionis called Interrupt and the special routine executed to service the
Interrupt is called Interrupt Service routine (ISR).

Figure 2.14 Interrupt Operation

2.5.5 Comparison between Programmed I/O and Interrupt Driven I/O

Table 2.5Comparison between Programmed I/O and Interrupt Driven I/O

2.5.6 Direct Memory Access (DMA) Transfer

In software control data transfer, processor executes a series of instructions to
carry out data transfer.
For each instruction execution fetch, decode arid execute phases are
required. Fig. 2.18 gives the flowchart to transfer data from memory
25
to I/O device.

26
 So this method of data transfer is not suitable for large data transfers.

Figure 2.15 Flowchart To Transfer Data from Memory to I/O Device

2.5.6.1 Drawbacks in Programmed I/O and Interrupt Driven I/O

Transfer rate is limited by the speed
The time that the CPU spends testing I/O device status and executing a number
of instructions for I/O data transfer can often be better spent on other
processing tasks

2.5.6.2 DMA Operation

DMA controlled data transfer is used for large data transfer. For example to
read bulk amount of data from disk to memory.
To read a block of data from the disk processor sends a series of commands to
the disk controller device
Readthe desired block of data from thedisk.
When disk controller is ready to transfer first byte of data from disk, it sends
DMA request DRQ signal to the DMA controller.
Then DMA controller sends a hold request HRQ, signal to the processor HOLD
Input. The processor responds this HOLD signal by floating itsbuses and
sending out a hold acknowledge signal HLDA to the DMA controller.

2.5.6.3 DMA Active Cycle

When DMA controller gets control of the buses, it sends tie memory address
and Italso sends a DMA acknowledge, DACK signal to the disk controller
device telling it to get ready to output the byte.
Finally, it asserts both the I/Oand MEMW signals on tie control bus.

27
 Figure 2.16DMA Controller Operating In A Microprocessor System

2.5.7 Comparison of I/O program controlled transfer and DMA transfer:

S.No I/O program controlled transfer DMA transfer

1 It is software controlled Hardware controlled transfer
transfer
2 Data transfer speed is low Data transfer is high
3 CPU is involved in the transfer
CPU is not involved in the transfer
4 Extra hardware is not requiredDMA controller is required to carry
out data transfer
5 During data transfer data is During data transfer data does not
routed through processor routed through processor
Table 2.6Comparison of I/O Program Controlled Transfer and DMA Transfer

2.6 Introduction to Multiprogramming

2.6.1 Multiprogramming:
A process can be defined as a programming unit which performs an
independent task.
A processor that process (execute) serially, because it can process one task
at a time that‘s why it is called uniprogramming system.
In a multiprogramming environment, the codes for two ‗or‘ more processes
are in memory at the same time and are executed by time-multiplexing.
The performance of a system is generally measured in terms of the
number of jobscompleted in a time period (that is referred as system through
put).

The following Figure presents completion of a taskconsisting two processes P1 and

P2 by using uniprogramming.
1) The P1 starts and continue until F/O is required (Point A), then FÍO is
initializedand the processing continues in parallel with 1/0 until the processing
requiresthe input data. At this time it should wait until I/O is finished (Point B).

28
 Figure 2.7UniprogrammingApproach

2) The 110 in finished (Point C) the processing is resumed and the same
description applies to point D, E and F. At the end of P1, P2 can start which
hasthe same operation as that P1.

Figure 2.21 Multiprogramming Approach

A multiprogramming system may be capable of accommodating several

users at thesame time.
Multiprogramming can be used in a system that includes more than
oneProcessor, such systems are called multiprogramming systems.

2.6.2 Process Management

A process is sequential program in execution. A process defines the fundamental
unitof computation for the computer. Components of the process are:
1) Object program
2) Data
3) Resources
4) Status of the process execution.
2.6.2.1 Processes and Programs
Process is a dynamic entity, which is a program in execution.
A process is a sequence of instruction executions. Process exists in a limited
span of time.
Two or more processes can execute the same program, each using their own
data and resources.
Program is a static entity made up of program statement.
2.6.2.2 Process State
29
 When process executes, it changes state.
Process state is defined as the current activityof the process.
Fig. 2.22 shows the general form of the process state transition
diagram. Process state contains five states. The states are
listedbelow.
1) New
2) Ready
3) Running
4) Waiting
5) Terminated(exist)

Figure 2.22 Process State transition Diagram

1. New:
A process that has just been created.
2. Ready:
Ready processes are waiting to have the processor allocated to them by
theoperating system so that they can run.
3. Running:
The process that is currently being executed.
A running processpossesses all the resources needed for its execution,
including the processor.
4. Waiting:
A process that cannot execute until some event occurs such as thecompletion
of an 1/O operation.
The running process may become suspended byinvoking an I/O routine.
5. Terminated:
A process that has been released from the pool of executable processes by the
operating system.

2.6.2.3 Process Control Block (PCB)

Each process contains the process control block(PCB). PCB is the data structure
used by the operating system.
1. Pointer:
Pointer points to another process controlblock. Pointer is used for maintaining
the list Scheduling list
2. Process state:
Process state may be new, ready, Memory locationrunning, waiting and so on. .
3. Program counter:
30
 It indicates the address of thenext instruction to be executed for this process.
4. CPU registers:

31
 It includes general purpose blockregister, stack pointers, index
registers andaccumulators etc.
5. Memory management information:
Include the value ofbase and limit register.
Information is useful for deallocating the memorywhen the process terminates.
6. Accounting information:
The information includes the amount of CPU and realtime used, time limits,
job or process numbers, account numbers etc.

2.6.3 Semaphore
The software technique used to solve the same problem is, Mutual exclusion.
The program region where the common resources, are used is called critical
program region.
Semaphore implementation in 8086:
In 8086, the XCHG instruction along withthe LOCK prefix can be used to set or reset
Semaphore.
Program sequence : MOV AL, 00H
Check again : LOCK XCHG semaphore, AL
TEST AL, AL
JZ checkagain
. . Critical region in which program access the shored
resources MOV semaphore, 1
The XCHG semaphore, AL instruction exchanges the contents of the AL register with
the contents of the memory location in which semaphore is stored.
The XCHG instruction requires two bus cycles.
1) During this XCHG instruction, achieved by LOCK prefix in the 8086. LOCK prefix
activates the LOCK output pin during the execution of the instruction that
follows the prefix.
2) During the execution of XCHG instruction, The LOCK output pin is in the active
state which does not allow other processor to getcontrol of the system bus.

2.6.4 Swapping
Swapping is a technique of temporarily removing inactive program (from the
memory al a system.)
It removes the process from the primary memory when it is blocked
anddeallocating the memory. Fig. 2.23shows the swapping of process.
For example. When process P1 requests an I/O operation. It becomes
blocked and will not return to the ready state.
Process manager places the process P1 into a blocked state, then the
memorymanager swaps the process P1 from primary memory to secondary

32
memory and process P,secondary memory to primary memory Process P,
changes the state, after swapping.
Figure 2.23 Swapping Of Processes

33
 When process is swapped out, its executable image is copied to secondary
memory. When the process is swapped back into available primary memory
and swapped out is copied into the new block allocated by the memory
manager.
Binding Method:
If the address binding is done at load time then the process is moved to same
location of previous one
If the address binding done at execution time then the process can be
swapped into a different memory space.
2.6.5 Memory Management:
The placement of blocks of information in a memory system is called memory
allocation. The memory management system keeps the table.
The table indicates which parts of memory are available and which are
occupied.
The criteria for selecting a particular block is replaced Is indicated by the
replacement policy.
Nonpreemptive allocation:
First fit :
In this algorithm, searching is started either at the beginning of the memoryor
where the previous first-fit search ended.
In this algorithm the first free memory block which is big enough is allocated
to the block
k. The searching process is stopped as soon as a free memory block with
enough space is allocated.
Best fit:
In this algorithm, all free memory blocks are searched and smallest free
memory block which is large enough to accommodate desired k Block is used
to allocate k.
This algorithm uses free memory space more efficiently than first-fit algorithm.
The Fig 2.24 Shows the allocation of memory blocks using first fit and best fit
algorithms.

34
 Figure 2.24 NonPreemptive Memory Allocation

Preemptive Allocation:
Nonpreemptive allocation cannot make efficient use of memory in all situations.

35
Much more efficient use of the available memory space is possible if the
occupied space can be reallocated to make room for incoming blocks.
Reallocation of the blocks can be done by a method is called Compaction.
2.7 System Bus Structure
The following figure 2.25 illustrates the fundamental structure of a system
bus and its relationship to be various components if the computer system.
The complexity of the bus control logic depends in the amount of
translation needed between the system bus and the pins on the CPU.
All of the address and data lines and most of the control lines use are capable
of being logically disconnected from the CPU or bus control logic.
The timing of the signals within the CPU and bus control logic is controlled by
a clock. The bus cycles and CPU activity are controlled by ground of clock
pulses.
The CPU on put is transaction would processed by outputting the address of
the data during first clock cycle.

Figure 2.25Typical System bus Architecture

36
Read is to take place during the second clock cycle.

37
 Waiting an intermediate number of clock cycles for the addressed device to
put the data on the data lines, inputting the data and signaling the device that
the transfer is complete during the last clock cycle.

2.8 Multiprocessor configurations

2.8.1 Definition:
If a microprocessor system contains two or more components that can
execute instructions independently, then the system is called multiprocessor
system.
Multiprocessor system uses a distributed approach.
Here More than one processor isused to do the subtasks instead of doing entire
task by a single processor.
Advantages:
I. Improves cost/performance ratio of the system.
2. Avoiding the expense of the unneeded capabilities of a centralized system.
3. Tasks are divided among the modules. If failure occurs, it is easier and
cheaper to find and replace the malfunctioning processor.

Types:
The multiprocessor systems are implemented using one of the two basic
architectures: Loosely coupled architecture and closely coupled architecture.
The systems using these architectures are known as loosely coupled
systems and closely coupled systems respectively.
COPROCESSOR, CLOSELY COUPLED AND LOOSELY COUPLED
CONFIGURATIONS
2.8.2 Closely Coupled Multiprocessor Configuration
In the closely coupled system (CCS) the processors or supporting processors
(coprocessor, math‘sprocessor) share clock generator, bus control logic, and
entire memory and I/O subsystem.
Such systems communicate through a shared main memory.
Data can communicate from one processor to the other is on the order of the
bandwidth of the memory.
Due to memory contentions two or more processors attempt to access the
same memory unit concurrently. When high-speed or real-time processing is
desired. Closely coupled systems (CCS) may be used.
o There are two models of a
CCS: 1, CCS without private
cache
2. CCS with private cache.

2.8.2.1 CCS without Private Cache

The Fig 2.26shows the closely coupled multiprocessor system without
private cache. It consists of Pprocessors, M memory modules and C input-
output channels.
These units are connected through a set of three interconnection
networks, viz.
1. The processor-memory interconnection network (PMIN)
2. The input-output processor interconnection network (IOPIN)
3. The interrupt-signal interconnection network (ISIN)

38
 Figure 2.26CCS without Private Cache

The PMIN is a switch which is used to connect every processor to every memory
module.
This switch is P by M crossbar with PM sets of cross points.
When the crossbar switch is distributed across the memory modules, the
system is known as a multiported memory system.
A memory can satisfy only one processor‘s request in a given memory cycle.
Hence, if two or more processors attempt to access the same memory
module, a conflict occurs which is resolved or arbitrated by PMIN.
To avoid excessive conflicts the number of memory module L is usually as large
as P. Another method to minimize conflicts is to associate a reserved storage
area with each processor. This is the unmapped Local memory (ULM).
ULM is used to store kernel code and operating system tables often used
by the processes running on that processor.
The IOPIN is used to allow a processor to communicate with an I/O channel
which is connected to peripheral devices.
The ISIN is used for two purposes: To direct an interrupt to any other
interprocessor network and to initiate hardware alarm in case of processor
failure.

2.8.2.2 CCS with Private Cache

39
 Figure 2.27CCS with Private Cache

In the first model (that is without private cache) each memory reference goes
through the PMIN, it encounters delay in the process or memory switch and
hence the instruction cycle time increases.
The increase in the instruction cycle lime reduces the system throughput.
This delay can be reduced by associating a cache with each processor to
capture most of the references made by a processor.
Another advantage of the cache is that the traffic through the crossbar switch
can be reduced, which subsequently reduces the contention at the cross
points.
More than one inconsistent copy of data may exist in the system as this
multiprocessor organization encounters the cache coherence problem.
2.8.2.3 Closely Coupled System using 8086
The CPU (8086) is the master or host and the supporting processor is
the slave. Therefore, two 8086s cannot appear in this configuration.
The CPU provides the bus control logic.
So the bus request signal from the supporting processor is connected to

the CPU. The Fig. 2.28 shows the simplest form of closely coupled

configuration.

40
 Figure 2.28Closely Coupled Configurations

2.8.2.4 Interaction between CPU and independent processor

In a closely coupled system no special instruction such as WAIT or ESC is used.
The communication between host and independent processor is done through
memory space.
The independent processor then accesses the memory to execute the task
in parallel with the host.
When task is completed, the external processor informs the host processor
about the completion of task by using either a status bit or an interrupt
request.

Fig. 2.29 shows the interaction between CPU and independent processor in closely
coupled configuration.

Figure 2.29 Interactionsbetween CPU and Independent Processor

2.8.3 Loosely Coupled Multiprocessor Configuration

Each processor has a set of input-output devices and a large local memory.
The processor, its local memory and input-output interfaces are together
called computer module.
Processes which execute on different computer modules communicate by
exchanging messages through a Message Transfer System (MTS).
The coupling in such a system is very loose. Hence, such systems are also
referred to as distributed systems. The Fig. 2.30shows nonhierarchical loosely
coupled multiprocessor system.

41
 Figure 2.30Loosely Coupled Configurations

2.8.3.1 Loosely Coupled System using 8086

It consists of different modules. Each module may consist of an 8086.
A processorcapable of being a bus master, or a co-processor or closely
coupled configuration.
Normally each processor has its own local memory and I/O devices, to with
other processors do not have direct access. Fig.2.30showsthe loosely coupled
configuration.
2.8.3.2 Advantages of Loosely Coupled System
1. Better system throughput by having more than one processor.
2. Each processor may have a local bus to access local memory or I/O devices so
that a greater degree of parallel processing can be achieved.
3. System structure is more flexible. As the system consist of different modules,
one can easily add or remove modules to change the System configuration
4. A failure in one module normally does not cause a breakdown of the entire system.

2.8.4 Numeric Processor 8087

The numeric processor 8087 is a coprocessor which has been specially
designed to work under the control of the processor 8086 and to support
additional numeric processing capabilities.
2.8.4.1 Features of 8087
1. It can operate on data of the integer, decimal, and real types, with lengths ranging
from 2 to 10 bytes.
2. Its instruction set not only includes various forms of addition and subtraction, but
also provides many useful functions such as square root, exponential, tangent, and
42
so on.
3. It is high performance numeric data processor. It can multiply two 64 bit real
numbers in about 27 is and calculate square root in about 36 ps.

43
 4. It follows IEEE floating point standard.
5. It is multi bus compatible.
2.8.4.2 Pin Diagram of 8087
Fig. 2.31 shows pin diagram of 8087.

Figure 2.31 Pin Diagram of NOP 8087

The address/data, status, ready, reset, dock, power and ground pins of the NDP are
similar to the 8086 pins. Among the remaining 8 pins, four are not used. The other
pins are as follows:
1. BUSY:
BUSY signal from the 8087 is connected to the TEST input of the 8086.
If the 8086 needs the result of some computation that the 8087 is doing
before it can execute next instruction in the program.
A low on the 8087 BUSY output indicates that the 8087 has completedthe
computation
2. RQ / GT0
This request / grant signal from the 8087 is usually connected to the request /
grant (RQ
/ GT0 or RQ / CT1) pin of the 8086.
3. RQ / GT1:
This request / grant signal is connected to the request I grant pin of the
independent processor such as 8089.
4. INT:
The interruptpin is connected to the interrupt management logic.
The 8087 can interrupt the 8086 through this interrupt management logic
at the time, error condition exists.
5. S0 - S2: These are the status bits of 8087 which arc encoded as follows:
44
S2 S1 S0 Status
0 X X - unused
1 0 0 - unused

45
 1 0 1 - read
memory
1 1 0 - write
memory
1 1 1 - passive

6. QS0- QS1: These signals give the queue status as follows:

QS1 QS0 Operation
0 1 no operation
0 1 first byte of opcodefrom
Queue
1 0 queue empty
1 1 subsequent byte from the
queue

2.8.4.38087 Architecture

Figure 2.32 Block Diagram of 8087

2.8.4.3.1 Instruction Queue

It maintains a 6 byte instruction queue and tracks a execution sequence of
the host. The 8087 decodes the external opcode to perform the specified
operation and captures the operand address.
2.8.4.3.2 Data Registers
It has 8 data registers.
Each register is 80-bit and it is accessed as a stack.
An operand may be pushed or popped from top of stack.
‗Push‘ operation decrements TOP of stack by 1 and loads a value into the
new top register.
A ‗pop‘ operation stores the value from the current top register and then
increments TOP by 1. The top stack element is pointed by ST bits, i.e., bits
13, 12 and 11 of the status register.
2.8.4.3.3 Status Registers
The status register is 16 bit register.
It indicates various errors, stores condition code for
instructions, Fig 2.33 shows the bit definitions of the
46
 Status Register.

Error Flags
1) IE: An invalid operation such as stack overflow, stack underflow, invalid
operand, square root of a negative number etc.

47
 2) DE: The operand is not normalized.
3) ZE: A divide by zero error.
4) OE:An exponent overflows error.
5) PE: A precision error.
Interrupt Flag:IR:indicates the existence of the interrupt request.
Condition Code
C0 - C3 indicates the condition code.
The condition codes are set by the compare and examine instructions.
Stack Bits
ST: S0-S2 indicates the top of stack.
Busy Status:
B: Indicates current operation is not
completed.

Figure 2.33 Bit Pattern of Status Register

2.8.4.3.4 Control Register

The control register is also 16 bit.
The 8087 provides several processing options which are selected by loading a
word from memory into the control register.
The control register gives the facility to mask each error type individually from
causing an interrupt
It can be used to set precision levels, rounding type and infinity representation.

Fig. 2.34 shows the bit definition of control register.

Bits 5-0 of the control registers contain individuals masks for each of the six
exceptions Bit 7 containsa general mask bit for all 8087 interrupts.
The high order byte of the control register configures the 8087 operating mode
including precision, rounding, and infinity controls.
After reset or initialization of the 8087, these bits are PC = 11, RC= 00, IC =0,
IEM = 0 and all error mask bits are 1.

48
 Figure 2.34 Bit definition of control register

Tag Register: TAG register holds the status of the contents of data register. This
includes 0 0–DataValid
0 1 -Zero
1 0 –Aspecialvalue
1 1 - Empty

2.8.4.4 Data Formats and Conversions of 8087:

The 8087 can operate on memory operands of seven different data types:
1) Word integer
2) Short integer
3) Long integer
4) Packed BCD
5) Short real
6) Long real
7) Temporary real

A real format is divided into three fields:

1. Sign
2. Exponent
3. Mantissa.

Real number n = sign x mantissa.

To convert any number to real format, we have to move the decimal point to
the right of the most significant, non zero digit.
This process of moving the decimal point to the right of the most significant,
nonzero digit is referred to as Normalization.

The 8087 recognizes three real data types:

1) Short real (32-bit)
2) Long real (64-bit)
3) Temporary real (80-bits)

Format has field:sign, exponent and mantissa.

49
 Figure 2.35 Data Format of NDP 8087

Example 1: Convert125912510in short real, long real and temporary real formats

50
2.8.4.5 Stacks in 8087
The 8087 has a 3-bit stack pointer which holds the number of the register
which is the current top-of-stack.
When the 8087 is initialized, the 3-bit stack pointer in the 8087 is loaded with
000 that indicates register C) is a top of stack.
As shown in Fig. 2.36, the stack of 8087.When 8087 reads the first number,
stack is decremented to 111(7) and the number is stored in register number
111(7), now register 7 is the top of stack.

Figure 2.36 Register Stack in 8087

51
2.8.4.6 Instructions in 8087
The 8087 instructions, which can be divided into six groups.
1) Data transfer instructions
2) Arithmetic instructions
3) Compare instructions
4) transcendental instructions
5) Load constant instructions
6) Processor control instructions.

2.8.4.6.1 Data Transfer Instructions

a) Real Transfers
FLD source:
Decrements the stack pointer by one and copies a real number from a slack
element or memory location to the new ST.
A short-real or Long-real number from memory is automatically converted to
temporary real format by the 8087 before it is put in ST.
Exceptions: I, D.
Examples:
FLD ST (2) ; CopiesST(2) to ST
FLD [BX] ; Number from memory pointed by BX copied to ST

FST destination:
Copies ST to a specified stack position or to a specified memory location.
Exceptions: 1, 0, U. P.
Examples:
FST ST (3) ; Copy ST to ST(3)
FST [BX] ; Copy ST to memory pointed by IBXI

FSTP destination:
Copies ST to a specified stack element or memory location and increments the
stack
pointer by one to point to the next element on the stack.
This is a stack POP operation.

2.8.4.6 .2 Arithmetic Instructions

a) Addition
FADD destination, source:
Adds real number from specified source to real number at specified
destination. Source can be stack clement or memory location.
Destination must be a stack element
Exceptions: I, D, O, U, P.
Examples:
FADD ST(2), ST ; Add ST to ST(2), result in
ST(2) FADD ST. ST(5) ; Add ST(5) to ST.
result in ST FADD SUM ; Real number from
memory + ST FADD ; ST + ST(1), pop stack-result
at ST

FADDP destination, source:

Adds ST to specified stack element and increments stack pointer b one.
Exceptions: I. D, O, U, P.
Example:

52
FADDP ST(2) ; Add ST(2) to ST.
Increment stack pointer so ST(2) becomes ST.

53
FIADD source:
Adds integer from memory to ST, stores the result in ST.
Exceptions: I, D, O, P.
Example
FIADD CARS_SOLD ; Integer number from memory + ST

b) Subtraction
FSUB destination, source:
Subtracts the real number at the specified source from the real number at the
specified destination and puts the result in the specified destination.
Exceptions: I, D O, U, P.
Examples:
FSUI3 ST (3), ST ; ST(3) - ST(2) - ST
FSUL3 DIFFERENCE ; ST * ST - real from
memory FSUI3 ;ST* {ST(1)-ST)

FSUBP destination, source:

Subtracts ST from specified stack element and puts result in specified stack
element.
Then increments stack pointer by one.
Exceptions: I, D, 0, U, P.
Examples
FSUBP ST (2) ; ST (2) - ST. ST (l) becomes new ST.

FISUB source:
Subtracts integer number stored in memory from ST and stores result in ST.
Exceptions: I, D,O, P.
Example
FISUB DIFFERENCE ; ST ST - integer from memory

C) Reversed Subtraction
FSUBR destination, source
FSUBRP destination, source
FISUBR source
These instructions operate same as the FSUB instructions.
Subtract the contents of the specified destination from the contents of the
specified source and put the difference in the specified destination.
d) Multiplication
FMUL destination, source:
Multiply real umber from source by real number from specified destination,
and put result in specified stack element.
Exceptions: I, D, O, U, P.
FMUL ST(2), ST ; Multiply ST(2) and ST. result in
ST(2) FMUL ST,ST(5) ; Multiply ST(5) to ST. result in ST

2.8.4.6.3 Compare instructions

Compares the contents of ST with contents of specified or
default source. The source may be another stack element or real
number in memory.
These compare instructions set the condition code bits C3, Q, and CO of the
status word shown in Table:2.7

54
 Table 1.7C3, Q and CO Status word
2.8.4.6.4 Processor Control Instructions
These instructions do not perform computations.
They are used to do tasks such as initializing the 8087, enabling interrupts,
writing the status word to memory, etc.
FINIT / FNINT:
Initializes8087. Disables interrupt output, sets stack pointer to register 7,
sets default
status.
FDIS / FNDISI:
Disables the 8087 interrupt output pin so that it cannot cause an interrupt
when an exception (error) occurs.
FENI / FNENI:
Enables 8087 interrupt output so it can cause an interrupt when an exception
occurs.
FLDCW source:
Loads a status word from a memory location into the 8087 status register.
This instruction should be preceded by the FCLEX instruction to prevent a
possible exception response
FSTCWIFNSTCW destination:
Copies the 8087 control word to a memory location. Determine its current
value with 8086 Instructions.
FSTSW / FNSTW destination:
Copies the 8087 status word to a memory location.
FCLEX/FNCLEX:
Clears all of the 8(187 exception flag bits in the status register. Unasserts BUSY
and INT outputs.
FSAVE / FNSAVE destination:
Copies the 8087 control word, status word, pointers, and entire register stack
to 94-byte area of memory.
FRSTOR source:
Copies a 94-byte area of memory into the 8087 control register, status register.
pointer registers, and stack registers.
FSTENV / FNSTENV destination:
Copies the 6087 control register, status register, tagwords, and exception
pointers to a series of memory locations.
FLDENV source:
55
Loads the 8087 control register, status register, tag word, and exception
pointers from a named area in memory.

56
FINCSTP:
Increment the 8087 stack pointer by one.

2.8.4.7 I/O Processor 8089

Microprocessor can transfer data with input/output ports. Here Microprocessor
is required to set up and perform the actual transfer.
For high speed data transfers CPU uses the DMA controller to transfer data.
But microprocessor still needs to set up the device controller, initiate the DMA
operation, and examine the post transfer status after the completion of each
DMA operation.
Fig. 2.37 (a) shows input/output handled by microprocessor with DMA
controller. .

Fig. 2.37 (a) I/OHandled by Microprocessor

2.8.4.7.1 Features:
1) An IOP can fetch and execute its own instruction.
2) Instructions are design for I/O processing
3) 8089 can perform arithmetic and logic operations, branches, searching, and
translation.
4) IOP does all work involved transfer.
5) IOP can transfer data from an 8bit source to 16 bit destination
6) Communication through memory based controlblocks.
7) IOP supports multiprocessing environment.
8) IOP and CPU can do processing simultaneously.
9) CPU defines tasks in the control blocks to locate a program sequence called
a channel program.
2.8.4.7.2 Architecture of 8089
The following diagram shows the internal block diagram of the 8089.
a) Channel Registers
Fig. 2.38Internal block diagram of 8089. Each channel has an identical set of
registers.
Each set is divided into two groups
1. Pointer (20-bit) - GA, GB, GC, TP, PP
2. Register (16-bit) - IX, BC, MC, CC
Each pointer register, except PP is assigned with a tag bit.
Tag bit indicates whether the contents of pointer register represent 20-bit
memory address (tag = 0) or a 16-bit I/O address (tag = 1).
P register is always used to address memory. i.e. 20-bit address.
The registers GA, GB, CC, BC, IX and MC can be used as general purpose
registers in a channel program to do arithmetic and logic operations and
executing DMA operations.

57
 Figure 2.38 Internal Block Diagram 0f 8089

b) Addressing Memory Operands

GA, GB, CC, and PP can be used as a base pointer for accessing memory operands.

C) DMA operation
1. GA and GB:
GA and GB are used as source and destination pointers.
If GA points to source, GB points to destination, and vice versa.
2. GC:
When a translation operation is performed along with a DMA transfer, CC
stores the base address of 256 byte.
3. BC:
BC is used as a byte counter.
It is decremented by 1 after each, byte transfer and 2 after each word transfer.
4. MC:
MC is used for mask compare operation.
MC stores the byte to be compared in its lower byte and mask pattern in the
5. IX:
higher byte. IX register is used as an index register.
6. TP:
TP is a task pointer
Stores the address of the next instruction to be executed.
It has a TAG bit to indicate whether the next instruction is stored in the system
or I/O space.
7. PP:
PP is a parameter pointer.
It is automatically filled by 8089 at the time of initialization
of a task. It stores an address of the parameter block.

58
Figure 2.39 Channel control Register

59
 2.9 Introduction to advanced processors
2.9.1 80286 Microprocessor
2.9.1.1 Limitations of 80286:
1. Slow processing speed
2. Less addressing capacity
3. Smaller data paths
4. Not able to do floating point arithmetic on its own
5. Lack of security mechanism required for multiuser and multitaskingenvironment
6. Not able to do parallel processing
7. Lack of enhanced pipelined architecture
8. Lack of powerful instruction set which can support operating system
9. Does not support paging and virtual addressing
10.Does not support branch predictions to improve overall operation speed.

2.9.1.2 Features
1) The 80286 is a 16-bit processor. The 16-bit ALU allows to process 16-bit data.
2) It has 24-bit address bus. It can access up to 16 Mbytes (224) of
physicalmemory or 1 Gigabyte (2°) of virtual memory.
3) The 80286 can be operated at three different clock speeds. These are 4
MHz(80286-4), 6 MHz (80286-6), and 8 MHz (80286).
4) The 80286 includes special instructions to support operating systems.
5) The 80286 is housed in a 68-pin leadless flat package.
6) It contains four separate processing units. These are the Bus Unit (BU), the
Instruction Unit (lii), the Address Unit (AU) and the Execution Unit (EU
7) The 80286 microprocessor is compatible with their earlier 8086, 8088, 80186
and 80188 chips.
8) It has virtual memory-management circuitry and protection circuitry.

2.9.1.3 Block Diagram of 80286:

Fig. 2.40 shows the block diagram of Intel 80226 microprocessor. The 80286 isdivided
into four sub units:
1) Bus Unit (BU)
2) Address Unit (AU)
3) Execution Unit (EU) and Instruction Unit (lU)

Bus Unit:
It includes address latches and data transceivers, bus interface and control
circuitry, instruction pre fetches and a 6 byte instruction queue.
The Bus unit does all the memory and 1/O read/write operations.
It pre fetches instruction bytes and puts them in a 6 byte pre fetch queue.
The Bus unit is responsible for the transfer of data to and from the processor
extension devices

60
 Figure 2.40 Block Diagram of 80286

2. Address Unit:
It includes the segment registers (same as on 8086 and 80186), an offset adder
and a physical address adder.
The 80286 can be operated in two memory addressing modes:
1) Real address mode
2) Protected virtual address mode.
The address unit computes 20-bit physical address based on the 16-bit contents
of a segment register and a 16-bit offset just like an 8086.
The CS, DS, SS and ES registers are used to hold the base addresses for the
segments currently in use.
The instruction pointer IP, stack pointer SP is used to hold the offset for code
segment and stack segment respectively.

3. Execution Unit:
The execution unit includes ALU, registers (same as on 8086 and 80186) and
the CPU. The registers consists general purpose registers, index registers,
pointer registers, flag register and the 16-bit machine status word (MSW)
register.
4. Instruction Unit:
It includes an instruction decoder and a three decodedinstructions queue.
The instruction unit decodes unto three prefetchedinstructions and holds
them in the queue.
5. Flag Register:
The flag register of 80286 consists of two new flags: NT, IOPL.
1) NT (Nested flag): This flag is set when one system task invokes another task.
2) IOPL (110 Privilege level) : The two bits in the IOPL are used by the processor
and the operating system to determine your application‘s access to
I/Facilities.

61
 Figure 2.41 Bit Patterns of 80286 status word and flag register

2.9.1.4 Operating Modes of 80286

2.9.1.4.1 80286 Real Address Mode
It can access up to 1 Mbyte of physical memory.
Physical memory addresses are produced directly by adding an offset to a
segment base.
The interrupt vector table of the 80286 is located in the first 1 Kbyte of memory.

The table 2.8shows the 80286 interrupt types and their vector locations.
2.9.1.4.2 80286 Protected Virtual Address Mode (PVAM)
The protection bit of the machine status word, (MSW) it is possible to switch
operation mode from REAL to PVAM.
The Protected Virtual Address Mode (PVAM) provides memory management,
protection, task switching and interrupt processing.
The Protected Virtual Address Mode is also called protected mode.

2.9.1.4.3 Physical Address Generation

Its virtual address consists of a16-bit selector and 16-bit offset.
The memory management unit (MMU) uses 14 most significant bits.
The descriptor contains the 24-bit physical baseaddress, the privilege level,
and some control bits for the segment.
If the memory access meets the privilege level test andthe segment is
present in the physical memory.
The MMU will add the 16-bit offset tothe 24-bit base address from the
descriptor to produce the 24-bit physical address.

62
 Table 2.8 Interrupt Types

Figure 2.42 Physical address generation mechanism

2.9.1.4.4 Segment Descriptors:

Each 80286 descriptor describes a 64-Kbyte memory segment and the 80286
allows16K (2N) descriptors.
The size of the each descriptor in the descriptor table is 8 byte.
The 80286 has segment descriptors for code, stack and data segments, and
system control descriptor for special system data segments and control
transfer operations.
Fig. 2.43 shows the code/data segment and system segment descriptors.
P bit indicate whether the segment is present in the physical
memory or not. DPL gives the descriptor privilege level.
63
 Type field indicates the type of segment such as executable, readable,
conforming, and writeable, expand down, and expandup .
Base field gives 24-bit segment base address and limit field specifies the
maximum length of the segment.

Figure 2.43 Descriptors

2.9.1.4.5 Descriptor Tables

The descriptors for different segments are stored in a table in memory called
descriptor table.
There are two types of descriptor tables
1. Global descriptor table
2. Local descriptor table.
A global descriptor contains the segment descriptors for the operating
system segments. A local descriptor is set up for each task or closely related
tasks in the system.
The protected mode of 80286 has a third descriptor table, called the Interrupt
Descriptor Table (IDT).
It is used to define up to 256 interrupts.
The IDT has a 24-bit physical base register and 16-bit limit register in the CPU,
These two registers are used to store 24-bit base address of IDT and its 16-
bit limit,This is illustrated in the Fig. 2.44.
The privileged LIDT (Load IDT) instruction loads these registers with a six byte
value. The IDT must be at least 256 bytes in size to allocate space for all
reserved interrupt.

64
Figure 2.44 Interrupt Descriptor table Definition

65
Functions of Protection Mechanism:
The main functions of the protection mechanism in the 80286 are:
1. To protect system software from user programs.
2. To protect user tasks from each other.
3. To protect the regions of memory from accidental access.
Privilege Levels
The 80286 has a four-level hierarchical privilege system.
Controls the use of Privileged instructions and access to
descriptors The table 2.9shows the four privilege levels.

Table2. 9Four Privilege Levels

2.9.280386 Microprocessor
A feature of the 80386DX is its ability to operate in three different modes:
1. Real Address Mode
2. Virtual 8086 Mode
3. Protected Virtual 8086 Mode.
2.9.2.1 80386 Features:
1) The 80386 is a 32-bit processor. The 32-bit ALU allows to process 32-bit data.
2) It has 32-bit address bus.
3) The 80386 runs with speed up to20 MHz instructions per second.
4) The pipelined architecture of the 80386, allows simultaneous
instructionfetching, decoding, execution and memory management.
5) It allows programmers to switch between different operating systems
6) It can operate on 7 different data types:
a. Bit b. Byte c. Word d. Double word e. word f. Quad word g. Ten byte.
7) The 80386 can operate in real mode, protected mode or a variation of
protected mode called virtual 8086 mode.
8) The 80386 microprocessor is compatible with their earlier 8086, 8088.

2.9.2.2 Architecture of 80386DX

The internal architecture of the 80386 consists of six functional units:
1) Bus Interface Unit
2) Code Fetch Unit
3) Instruction Decode Unit
4) Execution Unit
5) Segmentation Unit
6) Paging Unit

These units operate in parallel. Fetching, decoding, execution, memory

managementand bus accesses for several instructions are performed
simultaneously. This paralleloperation is called pipelined instructions processing. Fig.
2.45 shows instructionpipelining in 80386.

66
 Figure 2.45 Block Diagram for 80386

Figure 2.46 Instructions Pipelining in 80386

67
 Figure 2.47 Functional units of 80386

i) Bus Interface Unit

it provides a full 32-bit bi-directional data bus and 32-bit
address bus. The bus Interface unit is responsible for following
operations:
1) It accepts internal requests for code fetch and for data transfers from the
code fetch unit and from the execution unit.
2) It sends address, data and control signals to communicate with memory and I/O
devices.
3) It controls the interface to external L bus masters and coprocessors.
4) It also provides the address relocation facility.
ii) Code Prefetch Unit
The code prefetch unit fetches sequentially the instruction byte stream from
the memory. The code prefetch unit uses bus interface unit to fetch instruction
bytes.
Theseprefetched instruction bytes are stored in the 16-byte code queue.
If memory access iswithout any wait state, prefetch activity never delays
execution. Due to prefetch activityprocessor spends practically zero time
waiting for the next instruction.
iii) Instruction Decode Unit
The instruction decodes unit takes Instruction bytes from the code prefetch
queueand translates them into microcode.
The decoded instructions are then stored in the instruction queue.

iv) Execution Unit

The execution unit reads the instruction from the instruction queue and
executesthe instructions.
It consists of three subunits: Control Unit, Data Unit and Protection Test Unit.
1. Control Unit:
It contains microcode and special hardware.
The microcode and special hardware allows 80386DX to reduce time
required for execution of multiply and divide instructions.
It also speeds the effective address calculation.
2. Data Unit:
The data unit contains the ALU, eight 32-bit general purpose registers and a 64-
bit barrel shifter.
The barrel shifter is used for multiple bit shifts in one dock.
68
 The entire data unit is responsible for data operations requested by the control
unit.
3. Protection Test Unit:
The protection test unit checks for segmentation violations under the
control of the microcode.

69
 The execution unit partially supports pipelining.
It overlaps the execution of anymemory reference instruction with the
previous instruction.

v) Segmentation Unit
The segmentation unit translates logical addresses into linear.
The segmentation unit compares the effective address forthe length limit.
The segment unit adds the segmentbase and the effective address to
generate linear address.

vi) Paging Unit

The paging unit translates linearaddresses generated by the segmentation unit or
the code prefetching unit into physicaladdresses.

vii) 80386 Functional Units

Bus Interface Unit:
Responsible for memory access, I/O access, and coprocessor interface and
address relocation.
Code PrefetchUnit :
Responsible for instruction fetch
Instruction Decode Unit:
Responsible for instruction decode
Execution Unit:
Execute instruction with the help of control, Data and Protection Unit
Segmentation Unit:
Translates Logical address to, linear address andprovides segment level
protection.

2.9.2.3 Register set of 80386:

The 80386 register set can be categories according to their usage.

1) General purpose registers

2) Segment registers
3) Index, pointers and base registers
4) Flag registers
5) System address registers
6) Control registers
7) Debug registers

2.9.2.3.1) General purpose registers

The 80386 contains 32-bit general purpose register called EAX, EBX, ECX, EDX,
ESP, EBP, ESI, and EDI.
Fig. 2.48 shows the general purpose registers in 80386.
These 16-bit registers are accessed as AX, BX, CX, DX, SP, BP, SI, and, Dl
respectively. The AX, BX, CX and DX registers can be further divided into two
separate bytes:
Higher byte and lower byte.
For example: AX  AH + AL. These bytes can be individually accessed as AH,
AL, BH, BL, CH, CL, DH, and DL

70
Figure 2.48 80386 register set (part1)

Figure 2.49 80386 register set (part2)

71
 Figure 2.49(a) General Purpose register

The other four general purpose registers, are the two pointer registers, ESP
and EBP, and the two index registers, ESI and EDI.
They are used to store offset addresses of memory locations relative to the
segment registers.
The index registers ESI and EDI are used to store offset values to be
incremented or decremented when stepping through block of data.
The index registers are also used to hold offset addresses for instructions that
access data stored in the data segment part of memory.
The pointer register ESP and EBP are used to store offset addresses of
memory locations relative to the stack segment register.
2.9.2.3 2) Segment Registers
The 80386 has a 1M-byteaddress space in real mode.
The 80386supports six simultaneouslyaccessible memory blocks
calledsegments. A segment memory consisting of64K consecutive byte-
wide storagelocations.
These segments areaddressed by 16-bit registers: CS, DS, ES, SS, FS and GS.

72
 Figure 2.50 Segment Registers

1. The CS (Code Segment) register holds the base address of the currently active code
segment
2. The OS (Data Segment) is used to hold the address of currently active data
segment.
3. The ES (Extra Segment), F5, and GS are used as general data segment registers.
4. The base address of the currently active stack segment is contained in the
SS(Stack Segment)register.
2.9.2.3.3) Index Pointers, and Base Registers
The offset used tocalculate physical address is contained in any of the pointer1
base, or index registers.

Table 2.10 Segment and offset Register

2.9.2.3 4) Flag Register (EFLAG)
A Flag is a flip-flop which indicates some condition produced by the execution of
an instruction or controls certain operations of the EU.
The EFLAG register containsthirteen flags. Fig 2.51 shows the bit pattern of the
EFLAG register.
These flags can be categorized in three different groups.
1. Status flags: These flags reflect the state of a particular program.
2. Control flags: These flags directly affect operation of few instructions.
3. System flags: These flags reflect the current status of the
2.9.2.3 5) Status Flags:
The status flags are: CF (Carry flag), PF (Parity flag) AF (Auxiliary carry flag),
ZF (Zero flag), SF (Sign flag), and OF (Overflow flag).
These flags indicate some condition produced by the execution of arithmetic
or logical instructions.

73
 Figure2.51 Bit Pattern of Flag Register

CF (Carry flag):
This bit is set by arithmetic instructions that generate either acarry or a borrow.
Carry flag is also used in shift and rotate instructionsto contain the bit shifted
or rotated out of the register.

PF (Parity flag):
The parity bit is set by most instructions if the least significant 8bit of the
result contain even number of one‘s.AF (Auxiliary carry flag) :
The programmer can‘t access this bitdirectly, but this bit is internally used for
BCD arithmetic.

ZF (Zero flag):
Zero flag is set to 1, if the result of an operation is zero.

Figure 2.52 Sign and magnitude Representation

SF (Sign flag):
The signed numbers are represented by combination of sign
andmagnitude. The most significant bit (MSB) indicates sign of the
number.

2.9.2.3 .6)Control Flags

DF (Direction flag):
The direction flag controls the direction of stringoperations.
Offset pointers (usually ST and DI)are incremented by 1 after each operation in
the string instructions when D flag iscleared.
If the D flag is set, then SI and DI are decremented by I after each operationto
process strings from high to low memory.
2.9.2.3 7) SystemFlags:
VM (Virtual Memory) flag:
This flag indicates operating mode of 80386.
WhenVM flag is set, 80386 switches from protected mode to virtual 8086
mode.
R (Resume) flag:
This flag, when set allows selective masking of some exceptionsat the time of
debugging.
NT (Nested flag):
This flag is set when one system task invokes another task (i.e. nested task).
IOPL WO Privilege level) :

74
The two bits In the IOPL are used by the processor
The operating system to determine your application‘s access to I/O
facilities. Itholds privilege level, from O to 3

75
IF (Interrupt Flag) :
When interrupt flag is set, the 80386 recognizes and handles external
hardware interrupts on its INTR pin.
If the interrupt flag is cleared, 80386 ignore any inputs on this pin.
TF (Trap Flag) :
Trap flag allows user to single-step through programs.
When an80386 detects that this flag is set, it executes one instruction and then
automaticallygenerates an internal exception 1.
2.9.2.3.8) System Address Registers
there are four systems address register:
1) TR (Task Register),
2) IDTR (InterruptDescriptor Table Register)
3) GDTR (Global Descriptor Table Register)
4) LDTR (LocalDescriptor Table Register).

Figure 2.53 protection mode register

These registers hold the addresses for the four special descriptor table segments.
1) The TR (Task Register) points to the Task state segment
2) The EDTR (Interrupt Descriptor Table Register) points to the
InterruptDescriptor Table (IDT)
3) The GDTR (Global Descriptor Table Register) points to the Global
Descriptor Table (CDT)
4) The LDTR (Local Descriptor Table Register) points to the local Descriptor
Table(LDT)

2.9.2.3.9 Control Registers

There are four control registers: CRO. CRI, CR2 and CR3. Fig. 2.54 shows
control registers.
These registers define the machine state that affects all the tasks in the
systems.

Figure 2.54 Control register

Control Register O (CR0)

The CR0 holds the MSW (Machine Status
Word). It contains six status bits:
1) PE (Protection Enable),
2) MP (Math Present).
76
3) EM (Emulate Coprocessor),
4) TS (Task Switched),

77
 5) ET (Extension Type),
6) PG (Paging).
PE (Protection Enable) :
This bit is similar to the VM bit in EFLAGs
. It controls the 80386‘s mode of
operation.
MP (Math Present) :
When this bit is set, the 80386 assumes that real floatingpoint hardware
(80287 or 80387) is present in the system.
EM (Emulate Coprocessor):
When this bit is set, the 80386 will generate
anexception 11. It attempts to execute a floating
pointinstruction.
Programmer can use this exception handler to emulate floating pointhardware in
software.
TS (Task Switched) :
The 80386 sets the bit automatically every time it performs atask
switch. It will never clear this bit on its own
ET (Extension Type) :
80386 detect whether numericprocessor connected is 80287 or
80387 Sets ET to logic 1, if numeric processor is80387.
This is necessary because the 80387 uses a slightly different protocol than
80287.
PG (Paging) :
This bit enables or disables paging mechanism in MemoryManagement Unit
(MMU). If bit is set, paging is enabled.
Control Register 1 (CR1): This is reserved by Intel.
Control Register 2 (CR2):
CR2 is read-only register.
Control Register 3 (CRy):
Control register 3 holds the physical address of the root of the two-level
pagingtables used when paging is enabled.
It is also called Page Directory Base Register (PDBR).

2.9.2.3.10Debug Registers 7
The DR0 to DR, registersare used to control debug feature.
The debug registers DRO to DR3 contain addressesassociated with one of four
breakpoints
(DR,) Fig. 2.55 shows debug registers.
The software Debugger can load breakpointaddresses in these registers to aid in
debugging.

78
 Figure 2.55Debug register

Debug Registers O through 3:

The first four debug registers (DR0 - DR3) hold four linear addresses
forbreakpoints.
The addresses in these registers are compared with address of the
eachinstruction at the time of instruction execution
Ifa match is found, an exception 1 (debug fault) is generated.
Debug Registers 4 and 5
Registers 4 and 5 are undefined.
Debug Register 6
Debug register 6 is also called debug status register.
This register which gives information of the probable causes for the last
debugfault.

The status bits are:

BO (Breakpoint O):
The 80386 sets this bit when it references the linear addresscontained in
DR0. Conditions set by the LEN0, RW0, L0, and G0. LE and GE fields in DR.
B1-3 (Breakpoint P-3) :
These bits are similar to B0.
The linearaddress is referred from the respective debug register.
BD (Break for debug register access) :
The access for the debug registers can belocked by setting GD bit in DR7.
The BD bit, if set, allows to invoke exception 1handler, if processor tries to
access debug register eventhough the accessed is locked.
BS (Break for single step) :
This bit is set if the 80386 has invoked exception 1 since trace bit is set (TF bit
is set in EFLAGs)
BT (Break for task switch):
When a task is initiated who‘s trace bit is set, the80386 invokes an exception I
if BT bit is set.
Debug Register 7
It controls the debug feature. The debug operation of the four linear address
breakpoints. Each breakpointis controlled by a set of four fields. These are:
LO (Local Enable) :
When this bit is set, the breakpoint address in DR0 ismonitored as long as
80386 is executing current task.
GO (Global Enable) :
79
 When this bit is set, the breakpoint address in DR0 .
RWO (Read/Write access) :
This bit decides the type of access that must occur at the address in DR0.

80
Figure 2.56 gives the list of different access types.

Figure 2.56 RW Bit

LENO (Breakpoint length):

The breakpoints are further distinguished by its size.
The figure 2.57 shows thedifferent sizes of the breakpoints.

Figure 2.57 LEN Bits

There are in all four such fields (L. G, RW and LEN) for four breakpoints (B0-B3).
The DR7 contains three more bits. These are

LE (Local Exact):
The pipelined architecture of 80386 fetches, decodes nextinstruction before
the current one completes.
This bit appliesto all four linear breakpoints.
GE (Global Exact) :
This is similar to the LE bit.
If this bit is set, 80386 informsabout breakpoint at the instant it occurs
regardless of task
GD (Global debug access) :
When this bit is set, the 80386 denies the further access to any of the debug
registers, either for reading or writing.

2.9.2.3.11) Test Registers

It consists of eight test registers (TR0-TR7), only two test registers (TRTR7)
arecurrently defined.

Figure 2.58 Test Register

These registers are used to check translation look aside buffer (TLB) of the pagingunit.

Test Register 6:
The TLB testing command

81
 registers. TR6 is divided into fields
as follows:

C : This s a command bit. When this bit is cleared, awrite to the TLB is
performed.

82
 W (bit 5) : Not
writable W (bit 6)
: Writable
U (bit7) : Not
user U(bit8) :
User
13 (bit 9) : Not
dirty D(bitl0) :
Dirty
V (bit 11) : Valid

2.9.2.4 Data Types

The 80386DX is a 32-bit processor.
The 80386DX‘s 32-bit wide data path allows memory to be read and written 32-
bits at a time.
The 80386DX interpret the data it reads from memory in
different ways. The data can be interpreted as a signed value or
unsigned value.
Fig. 8.16 shows the data formats for signed and unsigned values.

BCD numbers:
The 803S6DX has the ability to perform four-function arithmetic on numbers
that are represented in binary-coded decimal (BCD).
The 80386DX can handle two different BCD formats:
1) Unpacked BCD
2) Packed BCD
BIT:
The 80386DX also supports BIT‖ data type.
The bit data type a Allows a program to directly access and modify any selected
bit within a bit string.
The 80386DX assembler supports eight instructions for bit
operations. These are: BT, BTC, BTS, BTR, BSF, BSR, IBTS, and
XBTS.

Figure 2.59 Signed and unsigned data types

Strings:
The 80386DX supports bit string, byte string, word string, and word strings.

83
2.9.2.5 Operating Modes of 80386:
Real Mode
The 80386 microprocessor can operate basically in either Real Mode, or
Protected Mode. The 80386 maintains the compatibility of the object code
with 8086 and 80286 running in real mode.
The 80386 can access the 32-bit register set of 80386DX.

84
 It is also possible to use addressing modes with the 32-bit override instruction
prefixes.

Protected Mode:
80386DX are unlocked when the 80386DX operates in Protected Mode.
Features of Protected Mode:
1. Protected Mode vastly increases the linear address space to four gigabyte (232
bytes)
2. It allows the running of virtual memory programs of almost unlimited size (64
terabytes or 2‘ bytes).
3. Protected Mode allows the 80386DX to run all of the existing 8086 and 80286
programs.
4. It provides a sophisticated memory management and a hardware-assisted
protection mechanism.
5. It provides special 80386 instructions for multitasking operating systems.
6. It supports paging mechanism.

Figure 2.60 Data types supported by 80386DX

Virtual 8086 mode:

In multitasking system, it is necessary to switch back and forth between real
and protected mode. In multitasking system, there is a mixture of tasks.
Use segment-offset addressing (Real mode addressing) and some use

85
descriptors (protected mode addressing). The 8086 virtual mode solves this
problem.

2.9.3 80486 Microprocessor:

86
2.9.3.180486 Processor Features

1. It is a highly integrated device containing about 1.2 million transistors.

2. The 80486 operates on 25 MHz, 33 MHz, 50 MHz, 66 MHz or 100 MHz.
3. It has built-in math coprocessor.
4. 80486 is a 32-bit architecture with on-chip memory management and cache
memory units.
5. On-chip cache memory allows reducing accesses to the external bus.
6. MMU consists of segmentation unit and paging unit.
7. The MMU provides four levels of protection
8. The 80486 has three modes of operation : Read mode, Protected mode and
Virtual 8086 mode.
9. It is available in two versions: 80486 DX and 80486SX.
10. Most of the 80486 instructions require only one clock instead of two clocks
required by the 80386.
11.It supports five-stage instruction pipeline scheme
12.It executes conditional JUMP instructions more efficiently.
13. It has built-in parity check/generator unit to implement parity detection and
generation for memory reads and writes.
14.It supports burst mode memory reads and writes to implement fast cache fills.
15. It executes a few new instructions that control the internal cache memory and
allow addition (XADD) and comparison (CMPXCHG) with an exchange and a
16.It supports built-in-self-test.
17.It has additional test registers (TR3 - TR5) to test the cache memory.

2.9.3.2Block Diagram of 80486

The Fig. 2.60 shows the block diagram of the internal architecture of the 80486.
It consists the execution unit, segmentation unit, paging unit, bus interface
unit, prefetch unit and decode unit are similar to the 80386 architecture.
The code queue in the prefetch unit has been doubled in size to 32 bytes.
This allows more instructions to be held on chip ready for decode and
execution.
Also an improved algorithm is now used by the translation look aside buffer in
the paging unit.
Finally, the bus interface unit has been modified to give the 80486.
Architecture a much faster and more versatile processor bus.
It is supported with additional parity checker/generator.
Parity checker/generator generates parity during each write cycle. Parity is
generated as an even parity and parity bit is provided for each byte of
memory
The cache unit of 80486 consists of an 8 Kbyte code and data cache.

Faster Floating Point Unit:

The floating-point unit has been completely redesigned over the 80486 CPU.
Faster algorithms provide up to ten tines speed-up for common operations
including add, multiply, and load.

Improved Cache Structure:

Pentium processors include separate code and data caches integrated on-chip
to meet performance goals.
Each cache is 8 Kbytes in size, with a 32-by Look aside Buffer TLB) to
translate linear addresses to physical addresses.
The data cache tags are triple ported to support two data transfers aid an
87
 inquire cycle in the same clock.
Individual pages can be configured as cacheable or non-cacheable by
software or hardware. The caches: A be enabled or disabled by software or
hardware.
Dual Integer Processor:

88
 Pentium processor has a dual integer
processor. It allows execution of two
instructions per clock.

Branch Prediction Logic:

The Pentium uses technique called branch prediction to check whether a branch
will be valid or invalid.

Data Integrity and Error Detection:

The Pentium processors are added significant data integrity and error
detection capability. Data part checking is still supported on a byte-by-byte
basis.
parity checking, and internal panty checking features have been added alone
with a new exception, the machine check exception.

Functional Redundancy Checking:

The Pentium processors have implemented functional redundancy
checking Toexecute in lock step with the ―master‘ processor.
The checker applies the masters outputs and compares those values with the
values the computes internally, and asserts an error signal if a mismatch
occurs

Enhancement Virtual 8086 Mode:

To increase performance by reducing the number of times it is necessary to
trap to a virtual 8086 monitor.

Superscalar Processor:
Processors capable of parallel instruction execution of multiple instructions are
known as superscalar processors.
Executing two integer or two floating point instructions simultaneously and thus
it support superscalar architecture.

89
 Figure 2.61 Block Diagram of 80486

2.9.4 Pentium Processor Architecture

Fig. 2.62showsinternal architecture of Pentium
program. There are two pipelines, the U pipeline and
the V pipeline.
The U-pipeline can execute all integers and floating point instructions.
The V pipeline can execute simple integer instructions and the FXCH floating-
point instructions.
Bus Unit
It consists of following functional entities:
Address Driven and Receivers:
During bus cycles the address drivers push the address onto the processors
local address bus (A31:A3 and BE7:BE,,).
The address bus transfers addresses back to the Pentium address
receivers during cache snoop cycles.
90
Only address lines A31:A5 are input during cache snoop cycles.

91
Write Buffers:
The Pentium processor provides two write buffers, one for each of the two
internal execution pipelines.
This architecture improves performance when back-to-back writes occur.

Figure 2.62 Block Diagram of Pentium processor

Data Bus Transceivers:

The transceivers send data onto the Pentium processors local data bus during
write bus cycles.
Receive data into the processor during read bus cycles.
Bus Control Logic:
The Bus Control Logic control whether a standard or burst bus cycle is to be
run.
Bus Master Control:
Bus Master control signals allow the processor to request the use of the

Level Two (U) Cache Control:

92
The Pentium processor includes the ability to control a (secondary) external
cache operation.

93
Internal Cache Control:
Internal Cache Control logic monitors input signals to determine when to
snoop the address bus and outputs signals
Parity Generation and Control:
It generates even data parity for each of the eight data paths
It also generates a parity bit for the address during write bus cycles
Code Cache
It holds copies of the most frequently used instructions,
It is dedicated to supplying instructions to each of the processor‘s execution
pipelines. The cache is organized as a two-way set associative cache.
Prefetcher
Prefetcher requests for Instructions from the code cache.
Prefetch Buffers
Pentium provides four prefetch buffers.
They work as two independent pairs. When instructions are prefetchedfrom
the cache, they are placed into one set of prefetchbuffers
Instruction Decode Unit
Pentium provides two stage decoding.
The instructions are decoded in two stages known as Decode I (Dl) and Decode
2 (D2).
Control Unit
It is also referred to as the Microcode Unit. This control unit consists of the
following sub- units:
1) Microcode Sequencer
2) Microcode Control ROM
Arithmetic Logic Units (ALUs)
Pentium provides two ALUs to perform the arithmetic and logical operations.
The ALU for the UM pipeline can complete and operation prior to the ALU in
the ―V‖ pipeline,
Address Generators
Pentium provides two Address Generators (one for each pipeline).
They generate the address specified by the instructions in their respective
pipeline.
Data Cache
A separate internal Data Cache holds copies of the most frequently used data
requested by the two integer pipelines and the Floating Point Unit.
The internal data cache is an 8KB write-back cache, organized as two-way set
associative with 32-byte lines.
The Data Cache directory is triple ported to allow simultaneous access from
each of the pipelines and to support snooping.
Paging Unit
It can handle two linear addresses at the same time to support both pipelines.
Floating-Point Unit
The floating point unit performs floating point operations.
It can accept up to two floating point operations per clock when one of the
instructions is an exchange instruction.

94
 Part-A (2 Marks Questions and Answers)
1. What are tightly coupled systems or closely coupled systems?
In a tightly coupled systems the microprocessor (either coprocessor
orindependent processors may share a common clock and bus control logic.. The
twoprocessors in a closely coupled system may communicate using a common
system busor common memory.

2. What are loosely coupled systems?

In loosely coupled systems each CPU may have its own bus control logic.
Thebus arbitration is handled by an external circuit, common to all processors.
Theloosely coupled system configuration like LAN & WAN can be spreader over a
largearea.

3. Write some advantages of loosely coupled systems over tightly coupled systems
More number of CPUs can be added in loosely coupled systems to improvethe
system performance. The system structure is modular and hence easy tomaintain
and troubleshoot.
A fault in a single module does not lead to a complete system breakdown.
Due to the independent processing modules used in the system, it is more
faulttolerant, more suitable to parallel applications due to its modularorganizations.

4. Write some disadvantages of loosely coupled systems

More complicated due to the required additional communication
hardware.They are less portable and more expensive due to the additional hardware
andthe communication media requirement.

5. What are the multi microprocessor configuration methods?

Tightly coupled systems or closely coupled systems
Loosely coupled systems

6. What is meant by Daisy chaining method?

It does not require any priority resolving network, rather the priorities of allthe
devices are essentially assumed to be in sequence.All the masters use a single bus
request line for requesting the bus access. Thecontroller sends a bus grant signal, in
response to the request, if the busy signal isinactive when the bus is free. The bus
grant pulse goes to each of the masters in thesequence till it reaches a requesting
master .The master then receives the grant signal,activates the busy line and gains
the control of the bus. The priority is decided by theposition of the requesting master
in the sequence.

7. What is independent bus request scheme?

Each of the masters requires a pair of request and grant pins which
areconnected to the controlling logic. The busy line is common for all the masters.
Thecontrolling logic receives a request on a bus request line, it immediately grants
thebus access using the corresponding bus grant signal, provided the BUSY line
isinactive, and then grants the request. This is quite fast, because each of the
masterscan independently communicate with the controller.

8. What are the functional units available in 8087?

CU-Control unit
NEU - Numeric execution unit.

9. What is meant by polling?

In polling schemes, a set of address lines is driven by the controller to
addresseach of the masters in sequence. When a bus request is received from a
95
device by thecontroller, it generates the address on the address lines. If the
generated addressmatches with that of the requesting masters, the controller
activates the BUSY line.

10. Name the data types of 8087.

Binary integer

96
 Wor
d
Shor
t
Long
Packed decimal
number(BCD) Floating point
/real number Short
Long
Temporary
real

11. Explain numeric processor 8087.

Numeric processor 8087 is a coprocessor which has been designed to
workunder the control of the processor 8086 and offer it additional numeric
processingcapabilities. It supports 16, 32, 64-bit integers 32, 64, 80-bit floating point
and 16digit BCD data types.

12. What are the three basic Multiprocessor Configurations that the 8086 can support?
i. Coprocessor Configuration
ii. Closely Coupled Configuration
iii.Loosely Coupled Configuration

13. What do you meant by Numeric Data Processor?

Numeric Data Processor is specially designed to perform arithmetic
operationsefficiently. It adds arithmetic, trigonometric, exponential and logarithmic
instructions to8086/8088 instruction set for all data types.

14. What are the functional blocks of 8089?

a. I/O Channels
b. Channel registers
c. Control Logic
d. Channel Control Pointer
e. ALU

15. Define coprocessor.(April /May 2011)

A processor, which can be connected with the mainprocessor in a parallel
manner, in order to do some complex problems, referred to as co-processor.

16. List the advantages of co-processor.(April / May 2014)

Speed operation
Can solve complex
problems Can be acted as
such processor

17. List the advantages of the multiprocessor configurations.

Improves cost/performance ratio of the system.
Several processors may be combined to fit the needs of an application while
avoiding the expense of the unneeded capabilities of a centralized system.
Tasks are divided among modules if failure occurs, it is easier and cheaper to
find and replace the malfunctioning processor than replacing the failing
part of the complex processor

97
18. How does CPU differentiate the 8087 instructions from its own instructions (May/June
2013)
The 8087 instructions can be distinguished from 8086 instructions by letter F which
stands for floating point number. All mnemonics in 8087 begins with the letter F.

98
19. What are the modes of operation of 8087? (May/June 2013)
1) Real Mode
2) Protected mode
3) Virtual mode
20. How 8089 operates in loosely coupled configuration and tightly coupled configuration
(May/June 2013)
In 8086 is used in its maximum mode. The 8089, 8086 reside on the same local bus,
sharing the same set of system buffers.

21. In what ways are the standard microprocessor and coprocessor differ from each other
(Nov/Dec 2012)
A processor provides auxiliary functions or features that the main processor does not
have. These might include floating point support or hardware encryption.A
coprocessor is generally not usable without its main processor, whereas a processor
may function in a crippled or less powerful form without a coprocessor. An example
of a processor and a coprocessor pair would be the 80386 and the 80486

22. What do you meant by CCW in an I/O processor? (Nov/Dec 2011)

CCW is the first byte of the control block, which indicates the action to be taken by
the channel.CCW consists of Parity bit ,Zero, Bus load limit, interrupt control field,
common field

23. Compare closely coupled configuration features with loosely coupled configuration
features. (May /June 2012)

SI.No Closely Coupled System Loosely Coupled System

1 It has common memory Each processor have
own private local memory
2 System structure is less flexible System structure is
more flexible
3 Parallelism can be implemented less Parallelism can be
efficiently implemented more
efficiently
4 Information can be shared among CPU Information is transferred
from
one processor to
other processor

24. When we are using closely coupled systems?

When high-speed or real processing is desired, closely coupled systems (CCS)
may be used. Thereare two models of a CCS:CCS without private cache.CCS with
private cache.

25. What are the two modes of DMA execution?

Slave Mode, Master mode

26. What is multiprogramming?

If more than one process is carried out at the same time, then it is know as
multiprogramming. Another definition is the interleaving of CPU and I/O operations
among several programs is called multiprogramming. To improve the utilization of
CPU and I/O devices, we are designing to process a set of independent programs
concurrently by a single CPU. This technique is known as multiprogramming.
Part-B (16 Marks Questions)
1. Explain in detail about various signals of 8086 microprocessor.(Refer Sec 2.1)
(Nov/Dec 2010)
99
2. Draw the internal block diagram of 8087 Co-processor and explain it with 8087
control word and status word formats.(Refer Sec 2.8.4.3) (May/June 2010)
3. Draw the block diagram of 8087 numeric Data processor and explain.(Refer Sec
2.8.4)(Nov
/Dec 2011, May/June 2013)

100
4. Discuss briefly the instructions supported by 8087 Numeric Data Processor.
(Refer Sec 2.8.6)(Nov /Dec 2011)
5. Explain the block diagram of 8089 I/O processor.(Refer Sec 2.8.4.7)(Nov /Dec 2011,
2012 and May/June 2010.2012,2014)
6. Explain the salient features of 8087 coprocessor units in architectural diagram
(Refer Sec 2.8.4.1)(Nov /Dec 2011)
7. Describe maximum mode of operation of 8086 (Refer Sec 2.2.2) (May/June 2013)
8. Draw and discuss a typical minimum mode 8086 system (Refer Sec 2.2.1) (May/June
2013)
9. Give two examples of 8087 data transfer instructions, arithmetic instructions,
Processor control instructions and transcendental instructions.(Refer Sec 2.8.4.6)
(May/June 2012)

101