Computer Operation Cycle Register Set

ƒ Programmer accessible registers (R0 to R7 in

previous multi-cycle computer)

ƒ Other registers
• Registers in the register file accessible only to
microprograms (R8 to R15)
• Instruction registers (IR)
• Program counter (PC)
• Pipeline registers
• Processor status register (PSR: CVNZ state)
• Stack pointer (SP)
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Overview Operand Addressing

ƒ Computer architecture ƒ Operand: register value, memory content, or

ƒ Operand addressing immediate
• Addressing architecture
• Addressing modes ƒ Explicit address: address field in the
ƒ Elementary instructions instruction
• Data transfer instructions
• Data manipulation instructions ƒ Implied address: the location of operand is
ƒ Floating point computations
specified by the opcode or other operand
• Program control instructions address
ƒ Program interrupt and exceptions

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Three Address Instructions Two Address Instructions

ƒ Example: X=(A+B)(C+D) ƒ The first operand address also serves as the

ƒ Operands are in memory address symbolized by the
letters A,B,C,D, result stored memory address of X implied address for the result
MOVE T1, A M[T1] Å M[A]
ADD T1, A, B M[T1] Å M[A] + M[B] ADD T1, B M[T1] Å M[T1] + M[B]
ADD T2, C, D M[T2] Å M[C] + M[D] MOVE X, C M[X] Å M[C]
MUX X, T1, T2 M[X] Å M[T1] X M[T2]
OR ADD X, D M[X] Å M[X] + M[D]
ADD R1, A, B R1 Å M[A] + M[B] MUX X, T1 M[X] Å M[X] X M[T1]
ADD R2, C, D R2 Å M[C] + M[D]
MUX X, R1, R2 M[X]Å R1 X R2 ƒ 5 instructions
ƒ +: Short program, 3 instructions
ƒ -: Binary coded instruction require more bits to
specify three addresses

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2
 One Address Instructions Zero Address Instructions

ƒ Implied address: a register called an ƒ Use stack (FILO):

accumulator ACC for one operand and the • ADD TOS Å TOS + TOS-1
result, single-accumulator architecture • PUSH X TOS Å M[X]
LD A ACC Å M[A]
• POP X M[X] Å TOS
ADD B ACC Å ACC + M[B]
PUSH A TOS Å M[A]
ST X M[X] Å ACC
PUSH B TOS Å M[B]
LD C ACC Å M[C] 7 instructions ADD TOS Å TOS + TOS-1
ADD D ACC Å ACC + M[D] PUSH C TOS Å M[C]
MUX X ACC Å ACC X M[X] 8 instructions
PUSH D TOSÅ M[D]
ST X M[X] Å ACC ADD TOS Å TOS + TOS-1
ƒ All operations are between the ACC register MUX TOS Å TOS X TOS-1
POP X M[X] Å TOS
and a memory operand
ƒ Data manipulation operations: between the stack
elements
ƒ Transfer operations: between the stack and the memory
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Stack Instructions Addressing Architecture

ƒ Defines:
• Restriction on the number of memory addresses in instructions
Memory • Number of operands
Address ƒ Two kinds of addressing architecture:
• Memory-to-memory architecture
ƒ Push: 100 ƒ Only one register - PC
• SP Å SP-1; TOS Å R1 SP=101 ƒ All operands from memory, and results to memory
C 101
ƒ Many memory accesses
ƒ Pop:
B 102
• R1 Å TOS; SP Å SP +1 • Register-to-register (load/store) architecture
R1 A 103 ƒ Restrict only one memory address to load/store types, all other
operations are between registers
104 LD R1, A R1 Å M[A]
LD R2, B R2 Å M[B]
ADD R3, R1, R2 R3 Å R1 + R2
LD R1, C R1 Å M[C]
LD R2, D R2 Å M[D]
ADD R1, R1, R2 R1 Å R1 + R2
MUL R1, R1, R3 R1 Å R1 X R3
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ST X, R1 M[X] Å R1 16

Addressing Modes Addressing Modes

ƒ Address field: contains the information needed ƒ Implied mode - implied in the opcode, such as stack,
to determine the location of the operands and accumulator
the result of an operation ƒ Immediate mode (operand) - a = 0x0801234
ƒ Addressing mode: specifies how to interpret ƒ Register mode - a=R[b]
the information within this address field, how to ƒ Register-indirect mode – a =M[R[b]]
compute the actual or effective address of the ƒ Direct addressing mode - a = M[0x0013df8]
data needed. ƒ Indirect Addressing mode - a= M[M[0x0013df8]]
ƒ Availability of a variety of addressing modes ƒ PC-relative addressing – branch etc. (offset + PC)
lets programmers write more efficient code ƒ Indexed addressing - a=b[1]

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3
 PC=250
Example ADRS or NBR =500 R1=400 Overview
ACC
Addressing Symbolic Register transfer Effective Content
mode conversion address of ACC
250 Opcode Mode
ƒ Computer architecture
251

Immediate LDA #NBR ACCÅNBR - 500

ƒ Operand addressing
252 Next instruction
• Addressing architecture
• Addressing modes
Register LDA R1 ACCÅR1 - 400
400 700

Register- LDA (R1) ACCÅM[R1] 400 700

indirect 500 800 ƒ Elementary instructions
Direct LDA ADRS ACCÅM[ADRS] 500 800 • Data transfer instructions
Indirect LDA [ADRS] ACCÅM[M[ADRS]] 800 300
750 600 • Data manipulation instructions
ƒ Floating point computations
Relative LDA $ADRS ACCÅM[ADRS+PC] 750 600
800 300
• Program control instructions
900 200 ƒ Program interrupt and exceptions
Index LDA ACCÅM[ADRS+R1] 900 200
ADRS(R1)

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Instruction Set Architecture Data Transfer Instructions

RISC (reduced CISC (complex instruction ƒ Data transfer: memory ÅÆ registers, processor
instruction set set computers) registers ÅÆ input/output registers, among the
computers) processor registers
Memory restricted to load/store is directly available to most
access instructions, and data types of instructions ƒ Data transfer instructions
manipulation instructions are
Name Mnemonic
register-to-register
Load LD
Addressing limited in number substantial in number Store ST
mode Move MOVE
Instruction all of the same length of different lengths Exchange XCH
formats Push PUSH
Instructions perform elementary perform both elementary and Pop POP
operations complex operations Input IN
Output OUT
Control unit Hardwired, high throughput Microprogrammed, facilitate
and fast execution compact programs and
conserve memory, 21 22

I/O Data Manipulation Instructions

Arithmetic Logical and bit Shift instructions

ƒ Input and output (I/O) instructions transfer manipulation
data between processor registers and I/O Name Mnemo Name Mnem Name Mnem
devices nic onic onic

• Ports
Increment INC Clear CLR Logical shift right SHR
Decrement DEC Set SET Logical shift left SHL

ƒ Independent I/O system: address range Add ADD Complement NOT Arithmetic shift right SHRA

assigned to memory and I/O ports are Subtract SUB AND AND Arithmetic shift left SHRL
Multiply MUL OR OR Rotate right ROR
independent from each other Divide DIV Exclusive-OR XOR Rotate left ROL

ƒ Memory-mapped I/O system: assign a Add with carry ADDC Clear carry CLRC Rotate right with
carry
RORC

subrange of the memory addresses for Subtract with SUBB Set Carry SETC Rotate left with ROLC
borrow carry
addressing I/O ports Subtract reverse SUBR Complement COMC
carry
Negate NEG

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4
Floating-Point Computation Recall Scientific Notation
decimal point exponent
ƒ What can be represented in N bits? (Sign, magnitude)

Unsigned 0 to 2N-1 23 -24

6.02 x 10 1.673 x 10
2s Complement -2N-1 to 2N-1 - 1
1s Complement -2N-1+1 to 2N-1-1
Mantissa radix (base)
BCD 0 to 10N/4 - 1
ƒ But, what about? (Sign, magnitude) e - 127
ƒ Issues: IEEE F.P. ± 1.M x 2
• very large numbers? • Representation, Normal form
9,349,398,989,787,762,244,859,087,678
• very small number? 0.0000000000000000000000045691 • Range and Precision
• rationals 2/3
• Arithmetic (+, -, *, / )
• irrationals 2
• Rounding
• transcendentals e • Exceptions (e.g., divide by zero, overflow, underflow)
• Errors
• Properties (negation, inversion, if A z B then A - B z 0 )
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Floating-Point Numbers

ƒ Representation of floating point numbers in IEEE 754 standard:

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•single precision sign S E M
exponent: mantissa:
Biased exponent: binary integer sign + magnitude, normalized
actual exponent is binary significand w/ hidden
e = E – 127 (0 < E < 255) integer bit: 1.M
S E-127
N = (-1) 2 (1.M)

0 = 0 00000000 0 . . . 0 -1.5 = 1 01111111 10 . . . 0

ƒ Exponent field (E):
E=0 reserved for zero (with fraction M=0), and denormalized #s (M z 0)
E=255 reserved for rf (with fraction M=0), and NaN (M z 0)
ƒ Magnitude of numbers that can be represented is in the range: (with E in
[1, 254]):
2-126 (1.8 ҳ 10-38) ~ 2127 (2-2-23) (3.4 ҳ 1038)

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