Static and dynamic D flip-flops

Introduction to static and dynamic D flip-flops

Static and dynamic D flip-flops

Flip-flops can be categorised in the following ways

a) According to their inputs (functions)

RS flip-flops (R = Reset, S = Set)

D flip-flops (D = Data)
JK flip-flops (J = Jump, K = Kill)
T flip-flops (T = Toggle)

b) According to the type of triggering they use (time response) in

Unclocked (static) flip-flops (static flip-flops)

Clocked status-triggered flip-flops (static flip-flops)
Clocked edge-triggered flip-flops (dynamic flip-flops)

Design and function

Bistable multivibrators can be implemented using discrete components or by means of binary logic
gates (TTL standard gates). The following observations apply solely to binary logic gates.
NAND gates form the basis for all flip-flops. However, using NAND gates means that the resulting
flip-flop is set with a low logic level and also reset by a low signal. The save-and-hold state occurs
when both inputs are set to high.
Training contents
After completing this experiment, students should be able to accomplish the following:

Construct a clocked (static) D flip-flop using NAND gates

Realise that a D flip-flop can be developed from a clocked RS flip-flop whereby an inverted copy of the set signal
is applied to the reset input
Draw a truth table and the circuit symbol for a D flip-flop
Set up a D flop-flop triggered by a positive edge using two NOR gates, three NAND gates and two
AND/NAND gates
Use a timing diagram to identify the key differences between a static and a dynamic D flip- flop
Draw a truth table and the circuit symbol for a dynamic D flip-flop

Prerequisites
Prerequisites for successful completion of this course:

Knowledge of basic circuits

Compiling truth tables
Plotting timing diagrams
 Experiment: Static D flip-flop

This first experiment involves construction of a static D flip-flop.

Circuit diagram

Virtual instruments

Set the instruments to 8 bits and the display to decimal (DEC).

Experiment set-up
Evaluation

Observe the response of the circuit and enter the results into the table. To set up the circuit,
use the digital inputs and outputs of the UniTrain-I Interface.

Truth table:

When the state is indeterminate, simply enter an (x).

D Cp Output(Q) Output(Q')
0 0
0 1
1 0
1 1

Which of the three signal timing plots in the timing diagram correspond to the static signal
timing plot for output Q?

Signal plot Q1
Signal plot Q3

Signal plot Q2
 Experiment: Dynamic D flip-flop

In the second experiment of this particular set, a dynamic D flip-flop is to be constructed.

Circuit diagram

Virtual instruments

Set the instruments to 8 bits and the display to decimal (DEC).

Experiment set-up
Evaluation

Observe the response of the circuit and enter the results into the table. To set up the circuit,
use the digital inputs and outputs of the UniTrain-I Interface.

Truth table:

When the state is indeterminate, simply enter an (x), for a rising edge use ( ) and for a falling
edge use ( ).
Which of the three signal plots in the timing diagram corresponds to the dynamic signal at
output Q?

Signal plot Q1

Signal plot Q2

Signal plot Q3
JK flip-flops
 Introduction to JK flip-flops

JK flip-flops
JK flip-flops belong to the clocked flip-flop category.

Clocking, in this case, means that it is only possible to change the output of the flip-flop in conjunction with a clock signal.
This makes the circuit more resistance to faults but makes the circuit more complicated. A distinction is made between two
types of clocked flip-flops, one using a single edge for triggering and another which utilises two edges.

JK flip-flops are triggered by a single edge, in this case a falling edge. This only allows the output to change when a falling
edge occurs at the C input. This means we can consider the clock input C and the two inputs J and K to be linked by an
AND operation.

The designations "J" for the set input and "K" for the reset are said to derive from Jump and Kill. In addition to these inputs,
there is also a static input "S". This is a dominant set input, which thus overwrites all previous resulting states. This input is not
edge-controlled.

The static (asynchronous) input S and the clock

input C are inverted inputs (active low), i.e. the
function is activated by a low signal at the input.
The clock input responds to a falling edge (a
change in the clock signal from HIGH to LOW).

Training contents
After completing this experiment, students should be able to accomplish the following:

Describe the functioning of a JK flip-flop triggered by a single edge on the basis of signal
timing diagrams they have made themselves
Discover that the preparatory signals, R or S can have an effect independent of the clock
signal and the data inputs (J and K), i.e. that they are static
Draw up a simplified form of the truth table for a single-edge-triggered JK flip-flop and use
the standard circuit symbols
Wire up a JK flip-flop to make it into a D flip-flop and into a T (toggle) flip-flop
Prerequisites
Prerequisites for successful completion of this courses

Compiling truth tables

Knowledge of basic circuits
 Experiment: JK flip-flop

This experiment involves setting up a JK flip-flop controlled by a single edge

Circuit diagram

Virtual instruments

Set the instruments to 8 bits and the display to decimal (DEC).

Experiment set-up
Evaluation

Observe the response of the circuit and enter the results into the table. To set up the circuit,
use the digital inputs and outputs of the UniTrain-I Interface.

Truth table:

When the state is indeterminate, simply enter an (x), for a rising edge use ( ) and for a falling
edge use ( ).

What sort of JK flip-flop is this?

This JK flip-flop is triggered by a single edge. The active clock-edge is rising (a positive edge).

This JK flip-flop is triggered by a single edge. The active clock-edge is falling (a negative edge).
This JK flip-flop is triggered by two edges. The active clock-edge is rising (a positive edge).
Set both the data inputs "J" and "K" simultaneously and maintain a logical "1" signal to them for the

duration of the experiment, while you repeatedly apply a clock signal. How do the circuit's outputs

behave?

The signal outputs always go to the same state whenever an active edge is applied.
The signal outputs always change to the opposite state on every second active edge.
The signal outputs always change to the opposite state whenever an active edge is applied.

Modify the circuit in such a way that the K input is connected to the J input by an inverter. What sort

of operating mode does this create?

With the inputs connected in this way, the JK flip-flop turns into a D flip-flop.
With the inputs connected in this way, the JK flip-flop turns into an RS flip-flop.
With the inputs connected in this way, the JK flip-flop stops working at all.

Which of these characteristics matches the signal at output Q?

Characteristic Q1
Characteristic Q2

Characteristic Q3
JK master-slave flip-flops
 Introduction to JK master-slave flip-flops

JK master-slave flip-flops
Unlike a simple JK flip-flop, a JK master-slave flip-flop is triggered by two edges. This means that both rising and falling edges are
registered at the clock input C and processed by the flip-flop. A rising edge causes the inputs to be read in and processed. The
results are then output only when a falling edge arrives. Therefore, to change the outputs only requires a single complete clock
cycle. A clock cycle always includes one rising edge and one falling edge.

S and the clock input C are inverted inputs (active

low), i.e. a low signal at the in0put activates the
function. The clock input responds to both rising
and falling edges.

Training contents

After completing this experiment, students should be able to accomplish the following:

Describe the function of a JK flip-flop triggered by two edges (a pulse-triggered flip-flop) by means of signal timing diagrams
they have put together themselves
Identify the difference between flip-flops triggered by one or two edges

Prerequisites
Prerequisites for successful completion of this courses

Plotting timing diagrams

Knowledge of basic circuits
 Experiment: JK master-slave flip-flop

In this experiment, the circuit for a JK master-slave flip-flop is to be built.

Circuit diagram

Virtual instruments

Set the instruments to 8 bits and the display to decimal (DEC).

Experiment set-up
Evaluation

Observe the response of the circuit and enter the results into the table. To set up the circuit,
use the digital inputs and outputs of the UniTrain-I Interface.

Truth table:

When the state is indeterminate, simply enter an (x). For a clock signal use ( ).

Which of these characteristics matches the signal timing at output Q?

Characteristic Q1
Characteristic Q2

Characteristic Q3