Qucs

A Tutorial
Transient Domain Flip-Flop Models for Mixed-Mode
Simulation

Mike Brinson

Copyright
c 2006 Mike Brinson <mbrin72043@yahoo.co.uk>

Permission is granted to copy, distribute and/or modify this document under the
terms of the GNU Free Documentation License, Version 1.1 or any later version
published by the Free Software Foundation. A copy of the license is included in
the section entitled ”GNU Free Documentation License”.
Introduction
One of the primary aims of the Qucs project is the development of a universal
circuit simulator that allows circuit performance to be investigated from DC to
microwave frequencies. Adding performance analysis in the digital domain makes
Qucs a truly universal simulator. Qucs 0.0.8 was the first release to include digi-
tal simulation. Qucs digital simulation centres around VHDL using the FreeHDL
VHDL compiler to generate a machine code simulation of a circuit under test. Re-
lease 0.0.8 includes built-in models for the basic digital gates and a number of the
common sequential flip-flops. The Qucs gate models can be used in both digital
and transient simulation. Unfortunately, the flip-flop models are only available
in digital simulation. The current version of Qucs models flip-flops using VHDL
and does not provide time domain models for transient simulation. This is an
important omission which limits the Qucs simulator mixed-mode simulation ca-
pabilities. Mixed-mode simulation is a term commonly employed to describe the
simulation of circuits that contain both analogue and digital components. In the
real world circuits are, of course, not subdivided into neat boxes labelled analogue,
S-parameter, digital or any other physical domain. So it is of some importance
that Qucs device modelling be developed to allow circuits consisting of a range of
different analogue and digital components, to be simulated at the same time. Nor-
mally such systems are simulated in the time domain using large signal transient
simulation. Performance data being both analogue and digital expressed in tabu-
lar or graphical form. This tutorial note presents a number of transient simulation
models for flip-flops based on structural digital circuits, describes their use, and
outlines a number of example simulations derived from practical circuits.

Latches and flip-flops

Sequential digital devices generically known as flip-flops (SR, D, JK and T types)
are commonly classified into three major groups.
• Latches: basic or gated

• Pulse triggered flip-flops: master slave devices with or without data-lockout

• Edge-triggered flip-flops: leading or trailing edge triggered.

As the speed of electronic systems has increased so has the popularity of the
single edge-triggered flip-flops over the slower master slave devices. Today most
IC designs are based on D type edge-triggered devices rather than the earlier JK
master slave devices. Our concern here is the development of a consistant set of
models that allow the common flip-flops to be modelled accurately, and reliably,

1
in the transient time domain. In order to keep these models simple the D gated
and edge-triggered devices have been chosen as the fundamental building blocks
for the transient domain Qucs models. Using basic Boolean logic concepts it is
straightforward to show that JK and T edge-triggered flip-flop models can be
derived from the D flip-flop models.

The gated D latch

The circuit diagram for a gated D latch constructed from two input nand gates
is shown in Fig. 11 . Outputs Q and not Q (QB in Fig. 1) are derived from the
two cross coupled nand gates connected as a basic SR nand latch. Fig. 2 shows
the performance characteristics for this circuit. These were obtained using the
simple test configuration shown in Fig. 3. Logic one digital signals are represented
by 1V and logic 0 signals by 0V in the transient analysis domain. Propagation
delays through the various circuit gates can be set by changing the delay time
for each gate. Cross coupled gates are often a cause of simulation failure due to
the fact that DC analysis fails to converge to a stable solution at the start of
a transient simulation. One approach that helps to force a stable DC solution
is to set Q and QB to known values, say logic 0 and logic 1, at the start of
a simulation. In circuits like the basic gated D latch shown in Fig. 1, where
asynchronous set and reset inputs are not included, this is not possible. However,
flip-flops with asynchronous set and reset inputs do allow the state of a flip-flop
to be determined at a given time in a simulation. In the examples that follow,
whenever possible, the state of the latch or flip-flop devices is set at the start of a
simulation. In the majority of the example circuits, device delays have also been
set to zero. It therefore follows that most waveform plots show functional data
rather than accurate timing characteristics. In many mixed-mode simulations the
digital elements present in a design are often modelled as functional devices whose
primary task is to generate the signals needed for the overall circuit to function. A
more detailed discussion of the effects on transient simulation caused by including
device timing delays is presented in a later section of these notes.

1
Richard S. Sandige, Modern Digital Design, 1990, McGraw-Hill International Editions.

2
 D

& Q
&
D
times=20ns; 20ns
Y3
C Y1
QB
&
C &
times=5ns; 5ns
&
Y2
Y4
Y5

transient
simulation

TR1
Type=lin
Start=0
Stop=100 ns

Figure 1: Gated D latch with digital signal generators D and C

1
D.Vt

0
0 2e-8 4e-8 6e-8 8e-8 1e-7 1.2e-7 1.4e-7 1.6e-7 1.8e-7 2e-7
time
1
C.Vt

0
0 2e-8 4e-8 6e-8 8e-8 1e-7 1.2e-7 1.4e-7 1.6e-7 1.8e-7 2e-7
time

1
Q.Vt

0 2e-8 4e-8 6e-8 8e-8 1e-7 1.2e-7 1.4e-7 1.6e-7 1.8e-7 2e-7
time

1
QB.Vt

0 2e-8 4e-8 6e-8 8e-8 1e-7 1.2e-7 1.4e-7 1.6e-7 1.8e-7 2e-7
time

Figure 2: Gated D latch simulation waveforms

3
 D Q

D Q transient
simulation
D
C QB
TR1
C Q Type=lin
C SUB1 Start=0
Num=2 File=gated_d_latch.sch Stop=200 ns

Figure 3: Gated D latch test circuit

4
Edge-triggered D type flip-flop
The schematic for a positive edge-triggered D flip-flop is shown in Fig. 42 . Asyn-
chronous set (SET) and reset (RESET) control inputs allow the flip-flop outputs
Q and not Q (QB in Fig. 4) to be set to known values at the start of a simulation.
The nand gates forming each of the cross coupled SR latches have their delay times
set at 0 ns. The edge-triggered D device is a building block for both the JK and
T types of flip-flop. A typical set of transient simulation test results for the D
flip-flop model are illustrated in Fig. 5. These where obtained using the basic test
configuration shown in Fig. 6.

SET

&
SET

Y7
I0

RESET & Q Q
&
I1
RESET Y10
CLOCK Y8

QB
& I2 &
CLOCK
Num=1 QB

Y11 Y2

I3

&
DIN

DIN Y9
Num=2

Figure 4: Positive edge-triggered D flip-flop circuit

2
David A. Hodges and Horace G. Jackson, Analysis and Design of Digital Integrated Circuits,
1998, Second edition, McGraw-Hill Book Company.

5
 1
R.Vt

0
0 5e-8 1e-7 1.5e-7 2e-7 2.5e-7 3e-7 3.5e-7 4e-7 4.5e-7 5e-7
time

1
DIN.Vt

0
0 5e-8 1e-7 1.5e-7 2e-7 2.5e-7 3e-7 3.5e-7 4e-7 4.5e-7 5e-7
time
CLOCK.Vt

0
0 5e-8 1e-7 1.5e-7 2e-7 2.5e-7 3e-7 3.5e-7 4e-7 4.5e-7 5e-7
time

1
Q.Vt

0 5e-8 1e-7 1.5e-7 2e-7 2.5e-7 3e-7 3.5e-7 4e-7 4.5e-7 5e-7
time

1
QB.Vt

0 5e-8 1e-7 1.5e-7 2e-7 2.5e-7 3e-7 3.5e-7 4e-7 4.5e-7 5e-7
time

Figure 5: Transient waveforms for the circuit shown in Fig. 6

1
DIN SUB2
S Q
D Q transient
S4 simulation
times=40ns; 40ns
CLOCK QB TR1
Q Type=lin
R Start=0
S2
times=5ns; 5ns Stop=500 ns
SUB1
R

S3
times=20ns; 1000ns

Figure 6: D flip-flop test circuit

6
The edge-triggered JK flip-flop
A leading edge-triggered JK flip-flop can be constructed using a positive edge-
triggered D flip-flop and external logic3 . The external logic generates the required
JK flip-flop characteristic equation given by

Q+ = J.Q + K.Q
Were Q, Q, J and K are the current state values of the device signals and Q+ is
the next state value of Q following the rising edge of the device clock pulse. The
schematic diagram for the edge triggered flip flop is shown in Fig. 7 and a typical
set of test waveforms in Fig. 8. These were obtained using the test circuit shown
in Fig. 9.

SET Q
&
1 S
D Q
J Y1 QB
Y2

CLOCK
1 Q
&
R
K
Y4
Y3 SUB1
File=dff_sr.sch
RESET

Figure 7: Positive edge-triggered JK flip-flop circuit

3
M. Morris Mano and Charles R Kime, Logic and Computer Design Fundamentals, 2004,
Third edition, Pearson Education International, Prentice Hall

7
RESET.Vt 1

0
0 1e-8 2e-8 3e-8 4e-8 5e-8 6e-8 7e-8 8e-8 9e-8 1e-7
time

1
CLOCK.Vt

0
0 1e-8 2e-8 3e-8 4e-8 5e-8 6e-8 7e-8 8e-8 9e-8 1e-7
time

1
Q.Vt

0 1e-8 2e-8 3e-8 4e-8 5e-8 6e-8 7e-8 8e-8 9e-8 1e-7
time

1
QB.Vt

0 1e-8 2e-8 3e-8 4e-8 5e-8 6e-8 7e-8 8e-8 9e-8 1e-7
time

Figure 8: Transient waveforms for the circuit shown in Fig. 9

1
SUB2

Q
S
J Q transient
CLOCK simulation

TR1
CLOCK QB Type=lin
Num=1 K Q Start=0
R Stop=100 ns

RESET SUB1

RESET

Figure 9: JK flip-flop test circuit showing JK operating in toggle mode

8
The edge-triggered T flip-flop
The characteristic equation for a leading edge-triggered flip-flop is4

Q+ = T ⊕ Q
where the symbols have the same meaning as the JK flip-flop. The circuit dia-
gram, test waveforms and test circuit for the edge-triggered flip-flop are given in
Figures 10 to 12.

SET

SET
TFF QQ
=1 S
D Q
TFF Y1
CLOCK QB
QB

Q
CLOCK
R

R SUB1
File=dff_sr.sch

Figure 10: Positive edge-triggered T flip-flop circuit

4
See footnote 2.

9
 1
SET.Vt

0
0 2e-8 4e-8 6e-8 8e-8 1e-7 1.2e-7 1.4e-7 1.6e-7 1.8e-7 2e-7
time
1
CLOCK.Vt

0
0 2e-8 4e-8 6e-8 8e-8 1e-7 1.2e-7 1.4e-7 1.6e-7 1.8e-7 2e-7
time
1
TFF.Vt

0
0 2e-8 4e-8 6e-8 8e-8 1e-7 1.2e-7 1.4e-7 1.6e-7 1.8e-7 2e-7
time

1
Q.Vt

0 2e-8 4e-8 6e-8 8e-8 1e-7 1.2e-7 1.4e-7 1.6e-7 1.8e-7 2e-7
time

1
QB.Vt

0 2e-8 4e-8 6e-8 8e-8 1e-7 1.2e-7 1.4e-7 1.6e-7 1.8e-7 2e-7
time

Figure 11: Transient waveforms for the circuit shown in Fig. 12

SET

transient
SET
simulation
times=10 ns; 1000 ns
TFF Q TR1
S
T Q Type=lin
Start=0
T1 QB Stop=200ns
times=30 ns; 60 ns IntegrationMethod=Trapezoidal
Q
CLOCK Order=2
R

CLOCK 1
times=5 ns; 5 ns
SUB2
SUB1 File=Logic_one.sch
File=tff.sch

Figure 12: T flip-flop test circuit

10
Two example digital circuits
• A synchronous BCD up-counter: Figure 13 shows a synchronous BCD
up-counter constructed from four edge-triggered JK flip flops connected as
toggle flip-flops. The input signal waveforms and the corresponding counter
outputs Q0, Q1, Q2 and Q3 are illustrated in Fig. 14. These simulation
results were obtained using the default trapezoidal integration method with
order 2.
SUB5
& & &
1

File=Logic_one.sch

Y1 Y2 Y3
Q0 Q1 Q2 Q3
S S S S
J Q J Q J Q J Q

CLOCK

K Q K Q K Q K Q
R R R R
CLOCK
times=5 ns; 5ns

COUNT &
SUB1 SUB2 SUB3 SUB4
File=jkff.sch File=jkff.sch File=jkff.sch File=jkff.sch
COUNT Y4
times=5 ns; 1000ns transient
simulation
CLEAR 1
TR1
CLEAR Type=lin
Num=3 Y5 Start=0
times=10 ns; 1000ns Stop=120ns
IntegrationMethod=Trapezoidal
Order=2

Figure 13: Synchronous BCD up-counter circuit

At the start of simulation signal CLEAR is set to logic 1 which in turn causes
the counter to be reset to 0000. Similarly signal COUNT has to be set to 1
for counting to take place. Notice that the counter counts from 0 to 9 and
then resets to 0.

• A simple state machine: Figure 15 shows a simple sequential state ma-

chine with input X and outputs Y1 and Y2. The outputs are synchronised
to the input clock. The state equations for this example are

J = X, K = 1, Y 1 = Q0.X, Y 2 = Q0

11
CLEAR.Vt

0
0 1e-8 2e-8 3e-8 4e-8 5e-8 6e-8 7e-8 8e-8 9e-8 1e-7 1.1e-7 1.2e-7
time
CLOCK.Vt

0
0 1e-8 2e-8 3e-8 4e-8 5e-8 6e-8 7e-8 8e-8 9e-8 1e-7 1.1e-7 1.2e-7
time
COUNT.Vt

0
0 1e-8 2e-8 3e-8 4e-8 5e-8 6e-8 7e-8 8e-8 9e-8 1e-7 1.1e-7 1.2e-7
time

1
Q0.Vt

0
0 1e-8 2e-8 3e-8 4e-8 5e-8 6e-8 7e-8 8e-8 9e-8 1e-7 1.1e-7 1.2e-7
time
1
Q1.Vt

0
0 1e-8 2e-8 3e-8 4e-8 5e-8 6e-8 7e-8 8e-8 9e-8 1e-7 1.1e-7 1.2e-7
time
1
Q2.Vt

0
0 1e-8 2e-8 3e-8 4e-8 5e-8 6e-8 7e-8 8e-8 9e-8 1e-7 1.1e-7 1.2e-7
time
1
Q3.Vt

0
0 1e-8 2e-8 3e-8 4e-8 5e-8 6e-8 7e-8 8e-8 9e-8 1e-7 1.1e-7 1.2e-7
time

Figure 14: Transient waveforms for the circuit shown in Fig. 13

12
 1
SUB4
X File=Logic_one.sch
Y2
1 S S
J Q D Q transient
X simulation
Y2 20ns
times=100ns;
TR1
Type=lin
K Q Q
R Start=0
CLOCK R Stop=350 ns
IntegrationMethod=Trapezoidal
SUB2
Order=2
CLOCK File=dff_sr.sch
times=5ns; 5ns
SUB1
File=jkff.sch

Y1
& S
D Q digital
simulation
Y1
Digi1
Type=TimeList
Q time=350 ns
R
RESET
SUB3
File=dff_sr.sch
RESET
times=15ns; 1000ns

Figure 15: A simple state machine

13
 1
CLOCK.Vt

0
0 2e-8 4e-8 6e-8 8e-8 1e-7 1.2e-7 1.4e-7 1.6e-7 1.8e-7 2e-7 2.2e-7 2.4e-7 2.6e-7 2.8e-7 3e-7 3.2e-7 3.4e-7
time
1
RESET.Vt

0
0 2e-8 4e-8 6e-8 8e-8 1e-7 1.2e-7 1.4e-7 1.6e-7 1.8e-7 2e-7 2.2e-7 2.4e-7 2.6e-7 2.8e-7 3e-7 3.2e-7 3.4e-7
time
1
X.Vt

0
0 2e-8 4e-8 6e-8 8e-8 1e-7 1.2e-7 1.4e-7 1.6e-7 1.8e-7 2e-7 2.2e-7 2.4e-7 2.6e-7 2.8e-7 3e-7 3.2e-7 3.4e-7
time

1
Y1.Vt

0 2e-8 4e-8 6e-8 8e-8 1e-7 1.2e-7 1.4e-7 1.6e-7 1.8e-7 2e-7 2.2e-7 2.4e-7 2.6e-7 2.8e-7 3e-7 3.2e-7 3.4e-7
time

1
Y2.Vt

0 2e-8 4e-8 6e-8 8e-8 1e-7 1.2e-7 1.4e-7 1.6e-7 1.8e-7 2e-7 2.2e-7 2.4e-7 2.6e-7 2.8e-7 3e-7 3.2e-7 3.4e-7
time

Figure 16: Transient waveforms for the circuit shown in Fig. 15

14
VHDL code for the transient domain flip-flop mod-
els
Although the primary purpose for developing the transient domain flip-flop mod-
els is the simulation of mixed-mode circuits, it is worth noting that because the
models have been constructed from Qucs gate primitives using a bottom-up de-
sign approach, Qucs can also use the models for digital simulation. Moreover,
provided the circuit being simulated does not contain any purely analogue compo-
nents Qucs will generate a VHDL model testbench that describes the function and
test sequence for the circuit being simulated. Shown in Fig. 17 is a digital timelist
waveform plot for the synchronous BCD up-counter introduced in the previous
section of these notes. Listing 1 lists the VHDL code generated by Qucs for the
synchronous BCD up-counter example.
dtime 0 5n 10n 15n 20n 25n 30n 35n 40n 45n 50n 55n 60n 65n 70n 75n 80n 85n 90n 95n
clear.X
count.X
clock.X
q0.X
q1.X
q2.X
q3.X

Figure 17: Digital TimeList waveforms for the circuit shown in Fig. 13

Listing 1: VHDL testbench code for the circuit shown in Fig. 13

−− Qucs 0 . 0 . 9
−− /mnt/ hda2 / D i g i t a l S u b c i r c u i t s p r j / Sync BCD counter . s c h

entity S u b L o g i c o n e i s
port ( nnout L1 : out b i t ) ;
end entity ;
use work . a l l ;
architecture Arch Sub Logic one of S u b L o g i c o n e i s
s i g n a l gnd ,
L1 : b i t ;
begin
gnd <= ’ 0 ’ ;
L1 <= not gnd ;
nnout L1 <= L1 or ’ 0 ’ ;

15
end architecture ;

entity S u b d f f s r i s
port (CLOCK: in b i t ;
DIN : in b i t ;
nnout Q : out b i t ;
nnout QB : out b i t ;
RESET: in b i t ;
SET : in b i t ) ;
end entity ;
use work . a l l ;
architecture A r c h S u b d f f s r of S u b d f f s r i s
s i g n a l I0 ,
I2 ,
I1 ,
I3 ,
QB,
Q : bit ;
begin
nnout QB <= QB or ’ 0 ’ ;
nnout Q <= Q or ’ 0 ’ ;
I 1 <= not (CLOCK and RESET and I 0 ) ;
I 3 <= not (DIN and I 2 and RESET ) ;
QB <= not (RESET and I 2 and Q) ;
Q <= not ( I 1 and QB and SET ) ;
I 0 <= not ( I 3 and I 1 and SET ) ;
I 2 <= not (CLOCK and I 3 and I 1 ) ;
end architecture ;

entity S u b j k f f i s
port ( nnnet6 : in b i t ;
nnnet1 : in b i t ;
nnnet8 : in b i t ;
nnout nnnet3 : out b i t ;
nnout nnnet7 : out b i t ;
nnnet9 : in b i t ;
nnnet10 : in b i t ) ;
end entity ;

16
use work . a l l ;
architecture A r c h S u b j k f f of S u b j k f f i s
s i g n a l nnnet0 ,
nnnet2 ,
nnnet4 ,
nnnet5 ,
nnnet7 ,
nnnet3 : b i t ;
begin
nnnet0 <= not nnnet1 ;
nnnet2 <= nnnet3 and nnnet0 ;
nnnet4 <= nnnet2 or nnnet5 ;
nnnet5 <= nnnet6 and nnnet7 ;
nnout nnnet7 <= nnnet7 or ’ 0 ’ ;
nnout nnnet3 <= nnnet3 or ’ 0 ’ ;
SUB1 : entity S u b d f f s r port map ( nnnet8 , nnnet4 , nnnet3 ,
nnnet7 , nnnet10 , nnnet9 ) ;
end architecture ;

entity TestBench i s
end entity ;
use work . a l l ;

architecture Arch TestBench of TestBench i s

s i g n a l CLEAR,
COUNT,
CLOCK,
Q3 ,
Q0 ,
Q1 ,
Q2 ,
nnnet0 ,
nnnet1 ,
nnnet2 ,
nnnet3 ,
nnnet4 ,
nnnet5 ,
nnnet6 ,
nnnet7 ,
nnnet8 ,

17
 nnnet9 : b i t ;
begin
SUB5 : entity S u b L o g i c o n e port map ( nnnet0 ) ;
nnnet1 <= Q0 and nnnet2 ;
nnnet3 <= Q1 and nnnet1 ;
nnnet4 <= Q2 and nnnet3 ;
SUB2 : entity S u b j k f f port map ( nnnet1 , nnnet1 , nnnet5 ,
Q1 , nnnet6 , nnnet0 , nnnet7 ) ;

SUB3 : entity S u b j k f f port map ( nnnet3 , nnnet3 , nnnet5 ,

Q2 , nnnet8 , nnnet0 , nnnet7 ) ;
SUB1 : entity S u b j k f f port map ( nnnet0 , nnnet0 , nnnet5 ,
Q0 , nnnet9 , nnnet0 , nnnet7 ) ;
nnnet5 <= COUNT and CLOCK;
nnnet7 <= not CLEAR;

CLEAR: process
begin
CLEAR <= ’ 1 ’ ; wait for 10 ns ;
CLEAR <= ’ 0 ’ ; wait for 1000 ns ;
end process ;

COUNT: process
begin
COUNT <= ’ 0 ’ ; wait for 5 ns ;
COUNT <= ’ 1 ’ ; wait for 1000 ns ;
end process ;

CLOCK: process
begin
CLOCK <= ’ 0 ’ ; wait for 5 ns ;
CLOCK <= ’ 1 ’ ; wait for 5 ns ;
end process ;

SUB4 : entity S u b j k f f port map ( nnnet4 , Q0 , nnnet5 ,

Q3 , nnnet2 , nnnet0 , nnnet7 ) ;
end architecture ;

18
Generating a library of mixed-mode digital com-
ponents
The Qucs project facilities offer users a simple and convenient approach to devel-
oping libraries of components that are linked by a common theme; in these notes
this is digital component models for transient simulation. To form a library create
a new folder, at a point on a disk file system that users have read/write access,
giving it a suitable name, for example
f l i p f l o p models t r a n sim p r j .
Next move into the new library folder a copy of each of the schematic capture files
for the flip-flop models introduced in these notes. These are:
d f f s r . sch , j k f f . sch , t f f . sch , and gated d l a t c h . sch .
A copy of the schematic for setting nodes to logic one is also required
( l o g i c one . sch ) .
These models are then freely available for use in any projects which users are
working on. They can be copied into such projects using the ”Add files to Project...”
menu button found under the Qucs Project drop-down menu. Similarly any new
models developed as part of a project can be added to the library and used again
in the future.

Digital component propagation time delays and

transient simulation numerical stability
Transient simulation is in general much slower than digital simulation using VHDL
generated machine code. The large signal transient simulation models of flip-flops
and other sequential digital devices are intended for use in mixed-mode circuit
simulation rather than being used for pure digital circuit simulation. An interest-
ing, and indeed very important question, relates to the efficiency, and accuracy,
of the numerical analysis algorithms employed in the integration routines that are
central to transient circuit simulation. Qucs allows users to select the algorithm
they wish to employ for transient simulation. The available algorithms are Trape-
zoidal, Euler, Gear and Adams Moulton; in each case the algorithm order can be
set from 1 to 6. The second order Trapezoidal integration algorithm is used by
Qucs as the default for transient simulation. To test which of these algorithms
offers the most time efficient solution to the transient simulation of digital circuits,
that include flip-flops, the BCD counter shown in Fig. 13 was used as a test case
and repeatedly simulated using different integration routines and algorithm orders.

19
 Order Trapezoidal Euler Gear Adams Moulton
1 1 1.62 1.65 1.62
2 1 1.62 0.44 1
4 1 1.62 1.28 0.39
6 1 1.62 0.28 0.18

Table 1: Relative simulation times for the circuit shown in Fig. 13

Order Number or rejections Average time step

1 1470 5.17737e-12
2 1750 9.4585e-12
4 1454 2.866e-11
6 61 5.76646e-11

Table 2: Number of rejections and average time step data for the Adams Moulton
algorithm

The test results are shown in Table 1. Very little difference was found between
circuits where the cross coupled gates both had zero propagation delays and the
case where one gate had 0.5ns delay and the other zero delay.

One obvious fact emerges from the data given in Table 1; namely that the Adams
Moulton higher order integration routines appear to be faster than the default
trapezoidal algorithm. This is corroborated by the average time step and number
of rejection data points output by Qucs at the end of a simulation. Table 2 lists
this data for the Adams Moulton algorithm tabulated in Table 1.

Table 2 points to the increase in average time step and the dramatic reduction
in the number of simulation solution rejections as the probable reason for the
reduction in transient simulation time when using the higher order Adams Moulton
integration routines. However, other factors may influence the choice of integration
routine. Often speed is not the only criteria that is of importance when simulating
large complex circuits. Consider the following case (the circuit shown in Fig. 13
with order 6 Adams Moulton transient analysis integration); setting one of the
gate delays to 1ns, and the other to 0ns, in each of the RS latches in the edge-
triggered D flip-flop yields the signal waveforms illustrated in Fig. 18. Clearly here
the solution is incorrect pointing to probable numerical instability caused by the
choice of integration routine.

20
 CLEAR.Vt
1

0
0 1e-8 2e-8 3e-8 4e-8 5e-8 6e-8 7e-8 8e-8 9e-8 1e-7 1.1e-7 1.2e-7
time

CLOCK.Vt
1

0
0 1e-8 2e-8 3e-8 4e-8 5e-8 6e-8 7e-8 8e-8 9e-8 1e-7 1.1e-7 1.2e-7
time
COUNT.Vt

0
0 1e-8 2e-8 3e-8 4e-8 5e-8 6e-8 7e-8 8e-8 9e-8 1e-7 1.1e-7 1.2e-7
time
1
Q0.Vt

0
0 1e-8 2e-8 3e-8 4e-8 5e-8 6e-8 7e-8 8e-8 9e-8 1e-7 1.1e-7 1.2e-7
time
1
Q1.Vt

0
0 1e-8 2e-8 3e-8 4e-8 5e-8 6e-8 7e-8 8e-8 9e-8 1e-7 1.1e-7 1.2e-7
time
1
Q2.Vt

0
0 1e-8 2e-8 3e-8 4e-8 5e-8 6e-8 7e-8 8e-8 9e-8 1e-7 1.1e-7 1.2e-7
time
1
Q3.Vt

0
0 1e-8 2e-8 3e-8 4e-8 5e-8 6e-8 7e-8 8e-8 9e-8 1e-7 1.1e-7 1.2e-7
time

Figure 18: Digital TimeList waveforms for the circuit shown in Fig. 13

Mixed-mode example simulations

Mixed-mode simulation involves the simulation of circuits that contain electronic
devices and circuits from different physical domains; the most obvious being cir-
cuits with a mixture of analogue and digital components. Qucs has developed to
a point where it can handle this type of circuit given device models that can span
across the different physical domains. In the future such circuits are likely to incor-
porate components from other domains, including for example, digital signal pro-
cessing components (DSP) and possibly nano mechanical devices. Multi-domain
simulation adds additional complexity to the simulation process not normally found
in single domain simulation. Each domain usually represents signal data in a spe-
cific way attributed to a given domain; voltage and current for analogue quantities,
boolean ’1’ and ’0’ for digital signals and floating point numbers for DSP. Hence,
signals passing from one domain to another have to be converted from one format
to another. These conversion elements are often called node-bridges and form an
essential part of the mixed-mode simulation process. The three examples that are
introduced in this section of these notes have been chosen to illustrate a number
of the basic ideas concerned with mixed-mode simulation of circuits containing
analogue and digital components, and to show how Qucs deals with this type of
simulation. In the last section the importance of correct selection of integration
routine when simulating circuits in the time domain was stressed. Mixed-mode

21
circuits often include a wide diversity of components that exhibit widely differing
time constants. This makes the problem of numerical stability versus simulation
run time even more critical. With the explicit numerical integration routines, like
the trapezoidal routine, numerical instability results if the simulation time step be-
comes much larger than the smallest time constant in a circuit. Hence, to achieve
successful completion of a simulation the integration time step must be reduced
which in turn makes the overall simulation time increase significantly. The implicit
Gear algorithm5 does not suffer from this problem and is the natural choice for
circuits with components that have widely differing time constants.

• Example 1: Analogue waveform driven digital devices with output node-

bridge.
The circuit in Fig. 19 shows an analogue voltage source driving a digital in-
verter with a node-bridge element processing the inverter output signal. The
input signal is a sinusoidal voltage of amplitude 1V peak. The inverter out-
put signal, V1 in Fig. 19, has an nonsymmetrical mark to space ratio because
the threshold point for the inverter is set at 0.5V; the halfway point for the
two logic levels. The node-bridge element is basically a voltage controlled
voltage source where the device gain and time delay can be programmed. In
this first example the gain has been set to 5 and the time delay to 0.5ns.
Figure 20 illustrates the simulation TimeList waveforms for this example
mixed-mode circuit. The node-bridge shown in Fig. 19 is a very basic de-
vice. Moreover, by adding additional features, parameters like fall and rise
time can set to specific values. The next example demonstrates the use of
an active node-bridge.

5
The Gear integration algorithm is a powerful method for solving stiff systems of differential
equations, see Donald A. Calahan, Computer Aided Network Design, Revised edition, 1972,
McGraw-Hill.

22
 Vin V1 V5D
1 VINP VOUTP
V1
D to A
U=1 V Node
Y1
Bridge
transient
simulation VINN VOUTN

SUB1
TR1 File=a_node_bridge.sch
Type=lin
Start=0
Stop=20us
IntegrationMethod=Gear
Order=6

Figure 19: Analogue waveform driven digital device with output node-bridge
Vin.Vt

0 2e-6 4e-6 6e-6 8e-6 1e-5 1.2e-5 1.4e-5 1.6e-5 1.8e-5 2e-5
time

1
V1.Vt

0 2e-6 4e-6 6e-6 8e-6 1e-5 1.2e-5 1.4e-5 1.6e-5 1.8e-5 2e-5
time
5
V5D.Vt

0
0 2e-6 4e-6 6e-6 8e-6 1e-5 1.2e-5 1.4e-5 1.6e-5 1.8e-5 2e-5
time

Figure 20: Digital TimeList waveforms for the circuit shown in Fig. 19

23
• Example 2: Pulse driven digital inverter with an active node bridge.
Illustrated in Fig. 21 is a similar circuit to the previous example. In Fig. 21
a pulse generator drives a digital inverter. The inverter output signal is
processed by an active node-bridge derived from a basic BJT switching am-
plifier. The output waveforms for this circuit are shown in Fig. 22. Notice
that the pulse rise and fall times are determined by the node-bridge amplifier
and that the resulting analogue signal amplitude is set to 5V.

transient
simulation
V2
TR1
U=5 V
Type=lin
Start=0 R2
Stop=30ns R=4.7 k Ohm
IntegrationMethod=Gear
VC
Order=6

VPIN V1 VB T1 C1
1 Type=npn C=0.1 pF
V3 Is=1e-16
U1=0 V R1 Nf=1
Y1 R=10k Ohm
U2=1 V Vaf=0
T1=5ns Bf=100
T2=20ns

Figure 21: Pulse driven digital inverter with active node-bridge

24
 1
VPIN.Vt

0
0 2e-9 4e-9 6e-9 8e-9 1e-8 1.2e-8 1.4e-8 1.6e-8 1.8e-8 2e-8 2.2e-8 2.4e-8 2.6e-8 2.8e-8 3e-8
time
1
V1.Vt

0 2e-9 4e-9 6e-9 8e-9 1e-8 1.2e-8 1.4e-8 1.6e-8 1.8e-8 2e-8 2.2e-8 2.4e-8 2.6e-8 2.8e-8 3e-8
time
1
VB.Vt

0 2e-9 4e-9 6e-9 8e-9 1e-8 1.2e-8 1.4e-8 1.6e-8 1.8e-8 2e-8 2.2e-8 2.4e-8 2.6e-8 2.8e-8 3e-8
time

4
VC.Vt

0
0 2e-9 4e-9 6e-9 8e-9 1e-8 1.2e-8 1.4e-8 1.6e-8 1.8e-8 2e-8 2.2e-8 2.4e-8 2.6e-8 2.8e-8 3e-8
time

Figure 22: Digital TimeList waveforms for the circuit shown in Fig. 21

• Example 3: A more complex mixed-mode simulation example.

The circuit shown in Fig. 23 brings together a number of the ideas outlined
in these tutorial notes. A 4-bit digital signal is generated from a simple asyn-
chronous binary counter operated from a digital clock signal. The counter
output is transformed to the analogue domain using a simple node-bridge,
of the type introduced in mixed-mode example 1. A 4-bit binary weighted
DAC converts the transformed node-bridge signals into the final analogue
output signal. The DAC operational amplifier is modelled as a gain block
with a single pole frequency response and DC voltage output limiting. The
output waveforms for this example are shown in Fig. 24 and the details of
the operational amplifier model in Fig. 25.

25
 CLOCK
SUB5
S1 1
Num=1
SUB9
T

File=tff.sch
R

File=Logic_one.sch
Q

B0
VINP VOUTP

D to A R1
Node
SUB6 Bridge R=10k Ohm A_VOUT
T

File=tff.sch
R

VINN VOUTN
Q

SUB10 R2
File=a_node_bridge.sch R=10k Ohm
B1 SUB14
File=spole_op_amp.sch
VINP VOUTP

D to A R10 V-
Node V1
SUB7 Bridge R=5k Ohm
U=18 V
T

File=tff.sch
R

VINN VOUTN
Q

SUB11
File=a_node_bridge.sch +
B2 V+
V2
VINP VOUTP U=18 V

SUB8
D to A R4
Node
R=2.5k
T

File=tff.sch Bridge transient

R

simulation
Q

VINN VOUTN
RESET
SUB12
TR1
File=a_node_bridge.sch
B3 Type=lin
S2 VINP VOUTP Start=0
Num=2 Stop=40 m
D to A R5
Node IntegrationMethod=Gear
Bridge R=1.25k Ohm Order=6
VINN VOUTN

SUB13
File=a_node_bridge.sch

Figure 23: A more complex analogue-digital mixed-mode simulation example

26
 RESET.Vt

0
0 0.002 0.004 0.006 0.008 0.01 0.012 0.014 0.016 0.018 0.02 0.022 0.024 0.026 0.028 0.03 0.032 0.034 0.036 0.038 0.04
time
CLOCK.Vt

0
0 0.002 0.004 0.006 0.008 0.01 0.012 0.014 0.016 0.018 0.02 0.022 0.024 0.026 0.028 0.03 0.032 0.034 0.036 0.038 0.04
time
1
B0.Vt

0 0.002 0.004 0.006 0.008 0.01 0.012 0.014 0.016 0.018 0.02 0.022 0.024 0.026 0.028 0.03 0.032 0.034 0.036 0.038 0.04
time
1
B1.Vt

0
0 0.002 0.004 0.006 0.008 0.01 0.012 0.014 0.016 0.018 0.02 0.022 0.024 0.026 0.028 0.03 0.032 0.034 0.036 0.038 0.04
time

1
B2.Vt

0
0 0.002 0.004 0.006 0.008 0.01 0.012 0.014 0.016 0.018 0.02 0.022 0.024 0.026 0.028 0.03 0.032 0.034 0.036 0.038 0.04
time

1
B3.Vt

0
0 0.002 0.004 0.006 0.008 0.01 0.012 0.014 0.016 0.018 0.02 0.022 0.024 0.026 0.028 0.03 0.032 0.034 0.036 0.038 0.04
time
A_VOUT.Vt

-20
0 0.002 0.004 0.006 0.008 0.01 0.012 0.014 0.016 0.018 0.02 0.022 0.024 0.026 0.028 0.03 0.032 0.034 0.036 0.038 0.04
time

Figure 24: Digital TimeList waveforms for the circuit shown in Fig. 23

27
 VDCP
Num=4

D1
Is=1e-15 A
N=1
Cj0=10 fF
M=0.5
Vj=0.7 V R5
R=5 Ohm
VOUT
Num=3

R1 C1
VINP R4 R3
R=200k Ohm C=3.2uF R6
Num=1 R=10k Ohm R=50 Ohm
R=5 Ohm

SRC2 SRC1
VINN
G=200k G=1
Num=2
T=0 T=0 D2
Is=1e-15 A
N=1 VDCN
Cj0=10 fF Num=5
M=0.5
Vj=0.7 V

Figure 25: Operational amplifier model with Rin = 200k Ω, pole frequency = 5Hz,
DC differential gain = 200k and Rout = 50 Ω

28
End Note
The examples described in these notes were all simulated using the latest CVS
code version of Qucs. Since release of version 0.0.8, Qucs has matured enough
to allow it to be used for mixed-mode simulation and many of the known bugs
in Qucs 0.0.8 will be corrected with the release of Qucs 0.0.9 some time in the
future. Release 0.0.9 will represent another important step in the development of
a truly universal simulator. However, much more work needs to be done on the
development of models for use across the different physical domains. My thanks
to Michael Margraf and Stefan Jahn for all their hard work in correcting the bugs
which surfaced while the examples presented in this tutorial note where being
tested.

29