School of Computing
SASTRA Deemed University
Agenda IV ()
Architecture and CSE206:
i. syllabi for the courses CSE205: Computer
Modification of
programmes for the
semesterof the following
ComputerSystem Design laboratory in IV
2021-2022
students admitted from the academic year
a. B. Tech. Computer Science & Engineering
specialisation in
b. B. Tech. Computer Science &Engineering(with
Artificiallntelligence & Data Science)
c. B. Tech. Computer
Science & Engineering (with specialisation in Cyber
Security & Block Chain Technology)
& Engineering (with specialisation in loT &
d. B. Tech. Computer Science
Automation)
Electronics Engineering
e. B.Tech. Electrical &
f. B.Tech. Electrical & Electronics Engineering (with specialisation in Smart Grid
& Electric Vehicles)
Course Code: CSE205RO1
Semester: V
COMPUTER ARCHITECTURE
15 Periods
UNIT-I
ARM Design Philosophy System Embedded
ARM Architecture and Instruction Set: Status Register.
Hardware Embedded System Software Registers Current
-
Program
Thumb
-
and the Vector Table ARM Instruction Set
-
Pipeline Exceptions Interrupts
Instruction Set.
15 Periods
UNIT II
Architectural overview -Vectored
ARM processor LPC214x: Introduction -
Features -
/ Output UART 12C RTC: Pin & Register-
Interrupt Controller General Purpose Input
-
-
Timer-ADC & DAC.
Description -Watchdog
15 Periods
UNIT I1
Architecture
of Computers-Defining Computer
-
Advanced Architecture Features: Classes
Instruction-Level Parallelism: Concepts and
Quantitative Principles of Computer Design. with
for Exposing ILP-Reducing Branch Costs
Challenges-Basic Compiler Techniques Scheduling-Dynamic
Advanced Branch Prediction-Overcoming Data
Hazards with Dynamic
Examples and the Algorithm-Hardware-Based Speculation
Scheduling:
15 Periods
UNIT IV
Introduction-Vector
Vector Architecture and Parallelism: Data level parallelism:
Architecture-SIMD Instruction Set Extensions for
Multimedia-Graphics Processing Units-
Thread-Level Parallelism: Introduction-
Detecting and Loop-Level Parallelism-
Enhancing
Centralized Shared-Memory
Architectures-Performance of Symmetric Shared-Memony
and Directory-Based Coherence-
Multiprocessors-Distributed Shared-Memory
Consistency: An Introduction
Synchronization:The Basics-Models of Memory
School of Computing
SASTRA Deemed University
TEXT BOOKS
Guide:
1. Andrew N Sloss, Dominic Symes and Chris Wright, "ARM System Developers
2004.
Designing and optimizing system software", Morgan Kaufmann,
2. UM10139LPC214x User manual Rev 4-23 April 2012.
3. JohnL. Hennessy, David A. Patterson. Computer Architecture A Quantitative
2012.
Approach, Morgan Kaufmann is an imprint of Elsevier, Fifth Edition,
REFERENCES
1. William Stallings. Computer Organization and Architecture Designing for Performance,
Pearson Education, Tenth edition, 2006.
ONLINE MATERIALS
1. https://nptel.ac.in/courses/106/108/106108100/
2. https://nptel.ac.in/courses/106/105/106105193/
UNITWISE LEARNING OUTCOMES
Upon successful completion of each unit, the learner will be able to
Unit Describe the architecture, instruction set and advanced features of
ARM7 processor
Unit ll ldentify the significance of ARM processor along with its Pin and
register description withits features for designing an embedded system
Unit ll Select techniques for extending basic pipelining to increase parallelism
explored at instruction level
Unit IV Illustrate vector architecture and summarize SIMD instruction set
. Extend enhancement of loop level parallelism and Thread Level
Parallelism
COURSE LEARNING oUTCOMEs
Upon successful completion of this course, the learner will be able to
Describe the architecture, instruction set and advanced features of ARM7 processor.
Identify the significance of ARM based Microcontroller along with its Pin and register
description with its features for designing an loT system
Select techniques for extending basic pipelining to increase parallelism explored at
instruction level
lustrate vector architecture and extend enhancement of loop level parallelism and
Thread Level Parallelism
SASTRA Deemed University School of Computing
Course Code: CSE206R01
Semester: IV
LABORATORY
COMPUTER SYSTEM DESIGN
Course Objectives
I/O operations, Timer,
the learner to understand assembly language,
This course will help
architecture.
ADC operations and Interrupts of ARM
LIST OF EXPERIMENTS
Assembly Language Programming
Instructions
1. Programs on Data transfer
instructions
2. Programs on ALU
3. Programs on Stack
with ARM
Interfacing On and Off Chip Peripherals
LEDs
4. Controlling the on-board
on-board Switch
5. Controling the
control using Internal Timers
6. Designing Program flow
7. Implementation of Hardware Interrupt
Communication
8. Data transfer using Serial
9. Interfacing ADC
10. Interfacing Stepper Motor
Using GEM5
maintenance
11. Program on Task context
12. Perfomance analysis of cache memory
cOURSE LEARNING OUTCOMES
the learner will be able to
Upon successful completion of this course,
problem using ARM
.Develop Assembly language program for any given
processors
Microcontroller
Demonstrate l/O operations for Advanced
Demonstrate Timer operations
llustrate the ADC and UART functions in ARM board
. Demonstrate interrupt routines
Analysis ofsystem architecture using GEM5
