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PFD Circuits

This document discusses the implementation of a phase frequency detector (PFD) circuit for use in memory and clock synchronization integrated circuit design. It describes several common PFD circuit designs including those based on flip-flops, NAND gates, and pass transistors. It also discusses design considerations for the PFD such as operating point, duty cycle sensitivity, and dead zones. The document is authored by Dr. Vishal Saxena from the Electrical and Computer Engineering Department at Boise State University.

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0% found this document useful (0 votes)

93 views11 pages

PFD Circuits

Uploaded by

Vickey Kumar

We take content rights seriously. If you suspect this is your content, claim it here.

Available Formats

Download as PDF, TXT or read online on Scribd

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Department of Electrical and Computer Engineering

ECE518 Memory/Clock Synchronization IC Design

PFD Circuit Implementation

Dr. Vishal Saxena

Electrical and Computer Engineering Department
Boise State University, Boise, ID

© Vishal Saxena -1-

PFD Implementation

© Vishal Saxena -2-

Compact SR Latch

© Vishal Saxena -3-

Gate Level PFD

 Since the FF D input is always 1, the logic can be optimized for higher speed

© Vishal Saxena -4-

PFD Contd.

 The nominal lock point of the PFD is 0

 Not sensitive to input duty cycle
 Near lock, the propagation of narrow pulses to switch the
charge pump can case a PFD “dead zone”
 Add extra delay in the PFD reset path to prevent dead zone

Other PFD Implementations

NAND-based PFD

 NAND implementation is preferred in CMOS design

NAND-based PFD

 From the CMOS Book

Pass-Transistor PFD

Fast Latch-based PFD

References
1. B. Razavi, “Design of CMOS Analog Integrated Circuits,” McGraw Hill, 2002.
2. B. Razavi, “RF Microelectronics,” 2nd Ed., Prentice Hall, 2012.
3. R. J. Baker , “CMOS Circuit Design, Layout and Simulation,” 3nd Edition, Wiley-
IEEE, 2010.
4. M. Mansuri, D. Liu, C.-K. K. Ken, “Fast Frequency Acquisition Phase-Frequency
Detectors for GSamples/s Phase-Locked Loops,” IEEE JSSC, vol. 37, no. 10, Oct.
2002.

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PFD Circuits

Uploaded by

PFD Circuits

Uploaded by

Department of Electrical and Computer Engineering

ECE518 Memory/Clock Synchronization IC Design

PFD Circuit Implementation

Dr. Vishal Saxena

© Vishal Saxena -1-

© Vishal Saxena -2-

© Vishal Saxena -3-

© Vishal Saxena -4-

 The nominal lock point of the PFD is 0

© Vishal Saxena -5-

© Vishal Saxena -6-

 NAND implementation is preferred in CMOS design

© Vishal Saxena -7-

 From the CMOS Book

© Vishal Saxena -8-

© Vishal Saxena -9-

© Vishal Saxena -10-

© Vishal Saxena -11-

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