Interrupts of 8086
When microprocessor receives any interrupt signal from peripheral(s) which are
requesting its services, it stops its current execution and program control is
transferred to a sub-routine called Interrupt Service Routine (ISR).
Types of Interrupts in 8086
256(FFH) types - INT 00H, INT 01H, INT 02H,….INT FEH, INT FFH
I) Dedicated Interrupts: 5
II) Reserved/System Interrupts: 27
III)User Interrupts: 224
I) Dedicated Interrupts:
INT 00 – Divide By Zero
INT 01 – TRAP (Single step)
INT 02 – NMI (Non Maskable Interrupt)
INT 03 – Break point
INT 04 – Overflow
II) Reserved/ System Interrupts:
INT 05 to INT 31(1FH)
III) User Interrupt: INTR – 8259 Programmable Interrupt Controller
INT 32(20H) – INT 255(FFH)
Interrupt Vector Table (IVT)
IVT holds vector addresses of 256 interrupts. (256x4=1024 bytes)(000-3FFH)
Each Interrupt has 4 bytes in IVT.
INT 00H – Divide By Zero
IP- 000H [000 & 001 – IP offset address, 002& 003 – CS Base address]
INT 01H- Single Step
IP- 0004H [0004 & 0005 – IP offset address, 0006& 0007 – CS Base address]
Steps involved at the time of interrupt occurs
i) Pushes all the registers onto stack.
ii) Disables the INTR
iii) Moves to IVT, and CS and IP are updated according to the address in
assigned in specified address.
iv) Executes ISR, RETI
v) After execution of ISR, retrieves stored IP and CS, registers from
stack.
Position in the IVT : INT type x 4= INT 3x 4=12-0CH
Assembler Directives
Assembler Directives are the special instructions of assembler, it instruct
the assembler to do defined specific operations.
DB, DW, DQ, EQU, ASSUME, SEGMENT, ORG, END,ENDS, PROC, ENDP, MACRO,
ENDM,PTR, OFFSET
1) DB – DEFINE BYTE (To reserve the bytes or bytes of memory locations)
Ranks DB 02, 03, 04, 05
2) DW - DEFINE WORD
WORD1 DW 1234H, 4567H, 789AH, ABCDH
3) DQ - DEFINE QUADWORD
QUAD1 DQ 12345678H, 87654321H
4) EQU – Equate
Labels/variables with values
5) ASSUME – assume
To assign names to the segment
ASSUME DS: DATA, CS: CODE1, ES: Extra1, SS: Stack2
6) SEGMENT – segment
Start of the segment
CODE1 SEGMENT
7) ENDS (End of Segment)
CODE1 ENDS
8) ORG – Origin
ORG 2200H
Ranks DB 02, 03, 04, 05
9) END (End of the program)
10) PROCEDURE – (Procedure)
PROCEDURE SUBPROGRAM1
11) ENDP – (End of Procedure)
ENDP
12) MACRO – (Macro)
MACRO SUBPROGRAM2
13) ENDM (End of Macro)
14) PTR (pointer)
To declare the type of label, variable, memory operand
MOV AL, BYTE PTR [DI]
MOV AX, WORD PTR [SI]; MOV AX, [SI]
15) OFFSET (provides the offset of variable)
MOV SI, OFFSET Ranks; SI-2200
ASSUME DS: DATA, CS: CODE1, ES: Extra1, SS: Stack2
DATA SEGMENT
ORG 2505H
Ranks DB 02, 03, 04, 05
LIST1 DW 1234H, 4567H, 789AH, ABCDH
COUNT EQU 05H
DATA ENDS
CODE SEGMENT
ORG 3000H
MOV CX, COUNT;
MOV SI, OFFSET LIST1; MOV SI, 2509
MOV AL, BYTE PTR [DI]
MOV WORD PTR[2700], DX
INC SI
CODE ENDS
Procedure and Macros
CODE SEGMENT
ORG 3000H
MOV CX, COUNT;
MOV SI, OFFSET LIST1; MOV SI, 2509
MOV AL, BYTE PTR [DI]
MOV WORD PTR[2700], DX
INC SI
CALL
…….
……
…..
---
---CALL SUBPROGRAM1
…….
……
…..
----
MACRO SUBRPROGRAM1
……. 3500
……
…..
ENDP
CODE ENDS
MULTIPROCESSOR SYSTEM
A system that consists of two or more microprocessors, and executes the
instructions simultaneously is called Multiprocessor System.
Advantages:
Through put
Tasks can be divided among the processors
Failure of any processor will not affect the system
Disadvantages:
Bus contention
Inter processor communication
Multiprocessor Configuration
Coprocessor Configuration
Closely Coupled Configuration
Loosely Coupled Configuration
Coprocessor Configuration
A Coprocessor is a specially designed circuit on microprocessor chip which can
perform the same task very quickly, which the microprocessor performs.
• It reduces the work load of the main processor.
• The coprocessor shares the same memory, IO system, bus, control logic and
clock generator.
• The coprocessor handles specialized tasks like mathematical calculations,
graphical display on screen, etc.
• The 8086 and 8088 can perform most of the operations but their instruction set
is not able to perform complex mathematical operations, so in these cases the
microprocessor requires the math coprocessor like Intel 8087 math coprocessor,
which can easily perform these operations very quickly.
Closely Coupled Configuration
Loosely Coupled Configuration
Loosely coupled configuration consists of the number of modules of the
microprocessor based systems, which are connected through a common
System bus.
• Each module consists of their own clock generator, memory, I/O devices and
are connected through a local bus.
• Clocks are of similar frequency, but asynchronous towards each other.
• Used for medium to large multiprocessor systems
• Each module is capable of being the bus master
• No direct connections between the modules.
• Each share the system bus and communicate through shared resources.
• Processor in their separate modules can simultaneously access their private
subsystems through their local buses, and perform their local data references
and instruction fetches independently.
• This results in improved degree of concurrent processing.
• Excellent for real time applications, as separate modules can be assigned
specialized tasks.
Bus Arbitration Schemes
Daisy Chain, Polling, Independent requesting
Daisy Chain
It is simple and cheaper method. All masters make use of the same line for
bus request.
In response to the bus request the controller sends a bus grant if the bus is
free.
The bus grant signal serially propagates through each master until it
encounters the first one that is requesting access to the bus. This master
blocks the propagation of the bus grant signal, activities the busy line and
gains control of the bus.
Therefore any other requesting module will not receive the grant signal and
hence cannot get the bus access.
Polling
The system connections for polling method are shown in figure above.
In this the controller is used to generate the addresses for the master.
Number of address line required depends on the number of master
connected in the system.
For example, if there are 8 masters connected in the system, at least three
address lines are required.
In response to the bus request controller generates a sequence of master
address. When the requesting master recognizes its address, it activated
the busy line ad begins to use the bus.
Independent Requesting
In this scheme each master has a separate pair of bus request and bus
grant lines and each pair has a priority assigned to it.
The built in priority decoder within the controller selects the highest
priority request and asserts the corresponding bus grant signal.
