GURU NANAK DEV ENGINEERING COLLEGE,BIDAR
DEPARTMENT OF
ELECTRONICS AND COMMUNICATION ENGINEERING
Submitted in partial fulfillment of requirements of 3 semester of B.E course
rd
during the year 2021-2022
SIMULATION BASED LEARNING ON DIGITAL SYSTEM DESIGN
SUBMITTED BY
SHREYA (3GN20EC063)
SHREYA (3GN20EC064)
SHUBHAM (3GN20EC065)
SHUBHAM DILIP S (3GN20EC066)
UNDER THE GUIDANCE OF
Prof. PAVAN MANKAL
AIM:
Simulation of 2:4 decoder by using the Xilinx ise design suit.
THEORY:
A decoder is a multiple input, multiple output logic circuit that changes codes i/ps into coded
o/ps, where both the inputs and outputs are dissimilar for instance n-to-2n, and binary coded
decimal decoders. Decoding is essential in applications like data multiplexing, memory
address decoding, and 7 segment display. The best example of decoder circuit would be an
AND-gate because when all its inputs are “High.”, the output of this gate is “High” which is
called “active High output”. As an alternative to AND gate, the NAND gate is connected the
output will be “Low” (0) only when all its inputs are “High”. Such o/p is called “active low
output”.
Designing of 2 to 4 Line Decoder Circuit
Similar to the multiplexer circuit, the decoder is not restricted to a particular address line, and
thus can have more than two outputs (with two, three, or four address lines). The decoder
circuit can decode a 2, 3, or 4-bit binary number, or can decode up to 4, 8, or 16 time-
multiplexed signals.
2 to 4 Line Decoder Truth Table
SOFTWARE USED:
Xilinx ISE Design suit.
VHDL CODE FOR SIMULATION :
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity decoder1 is
port(
a : in STD_LOGIC_VECTOR(1 downto 0);
b : out STD_LOGIC_VECTOR(3 downto 0)
);
end decoder1;
architecture bhv of decoder1 is
begin
process(a)
begin
if (a="00") then
b <= "0001";
elsif (a="01") then
b <= "0010";
elsif (a="10") then
b <= "0100";
else
b <= "1000";
end if;
end process;
end bhv;
VHDL Code for 2 to 4 decoder using logic gates
view source
print?
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity decoder2 is
port(
a : in STD_LOGIC_VECTOR(1 downto 0);
b : out STD_LOGIC_VECTOR(3 downto 0)
);
end decoder2;
architecture bhv of decoder2 is
begin
b(0) <= not a(0) and not a(1);
b(1) <= not a(0) and a(1);
b(2) <= a(0) and not a(1);
b(3) <= a(0) and a(1);
end bhv;
Result after the syntax check:
Result after the simulation of the code
RESULT :
Truth table and the waveforms has been verified of 2:4 decoder.
Applications of Decoder:
The applications of decoder involve in the making of various electronic projects.
War- Field -Flying Robot with a Night Vision Flying Camera
Robotic Vehicle with Metal Detector
RF-based Home Automation System
Speed Synchronization of Multiple Motors in Industries
Automatic Wireless Health Monitoring System in Hospitals for Patients
Secret Code Enabled Secure Communication using RF Technology
