Sequential Logic Solutions
Examples for Lecture 1
1.1 An RS latch has its Q output initially at a value of 0. How does Q subsequently behave when given
the following input waveforms? What is the final value of Q at the end of the sequence?
time
Q
1.2 An RS latch has its Q output initially at a value of 0. We would like to make the output 1 at time 100
ns and then 0 at time 200 ns. Show a waveform for R and S that would accomplish this.
100 ns 200 ns
time
Q
Examples for Lecture 2
2.1 The following ring oscillator circuit is measured to have a frequency of oscillation of 50 MHz.
Output
What can we conclude about the value of the inverter delay ?
Output is low for 5, high for 5
Total period is 10
Period of 50 MHz wave is 20 ns
=2ns
1
2.2 We would like to construct a ring oscillator circuit whose frequency of oscillation is less than 1 MHz,
using inverters of delay =75 ns. What circuit should we use?
Period of 1 MHz wave is 1000 ns
We will use a ring oscillator of x stages. x must be an integer that is an odd number
Output is low for 75x ns, high for 75xns
Total period is 150x ns
We need the smallest odd integer x such that 150x > 1000
X=7
Output
2.3 How does the output Q of the following circuit behave when Input=0?
Input=0 1 0
Q
Input=0 forces the NAND gate to output a 1, regardless of the initial value at Q. This in turn forces Q to
become zero. This is a reset instruction.
How does the output behave when Input=1?
Input=1 0 1
Q
Input=1 1 0
Q
Input=1 causes the NAND gate to output 0 when the initial value of Q=1, and to output 1 when the
initial value of Q=0. This causes a self-perpetuating loop. This is hold instruction.
2
Examples for Lecture 3
3.1 A D-type flip-flop has a starting value for its output Q=0. It then receives the following input
waveform. What would be the response of its output Q?
Whatever value D has just before the clock edge becomes the value of Q after the clock edge
3.2 A T-type flip-flop has a starting value for its output Q=0. It then receives the following input
waveform. What would be the response of its output Q?
If T=1 just before the clock edge, Q toggles it value; If T=Q just before the clock edge, Q holds it value;
3.3. A JK-flip-flop has a starting value for its output Q=0. It then receives the following input waveform.
What would be the response of its output Q?
Clock
Q
HOLD TOGGLE SET TOGGLE RESET
3
Examples for Lecture 4
4.1 The circuit starts with Q1=0, Q0=0. What will be the values of Q1 and Q0 on subsequent clock cycles?
Q0 Q0+Q1
D0 Q0 D1 Q1
Ck Q0 Ck Q1
Cycle Q1 Q0 D1 D0 Q+1 Q+0
Start 0 0 1 1 1 1
1 1 1 1 0 1 0
2 1 0 0 1 0 1
3 0 1 1 0 1 0
Thereafter (cycle 4 onwards) Q1Q0 = 10 then 01 then 10 then 01… will repeat forever
4.2 The circuit starts with Q1=0, Q0=0. What will be the values of Q1 and Q0 on subsequent clock cycles?
Q0 Q0
D0 Q0 D1 Q1
Ck Q0 Ck Q1
Cycle Q1 Q0 D1 D0 Q+1 Q+0
Start 0 0 0 1 0 1
1 0 1 1 0 1 0
2 1 0 0 1 0 1
3 0 1 1 0 1 0
Thereafter (cycle 4 onwards) Q1Q0 = 10 then 01 then 10 then 01 … will repeat forever
4
Examples for Lecture 5
5.1 Use D flip flops to design a counter follows the count sequence Q1Q0=00→01→11→10→00, etc….
(This is a 2-bit Gray-code up-counter)
Value before Required value Input to give us
clock edge after clock edge required next value
Q1 Q0 Q1+ D1
0 0 0 0
0 1 1 1
1 0 0 0
1 1 1 1
Value before Required value Input to give us
clock edge after clock edge required next value
Q1 Q0 Q0+ D0
0 0 1 1
0 1 1 1
1 0 0 0
1 1 0 0
Q1 Q1
Q0 0 1 Q0 0 1
0
1 0 0
0 0
1 1 0 1 1 1
Table for D0 Table for D1
𝑄 𝑄
D0 Q0 D1 Q1
Ck Q0 Ck Q1
5
Examples for Lecture 6
6.1 The circuit starts with Q1=0, Q0=0. What will be the values of Q1 and Q0 on subsequent clock cycles?
Q0+Q1 Q0+Q1
T0 Q0 T1 Q1
Ck Q0 Ck Q1
Cycle Q1 Q0 T1 T0 Q+1 Q+0
Start 0 0 1 0 1 0
1 1 0 1 1 0 1
2 0 1 0 1 0 0
3 0 0 1 0 1 0
Thereafter (cycle 4 onwards) Q1Q0 = 10 then 01 then 00… will repeat forever
Examples for Lecture 7
7.1 Use T flip flops to design a counter follows the count sequence Q1Q0=00→01→11→10→00, etc….
(This is a 2-bit Gray-code counter)
Value before Required value Input to give us
clock edge after clock edge required next value
Q1 Q0 Q1+ T1
0 0 0 0
0 1 1 1
1 0 0 1
1 1 1 0
Value before Required value Input to give us
clock edge after clock edge required next value
Q1 Q0 Q0+ T0
0 0 1 1
0 1 1 0
1 0 0 0
1 1 0 1
6
Q1 Q1
0 1 Q0 0 1
Q0
0 0 0 1
1 0
1 0 1
1 1 0
Table for T0 Table for T1
𝑇 = 𝑄 .𝑄 + 𝑄 .𝑄 𝑇 = 𝑄 .𝑄 + 𝑄 .𝑄
T0 Q0 T1 Q1
Ck Q0 Ck Q1
(in lectures, we said that a circuit built from T flip-flops is often simpler than a circuit of equivalent
function built from D flip-flops, but this not always the case. If you compare this solution with the
solution of question 5.1, you will see that in for this sequence the D flip flops lead to a simpler circuit.)
