Effective Training Program – optimal filling of The Hexagon
ENGINEERING – IP OR IC
Focused SKILL areas – chosen for outcomes
Architecting and Algorithms – Physics and Maths
Identifying Problem, Solution Proposal
Practical Development (Module/Block/IP)
Design Patterns
Presentation and Documentation
NON- ENGINEERING
COMMITMENT EXPLORING TEACHING
Training Program Structure
600 Students filtering by NAIN, SFAL, Recruiters
SFAL training Program Internship Program
VSD, Recruiting Partners
15th December 1st January 1st January
to Till Till
1st January 2022 30th April 2022 30th April 2022
Salient Features
Job offer post Internship completion by Recruiters
Unsuccessful Trainees will be given 3 months of Additional Training Support
Instructor Profile Samples – Executed by VSD and SFAL
Tim Edwards, Founder at opencircuitdesign.com and SVP and Efabless. Analog VLSI designer and developer of open-source EDA tools for over 27
years. Worked for the Johns Hopkins Applied Physics Lab, startups MultiGiG and Analog Devices. Developed open-source EDA software tools
such as Magic, Qflow, Netgen, and Xcircuit
Topics: Physical Verification and Physical design using Sky130
Physical Verification methodology using Magic, Netgen and OpenLANE flow. It starts with Basic idea of the design flow, PDK libraries and then
deep dive into the intricate concepts of Physical Verification with dedicated lectures and labs for each topic. Generate a full GDSII from an RTL
netlist in the OpenLANE flow, a fully-automated RTL2GDSII. Commercial flow based “repeat and compare sessions” supervised by him and other
expert Trainers.
Srikanth Jadcherla, Founder, President and CEO, iMedrix Inc. A Low Power Electronics Guru, technologist, serial entrepreneur, investor and
pioneering educator. He was Group Director of R&D in the Low Power Verification Group at Synopsys – through ArchPro acquisition, where he
was founder and CTO. Most of the System on Chip ICs in the world today use his fundamental work on Voltage Aware Boolean Algebra.
Topics: Low Power design using Sky130
It provides a comprehensive view of low power design from system level to device level. Covers Voltage Aware Booleans in detail with labs,
equivalent to a 3-credit university at the graduate level. This is a front-end course and needs to be followed up with a backend
implementation course.
Steve Hoover, Founder of RedwoodEDA is building open silicon ecosystem through technologies like WARP-V CPU core generator with support
for RISC-V. Focused on design methodology and tools enabled by Transaction-Level Verilog (TL-Verilog), Lead developer of the 1st CLaaS
open-source framework for cloud FPGAs. Steve holds a BS in electrical engineering summa cum laude from Rensselaer Polytechnic Institute
and an MS in computer science from the University of Illinois. Designed numerous components for high-performance server CPUs and
network architectures for DEC, Compaq, and Intel.
Topics: RISC-V based MYTH (Microprocessors for you in Thirty hours)
Covers RISC-V specs, RISC-V software, How to implement RISC-V basic specs using TL-Verilog by simulating your own RISC-V core
Sample Design Block/Module/IP for Trainees to develop
RISC-V based SoC for 8x-PLL and 10-bit RISC-V core with an external Instruction
DAC calibration Memory SRAM
10bit potentiometric DAC 3.3v analog voltage,
VEZZAL – A Testing Environment for EDA 1.8v digital voltage and 1 off-chip external
tools voltage reference
Lower power current programmable
General Purpose bandgap CMOS comparator with hysteresis
OpenRAM configuration for SRAM (1024 x 32):
Open-source Layout Generator (32kbits or 4kB), 1.8V and access time is
FPGA Fabric based Projects <2.5ns
DAC IP design10-bit ADC 3.3v analog voltage,
Two Stage CMOS Operational Amplifier 1.8v digital voltage and 1 off-chip external
with Frequency Compensation voltage reference
Core Courses
Technology - Skywater 130nm and Basys/Quicklogic
RISC-V based microprocessor design
FPGA flow and fabric design
RTL design and synthesis
CMOS Circuit design
PD/SoC design
Physical Verification
On-chip multiplier PLL IP design
Bandgap,DAC,SRAM IP design
Analog comparator IP design
Analog/Digital/Mixed-signal/FPGA Fabric-based Projects
