Computer Architecture Lab Solution
TRIDENT TECHLABS PVT.LTD. (KOLKATA)
D-204, Salt Lake City Centre
Block-DC
Kolkata-700064, W.B., India
Tel : 033-40000492
Fax: 033-40000491
Website: www.tridenttechlabs.com
Please contact us on :
Email id : r.rajak@tridenttechlabs.com
Cell no : 9007106735
Overview
THIS WORK BOOK IS BASED ON SIMULATION OF HDL CODES IN
MODELSIM (MENTOR GRAPHICS) ACCORDING TO THE MAKAUT
SYLLABUS
[1]
Table of Content
1. BASIC DIGITAL LOGIC BASE PROGRAMMING WITH HDL............. 3
1.1 AND GATE...................................................................................................... 3
1.2 OR GATE ......................................................................................................... 4
..................................................................................................................................... 5
1.3 NAND GATE .................................................................................................. 6
1.4 NOR GATE...................................................................................................... 8
1.5 XOR GATE ...................................................................................................... 9
1.6 XNOR GATE ................................................................................................ 11
2. 8 BIT ADDITION, SUBTRACTION, MULTIPLICATION, DIVISION
12
3. 8 BIT REGISTER DESIGN ........................................................................... 17
4. MEMORY UNIT DESIGN AND PERFORM MEMORY OPERATION
19
..................................................................................................................................... 21
5. 8 BIT SIMPLE ALU DESIGN ...................................................................... 21
6. 8 BIT SIMPLE CPU DESIGN ...................................................................... 26
7. INTERFACING OF CPU MEMORY ........................................................... 32
[2]
1. BASIC DIGITAL LOGIC BASE PROGRAMMING WITH
HDL
1.1 AND GATE
CODE :
library ieee;
use ieee.std_logic_1164.all;
entity and_gate is
port (a,b : in std_logic ;
c : out std_logic);
end and_gate;
architecture arc of and_gate is
begin
c <= a and b;
end arc;
DATA FLOW :
[3]
TIMING DIAGRAM :
1.2 OR GATE
CODE:
library ieee;
use ieee.std_logic_1164.all;
entity and_gate is
port (a,b : in std_logic ;
c : out std_logic);
end and_gate;
architecture arc of and_gate is
begin
c <= a or b;
end arc;
[4]
DATA FLOW:
TIMING DIAGRAM:
[5]
1.3 NAND GATE
CODE:
library ieee;
use ieee.std_logic_1164.all;
entity and_gate is
port (a,b : in std_logic ;
c : out std_logic);
end and_gate;
architecture arc of and_gate is
begin
c <= a nand b;
end arc;
DATA FLOW:
[6]
TIMING DIAGRAM:
[7]
1.4 NOR GATE
CODE:
library ieee;
use ieee.std_logic_1164.all;
entity and_gate is
port (a,b : in std_logic ;
c : out std_logic);
end and_gate;
architecture arc of and_gate is
begin
c <= a nor b;
end arc;
DATA FLOW :
[8]
TIMING DIAGRAM:
1.5 XOR GATE
CODE:
library ieee;
use ieee.std_logic_1164.all;
entity and_gate is
port (a,b : in std_logic ;
c : out std_logic);
end and_gate;
architecture arc of and_gate is
begin
c <= a xor b;
end arc;
[9]
DATA FLOW:
TIMING DIAGRAM:
[10]
1.6 XNOR GATE
CODE:
library ieee;
use ieee.std_logic_1164.all;
entity and_gate is
port (a,b : in std_logic ;
c : out std_logic);
end and_gate;
architecture arc of and_gate is
begin
c <= a xnor b;
end arc;
DATA FLOW:
[11]
TIMING DIAGRAM:
2. 8 BIT ADDITION, SUBTRACTION, MULTIPLICATION,
DIVISION
CODE(ADDITION,SUBTRACTION):
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity addsub is
port(A,B : in std_logic_vector(7 downto 0);
oper: in std_logic;
RES : out std_logic_vector(7 downto 0));
end addsub;
architecture archi of addsub is
begin
RES <= A + B when oper ='0'
[12]
else A - B;
end archi;
DATA FLOW:
TIMING DIAGRAM:
[13]
CODE (MULTIPLICATION):
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity signed_mult is
port
(a: in signed (7 downto 0);
b: in signed (7 downto 0);
result: out signed (15 downto 0)
);
end entity;
architecture rtl of signed_mult is
begin
result <= a * b;
end rtl;
DATA FLOW:
[14]
TIMING DIAGRAM:
CODE (DIVISION):
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity signed_div is
port
(a: in signed (7 downto 0);
b: in signed (7 downto 0);
result: out signed (7 downto 0)
);
end entity;
architecture rtl of signed_div is
[15]
begin
result <= a / b;
end rtl;
DATA FLOW :
TIMING DIAGRAM :
[16]
3. 8 BIT REGISTER DESIGN
CODE:
library ieee;
use ieee.std_logic_1164.all;
entity shift_siso is
port (Clock, Sin : in std_logic;
Sout : out std_logic);
end shift_siso;
architecture behav of shift_siso is
signal temp: std_logic_vector(7 downto 0);
begin
process (Clock)
begin
if (Clock'event and Clock='1') then
for i in 0 to 6 loop
temp(i+1) <= temp(i);
end loop;
temp(0) <= Sin;
end if ;
end process;
Sout <= temp(7);
end behav;
[17]
DATA FLOW:
TIMING DIAGRAM:
[18]
4. MEMORY UNIT DESIGN AND PERFORM MEMORY
OPERATION
CODE:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
USE ieee.numeric_std.ALL;
entity RAM_32X8 is
port(
address: in std_logic_vector(4 downto 0);
data_in: in std_logic_vector(7 downto 0);
write_in: in std_logic;
clock: in std_logic;
data_out: out std_logic_vector(7 downto 0)
);
end RAM_32X8;
architecture Behavioral of RAM_32X8 is
type ram_array is array (0 to 31 ) of std_logic_vector (7 downto 0);
signal ram_data: ram_array :=(
b"10000000",b"01001101",x"77",x"67",
x"99",x"25",x"00",x"1A",
x"00",x"00",x"00",x"00",
x"00",x"00",x"00",x"00",
x"00",x"0F",x"00",x"00",
x"00",x"00",b"00111100",x"00",
x"00",x"00",x"00",x"00",
x"00",x"00",x"00",x"1F"
);
[19]
begin
process(clock)
begin
if(rising_edge(clock)) then
if(write_in='1') then
ram_data(to_integer(unsigned(address))) <= data_in;
end if;
end if;
end process;
data_out <= ram_data(to_integer(unsigned(address)));
end Behavioral;
DATA FLOW:
[20]
TIMING DIAGRAM :
5. 8 BIT SIMPLE ALU DESIGN
CODE:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use ieee.NUMERIC_STD.all;
-----------------------------------------------
---------- ALU 8-bit VHDL ---------------------
-----------------------------------------------
entity ALU is
[21]
generic (
constant N: natural := 1 -- number of shited or rotated bits
);
Port (
A, B : in STD_LOGIC_VECTOR(7 downto 0); -- 2 inputs 8-bit
ALU_Sel : in STD_LOGIC_VECTOR(3 downto 0); -- 1 input 4-bit for selecting
function
ALU_Out : out STD_LOGIC_VECTOR(7 downto 0); -- 1 output 8-bit
Carryout : out std_logic -- Carryout flag
);
end ALU;
architecture Behavioral of ALU is
signal ALU_Result : std_logic_vector (7 downto 0);
signal tmp: std_logic_vector (8 downto 0);
begin
process(A,B,ALU_Sel)
begin
case(ALU_Sel) is
when "0000" => -- Addition
ALU_Result <= A + B ;
when "0001" => -- Subtraction
ALU_Result <= A - B ;
when "0010" => -- Multiplication
[22]
ALU_Result <= std_logic_vector(to_unsigned((to_integer(unsigned(A)) *
to_integer(unsigned(B))),8)) ;
when "0011" => -- Division
ALU_Result <= std_logic_vector(to_unsigned(to_integer(unsigned(A)) /
to_integer(unsigned(B)),8)) ;
when "0100" => -- Logical shift left
ALU_Result <= std_logic_vector(unsigned(A) sll N);
when "0101" => -- Logical shift right
ALU_Result <= std_logic_vector(unsigned(A) srl N);
when "0110" => -- Rotate left
ALU_Result <= std_logic_vector(unsigned(A) rol N);
when "0111" => -- Rotate right
ALU_Result <= std_logic_vector(unsigned(A) ror N);
when "1000" => -- Logical and
ALU_Result <= A and B;
when "1001" => -- Logical or
ALU_Result <= A or B;
when "1010" => -- Logical xor
ALU_Result <= A xor B;
when "1011" => -- Logical nor
ALU_Result <= A nor B;
when "1100" => -- Logical nand
ALU_Result <= A nand B;
when "1101" => -- Logical xnor
ALU_Result <= A xnor B;
when "1110" => -- Greater comparison
if(A>B) then
[23]
ALU_Result <= x"01" ;
else
ALU_Result <= x"00" ;
end if;
when "1111" => -- Equal comparison
if(A=B) then
ALU_Result <= x"01" ;
else
ALU_Result <= x"00" ;
end if;
when others => ALU_Result <= A + B ;
end case;
end process;
ALU_Out <= ALU_Result; -- ALU out
tmp <= ('0' & A) + ('0' & B);
Carryout <= tmp(8); -- Carryout flag
end Behavioral;
[24]
DATA FLOW:
TIMING DIAGRAM :
[25]
6. 8 BIT SIMPLE CPU DESIGN
CODE :
-- The mica cpu + ken's shell
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
ENTITY shell IS
PORT (
rxdat : IN std_logic;
xclk : IN std_logic;
rxstb : IN std_logic;
txstb : IN std_logic;
txdat : OUT std_logic;
clk : IN std_logic;
addr : BUFFER std_logic_vector(15 DOWNTO 0);
data : INOUT std_logic_vector(7 DOWNTO 0);
rd : BUFFER std_logic;
wr : BUFFER std_logic;
ramcs : OUT std_logic;
sevseg: OUT std_logic_vector(6 DOWNTO 0)
);
END shell;
[26]
ARCHITECTURE one OF shell IS
COMPONENT cpu PORT (
clk : IN std_logic;
addr : BUFFER std_logic_vector(15 DOWNTO 0);
data : INOUT std_logic_vector(7 DOWNTO 0);
rd : BUFFER std_logic;
wr : BUFFER std_logic;
--ramcs : OUT std_logic;
sevseg: OUT std_logic_vector(6 DOWNTO 0);
din : IN std_logic_vector(15 DOWNTO 0);
dout : OUT std_logic_vector(7 DOWNTO 0);
dsel : IN std_logic_vector(1 DOWNTO 0)
);
END COMPONENT;
SIGNAL din : std_logic_vector(15 DOWNTO 0);
SIGNAL clksel : std_logic_vector(4 DOWNTO 0);
SIGNAL dsel : std_logic_vector(1 DOWNTO 0);
SIGNAL dout : std_logic_vector(7 DOWNTO 0);
SIGNAL txshift : std_logic_vector(7 DOWNTO 0);
SIGNAL txshiftnext: std_logic_vector(7 DOWNTO 0);
SIGNAL rxshift : std_logic_vector(22 DOWNTO 0);
SIGNAL clkdiv : std_logic_vector(23 DOWNTO 0);
SIGNAL cpuclk : std_logic;
[27]
BEGIN
u1: cpu PORT MAP (
clk => cpuclk,
addr => addr,
data => data,
rd => rd,
wr => wr,
--ramcs => ramcs,
sevseg => sevseg,
din => din,
dout => dout,
dsel => dsel
);
-- select ram
ramcs <='0';
-- Drive serial interface
WITH txstb SELECT
txshiftnext <= txshift(6 DOWNTO 0)&'0' WHEN '0',
dout WHEN OTHERS;
txrx: PROCESS
BEGIN
WAIT UNTIL (xclk'event AND xclk='0');
rxshift <= rxshift(21 DOWNTO 0)&(NOT rxdat);
txshift <= txshiftnext;
[28]
END PROCESS txrx;
rx: PROCESS
BEGIN
WAIT UNTIL (rxstb'event AND rxstb='1');
din <= rxshift(15 DOWNTO 0);
dsel <= rxshift(17 DOWNTO 16);
clksel <= rxshift(22 DOWNTO 18);
END PROCESS rx;
txdat <= txshift(7);
-- Run clock divider
PROCESS
BEGIN
WAIT UNTIL (clk'event AND clk='1');
clkdiv <= clkdiv + 1;
END PROCESS;
WITH clksel SELECT
cpuclk <= clk WHEN "00000",
clkdiv(0) WHEN "00001",
clkdiv(1) WHEN "00010",
clkdiv(2) WHEN "00011",
clkdiv(3) WHEN "00100",
clkdiv(4) WHEN "00101",
clkdiv(5) WHEN "00110",
clkdiv(6) WHEN "00111",
[29]
clkdiv(7) WHEN "01000",
clkdiv(8) WHEN "01001",
clkdiv(9) WHEN "01010",
clkdiv(10) WHEN "01011",
clkdiv(11) WHEN "01100",
clkdiv(12) WHEN "01101",
clkdiv(13) WHEN "01110",
clkdiv(14) WHEN "01111",
clkdiv(15) WHEN "10000",
clkdiv(16) WHEN "10001",
clkdiv(17) WHEN "10010",
clkdiv(18) WHEN "10011",
clkdiv(19) WHEN "10100",
clkdiv(20) WHEN "10101",
clkdiv(21) WHEN "10110",
clkdiv(22) WHEN "10111",
clkdiv(23) WHEN "11000",
'0' WHEN "11110",
'1' WHEN "11111",
'0' WHEN OTHERS;
END one;
[30]
DATA FLOW :
TIMING DIAGRAM :
[31]
7. INTERFACING OF CPU MEMORY
CODE:
library ieee;
use ieee.std_logic_1164.all;
entity shift_siso is
port (Clock, Sin : in std_logic;
Sout : out std_logic);
end shift_siso;
architecture behav of shift_siso is
signal temp: std_logic_vector(7 downto 0);
begin
process (Clock)
begin
if (Clock'event and Clock='1') then
for i in 0 to 6 loop
temp(i+1) <= temp(i);
end loop;
temp(0) <= Sin;
end if ;
end process;
Sout <= temp(7);
end behav;
[32]
DATA FLOW :
TIMING DIAGRAM :
[33]
