Interfacing and Peripherals

What do you mean by interface?

An interface (hardware or software) is an agreed-upon method which specifies how one computer component
may exchange data with another component.

Instruction Cycle:

 An instruction cycle (also called fetch-and-execute cycle, fetch-decode-execute cycle) is the time
period during which a computer processes a machine language instruction from its memory or the
sequence of actions that the central processing unit (CPU) performs to execute each machine code
instruction in a program. The name fetch-and-execute cycle is commonly used. The instruction must
be fetched from main memory, and then executed by the CPU. This is fundamentally how a computer
operates, with its CPU reading and executing a series of instructions written in its machine language.
 The fundamental sequence of steps that a CPU performs. It is the time in which a single instruction is
fetched from memory, decoded and executed. The first half of the cycle transfers the instruction from
memory to the instruction register and decodes it. The second half executes the instruction.
 There are typically four stages of an instruction cycle that the CPU carries out:

1. Fetch the instruction from memory. This step brings the instruction into the instruction
register, a circuit that holds the instruction so that it can be decoded and executed.
2. Decode the instruction.
3. Read the effective address from memory if the instruction has an indirect address.
4. Execute the instruction.

Fetch and Execution Cycle:

 The fetch execute cycle is the time period of which the computer reads and processes the instructions
from the memory, and executes them. This process is a continuous cycle which is used until the
computer is turned off or there are no more instructions to process.
 Fetch Cycle: In this cycle, the opcode for the given instruction is fetched by the CPU from the
appropriate storage media (registers, RAM, secondary memory etc). At the beginning of the fetch
cycle, content of the program counter (which is the address of the memory location where opcode is
available) is sent to the memory. The memory places the opcode in the data bus so that it can be sent
to the CPU.
 Execution Cycle: The fetched opcode is sent to the data/address buffer and then to the instruction
register. From the IR it is send to the decoder circuitry where the instruction is decoded and then
executed. In other words, after the correct instructions have been fetched the CPU will then interpret
what the instruction is telling it to do then it will simply execute the instruction and the whole process
will begin again until there are no more instructions or the computer is turned off.

Timing Diagram:

 Necessary steps which are carried out in a machine cycle can be represented graphically. This
graphical representation is referred to as timing diagram.
 Timing Diagram is a graphical representation. It represents the execution time taken by each
instruction in a graphical format. The execution time is represented in T-states.
 Instruction Cycle: The time required to execute an instruction is called instruction cycle.
Machine Cycle:
The time required to access the memory or input/output devices is called machine cycle.
 T-State: The machine cycle and instruction cycle takes multiple clock periods. A portion of an
operation carried out in one system clock period is known as T-state.

 The processor takes a definite time to execute the machine cycles. The time taken by the
processor to execute a machine cycle is expressed in T-states.

 One T-state is equal to the time period of the internal clock signal of the processor.
 The T-state starts at the falling edge of a clock.
 The machine cycle consists of the following viz. Opcode fetch cycle (4T), Memory read cycle (3 T),
Memory write cycle (3 T), I/O read cycle (3 T), I/O write cycle (3 T).

Opcode Fetch Cycle:

The opcodes are stored in memory. So, the processor executes the opcode fetch machine cycle to
fetch the opcode from memory. Hence, every instruction starts with opcode fetch machine cycle. The
time taken by the processor to execute the opcode fetch cycle is 4T. In this time, the first, 3 T-states
are used for fetching the opcode from memory and the remaining T-states are used for internal
operations by the processor. The opcode fetch cycle is as shown:

Figure 1: Opcode Fetch Cycle

Memory Write Cycle:

The memory write machine cycle is executed by the processor to write a data byte in a memory
location. The processor takes 3T states to execute this cycle.
 Figure 2: Memory Write Cycle

I/O Read Cycle of 8085:

 The I/O Read cycle is executed by the processor to read a data byte from I/O port or from the
peripheral, which is I/O, mapped in the system.
 The processor takes 3T states to execute this machine cycle.
 The IN instruction uses this machine cycle during the execution.

Figure 3:I/O Read Cycle

I/O Write Cycle of 8085:

 The I/O write machine cycle is executed by the processor to write a data byte in the I/O port or to a
peripheral, which is I/O, mapped in the system.
  The processor takes 3T states to execute this machine cycle.

Figure 4:I/O Write Cycle

Microprogramming:
It is the process of writing microcode for a microprocessor. Microcode is low-level code that defines how a
microprocessor should function when it executes machine-language instructions. Typically, one machine-
language instruction translates into several microcode instructions. On some computers, the microcode is
stored in ROM and cannot be modified; on some larger computers, it is stored in EPROM and therefore can be
replaced with newer versions.

Control Unit:
A control unit in general is a central (or sometimes distributed but clearly distinguishable) part of whatsoever
machinery that controls its operation, provided that a piece of machinery is complex and organized enough to
contain any such unit.
Central Processing Unit is the principal part of any digital computer system and generally composed of the
main memory, control unit, and arithmetic-logic unit. It constitutes the physical heart of the entire computer
system; to it is linked various peripheral equipment, including input/output devices and auxiliary storage units
(see input/output device; computer memory).
The control unit of the central processing unit regulates and integrates the operations of the computer. It
selects and retrieves instructions from the main memory in proper sequence and interprets them so as to
activate the other functional elements of the system at the appropriate moment to perform their respective
operations. All input data are transferred via the main memory to the arithmetic-logic unit for processing,
which involves the four basic arithmetic functions (i.e. +,-,*,/) and certain logic operations such as the
comparing of data and the selection of the desired problem-solving procedure or a viable alternative based on
predetermined decision criteria.

Serial and Parallel data transmission

The need to provide data transfer between a computer and a remote terminal has led to the development of
serial communication. Serial data transmission implies transfer data transfer bit by bit on the single (serial)
communication line. In case of serial transmission data is sent in a serial form i.e. bit by bit on a single line.
Also, the cost of communication hardware is considerable reduced since only a single wire or channel is
require for the serial bit transmission. Serial data transmission is slow as compared to parallel transmission.
However, parallel data transmission is less common but faster than serial transmission. Most data are
organized into 8 bit bytes. In some computers, data are further organized into multiple bits called half words,
full words. Accordingly data is transferred sometimes a byte or word at a time on multiple wires with each wire
carrying individual data bits. Thus transmitting all bits of a given data byte or word at the same time is known
as parallel data transmission.
Parallel transmission is used primarily for transferring data between devices at the same site. For e.g.:
communication between a computer and printer is most often parallel, so that entire byte can be transferred
in one operation.

Advantages and disadvantages of Synchronous and Asynchronous Communication

Advantages Disadvantages
Asynchronous  Simple, doesn't require  Large relative overhead,
transmission synchronization of both a high proportion of the
communication sides transmitted bits are
 Cheap, timing is not as critical as for uniquely for control
synchronous transmission, therefore purposes and thus carry
hardware can be made cheaper no useful information
 Set-up is very fast, so well suited for
applications where messages are
generated at irregular intervals, for
example data entry from the keyboard

Synchronous  Lower overhead and thus, greater  Slightly more complex

transmission throughput  Hardware is more
 Good if communication is to be expensive
established at all times.  Timing must be accurate.
 Main advantage of Synchronous  Out of sync errors.
communication is the high speed.
The synchronous communications
requires high-speed
peripherals/devices and a good-
quality, high b/w communication
channel.

Synchronous Serial Data Transfer:

In Synchronous communication scheme, after a fixed number of data bytes a special bit pattern is send called
SYNC by the sending end.

Data transmission take place without any gap between two adjacent characters, however data is send block by
block. A block is a continuous stream of characters or data bit pattern coming at a fixed speed. You will find a
Sync bit pattern between any two blocks of data and hence the data transmission is synchronized.
Synchronous communication is used generally when two computers are communicating to each other at a high
speed or a buffered terminal is communicating to the computer.

To Summarize:

i. Transmitter (Tx) and receiver (Rx) are synchronized using same clock pulses.
ii. Blocks of info transmitted along with synchronous information.
iii. Synchronized by transmitting data and clock at the same time or embedding clock with
data.
iv. Longer series of data can be transmitted
v. Used for high speed transmission.

Asynchronous Serial Data Transfer:

Asynchronous communication is transmission of data without the use of an external clock signal. Any timing
required to recover data from the communication symbols is encoded within the symbols. The send and
receive clock generators are not synchronized as in a Synchronous Communication.

 Tx and Rx are not synchronized i.e. they do not have the same clock pulse.
 Each character carries the info of start and stop bit.
 When no data is transmitted, Rx stays high at logic 1.
 Transmission begins with one start bit followed by a character and one or two stop bits.
 Used for low speed transmission.

For Programmable Peripheral Interface (PPI) and 8255 refer to class notes

Programmable Interrupt Controller:

A programmable interrupt controller (PIC) is a device which allows priority levels to be assigned to its
interrupt outputs. When the device has multiple interrupt outputs to assert, it will assert them in the order of
their relative priority. Common modes of a PIC include hard priorities, rotating priorities, and cascading
priorities. PICs often allow the cascading of their outputs to inputs between each other. PICs typically have a
common set of registers: Interrupt Request Register (IRR), In-Service Register (ISR) and Interrupt Mask Register
(IMR). The IRR specifies which interrupts are pending acknowledgement, and is typically a symbolic register
which cannot be directly accessed. The ISR register specifies which interrupts have been acknowledged, but
are still waiting for an End Of Interrupt (EOI). The IMR specifies which interrupts are to be ignored and not
acknowledged. Intel 8259 is one of the most widely known PICs. The Intel 8259 is a family of Programmable
Interrupt Controllers (PICs) designed and developed for use with the Intel 8085 and Intel 8086 8-bit and 16-bit
microprocessors. The 8259 acts as a multiplexer, combining multiple interrupt input sources into a single
interrupt output to interrupt a single device. The pin specification and pin description is given below.