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F280023C Datasheet

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F280023C Datasheet

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TMS320F280025, TMS320F280025-Q1

TMS320F280025C, TMS320F280025C-Q1, TMS320F280025,

TMS320F280023, TMS320F280025-Q1
TMS320F280023-Q1
TMS320F280025C, TMS320F280025C-Q1, TMS320F280023, TMS320F280021-Q1
TMS320F280023C, TMS320F280021, TMS320F280023-Q1
www.ti.com TMS320F280023C, TMS320F280021,
SPRSP45B TMS320F280021-Q1
– MARCH 2020 – REVISED DECEMBER 2020
SPRSP45B – MARCH 2020 – REVISED DECEMBER 2020

TMS320F28002x Real-Time Microcontrollers

• Analog system
1 Features
– Two 3.45-MSPS, 12-bit Analog-to-Digital
• TMS320C28x 32-bit DSP core at 100 MHz Converters (ADCs)
– IEEE 754 Floating-Point Unit (FPU) • Up to 16 external channels
• Support for Fast Integer Division (FINTDIV) • Four integrated Post-Processing Blocks
– Trigonometric Math Unit (TMU) (PPB) per ADC
• Support for Nonlinear Proportional Integral – Four windowed comparators (CMPSS) with
Derivative (NLPID) control 12-bit reference Digital-to-Analog Converters
– CRC Engine and Instructions (VCRC) (DACs)
– Ten hardware breakpoints (with ERAD) • Digital glitch filters
• On-chip memory • Enhanced control peripherals
– 128KB (64KW) of flash (ECC-protected) – 14 ePWM channels with eight channels that
– 24KB (12KW) of RAM (ECC or parity-protected) have high-resolution capability (150-ps
– Dual-zone security resolution)
• Clock and system control • Integrated dead-band support
– Two internal zero-pin 10-MHz oscillators • Integrated hardware trip zones (TZs)
– On-chip crystal oscillator or external clock input – Three Enhanced Capture (eCAP) modules
– Windowed watchdog timer module • High-resolution Capture (HRCAP) available
– Missing clock detection circuitry on one of the three eCAP modules
– Dual-clock Comparator (DCC) – Two Enhanced Quadrature Encoder Pulse
(eQEP) modules with support for CW/CCW
• Single 3.3-V supply
operation modes
– Internal VREG generation
• Configurable Logic Block (CLB)
– Brownout reset (BOR) circuit
– Augments existing peripheral capability
• System peripherals
– Supports position manager solutions
– 6-channel Direct Memory Access (DMA)
• Host Interface Controller (HIC)
controller
– Access to internal memory from an external
– 39 individually programmable multiplexed
host
General-Purpose Input/Output (GPIO) pins
• Background CRC (BGCRC)
– 16 digital inputs on analog pins
– One cycle CRC computation on 32 bits of data
– Enhanced Peripheral Interrupt Expansion
(ePIE) • Diagnostic features
– Multiple low-power mode (LPM) support – Memory Power On Self Test (MPOST)
– Embedded Real-time Analysis and Diagnostic – Hardware Built-in Self Test (HWBIST)
(ERAD) • Package options:
– Unique Identification (UID) number – 80-pin Low-profile Quad Flatpack (LQFP)
• Communications peripherals [PN suffix]
– One Power-Management Bus (PMBus) – 64-pin LQFP [PM suffix]
interface – 48-pin LQFP [PT suffix]
– Two Inter-integrated Circuit (I2C) interfaces • Temperature options:
– One Controller Area Network (CAN) bus port – S: –40°C to 125°C junction
– Two Serial Peripheral Interface (SPI) ports – Q: –40°C to 125°C free-air
– One UART-compatible Serial Communication (AEC Q100 qualification for automotive
Interface (SCI) applications)
– Two UART-compatible Local Interconnect
Network (LIN) interfaces
– Fast Serial Interface (FSI) with one transmitter
and one receiver (up to 200Mbps)

An©IMPORTANT
Copyright NOTICEIncorporated
2020 Texas Instruments at the end of this data sheet addresses availability, warranty, changes, use in safety-critical
Submit Document applications,
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intellectual property matters and other important disclaimers. PRODUCTION DATA.
Product Folder Links: TMS320F280025 TMS320F280025-Q1 TMS320F280025C TMS320F280025C-Q1
TMS320F280023 TMS320F280023-Q1 TMS320F280023C TMS320F280021 TMS320F280021-Q1
TMS320F280025, TMS320F280025-Q1
TMS320F280025C, TMS320F280025C-Q1, TMS320F280023, TMS320F280023-Q1
TMS320F280023C, TMS320F280021, TMS320F280021-Q1
SPRSP45B – MARCH 2020 – REVISED DECEMBER 2020 www.ti.com

• Body electronics & lighting

2 Applications
– Automotive HVAC compressor module
• Appliances – DC/AC inverter
– Air conditioner outdoor unit – Headlight
• Building automation • AC inverter & VF drives
– Door operator drive control – AC drive control module
• Industrial machine & machine tools – AC drive position feedback
– Automated sorting equipment – AC drive power stage module
– Textile machine • Linear motor transport systems
• EV charging infrastructure – Linear motor power stage
– AC charging (pile) station • Single & multi axis servo drives
– DC charging (pile) station – Servo drive position feedback
– EV charging station power module – Servo drive power stage module
– Wireless EV charging station • Speed controlled BLDC drives
• Renewable energy storage – AC-input BLDC motor drive
– Energy storage power conversion system – DC-input BLDC motor drive
(PCS)
• Industrial power
• Solar energy
– Industrial AC-DC
– Central inverter
• UPS
– Micro inverter
– Three phase UPS
– Solar power optimizer
– Single phase online UPS
– Solar arc protection
• Telecom & server power
– Rapid shutdown
– Merchant DC/DC
– Electricity meter
– Merchant network & server PSU
– String inverter
– Merchant telecom rectifiers
• Hybrids, electric & powertrain systems
– DC/DC converter
– Inverter & motor control
– On-board (OBC) & wireless charger

3 Description
The TMS320F28002x (F28002x) is a member of the C2000™ real-time microcontroller family of scalable, ultra-
low latency devices designed for efficiency in power electronics, including but not limited to: high power density,
high switching frequencies, and supporting the use of GaN and SiC technologies.
These include such applications as:
• Industrial motor drives
• Motor control
• Solar inverters
• Digital power
• Electrical vehicles and transportation
• Sensing and signal processing
The real-time control subsystem is based on TI’s 32-bit C28x DSP core, which provides 100 MHz of signal-
processing performance for floating- or fixed-point code running from either on-chip flash or SRAM. The C28x
CPU is further boosted by the Trigonometric Math Unit (TMU) and VCRC (Cyclical Redundancy Check)
extended instruction sets, speeding up common algorithms key to real-time control systems.
High-performance analog blocks are integrated on the F28002x real-time microcontroller (MCU) and are closely
coupled with the processing and PWM units to provide optimal real-time signal chain performance. Fourteen
PWM channels, all supporting frequency-independent resolution modes, enable control of various power stages
from a 3-phase inverter to advanced multi-level power topologies.

2 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated

Product Folder Links: TMS320F280025 TMS320F280025-Q1 TMS320F280025C TMS320F280025C-Q1

TMS320F280023 TMS320F280023-Q1 TMS320F280023C TMS320F280021 TMS320F280021-Q1
TMS320F280025, TMS320F280025-Q1
TMS320F280025C, TMS320F280025C-Q1, TMS320F280023, TMS320F280023-Q1
TMS320F280023C, TMS320F280021, TMS320F280021-Q1
www.ti.com SPRSP45B – MARCH 2020 – REVISED DECEMBER 2020

The inclusion of the Configurable Logic Block (CLB) allows the user to add custom logic and potentially integrate
FPGA-like functions into the C2000 real-time MCU.
Interfacing is supported through various industry-standard communication ports (such as SPI, SCI, I2C, PMBus,
LIN, and CAN) and offers multiple pin-muxing options for optimal signal placement. The Fast Serial Interface
(FSI) enables up to 200 Mbps of robust communications across an isolation boundary.
New to the C2000 platform is the Host Interface Controller (HIC), a high-throughput interface that allows an
external host to access the resources of the TMS320F28002x directly.
Want to learn more about features that make C2000 MCUs the right choice for your real-time control system?
Check out The Essential Guide for Developing With C2000™ Real-Time Microcontrollers and visit the C2000™
real-time control MCUs page.
Ready to get started? Check out the TMDSCNCD280025C evaluation board and download C2000Ware.
Device Information
CONFIGURABLE LOGIC
PART NUMBER(1) FLASH SIZE
BLOCK (CLB)
TMS320F280025C 2 Tiles
128KB
TMS320F280025 –
TMS320F280023C 2 Tiles
64KB
TMS320F280023 –
TMS320F280021 – 32KB

(1) For more information on these devices, see the Device Comparison table.

Copyright © 2020 Texas Instruments Incorporated Submit Document Feedback 3

Product Folder Links: TMS320F280025 TMS320F280025-Q1 TMS320F280025C TMS320F280025C-Q1
TMS320F280023 TMS320F280023-Q1 TMS320F280023C TMS320F280021 TMS320F280021-Q1
TMS320F280025, TMS320F280025-Q1
TMS320F280025C, TMS320F280025C-Q1, TMS320F280023, TMS320F280023-Q1
TMS320F280023C, TMS320F280021, TMS320F280021-Q1
SPRSP45B – MARCH 2020 – REVISED DECEMBER 2020 www.ti.com

3.1 Functional Block Diagram

The Functional Block Diagram shows the CPU system and associated peripherals.

Boot ROM Secure Memories

shown in Red
C28x CPU Secure ROM

FPU32 Bus Legend

FINTDIV Flash Bank0
16 Sectors CPU
TMU
VCRC 64 KW (128 KB) DMA
HIC

CPU Timers BGCRC

DCC
DCSM M0-M1 RAM
ePIE 2 KW (4 KB)
ERAD
BGCRC
LS4-LS7 RAM
8 KW (16 KB)
Crystal Oscillator HIC
INTOSC1, INTOSC2
GS0 RAM
PLL DMA
2 KW (4 KB)
6 Channles

PF1 PF3 PF4 PF2 PF7 PF8 PF9

14x ePWM Chan. 14x ePWM Chan. Result Data 1x PMBUS 1x CAN 2x LIN 1x SCI
4x CMPSS
(8 Hi-Res Capable) (8 Hi-Res Capable) 2x 12-Bit ADC 39x GPIO 2x SPI 2x I2C
3x eCAP 3x eCAP Input XBAR
2x CLB 1x FSI RX NMI
(1 HRCAP Capable) (1 HRCAP Capable)
Output XBAR 1x FSI TX Watchdog
2x eQEP
(CW/CCW Support) ePWM XBAR Windowed
Watchdog
CLB XBAR

Figure 3-1. Functional Block Diagram

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Table of Contents
1 Features............................................................................1 8 Detailed Description....................................................153
2 Applications..................................................................... 2 8.1 Overview................................................................. 153
3 Description.......................................................................2 8.2 Functional Block Diagram....................................... 154
3.1 Functional Block Diagram........................................... 4 8.3 Memory................................................................... 155
4 Revision History.............................................................. 6 8.4 Identification............................................................160
5 Device Comparison......................................................... 9 8.5 Bus Architecture – Peripheral Connectivity.............161
5.1 Related Products...................................................... 10 8.6 C28x Processor...................................................... 162
6 Terminal Configuration and Functions........................ 11 8.7 Embedded Real-Time Analysis and Diagnostic
6.1 Pin Diagrams.............................................................11 (ERAD)...................................................................... 164
6.2 Pin Attributes.............................................................14 8.8 Background CRC-32 (BGCRC).............................. 164
6.3 Signal Descriptions................................................... 29 8.9 Direct Memory Access (DMA).................................165
6.4 Pin Multiplexing.........................................................39 8.10 Device Boot Modes...............................................166
6.5 Pins With Internal Pullup and Pulldown.................... 46 8.11 Dual Code Security Module.................................. 172
6.6 Connections for Unused Pins................................... 47 8.12 Watchdog.............................................................. 173
7 Specifications................................................................ 48 8.13 C28x Timers..........................................................174
7.1 Absolute Maximum Ratings ..................................... 48 8.14 Dual-Clock Comparator (DCC)............................. 174
7.2 ESD Ratings – Commercial...................................... 48 8.15 Configurable Logic Block (CLB)............................176
7.3 ESD Ratings – Automotive....................................... 49 9 Applications, Implementation, and Layout............... 178
7.4 Recommended Operating Conditions ......................49 9.1 TI Reference Design............................................... 178
Supply Voltages.............................................................. 50 10 Device and Documentation Support........................179
7.5 Power Consumption Summary................................. 51 10.1 Getting Started and Next Steps............................ 179
7.6 Electrical Characteristics ..........................................55 10.2 Device and Development Support Tool
7.7 Thermal Resistance Characteristics for PN Nomenclature............................................................ 179
Package...................................................................... 56 10.3 Markings............................................................... 180
7.8 Thermal Resistance Characteristics for PM 10.4 Tools and Software............................................... 182
Package...................................................................... 56 10.5 Documentation Support........................................ 183
7.9 Thermal Resistance Characteristics for PT 10.6 Support Resources............................................... 184
Package...................................................................... 57 10.7 Trademarks........................................................... 185
7.10 Thermal Design Considerations..............................57 10.8 Electrostatic Discharge Caution............................185
7.11 System.................................................................... 58 10.9 Glossary................................................................185
7.12 Analog Peripherals..................................................86 11 Mechanical, Packaging, and Orderable
7.13 Control Peripherals............................................... 106 Information.................................................................. 186
7.14 Communications Peripherals................................ 121 11.1 Packaging Information.......................................... 186

Copyright © 2020 Texas Instruments Incorporated Submit Document Feedback 5

4 Revision History
Changes from October 4, 2020 to December 31, 2020 (from Revision A (October 2020) to
Revision B (December 2020)) Page
• Global: Added TMS320F280025-Q1, TMS320F280025C-Q1, TMS320F280023-Q1, and TMS320F280021-
Q1....................................................................................................................................................................... 1
• Table 5-1 (Device Comparison): Added TMS320F280025-Q1, TMS320F280025C-Q1, TMS320F280023-Q1,
and TMS320F280021-Q1. Updated table...........................................................................................................1
• Table 6-1 (Pin Attributes): Updated muxed signal names of A7. Updated DESCRIPTION of VDD: Changed
recommended total capacitance from 22 µF to 10 µF.......................................................................................11
• Removed Digital Signals by GPIO section (Section 6.3.2 in SPRSP45A)........................................................29
• Section 6.3.2 (Digital Signals): Added section..................................................................................................29
• Table 6-4 (Power and Ground): Updated DESCRIPTION of VDD: Changed recommended total capacitance
from 22 µF to 10 µF...........................................................................................................................................29
• Section 7.2 (ESD Ratings – Commercial): Updated device numbers...............................................................48
• Section 7.3 (ESD Ratings – Automotive): Updated device numbers. Added data for 64-pin PM package...... 49
• Section 7.5.1 (System Current Consumption): Updated table..........................................................................51
• Section 7.11.1.1 (Internal 1.2-V LDO Voltage Regulator (VREG)): Updated Configuration 1.......................... 58
• Section 7.11.3.5.1 (INTOSC Characteristics): Updated table........................................................................... 69
• Table 7-5 (Flash Parameters): Changed "Nwec Write/Erase Cycles" to "Nwec Write/Erase Cycles per sector".
Added "Nwec Write/Erase Cycles for entire Flash (combined all sectors)"........................................................70
• Section 7.14.8 (Host Interface Controller (HIC)): Updated "The HIC module allows ..." paragraph............... 149
• Figure 7-70 (HIC Block Diagram): Removed "Bus Master Interface" label.....................................................149
• Figure 10-1 (Device Nomenclature): Updated figure...................................................................................... 179
• Section 10.4 (Tools and Software): Added LAUNCHXL-F280025C to Development Tools section............. 182

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Product Folder Links: TMS320F280025 TMS320F280025-Q1 TMS320F280025C TMS320F280025C-Q1

Changes from March 17, 2020 to October 3, 2020 (from Revision * (March 2020) to Revision A
(October 2020)) Page
• Global: Updated the numbering format for tables, figures, and cross-references throughout the document.... 1
• Global: This document is now PRODUCTION DATA........................................................................................ 1
• Global: Removed TMS320F280024, TMS320F280024C, and TMS320F280022............................................. 1
• Global: Removed 64 QFP-Q data......................................................................................................................1
• Section 1 (Features): Updated Serial Communication Interface (SCI) feature. Updated Local Interconnect
Network (LIN) feature......................................................................................................................................... 1
• Table 5-1 (Device Comparison): Updated table..................................................................................................1
• Section 2 (Applications): Updated section.......................................................................................................... 2
• Section 3 (Description): Updated section........................................................................................................... 2
• Device Information: Updated table..................................................................................................................... 2
• Figure 3-1 (Functional Block Diagram): Updated figure..................................................................................... 4
• Table 6-1 (Pin Attributes): Updated table.......................................................................................................... 11
• Figure 6-2 (64-Pin PM Low-Profile Quad Flatpack (Top View)): Updated figure...............................................11
• Removed "64-Pin PM Low-Profile Quad Flatpack – Q-Temperature (Top View)" figure...................................11
• Removed Digital Signals section (Section 4.3.2 in SPRSP45).........................................................................29
• Digital Signals by GPIO: Added section........................................................................................................... 29
• Table 6-4 (Power and Ground): Updated DESCRIPTION of VDD and VDDIO................................................ 29
• Section 6.4.1.1 (GPIO Muxed Pins Table): Added Note about AIO pins.......................................................... 40
• Table 6-6 (GPIO Muxed Pins): Updated table.................................................................................................. 40
• Section 6.4.4 (GPIO Output X-BAR, CLB X-BAR, CLB Output X-BAR, and ePWM X-BAR): Changed section
title from "GPIO Output X-BAR and ePWM X-BAR" to "GPIO Output X-BAR, CLB X-BAR, CLB Output X-
BAR, and ePWM X-BAR". Updated section..................................................................................................... 44
• Figure 6-5 (Output X-BAR, CLB X-BAR, CLB Output X-BAR, and ePWM X-BAR Sources): Replaced "Output
X-BAR and ePWM X-BAR Sources" figure with "Output X-BAR, CLB X-BAR, CLB Output X-BAR, and ePWM
X-BAR Sources" figure..................................................................................................................................... 44
• Table 6-9 (Connections for Unused Pins): Added "Analog input pins" in ANALOG section............................. 47
• Section 7 (Specifications): Updated section and tables....................................................................................48
• Section 7.1 (Absolute Maximum Ratings): Updated table................................................................................ 48
• Section 7.4 (Recommended Operating Conditions): Updated SRSUPPLY values and unit................................ 48
• Section 7.6 (Electrical Characteristics): Updated ROH and ROL values............................................................ 48
• Section 7.3 (ESD Ratings – Automotive): Removed F280024, F280024C, and F280022 data....................... 49
• Section 7.5.3 (Current Consumption Graphs): Added section..........................................................................52
• Section 7.5.4 (Reducing Current Consumption): Updated section................................................................... 54
• Section 7.5.4.1 (Typical Current Reduction per Disabled Peripheral): Updated table...................................... 54
• Section 7.7 (Thermal Resistance Characteristics for PN Package): Added section.........................................56
• Section 7.8 (Thermal Resistance Characteristics for PM Package): Added section........................................ 56
• Section 7.9 (Thermal Resistance Characteristics for PT Package): Added section......................................... 57
• Section 7.11.2.2.1 (Reset (XRSn) Timing Requirements): Updated tw(RSL2).................................................... 60
• Section 7.11.2.2.2 (Reset (XRSn) Switching Characteristics): Added tboot-flash................................................ 60
• Figure 7-8 (Power-on Reset): Updated figure...................................................................................................60
• Section 7.11.3.2.1.6 (Internal Clock Frequencies): Updated MAX f(VCOCLK).....................................................65
• Section 7.11.3.5 (Internal Oscillators): Updated section...................................................................................69
• Section 7.11.3.5.1 (INTOSC Characteristics): Updated fINTOSC MIN values and MAX values......................... 69
• Section 7.11.4 (Flash Parameters): Updated section....................................................................................... 70
• Table 7-4 (Minimum Required Flash Wait States with Different Clock Sources and Frequencies): Updated
table and footnotes........................................................................................................................................... 70
• Table 7-5 (Flash Parameters): Added "The on-chip flash memory is in an erased state ..." footnote.............. 70

Copyright © 2020 Texas Instruments Incorporated Submit Document Feedback 7

• Section 7.11.5 (Emulation/JTAG): Updated link of Hardware Breakpoints and Watchpoints for C28x in CCS....
72
• Figure 7-31 (Analog Group Connections): Added figure.................................................................................. 86
• Figure 7-35 (ADC Timings): Updated tINT......................................................................................................... 98
• Section 7.14.2.1.1 (I2C Timing Requirements): Updated table...................................................................... 125
• Section 7.14.2.1.2 (I2C Switching Characteristics): Updated table................................................................ 125
• Figure 7-54 (I2C Timing Diagram): Added figure............................................................................................125
• Figure 7-56 (SCI Block Diagram): Updated figure.......................................................................................... 130
• Figure 7-59 (SPI Master Mode External Timing (Clock Phase = 1)): Updated parameter 24.........................134
• Section 7.14.5.2.1 (SPI Slave Mode Timing Requirements): Updated MIN value of tsu(STE)S........................ 138
• Section 7.14.8 (Host Interface Controller (HIC)): Updated list of features......................................................149
• Figure 7-70 (HIC Block Diagram): Updated figure..........................................................................................149
• Section 7.14.8.1.1 (HIC Timing Requirements): Updated table......................................................................150
• Section 7.14.8.1.2 (HIC Switching Characteristics): Updated table................................................................150
• Figure 7-71 (Read/Write Operation With nOE and nWE Pins): Added figure.................................................151
• Figure 7-72 (Read/Write Operation With RnW Pin): Added figure..................................................................151
• Figure 8-1 (Functional Block Diagram): Added "Secure Memories shown in Red" legend box..................... 154
• Table 8-2 (Addresses of Flash Sectors): Updated table................................................................................. 156
• Table 8-4 (Device Identification Registers): Removed PARTIDH for TMS320F280024, TMS320F280024C,
and TMS320F280022..................................................................................................................................... 160
• Table 8-4: Added REVID for Revision A silicon.............................................................................................. 160
• Table 8-4: Updated ADDRESS of UID_UNIQUE............................................................................................160
• Section 8.10 (Device Boot Modes): Updated section..................................................................................... 166
• Section 8.10.1 (Device Boot Configurations): Added Note about CAN boot mode turning on the XTAL....... 166
• Figure 8-3 (Windowed Watchdog): Removed SCSR.WDOVERRIDE............................................................ 173
• Section 9.1 (TI Reference Design): Updated section..................................................................................... 178
• Removed Related Links section (Section 10.5 in SPRSP45).........................................................................179
• Section 10.1 (Getting Started and Next Steps): Added section......................................................................179
• Section 10.2 (Device and Development Support Tool Nomenclature): Updated section................................179
• Figure 10-1 (Device Nomenclature): Removed 280024, 280024C, and 280022 from DEVICE..................... 179
• Figure 10-2 (Package Symbolization for PM and PN Packages): Updated figure..........................................180
• Figure 10-3 (Package Symbolization for PT Package): Updated figure......................................................... 180
• Table 10-1 (Revision Identification): Added data for Revision A silicon..........................................................180
• Section 10.4 (Tools and Software): Updated section......................................................................................182
• Section 10.5 (Documentation Support): Updated section...............................................................................183

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5 Device Comparison
Table 5-1. Device Comparison
F280025
F280023
(1) F280025-Q1 F280021
FEATURE F280023-Q1
F280025C F280021-Q1
F280023C
F280025C-Q1
PROCESSOR AND ACCELERATORS
Frequency (MHz) 100
FPU32 Yes (with new instructions for Fast Integer Division)
C28x VCRC Yes
TMU – Type 1 Yes (with new instructions supporting NLPID)
Fast Integer Division Yes
DMA – Type 0 Yes
MEMORY
Flash 128KB (64KW) 64KB (32KW) 32KB (16KW)
Dedicated and Local Shared RAM 20KB (10KW)
RAM Global Shared RAM 4KB (2KW)
TOTAL RAM 24KB (12KW)
Code security for on-chip flash and RAM Yes
SYSTEM
(2)
Configurable Logic Block (CLB) (F280025C-2 tiles) (F280023C-2 tiles) -
32-bit CPU timers 3
Watchdog-timer 1
Nonmaskable Interrupt Watchdog (NMIWD) timers 1
Crystal oscillator/External clock input 1
0-pin internal oscillator 2
80-pin PN 39
64-pin PM 26

GPIO pins 48-pin PT 16

4 (When cJTAG is used, TDI and TDO can be GPIO;
Additional GPIO When INTOSC is used as clock source, X1 and X2 can be
GPIO)
80-pin PN 16
AIO inputs 64-pin PM 16
48-pin PT 14
External interrupts 5
ANALOG PERIPHERALS
Number of ADCs 2
ADC 12-bit MSPS 3.45
(3)
Conversion-time (ns) 290
80-pin PN 16
ADC channels (single-ended) 64-pin PM 16
48-pin PT 14
Temperature sensor 1
CMPSS (each has two comparators and two internal DACs) 4

Copyright © 2020 Texas Instruments Incorporated Submit Document Feedback 9

Table 5-1. Device Comparison (continued)

F280025
F280023
(1) F280025-Q1 F280021
FEATURE F280023-Q1
F280025C F280021-Q1
F280023C
F280025C-Q1
(4)
CONTROL PERIPHERALS
eCAP/HRCAP modules – Type 1 3 (1 with HRCAP capability)
ePWM/HRPWM channels – Type 4 14 (8 with HRPWM capability)
eQEP modules – Type 2 2
(4)
COMMUNICATION PERIPHERALS
CAN – Type 0 1
I2C – Type 1 2
SCI – Type 0 (UART-Compatible) 1
SPI – Type 2 2
LIN – Type 1 (UART-Compatible) 2
PMBus – Type 0 1
FSI – Type 1 1 (1 RX and 1 TX)
PACKAGE, TEMPERATURE, AND QUALIFICATION OPTIONS
80-pin PN –
F280025 F280023
S: –40°C to 125°C (TJ) 64-pin PM –
F280025C F280023C
48-pin PT F280021
80-pin PN –
(5) F280025-Q1
Q: –40°C to 125°C (TA) 64-pin PM F280023-Q1 –
F280025C-Q1
48-pin PT F280021-Q1

(1) A type change represents a major functional feature difference in a peripheral module. Within a peripheral type, there may be minor
differences between devices that do not affect the basic functionality of the module.
(2) C devices include additional Motor Control libraries in ROM. Contact TI for more information.
(3) Time between start of sample-and-hold window to start of sample-and-hold window of the next conversion.
(4) For devices that are available in more than one package, the peripheral count listed in the smaller package is reduced because the
smaller package has less device pins available. The number of peripherals internally present on the device is not reduced co
(5) The letter Q refers to AEC Q100 qualification for automotive applications.

5.1 Related Products

TMS320F2803x Real-Time Microcontrollers
The F2803x series increases the pin-count and memory size options. The F2803x series also introduces the
parallel control law accelerator (CLA) option.
TMS320F2807x Real-Time Microcontrollers
The F2807x series offers the most performance, largest pin counts, flash memory sizes, and peripheral options.
The F2807x series includes the latest generation of accelerators, ePWM peripherals, and analog technology.
TMS320F28004x Real-Time Microcontrollers
The F28004x series is a reduced version of the F2807x series with the latest generational enhancements.
TMS320F2838x Real-Time Microcontrollers
The F2838x series offers more performance, larger pin counts, flash memory sizes, peripheral and wide variety
of connectivity options. The F2838x series includes the latest generation of accelerators, ePWM peripherals, and
analog technology. Configurable logic block (CLB) versions are available.

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6 Terminal Configuration and Functions

6.1 Pin Diagrams
Figure 6-1 shows the pin assignments on the 80-pin PN low-profile quad flatpack (Q temperature). Figure 6-2
shows the pin assignments on the 64-pin PM low-profile quad flatpack. Figure 6-3 shows the pin assignments on
the 48-Pin PT low-profile quad flatpack.

GPIO37/TDO
GPIO35/TDI
GPIO19,X1

GPIO18,X2
GPIO42

GPIO39

GPIO43

GPIO32

GPIO27

GPIO26

GPIO25

GPIO24
VDDIO
GPIO3

GPIO4

GPIO8

VDD

TMS
VSS

TCK
60

41
GPIO2 61 40 GPIO17

GPIO1 62 39 GPIO16

GPIO0 63 38 GPIO33

GPIO40 64 37 GPIO11

GPIO23 65 36 GPIO12

GPIO41 66 35 GPIO13

GPIO22 67 34 FLT1

GPIO7 68 33 FLT2

GPIO44 69 32 VDDIO

VSS 70 31 VDD

VDD 71 30 VSS

VDDIO 72 29 A10,C10

GPIO45 73 28 A9,C8

GPIO5 74 27 A4,C14

GPIO9 75 26 VDDA

GPIO10 76 25 VSSA

GPIO34 77 24 A8,C11

GPIO15 78 23 A7,C3

GPIO14 79 22 A12,C1

GPIO6 80 21 VREFLO
10

20
11
1

Not to scale
GPIO30

GPIO31

GPIO29

GPIO28

GPIO46

VDDIO

VREFHI
XRSn

VDD

VSS

A3,C5

A2,C9

A15,C7

A14,C4

A11,C0

A5,C2

A0,C15

A. Only the GPIO function is shown on GPIO terminals. See Table 6-1 for the complete, muxed signal name.

Figure 6-1. 80-Pin PN Low-Profile Quad Flatpack (Top View)

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GPIO37/TDO
GPIO35/TDI
GPIO19_X1

GPIO18_X2
GPIO39

GPIO32

GPIO24

GPIO17

GPIO16
VDDIO
GPIO4

GPIO8

VDD

TMS
VSS

TCK
48

33
GPIO3 49 32 GPIO33

GPIO2 50 31 GPIO11

GPIO1 51 30 GPIO12

GPIO0 52 29 GPIO13

GPIO40 53 28 VDDIO

GPIO23 54 27 VDD

GPIO41 55 26 VSS

GPIO22 56 25 A10,C10

GPIO7 57 24 A9,C8

VSS 58 23 A4,C14

VDD 59 22 VDDA

VDDIO 60 21 VSSA

GPIO5 61 20 A8,C11

GPIO9 62 19 A7,C3

GPIO10 63 18 A12,C1

GPIO6 64 17 VREFLO
10

16
11
1

Not to scale
GPIO29

GPIO28

VREFHI
XRSn

VDD

VSS

A3,C5,VDAC

A2,C9

A15,C7

A14,C4

A11,C0

A5,C2

A0,C15

A. Only the GPIO function is shown on GPIO terminals. See Table 6-1 for the complete, muxed signal name.

Figure 6-2. 64-Pin PM Low-Profile Quad Flatpack (Top View)

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GPIO37/TDO
GPIO35/TDI
GPIO19_X1

GPIO18_X2

GPIO32

GPIO24

GPIO16

GPIO33
VDDIO
VDD

TMS

TCK
36

25
VSS 37 24 GPIO12

GPIO4 38 23 GPIO13

GPIO3 39 22 VSS

GPIO2 40 21 A10,C10

GPIO1 41 20 A9,C8

GPIO0 42 19 A4,C14

GPIO7 43 18 VDDA

VSS 44 17 VSSA

VDD 45 16 A8,C11

VDDIO 46 15 A7,C3

GPIO5 47 14 A12,C1

GPIO6 48 13 VREFLO
10

12
11
1

Not to scale
GPIO29

GPIO28

VREFHI
XRSn

A6,C6

A3,C5,VDAC

A2,C9

A11,C0
A15,C7

A5,C2

A0,C15

A. Only the GPIO function is shown on GPIO terminals. See Table 6-1 for the complete, muxed signal name.

Figure 6-3. 48-Pin PT Low-Profile Quad Flatpack (Top View)

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6.2 Pin Attributes

Table 6-1. Pin Attributes
MUX PIN
SIGNAL NAME 80 QFP 64 QFP 48 QFP DESCRIPTION
POSITION TYPE
ANALOG
A0 I ADC-A Input 0
C15 I ADC-C Input 15
CMP3_HP2 I CMPSS-3 High Comparator Positive Input 2
19 15 11
CMP3_LP2 I CMPSS-3 Low Comparator Positive Input 2
AIO231 0, 4, 8, 12 I Analog Pin Used For Digital Input 231
HIC_BASESEL1 15 I HIC Base Address Range Select 1
A1 I Analog Input
CMP1_HP4 I CMPSS-1 High Comparator Positive Input 4
CMP1_LP4 18 14 10 I CMPSS-1 Low Comparator Positive Input 4
AIO232 0, 4, 8, 12 I Analog Pin Used For Digital Input 232
HIC_BASESEL0 15 I HIC Base Address Range Select 0
A10 I ADC-A Input 10
C10 I ADC-C Input 10
CMP2_HP3 I CMPSS-2 High Comparator Positive Input 3
CMP2_HN0 I CMPSS-2 High Comparator Negative Input 0
29 25 21
CMP2_LP3 I CMPSS-2 Low Comparator Positive Input 3
CMP2_LN0 I CMPSS-2 Low Comparator Negative Input 0
AIO230 0, 4, 8, 12 I Analog Pin Used For Digital Input 230
HIC_BASESEL2 15 I HIC Base Address Range Select 2
A11 I ADC-A Input 11
C0 I ADC-C Input 0
CMP1_HP1 I CMPSS-1 High Comparator Positive Input 1
CMP1_HN1 I CMPSS-1 High Comparator Negative Input 1
16 12 8
CMP1_LP1 I CMPSS-1 Low Comparator Positive Input 1
CMP1_LN1 I CMPSS-1 Low Comparator Negative Input 1
AIO237 0, 4, 8, 12 I Analog Pin Used For Digital Input 237
HIC_A6 15 I HIC Address 6
A12 I ADC-A Input 12
C1 I ADC-C Input 1
CMP2_HP1 I CMPSS-2 High Comparator Positive Input 1
CMP4_HP2 I CMPSS-4 High Comparator Positive Input 2
CMP2_HN1 I CMPSS-2 High Comparator Negative Input 1
22 18 14
CMP2_LP1 I CMPSS-2 Low Comparator Positive Input 1
CMP4_LP2 I CMPSS-4 Low Comparator Positive Input 2
CMP2_LN1 I CMPSS-2 Low Comparator Negative Input 1
AIO238 0, 4, 8, 12 I Analog Pin Used For Digital Input 238
HIC_NCS 15 I HIC Chip Select
A14 I ADC-A Input 14
C4 I ADC-C Input 4
CMP3_HP4 I CMPSS-3 High Comparator Positive Input 4
15 11
CMP3_LP4 I CMPSS-3 Low Comparator Positive Input 4
AIO239 0, 4, 8, 12 I Analog Pin Used For Digital Input 239
HIC_A5 15 I HIC Address 5

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Table 6-1. Pin Attributes (continued)

MUX PIN
SIGNAL NAME 80 QFP 64 QFP 48 QFP DESCRIPTION
POSITION TYPE
A15 I ADC-A Input 15
C7 I ADC-C Input 7
CMP1_HP3 I CMPSS-1 High Comparator Positive Input 3
CMP1_HN0 I CMPSS-1 High Comparator Negative Input 0
14 10 7
CMP1_LP3 I CMPSS-1 Low Comparator Positive Input 3
CMP1_LN0 I CMPSS-1 Low Comparator Negative Input 0
AIO233 0, 4, 8, 12 I Analog Pin Used For Digital Input 233
HIC_A4 15 I HIC Address 4
A2 I ADC-A Input 2
C9 I ADC-C Input 9
CMP1_HP0 I CMPSS-1 High Comparator Positive Input 0
13 9 6
CMP1_LP0 I CMPSS-1 Low Comparator Positive Input 0
AIO224 0, 4, 8, 12 I Analog Pin Used For Digital Input 224
HIC_A3 15 I HIC Address 3
A3 I ADC-A Input 3
C5 I ADC-C Input 5
Optional external reference voltage for on-chip
CMPSS DACs. There is an internal capacitor to
VSSA on this pin whether used for ADC input or
VDAC I
CMPSS DAC reference which cannot be disabled. If
this pin is being used as a reference for the CMPSS
12 8 5 DACs, place at least a 1-µF capacitor on this pin.
CMP3_HP3 I CMPSS-3 High Comparator Positive Input 3
CMP3_HN0 I CMPSS-3 High Comparator Negative Input 0
CMP3_LP3 I CMPSS-3 Low Comparator Positive Input 3
CMP3_LN0 I CMPSS-3 Low Comparator Negative Input 0
AIO242 0, 4, 8, 12 I Analog Pin Used For Digital Input 242
HIC_A2 15 I HIC Address 2
A4 I ADC-A Input 4
C14 I ADC-C Input 14
CMP2_HP0 I CMPSS-2 High Comparator Positive Input 0
CMP4_HP3 I CMPSS-4 High Comparator Positive Input 3
CMP4_HN0 I CMPSS-4 High Comparator Negative Input 0
27 23 19
CMP2_LP0 I CMPSS-2 Low Comparator Positive Input 0
CMP4_LP3 I CMPSS-4 Low Comparator Positive Input 3
CMP4_LN0 I CMPSS-4 Low Comparator Negative Input 0
AIO225 0, 4, 8, 12 I Analog Pin Used For Digital Input 225
HIC_NWE 15 I HIC Data Write Enable
A5 I ADC-A Input 5
C2 I ADC-C Input 2
CMP3_HP1 I CMPSS-3 High Comparator Positive Input 1
CMP3_HN1 I CMPSS-3 High Comparator Negative Input 1
17 13 9
CMP3_LP1 I CMPSS-3 Low Comparator Positive Input 1
CMP3_LN1 I CMPSS-3 Low Comparator Negative Input 1
AIO244 0, 4, 8, 12 I Analog Pin Used For Digital Input 244
HIC_A7 15 I HIC Address 7

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Table 6-1. Pin Attributes (continued)

MUX PIN
SIGNAL NAME 80 QFP 64 QFP 48 QFP DESCRIPTION
POSITION TYPE
A6 I Analog Input
CMP1_HP2 I CMPSS-1 High Comparator Positive Input 2
CMP1_LP2 10 6 4 I CMPSS-1 Low Comparator Positive Input 2
AIO228 0, 4, 8, 12 I Analog Pin Used For Digital Input 228
HIC_A0 15 I HIC Address 0
A7 I ADC-A Input 7
C3 I ADC-C Input 3
CMP4_HP1 I CMPSS-4 High Comparator Positive Input 1
CMP4_HN1 I CMPSS-4 High Comparator Negative Input 1
23 19 15
CMP4_LP1 I CMPSS-4 Low Comparator Positive Input 1
CMP4_LN1 I CMPSS-4 Low Comparator Negative Input 1
AIO245 0, 4, 8, 12 I Analog Pin Used For Digital Input 245
HIC_NOE 15 O HIC Output Enable
A8 I ADC-A Input 8
C11 I ADC-C Input 11
CMP2_HP4 I CMPSS-2 High Comparator Positive Input 4
CMP4_HP4 I CMPSS-4 High Comparator Positive Input 4
24 20 16
CMP2_LP4 I CMPSS-2 Low Comparator Positive Input 4
CMP4_LP4 I CMPSS-4 Low Comparator Positive Input 4
AIO241 0, 4, 8, 12 I Analog Pin Used For Digital Input 241
HIC_NBE1 15 I HIC Byte Enable 1
A9 I ADC-A Input 9
C8 I ADC-C Input 8
CMP2_HP2 I CMPSS-2 High Comparator Positive Input 2
CMP4_HP0 I CMPSS-4 High Comparator Positive Input 0
28 24 20
CMP2_LP2 I CMPSS-2 Low Comparator Positive Input 2
CMP4_LP0 I CMPSS-4 Low Comparator Positive Input 0
AIO227 0, 4, 8, 12 I Analog Pin Used For Digital Input 227
HIC_NBE0 15 I HIC Byte Enable 0
C6 I Analog Input
CMP3_HP0 I CMPSS-3 High Comparator Positive Input 0
CMP3_LP0 11 7 4 I CMPSS-3 Low Comparator Positive Input 0
AIO226 0, 4, 8, 12 I Analog Pin Used For Digital Input 226
HIC_A1 15 I HIC Address 1
ADC- High Reference. In external reference mode,
externally drive the high reference voltage onto this
pin. In internal reference mode, a voltage is driven
VREFHI 20 16 12 I onto this pin by the device. In either mode, place at
least a 2.2-µF capacitor on this pin. This capacitor
should be placed as close to the device as possible
between the VREFHI and VREFLO pins.
VREFLO 21 17 13 I ADC- Low Reference

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Table 6-1. Pin Attributes (continued)

MUX PIN
SIGNAL NAME 80 QFP 64 QFP 48 QFP DESCRIPTION
POSITION TYPE
GPIO
GPIO0 0, 4, 8, 12 I/O General-Purpose Input Output 0
EPWM1_A 1 O ePWM-1 Output A
I2CA_SDA 6 I/OD I2C-A Open-Drain Bidirectional Data
SPIA_STE 7 63 52 42 I/O SPI-A Slave Transmit Enable (STE)
FSIRXA_CLK 9 I FSIRX-A Input Clock
CLB_OUTPUTXBAR8 11 O CLB Output X-BAR Output 8
HIC_BASESEL1 15 I HIC Base Address Range Select 1
GPIO1 0, 4, 8, 12 I/O General-Purpose Input Output 1
EPWM1_B 1 O ePWM-1 Output B
I2CA_SCL 6 I/OD I2C-A Open-Drain Bidirectional Clock
SPIA_SOMI 7 I/O SPI-A Slave Out, Master In (SOMI)
CLB_OUTPUTXBAR7 11 62 51 41 O CLB Output X-BAR Output 7
HIC_A2 13 I HIC Address 2
FSITX-A Time Division Multiplexed Additional Data
FSITXA_TDM_D1 14 I
Input
HIC_D10 15 I/O HIC Data 10
GPIO2 0, 4, 8, 12 I/O General-Purpose Input Output 2
EPWM2_A 1 O ePWM-2 Output A
OUTPUTXBAR1 5 O Output X-BAR Output 1
PMBUSA_SDA 6 I/OD PMBus-A Open-Drain Bidirectional Data
SPIA_SIMO 7 I/O SPI-A Slave In, Master Out (SIMO)
SCIA_TX 9 61 50 40 O SCI-A Transmit Data
FSIRXA_D1 10 I FSIRX-A Data Input 1
I2CB_SDA 11 I/OD I2C-B Open-Drain Bidirectional Data
HIC_A1 13 I HIC Address 1
CANA_TX 14 O CAN-A Transmit
HIC_D9 15 I/O HIC Data 9
GPIO3 0, 4, 8, 12 I/O General-Purpose Input Output 3
EPWM2_B 1 O ePWM-2 Output B
OUTPUTXBAR2 2, 5 O Output X-BAR Output 2
PMBUSA_SCL 6 I/OD PMBus-A Open-Drain Bidirectional Clock
SPIA_CLK 7 I/O SPI-A Clock
SCIA_RX 9 60 49 39 I SCI-A Receive Data
FSIRXA_D0 10 I FSIRX-A Data Input 0
I2CB_SCL 11 I/OD I2C-B Open-Drain Bidirectional Clock
HIC_NOE 13 O HIC Output Enable
CANA_RX 14 I CAN-A Receive
HIC_D4 15 I/O HIC Data 4

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Table 6-1. Pin Attributes (continued)

MUX PIN
SIGNAL NAME 80 QFP 64 QFP 48 QFP DESCRIPTION
POSITION TYPE
GPIO4 0, 4, 8, 12 I/O General-Purpose Input Output 4
EPWM3_A 1 O ePWM-3 Output A
OUTPUTXBAR3 5 O Output X-BAR Output 3
CANA_TX 6 O CAN-A Transmit
SPIB_CLK 7 I/O SPI-B Clock
59 48 38
EQEP2_STROBE 9 I/O eQEP-2 Strobe
FSIRXA_CLK 10 I FSIRX-A Input Clock
CLB_OUTPUTXBAR6 11 O CLB Output X-BAR Output 6
HIC_BASESEL2 13 I HIC Base Address Range Select 2
HIC_NWE 15 I HIC Data Write Enable
GPIO5 0, 4, 8, 12 I/O General-Purpose Input Output 5
EPWM3_B 1 O ePWM-3 Output B
OUTPUTXBAR3 3 O Output X-BAR Output 3
CANA_RX 6 I CAN-A Receive
SPIA_STE 7 I/O SPI-A Slave Transmit Enable (STE)
74 61 47
FSITXA_D1 9 O FSITX-A Data Output 1
CLB_OUTPUTXBAR5 10 O CLB Output X-BAR Output 5
HIC_A7 13 I HIC Address 7
HIC_D4 14 I/O HIC Data 4
HIC_D15 15 I/O HIC Data 15
GPIO6 0, 4, 8, 12 I/O General-Purpose Input Output 6
EPWM4_A 1 O ePWM-4 Output A
OUTPUTXBAR4 2 O Output X-BAR Output 4
SYNCOUT 3 O External ePWM Synchronization Pulse
EQEP1_A 5 I eQEP-1 Input A
SPIB_SOMI 7 80 64 48 I/O SPI-B Slave Out, Master In (SOMI)
FSITXA_D0 9 O FSITX-A Data Output 0
FSITXA_D1 11 O FSITX-A Data Output 1
HIC_NBE1 13 I HIC Byte Enable 1
CLB_OUTPUTXBAR8 14 O CLB Output X-BAR Output 8
HIC_D14 15 I/O HIC Data 14
GPIO7 0, 4, 8, 12 I/O General-Purpose Input Output 7
EPWM4_B 1 O ePWM-4 Output B
OUTPUTXBAR5 3 O Output X-BAR Output 5
EQEP1_B 5 I eQEP-1 Input B
SPIB_SIMO 7 68 57 43 I/O SPI-B Slave In, Master Out (SIMO)
FSITXA_CLK 9 O FSITX-A Output Clock
CLB_OUTPUTXBAR2 10 O CLB Output X-BAR Output 2
HIC_A6 13 I HIC Address 6
HIC_D14 15 I/O HIC Data 14

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Table 6-1. Pin Attributes (continued)

MUX PIN
SIGNAL NAME 80 QFP 64 QFP 48 QFP DESCRIPTION
POSITION TYPE
GPIO8 0, 4, 8, 12 I/O General-Purpose Input Output 8
EPWM5_A 1 O ePWM-5 Output A
ADCSOCAO 3 O ADC Start of Conversion A for External ADC
EQEP1_STROBE 5 I/O eQEP-1 Strobe
SCIA_TX 6 O SCI-A Transmit Data
SPIA_SIMO 7 I/O SPI-A Slave In, Master Out (SIMO)
58 47
I2CA_SCL 9 I/OD I2C-A Open-Drain Bidirectional Clock
FSITXA_D1 10 O FSITX-A Data Output 1
CLB_OUTPUTXBAR5 11 O CLB Output X-BAR Output 5
HIC_A0 13 I HIC Address 0
FSITXA_TDM_CLK 14 I FSITX-A Time Division Multiplexed Clock Input
HIC_D8 15 I/O HIC Data 8
GPIO9 0, 4, 8, 12 I/O General-Purpose Input Output 9
EPWM5_B 1 O ePWM-5 Output B
OUTPUTXBAR6 3 O Output X-BAR Output 6
EQEP1_INDEX 5 I/O eQEP-1 Index
SCIA_RX 6 I SCI-A Receive Data
SPIA_CLK 7 75 62 I/O SPI-A Clock
FSITXA_D0 10 O FSITX-A Data Output 0
LINB_RX 11 I LIN-B Receive
HIC_BASESEL0 13 I HIC Base Address Range Select 0
I2CB_SCL 14 I/OD I2C-B Open-Drain Bidirectional Clock
HIC_NRDY 15 O HIC Ready
GPIO10 0, 4, 8, 12 I/O General-Purpose Input Output 10
EPWM6_A 1 O ePWM-6 Output A
ADCSOCBO 3 O ADC Start of Conversion B for External ADC
EQEP1_A 5 I eQEP-1 Input A
SPIA_SOMI 7 I/O SPI-A Slave Out, Master In (SOMI)
76 63
I2CA_SDA 9 I/OD I2C-A Open-Drain Bidirectional Data
FSITXA_CLK 10 O FSITX-A Output Clock
LINB_TX 11 O LIN-B Transmit
HIC_NWE 13 I HIC Data Write Enable
FSITXA_TDM_D0 14 I FSITX-A Time Division Multiplexed Data Input
GPIO11 0, 4, 8, 12 I/O General-Purpose Input Output 11
EPWM6_B 1 O ePWM-6 Output B
OUTPUTXBAR7 3 O Output X-BAR Output 7
EQEP1_B 5 I eQEP-1 Input B
SPIA_STE 7 I/O SPI-A Slave Transmit Enable (STE)
FSIRXA_D1 9 37 31 I FSIRX-A Data Input 1
LINB_RX 10 I LIN-B Receive
EQEP2_A 11 I eQEP-2 Input A
SPIA_SIMO 13 I/O SPI-A Slave In, Master Out (SIMO)
HIC_D6 14 I/O HIC Data 6
HIC_NBE0 15 I HIC Byte Enable 0

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Table 6-1. Pin Attributes (continued)

MUX PIN
SIGNAL NAME 80 QFP 64 QFP 48 QFP DESCRIPTION
POSITION TYPE
GPIO12 0, 4, 8, 12 I/O General-Purpose Input Output 12
EPWM7_A 1 O ePWM-7 Output A
EQEP1_STROBE 5 I/O eQEP-1 Strobe
PMBUSA_CTL 7 I/O PMBus-A Control Signal - Slave Input/Master Output
FSIRXA_D0 9 I FSIRX-A Data Input 0
36 30 24
LINB_TX 10 O LIN-B Transmit
SPIA_CLK 11 I/O SPI-A Clock
CANA_RX 13 I CAN-A Receive
HIC_D13 14 I/O HIC Data 13
HIC_INT 15 O HIC Device Interrupt
GPIO13 0, 4, 8, 12 I/O General-Purpose Input Output 13
EPWM7_B 1 O ePWM-7 Output B
EQEP1_INDEX 5 I/O eQEP-1 Index
PMBUSA_ALERT 7 I/OD PMBus-A Open-Drain Bidirectional Alert
FSIRXA_CLK 9 I FSIRX-A Input Clock
35 29 23
LINB_RX 10 I LIN-B Receive
SPIA_SOMI 11 I/O SPI-A Slave Out, Master In (SOMI)
CANA_TX 13 O CAN-A Transmit
HIC_D11 14 I/O HIC Data 11
HIC_D5 15 I/O HIC Data 5
GPIO14 0, 4, 8, 12 I/O General-Purpose Input Output 14
I2CB_SDA 5 I/OD I2C-B Open-Drain Bidirectional Data
OUTPUTXBAR3 6 O Output X-BAR Output 3
PMBUSA_SDA 7 I/OD PMBus-A Open-Drain Bidirectional Data
SPIB_CLK 9 I/O SPI-B Clock
79
EQEP2_A 10 I eQEP-2 Input A
LINB_TX 11 O LIN-B Transmit
EPWM3_A 13 O ePWM-3 Output A
CLB_OUTPUTXBAR7 14 O CLB Output X-BAR Output 7
HIC_D15 15 I/O HIC Data 15
GPIO15 0, 4, 8, 12 I/O General-Purpose Input Output 15
I2CB_SCL 5 I/OD I2C-B Open-Drain Bidirectional Clock
OUTPUTXBAR4 6 O Output X-BAR Output 4
PMBUSA_SCL 7 I/OD PMBus-A Open-Drain Bidirectional Clock
SPIB_STE 9 I/O SPI-B Slave Transmit Enable (STE)
78
EQEP2_B 10 I eQEP-2 Input B
LINB_RX 11 I LIN-B Receive
EPWM3_B 13 O ePWM-3 Output B
CLB_OUTPUTXBAR6 14 O CLB Output X-BAR Output 6
HIC_D12 15 I/O HIC Data 12

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Table 6-1. Pin Attributes (continued)

MUX PIN
SIGNAL NAME 80 QFP 64 QFP 48 QFP DESCRIPTION
POSITION TYPE
GPIO16 0, 4, 8, 12 I/O General-Purpose Input Output 16
SPIA_SIMO 1 I/O SPI-A Slave In, Master Out (SIMO)
OUTPUTXBAR7 3 O Output X-BAR Output 7
EPWM5_A 5 O ePWM-5 Output A
SCIA_TX 6 O SCI-A Transmit Data
EQEP1_STROBE 9 I/O eQEP-1 Strobe
PMBUSA_SCL 10 39 33 26 I/OD PMBus-A Open-Drain Bidirectional Clock
External Clock Output. This pin outputs a divided-
XCLKOUT 11 O down version of a chosen clock signal from within the
device.
EQEP2_B 13 I eQEP-2 Input B
SPIB_SOMI 14 I/O SPI-B Slave Out, Master In (SOMI)
HIC_D1 15 I/O HIC Data 1
GPIO17 0, 4, 8, 12 I/O General-Purpose Input Output 17
SPIA_SOMI 1 I/O SPI-A Slave Out, Master In (SOMI)
OUTPUTXBAR8 3 O Output X-BAR Output 8
EPWM5_B 5 O ePWM-5 Output B
SCIA_RX 6 40 34 I SCI-A Receive Data
EQEP1_INDEX 9 I/O eQEP-1 Index
PMBUSA_SDA 10 I/OD PMBus-A Open-Drain Bidirectional Data
CANA_TX 11 O CAN-A Transmit
HIC_D2 15 I/O HIC Data 2
GPIO18_X2 0, 4, 8, 12 I/O General-Purpose Input Output 18_X2
SPIA_CLK 1 I/O SPI-A Clock
CANA_RX 3 I CAN-A Receive
EPWM6_A 5 O ePWM-6 Output A
I2CA_SCL 6 I/OD I2C-A Open-Drain Bidirectional Clock
EQEP2_A 9 I eQEP-2 Input A
PMBUSA_CTL 10 I/O PMBus-A Control Signal - Slave Input/Master Output
External Clock Output. This pin outputs a divided-
XCLKOUT 11 50 41 33 O down version of a chosen clock signal from within the
device.
LINB_TX 13 O LIN-B Transmit
FSITXA_TDM_CLK 14 I FSITX-A Time Division Multiplexed Clock Input
HIC_INT 15 O HIC Device Interrupt
Crystal oscillator output. For more information about
the ALT functionality, see the table that is in the
X2 ALT O External Oscillator (XTAL) section of the System
Control chapter in the TMS320F28002x Real-Time
Microcontrollers Technical Reference Manual.

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Table 6-1. Pin Attributes (continued)

MUX PIN
SIGNAL NAME 80 QFP 64 QFP 48 QFP DESCRIPTION
POSITION TYPE
GPIO19_X1 0, 4, 8, 12 I/O General-Purpose Input Output 19_X1
SPIA_STE 1 I/O SPI-A Slave Transmit Enable (STE)
CANA_TX 3 O CAN-A Transmit
EPWM6_B 5 O ePWM-6 Output B
I2CA_SDA 6 I/OD I2C-A Open-Drain Bidirectional Data
EQEP2_B 9 I eQEP-2 Input B
PMBUSA_ALERT 10 I/OD PMBus-A Open-Drain Bidirectional Alert
CLB_OUTPUTXBAR1 11 O CLB Output X-BAR Output 1
LINB_RX 13 I LIN-B Receive
51 42 34
FSITXA_TDM_D0 14 I FSITX-A Time Division Multiplexed Data Input
HIC_NBE0 15 I HIC Byte Enable 0
Crystal oscillator input or single-ended clock input.
The device initialization software must configure this
pin before the crystal oscillator is enabled. To use this
oscillator, a quartz crystal circuit must be connected
to X1 and X2. This pin can also be used to feed a
X1 ALT I
single-ended 3.3-V level clock. For more information
about the ALT functionality, see the table that is in the
External Oscillator (XTAL) section of the System
Control chapter in the TMS320F28002x Real-Time
Microcontrollers Technical Reference Manual.
GPIO22 0, 4, 8, 12 I/O General-Purpose Input Output 22
EQEP1_STROBE 1 I/O eQEP-1 Strobe
SPIB_CLK 6 I/O SPI-B Clock
LINA_TX 9 O LIN-A Transmit
CLB_OUTPUTXBAR1 10 67 56 O CLB Output X-BAR Output 1
LINB_TX 11 O LIN-B Transmit
HIC_A5 13 I HIC Address 5
EPWM4_A 14 O ePWM-4 Output A
HIC_D13 15 I/O HIC Data 13
GPIO23 0, 4, 8, 12 I/O General-Purpose Input Output 23
EQEP1_INDEX 1 I/O eQEP-1 Index
SPIB_STE 6 I/O SPI-B Slave Transmit Enable (STE)
LINA_RX 9 I LIN-A Receive
65 54
LINB_RX 11 I LIN-B Receive
HIC_A3 13 I HIC Address 3
EPWM4_B 14 O ePWM-4 Output B
HIC_D11 15 I/O HIC Data 11
GPIO24 0, 4, 8, 12 I/O General-Purpose Input Output 24
OUTPUTXBAR1 1 O Output X-BAR Output 1
EQEP2_A 2 I eQEP-2 Input A
SPIB_SIMO 6 I/O SPI-B Slave In, Master Out (SIMO)
LINB_TX 9 O LIN-B Transmit
41 35 27
PMBUSA_SCL 10 I/OD PMBus-A Open-Drain Bidirectional Clock
SCIA_TX 11 O SCI-A Transmit Data
Error Status Output. When used, this signal requires
ERRORSTS 13 O
an external pulldown.
HIC_D3 15 I/O HIC Data 3

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Table 6-1. Pin Attributes (continued)

MUX PIN
SIGNAL NAME 80 QFP 64 QFP 48 QFP DESCRIPTION
POSITION TYPE
GPIO25 0, 4, 8, 12 I/O General-Purpose Input Output 25
OUTPUTXBAR2 1 O Output X-BAR Output 2
EQEP2_B 2 I eQEP-2 Input B
EQEP1_A 5 I eQEP-1 Input A
SPIB_SOMI 6 42 I/O SPI-B Slave Out, Master In (SOMI)
FSITXA_D1 9 O FSITX-A Data Output 1
PMBUSA_SDA 10 I/OD PMBus-A Open-Drain Bidirectional Data
SCIA_RX 11 I SCI-A Receive Data
HIC_BASESEL0 14 I HIC Base Address Range Select 0
GPIO26 0, 4, 8, 12 I/O General-Purpose Input Output 26
OUTPUTXBAR3 1, 5 O Output X-BAR Output 3
EQEP2_INDEX 2 I/O eQEP-2 Index
SPIB_CLK 6 I/O SPI-B Clock
FSITXA_D0 9 43 O FSITX-A Data Output 0
PMBUSA_CTL 10 I/O PMBus-A Control Signal - Slave Input/Master Output
I2CA_SDA 11 I/OD I2C-A Open-Drain Bidirectional Data
HIC_D0 14 I/O HIC Data 0
HIC_A1 15 I HIC Address 1
GPIO27 0, 4, 8, 12 I/O General-Purpose Input Output 27
OUTPUTXBAR4 1, 5 O Output X-BAR Output 4
EQEP2_STROBE 2 I/O eQEP-2 Strobe
SPIB_STE 6 I/O SPI-B Slave Transmit Enable (STE)
FSITXA_CLK 9 44 O FSITX-A Output Clock
PMBUSA_ALERT 10 I/OD PMBus-A Open-Drain Bidirectional Alert
I2CA_SCL 11 I/OD I2C-A Open-Drain Bidirectional Clock
HIC_D1 14 I/O HIC Data 1
HIC_A4 15 I HIC Address 4
GPIO28 0, 4, 8, 12 I/O General-Purpose Input Output 28
SCIA_RX 1 I SCI-A Receive Data
EPWM7_A 3 O ePWM-7 Output A
OUTPUTXBAR5 5 O Output X-BAR Output 5
EQEP1_A 6 I eQEP-1 Input A
EQEP2_STROBE 9 I/O eQEP-2 Strobe
4 2 2
LINA_TX 10 O LIN-A Transmit
SPIB_CLK 11 I/O SPI-B Clock
Error Status Output. When used, this signal requires
ERRORSTS 13 O
an external pulldown.
I2CB_SDA 14 I/OD I2C-B Open-Drain Bidirectional Data
HIC_NOE 15 O HIC Output Enable

Copyright © 2020 Texas Instruments Incorporated Submit Document Feedback 23

Table 6-1. Pin Attributes (continued)

MUX PIN
SIGNAL NAME 80 QFP 64 QFP 48 QFP DESCRIPTION
POSITION TYPE
GPIO29 0, 4, 8, 12 I/O General-Purpose Input Output 29
SCIA_TX 1 O SCI-A Transmit Data
EPWM7_B 3 O ePWM-7 Output B
OUTPUTXBAR6 5 O Output X-BAR Output 6
EQEP1_B 6 I eQEP-1 Input B
EQEP2_INDEX 9 I/O eQEP-2 Index
3 1 1
LINA_RX 10 I LIN-A Receive
SPIB_STE 11 I/O SPI-B Slave Transmit Enable (STE)
Error Status Output. When used, this signal requires
ERRORSTS 13 O
an external pulldown.
I2CB_SCL 14 I/OD I2C-B Open-Drain Bidirectional Clock
HIC_NCS 15 I HIC Chip Select
GPIO30 0, 4, 8, 12 I/O General-Purpose Input Output 30
CANA_RX 1 I CAN-A Receive
SPIB_SIMO 3 I/O SPI-B Slave In, Master Out (SIMO)
OUTPUTXBAR7 5 O Output X-BAR Output 7
1
EQEP1_STROBE 6 I/O eQEP-1 Strobe
FSIRXA_CLK 9 I FSIRX-A Input Clock
EPWM1_A 11 O ePWM-1 Output A
HIC_D8 14 I/O HIC Data 8
GPIO31 0, 4, 8, 12 I/O General-Purpose Input Output 31
CANA_TX 1 O CAN-A Transmit
SPIB_SOMI 3 I/O SPI-B Slave Out, Master In (SOMI)
OUTPUTXBAR8 5 O Output X-BAR Output 8
2
EQEP1_INDEX 6 I/O eQEP-1 Index
FSIRXA_D1 9 I FSIRX-A Data Input 1
EPWM1_B 11 O ePWM-1 Output B
HIC_D10 14 I/O HIC Data 10
GPIO32 0, 4, 8, 12 I/O General-Purpose Input Output 32
I2CA_SDA 1 I/OD I2C-A Open-Drain Bidirectional Data
SPIB_CLK 3 I/O SPI-B Clock
LINA_TX 6 O LIN-A Transmit
49 40 32
FSIRXA_D0 9 I FSIRX-A Data Input 0
CANA_TX 10 O CAN-A Transmit
ADCSOCBO 13 O ADC Start of Conversion B for External ADC
HIC_INT 15 O HIC Device Interrupt
GPIO33 0, 4, 8, 12 I/O General-Purpose Input Output 33
I2CA_SCL 1 I/OD I2C-A Open-Drain Bidirectional Clock
SPIB_STE 3 I/O SPI-B Slave Transmit Enable (STE)
OUTPUTXBAR4 5 O Output X-BAR Output 4
LINA_RX 6 I LIN-A Receive
38 32 25
FSIRXA_CLK 9 I FSIRX-A Input Clock
CANA_RX 10 I CAN-A Receive
EQEP2_B 11 I eQEP-2 Input B
ADCSOCAO 13 O ADC Start of Conversion A for External ADC
HIC_D0 15 I/O HIC Data 0

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Table 6-1. Pin Attributes (continued)

MUX PIN
SIGNAL NAME 80 QFP 64 QFP 48 QFP DESCRIPTION
POSITION TYPE
GPIO34 0, 4, 8, 12 I/O General-Purpose Input Output 34
OUTPUTXBAR1 1 O Output X-BAR Output 1
PMBUSA_SDA 6 I/OD PMBus-A Open-Drain Bidirectional Data
77
HIC_NBE1 13 I HIC Byte Enable 1
I2CB_SDA 14 I/OD I2C-B Open-Drain Bidirectional Data
HIC_D9 15 I/O HIC Data 9
GPIO35 0, 4, 8, 12 I/O General-Purpose Input Output 35
SCIA_RX 1 I SCI-A Receive Data
I2CA_SDA 3 I/OD I2C-A Open-Drain Bidirectional Data
CANA_RX 5 I CAN-A Receive
PMBUSA_SCL 6 I/OD PMBus-A Open-Drain Bidirectional Clock
LINA_RX 7 I LIN-A Receive
EQEP1_A 9 48 39 31 I eQEP-1 Input A
PMBUSA_CTL 10 I/O PMBus-A Control Signal - Slave Input/Master Output
HIC_NWE 14 I HIC Data Write Enable
JTAG Test Data Input (TDI) - TDI is the default mux
selection for the pin. The internal pullup is disabled by
TDI 15 I default. The internal pullup should be enabled or an
external pullup added on the board if this pin is used
as JTAG TDI to avoid a floating input.
GPIO37 0, 4, 8, 12 I/O General-Purpose Input Output 37
OUTPUTXBAR2 1 O Output X-BAR Output 2
I2CA_SCL 3 I/OD I2C-A Open-Drain Bidirectional Clock
SCIA_TX 5 O SCI-A Transmit Data
CANA_TX 6 O CAN-A Transmit
LINA_TX 7 O LIN-A Transmit
EQEP1_B 9 I eQEP-1 Input B
46 37 29
PMBUSA_ALERT 10 I/OD PMBus-A Open-Drain Bidirectional Alert
HIC_NRDY 14 O HIC Ready
JTAG Test Data Output (TDO) - TDO is the default
mux selection for the pin. The internal pullup is
disabled by default. The TDO function will tristate
TDO 15 O when there is no JTAG activity, leaving this pin
floating; the internal pullup should be enabled or an
external pullup added on the board to avoid a floating
GPIO input.
GPIO39 0, 4, 8, 12 I/O General-Purpose Input Output 39
FSIRXA_CLK 7 I FSIRX-A Input Clock
EQEP2_INDEX 9 I/O eQEP-2 Index
CLB_OUTPUTXBAR2 11 56 46 O CLB Output X-BAR Output 2
SYNCOUT 13 O External ePWM Synchronization Pulse
EQEP1_INDEX 14 I/O eQEP-1 Index
HIC_D7 15 I/O HIC Data 7

Copyright © 2020 Texas Instruments Incorporated Submit Document Feedback 25

Table 6-1. Pin Attributes (continued)

MUX PIN
SIGNAL NAME 80 QFP 64 QFP 48 QFP DESCRIPTION
POSITION TYPE
GPIO40 0, 4, 8, 12 I/O General-Purpose Input Output 40
SPIB_SIMO 1 I/O SPI-B Slave In, Master Out (SIMO)
EPWM2_B 5 O ePWM-2 Output B
PMBUSA_SDA 6 I/OD PMBus-A Open-Drain Bidirectional Data
FSIRXA_D0 7 64 53 I FSIRX-A Data Input 0
EQEP1_A 10 I eQEP-1 Input A
LINB_TX 11 O LIN-B Transmit
HIC_NBE1 14 I HIC Byte Enable 1
HIC_D5 15 I/O HIC Data 5
GPIO41 0, 4, 8, 12 I/O General-Purpose Input Output 41
EPWM2_A 5 O ePWM-2 Output A
PMBUSA_SCL 6 I/OD PMBus-A Open-Drain Bidirectional Clock
FSIRXA_D1 7 I FSIRX-A Data Input 1
EQEP1_B 10 66 55 I eQEP-1 Input B
LINB_RX 11 I LIN-B Receive
HIC_A4 13 I HIC Address 4
SPIB_SOMI 14 I/O SPI-B Slave Out, Master In (SOMI)
HIC_D12 15 I/O HIC Data 12
GPIO42 0, 4, 8, 12 I/O General-Purpose Input Output 42
LINA_RX 2 I LIN-A Receive
OUTPUTXBAR5 3 O Output X-BAR Output 5
PMBUSA_CTL 5 I/O PMBus-A Control Signal - Slave Input/Master Output
I2CA_SDA 6 57 I/OD I2C-A Open-Drain Bidirectional Data
EQEP1_STROBE 10 I/O eQEP-1 Strobe
CLB_OUTPUTXBAR3 11 O CLB Output X-BAR Output 3
HIC_D2 14 I/O HIC Data 2
HIC_A6 15 I HIC Address 6
GPIO43 0, 4, 8, 12 I/O General-Purpose Input Output 43
OUTPUTXBAR6 3 O Output X-BAR Output 6
PMBUSA_ALERT 5 I/OD PMBus-A Open-Drain Bidirectional Alert
I2CA_SCL 6 I/OD I2C-A Open-Drain Bidirectional Clock
54
EQEP1_INDEX 10 I/O eQEP-1 Index
CLB_OUTPUTXBAR4 11 O CLB Output X-BAR Output 4
HIC_D3 14 I/O HIC Data 3
HIC_A7 15 I HIC Address 7
GPIO44 0, 4, 8, 12 I/O General-Purpose Input Output 44
OUTPUTXBAR7 3 O Output X-BAR Output 7
EQEP1_A 5 I eQEP-1 Input A
FSITXA_CLK 7 69 O FSITX-A Output Clock
CLB_OUTPUTXBAR3 10 O CLB Output X-BAR Output 3
HIC_D7 13 I/O HIC Data 7
HIC_D5 15 I/O HIC Data 5

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Table 6-1. Pin Attributes (continued)

MUX PIN
SIGNAL NAME 80 QFP 64 QFP 48 QFP DESCRIPTION
POSITION TYPE
GPIO45 0, 4, 8, 12 I/O General-Purpose Input Output 45
OUTPUTXBAR8 3 O Output X-BAR Output 8
FSITXA_D0 7 73 O FSITX-A Data Output 0
CLB_OUTPUTXBAR4 10 O CLB Output X-BAR Output 4
HIC_D6 15 I/O HIC Data 6
GPIO46 0, 4, 8, 12 I/O General-Purpose Input Output 46
LINA_TX 3 O LIN-A Transmit
6
FSITXA_D1 7 O FSITX-A Data Output 1
HIC_NWE 15 I HIC Data Write Enable
GPIO61 0, 4, 8, 12 I/O General-Purpose Input Output 61
GPIO62 0, 4, 8, 12 I/O General-Purpose Input Output 62
GPIO63 0, 4, 8, 12 I/O General-Purpose Input Output 63
TEST, JTAG, AND RESET
Flash test pin 1. Reserved for TI. Must be left
FLT1 34 I/O
unconnected.
Flash test pin 2. Reserved for TI. Must be left
FLT2 33 I/O
unconnected.
TCK 45 36 28 I JTAG test clock with internal pullup.
JTAG test-mode select (TMS) with internal pullup.
This serial control input is clocked into the TAP
controller on the rising edge of TCK. This device does
TMS 47 38 30 I/O not have a TRSTn pin. An external pullup resistor
(recommended 2.2 kΩ) on the TMS pin to VDDIO
should be placed on the board to keep JTAG in reset
during normal operation.
Device Reset (in) and Watchdog Reset (out). During a
power-on condition, this pin is driven low by the
device. An external circuit may also drive this pin to
assert a device reset. This pin is also driven low by
the MCU when a watchdog reset occurs. During
watchdog reset, the XRSn pin is driven low for the
watchdog reset duration of 512 OSCCLK cycles. A
resistor between 2.2 kΩ and 10 kΩ should be placed
XRSn 5 3 3 I/OD
between XRSn and VDDIO. If a capacitor is placed
between XRSn and VSS for noise filtering, it should
be 100 nF or smaller. These values will allow the
watchdog to properly drive the XRSn pin to VOL
within 512 OSCCLK cycles when the watchdog reset
is asserted. This pin is an open-drain output with an
internal pullup. If this pin is driven by an external
device, it should be done using an open-drain device.

Copyright © 2020 Texas Instruments Incorporated Submit Document Feedback 27

Table 6-1. Pin Attributes (continued)

MUX PIN
SIGNAL NAME 80 QFP 64 QFP 48 QFP DESCRIPTION
POSITION TYPE
POWER AND GROUND
1.2-V Digital Logic Power Pins. TI recommends
placing a decoupling capacitor near each VDD pin
8, 31, 4, 27,
VDD 36, 45 with a minimum total capacitance of approximately 10
53, 71 44, 59
µF. It is also recommended that all VDD pins be
externally connected to each other.
3.3-V Analog Power Pins. Place a minimum 2.2-µF
VDDA 26 22 18
decoupling capacitor on each pin.
3.3-V Digital I/O Power Pins. Place a minimum 0.1-µF
decoupling capacitor on each pin. It is recommended
7, 32, 28, 43,
VDDIO 35, 46 to place an additional bulk cap of around 20uF shared
52, 72 60
by all the pins. However, the exact value of this bulk
cap will depend on the regulator being used.
9, 30, 5, 26, 22, 37,
VSS Digital Ground
55, 70 45, 58 44
VSSA 25 21 17 Analog Ground

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6.3 Signal Descriptions

6.3.1 Analog Signals
Table 6-2. Analog Signals
PIN
SIGNAL NAME DESCRIPTION GPIO 80 QFP 64 QFP 48 QFP
TYPE
A0 I ADC-A Input 0 19 15 11
A1 I Analog Input 18 14 10
A2 I ADC-A Input 2 13 9 6
A3 I ADC-A Input 3 12 8 5
A4 I ADC-A Input 4 27 23 19
A5 I ADC-A Input 5 17 13 9
A6 I Analog Input 10 6 4
A7 I ADC-A Input 7 23 19 15
A8 I ADC-A Input 8 24 20 16
A9 I ADC-A Input 9 28 24 20
A10 I ADC-A Input 10 29 25 21
A11 I ADC-A Input 11 16 12 8
A12 I ADC-A Input 12 22 18 14
A14 I ADC-A Input 14 15 11
A15 I ADC-A Input 15 14 10 7
AIO224 I Analog Pin Used For Digital Input 224 13 9 6
AIO225 I Analog Pin Used For Digital Input 225 27 23 19
AIO226 I Analog Pin Used For Digital Input 226 11 7 4
AIO227 I Analog Pin Used For Digital Input 227 28 24 20
AIO228 I Analog Pin Used For Digital Input 228 10 6 4
AIO230 I Analog Pin Used For Digital Input 230 29 25 21
AIO231 I Analog Pin Used For Digital Input 231 19 15 11
AIO232 I Analog Pin Used For Digital Input 232 18 14 10
AIO233 I Analog Pin Used For Digital Input 233 14 10 7
AIO237 I Analog Pin Used For Digital Input 237 16 12 8
AIO238 I Analog Pin Used For Digital Input 238 22 18 14
AIO239 I Analog Pin Used For Digital Input 239 15 11
AIO241 I Analog Pin Used For Digital Input 241 24 20 16
AIO242 I Analog Pin Used For Digital Input 242 12 8 5
AIO244 I Analog Pin Used For Digital Input 244 17 13 9
AIO245 I Analog Pin Used For Digital Input 245 23 19 15
C0 I ADC-C Input 0 16 12 8
C1 I ADC-C Input 1 22 18 14
C2 I ADC-C Input 2 17 13 9
C3 I ADC-C Input 3 23 19 15
C4 I ADC-C Input 4 15 11
C5 I ADC-C Input 5 12 8 5
C6 I Analog Input 11 7 4
C7 I ADC-C Input 7 14 10 7
C8 I ADC-C Input 8 28 24 20
C9 I ADC-C Input 9 13 9 6
C10 I ADC-C Input 10 29 25 21

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Table 6-2. Analog Signals (continued)

PIN
SIGNAL NAME DESCRIPTION GPIO 80 QFP 64 QFP 48 QFP
TYPE
C11 I ADC-C Input 11 24 20 16
C14 I ADC-C Input 14 27 23 19
C15 I ADC-C Input 15 19 15 11
CMPSS-1 High Comparator Negative
CMP1_HN0 I 14 10 7
Input 0
CMPSS-1 High Comparator Negative
CMP1_HN1 I 16 12 8
Input 1
CMPSS-1 High Comparator Positive
CMP1_HP0 I 13 9 6
Input 0
CMPSS-1 High Comparator Positive
CMP1_HP1 I 16 12 8
Input 1
CMPSS-1 High Comparator Positive
CMP1_HP2 I 10 6 4
Input 2
CMPSS-1 High Comparator Positive
CMP1_HP3 I 14 10 7
Input 3
CMPSS-1 High Comparator Positive
CMP1_HP4 I 18 14 10
Input 4
CMPSS-1 Low Comparator Negative
CMP1_LN0 I 14 10 7
Input 0
CMPSS-1 Low Comparator Negative
CMP1_LN1 I 16 12 8
Input 1
CMPSS-1 Low Comparator Positive
CMP1_LP0 I 13 9 6
Input 0
CMPSS-1 Low Comparator Positive
CMP1_LP1 I 16 12 8
Input 1
CMPSS-1 Low Comparator Positive
CMP1_LP2 I 10 6 4
Input 2
CMPSS-1 Low Comparator Positive
CMP1_LP3 I 14 10 7
Input 3
CMPSS-1 Low Comparator Positive
CMP1_LP4 I 18 14 10
Input 4
CMPSS-2 High Comparator Negative
CMP2_HN0 I 29 25 21
Input 0
CMPSS-2 High Comparator Negative
CMP2_HN1 I 22 18 14
Input 1
CMPSS-2 High Comparator Positive
CMP2_HP0 I 27 23 19
Input 0
CMPSS-2 High Comparator Positive
CMP2_HP1 I 22 18 14
Input 1
CMPSS-2 High Comparator Positive
CMP2_HP2 I 28 24 20
Input 2
CMPSS-2 High Comparator Positive
CMP2_HP3 I 29 25 21
Input 3
CMPSS-2 High Comparator Positive
CMP2_HP4 I 24 20 16
Input 4
CMPSS-2 Low Comparator Negative
CMP2_LN0 I 29 25 21
Input 0
CMPSS-2 Low Comparator Negative
CMP2_LN1 I 22 18 14
Input 1
CMPSS-2 Low Comparator Positive
CMP2_LP0 I 27 23 19
Input 0

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Table 6-2. Analog Signals (continued)

PIN
SIGNAL NAME DESCRIPTION GPIO 80 QFP 64 QFP 48 QFP
TYPE
CMPSS-2 Low Comparator Positive
CMP2_LP1 I 22 18 14
Input 1
CMPSS-2 Low Comparator Positive
CMP2_LP2 I 28 24 20
Input 2
CMPSS-2 Low Comparator Positive
CMP2_LP3 I 29 25 21
Input 3
CMPSS-2 Low Comparator Positive
CMP2_LP4 I 24 20 16
Input 4
CMPSS-3 High Comparator Negative
CMP3_HN0 I 12 8 5
Input 0
CMPSS-3 High Comparator Negative
CMP3_HN1 I 17 13 9
Input 1
CMPSS-3 High Comparator Positive
CMP3_HP0 I 11 7 4
Input 0
CMPSS-3 High Comparator Positive
CMP3_HP1 I 17 13 9
Input 1
CMPSS-3 High Comparator Positive
CMP3_HP2 I 19 15 11
Input 2
CMPSS-3 High Comparator Positive
CMP3_HP3 I 12 8 5
Input 3
CMPSS-3 High Comparator Positive
CMP3_HP4 I 15 11
Input 4
CMPSS-3 Low Comparator Negative
CMP3_LN0 I 12 8 5
Input 0
CMPSS-3 Low Comparator Negative
CMP3_LN1 I 17 13 9
Input 1
CMPSS-3 Low Comparator Positive
CMP3_LP0 I 11 7 4
Input 0
CMPSS-3 Low Comparator Positive
CMP3_LP1 I 17 13 9
Input 1
CMPSS-3 Low Comparator Positive
CMP3_LP2 I 19 15 11
Input 2
CMPSS-3 Low Comparator Positive
CMP3_LP3 I 12 8 5
Input 3
CMPSS-3 Low Comparator Positive
CMP3_LP4 I 15 11
Input 4
CMPSS-4 High Comparator Negative
CMP4_HN0 I 27 23 19
Input 0
CMPSS-4 High Comparator Negative
CMP4_HN1 I 23 19 15
Input 1
CMPSS-4 High Comparator Positive
CMP4_HP0 I 28 24 20
Input 0
CMPSS-4 High Comparator Positive
CMP4_HP1 I 23 19 15
Input 1
CMPSS-4 High Comparator Positive
CMP4_HP2 I 22 18 14
Input 2
CMPSS-4 High Comparator Positive
CMP4_HP3 I 27 23 19
Input 3
CMPSS-4 High Comparator Positive
CMP4_HP4 I 24 20 16
Input 4
CMPSS-4 Low Comparator Negative
CMP4_LN0 I 27 23 19
Input 0

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Table 6-2. Analog Signals (continued)

PIN
SIGNAL NAME DESCRIPTION GPIO 80 QFP 64 QFP 48 QFP
TYPE
CMPSS-4 Low Comparator Negative
CMP4_LN1 I 23 19 15
Input 1
CMPSS-4 Low Comparator Positive
CMP4_LP0 I 28 24 20
Input 0
CMPSS-4 Low Comparator Positive
CMP4_LP1 I 23 19 15
Input 1
CMPSS-4 Low Comparator Positive
CMP4_LP2 I 22 18 14
Input 2
CMPSS-4 Low Comparator Positive
CMP4_LP3 I 27 23 19
Input 3
CMPSS-4 Low Comparator Positive
CMP4_LP4 I 24 20 16
Input 4
HIC_A0 I HIC Address 0 10 6 4
HIC_A1 I HIC Address 1 11 7 4
HIC_A2 I HIC Address 2 12 8 5
HIC_A3 I HIC Address 3 13 9 6
HIC_A4 I HIC Address 4 14 10 7
HIC_A5 I HIC Address 5 15 11
HIC_A6 I HIC Address 6 16 12 8
HIC_A7 I HIC Address 7 17 13 9
HIC_BASESEL0 I HIC Base Address Range Select 0 18 14 10
HIC_BASESEL1 I HIC Base Address Range Select 1 19 15 11
HIC_BASESEL2 I HIC Base Address Range Select 2 29 25 21
HIC_NBE0 I HIC Byte Enable 0 28 24 20
HIC_NBE1 I HIC Byte Enable 1 24 20 16
HIC_NCS I HIC Chip Select 22 18 14
HIC_NOE O HIC Output Enable 23 19 15
HIC_NWE I HIC Data Write Enable 27 23 19
Optional external reference voltage
for on-chip CMPSS DACs. There is
an internal capacitor to VSSA on this
pin whether used for ADC input or
VDAC I CMPSS DAC reference which cannot 12 8 5
be disabled. If this pin is being used
as a reference for the CMPSS DACs,
place at least a 1-μF capacitor on this
pin.
ADC- High Reference. In external
reference mode, externally drive the
high reference voltage onto this pin.
In internal reference mode, a voltage
is driven onto this pin by the device.
VREFHI I 20 16 12
In either mode, place at least a 2.2-
µF capacitor on this pin. This
capacitor should be placed as close
to the device as possible between the
VREFHI and VREFLO pins.
VREFLO I ADC- Low Reference 21 17 13

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6.3.2 Digital Signals

Table 6-3. Digital Signals
PIN
SIGNAL NAME DESCRIPTION GPIO 80 QFP 64 QFP 48 QFP
TYPE
ADC Start of Conversion A for
ADCSOCAO O 33, 8 38, 58 32, 47 25
External ADC
ADC Start of Conversion B for
ADCSOCBO O 10, 32 49, 76 40, 63 32
External ADC
12, 18, 3, 30, 1, 36, 38, 48, 30, 32, 39, 24, 25, 31,
CANA_RX I CAN-A Receive
33, 35, 5 50, 60, 74 41, 49, 61 33, 39, 47
13, 17, 19, 2, 2, 35, 40, 46, 29, 34, 37, 23, 29, 32,
CANA_TX O CAN-A Transmit
31, 32, 37, 4 49, 51, 59, 61 40, 42, 48, 50 34, 38, 40
CLB_OUTPUTXBAR1 O CLB Output X-BAR Output 1 19, 22 51, 67 42, 56 34
CLB_OUTPUTXBAR2 O CLB Output X-BAR Output 2 39, 7 56, 68 46, 57 43
CLB_OUTPUTXBAR3 O CLB Output X-BAR Output 3 42, 44 57, 69
CLB_OUTPUTXBAR4 O CLB Output X-BAR Output 4 43, 45 54, 73
CLB_OUTPUTXBAR5 O CLB Output X-BAR Output 5 5, 8 58, 74 47, 61 47
CLB_OUTPUTXBAR6 O CLB Output X-BAR Output 6 15, 4 59, 78 48 38
CLB_OUTPUTXBAR7 O CLB Output X-BAR Output 7 1, 14 62, 79 51 41
CLB_OUTPUTXBAR8 O CLB Output X-BAR Output 8 6 63, 80 52, 64 42, 48
EPWM1_A O ePWM-1 Output A 30 1, 63 52 42
EPWM1_B O ePWM-1 Output B 1, 31 2, 62 51 41
EPWM2_A O ePWM-2 Output A 2, 41 61, 66 50, 55 40
EPWM2_B O ePWM-2 Output B 3, 40 60, 64 49, 53 39
EPWM3_A O ePWM-3 Output A 14, 4 59, 79 48 38
EPWM3_B O ePWM-3 Output B 15, 5 74, 78 61 47
EPWM4_A O ePWM-4 Output A 22, 6 67, 80 56, 64 48
EPWM4_B O ePWM-4 Output B 23, 7 65, 68 54, 57 43
EPWM5_A O ePWM-5 Output A 16, 8 39, 58 33, 47 26
EPWM5_B O ePWM-5 Output B 17, 9 40, 75 34, 62
EPWM6_A O ePWM-6 Output A 10, 18 50, 76 41, 63 33
EPWM6_B O ePWM-6 Output B 11, 19 37, 51 31, 42 34
EPWM7_A O ePWM-7 Output A 12, 28 36, 4 2, 30 2, 24
EPWM7_B O ePWM-7 Output B 13, 29 3, 35 1, 29 1, 23
10, 25, 28, 4, 42, 48, 64, 2, 39, 53, 63,
EQEP1_A I eQEP-1 Input A 2, 31, 48
35, 40, 44, 6 69, 76, 80 64
11, 29, 37, 41, 3, 37, 46, 66, 1, 31, 37, 55,
EQEP1_B I eQEP-1 Input B 1, 29, 43
7 68 57
13, 17, 23, 2, 35, 40, 54, 29, 34, 46,
EQEP1_INDEX I/O eQEP-1 Index 23
31, 39, 43, 9 56, 65, 75 54, 62
12, 16, 22, 1, 36, 39, 57,
EQEP1_STROBE I/O eQEP-1 Strobe 30, 33, 47, 56 24, 26
30, 42, 8 58, 67
EQEP2_A I eQEP-2 Input A 11, 14, 18, 24 37, 41, 50, 79 31, 35, 41 27, 33
15, 16, 19, 38, 39, 42,
EQEP2_B I eQEP-2 Input B 32, 33, 42 25, 26, 34
25, 33 51, 78
EQEP2_INDEX I/O eQEP-2 Index 26, 29, 39 3, 43, 56 1, 46 1
EQEP2_STROBE I/O eQEP-2 Strobe 27, 28, 4 4, 44, 59 2, 48 2, 38
Error Status Output. When used, this
ERRORSTS O 24, 28, 29 3, 4, 41 1, 2, 35 1, 2, 27
signal requires an external pulldown.
13, 30, 33, 1, 35, 38, 56, 29, 32, 46,
FSIRXA_CLK I FSIRX-A Input Clock 23, 25, 38, 42
39, 4 59, 63 48, 52

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Table 6-3. Digital Signals (continued)

PIN
SIGNAL NAME DESCRIPTION GPIO 80 QFP 64 QFP 48 QFP
TYPE
FSIRXA_D0 I FSIRX-A Data Input 0 12, 3, 32, 40 36, 49, 60, 64 30, 40, 49, 53 24, 32, 39
FSIRXA_D1 I FSIRX-A Data Input 1 11, 2, 31, 41 2, 37, 61, 66 31, 50, 55 40
FSITXA_CLK O FSITX-A Output Clock 10, 27, 44, 7 44, 68, 69, 76 57, 63 43
FSITXA_D0 O FSITX-A Data Output 0 26, 45, 6, 9 43, 73, 75, 80 62, 64 48
42, 58, 6, 74,
FSITXA_D1 O FSITX-A Data Output 1 25, 46, 5, 6, 8 47, 61, 64 47, 48
80
FSITX-A Time Division Multiplexed
FSITXA_TDM_CLK I 18, 8 50, 58 41, 47 33
Clock Input
FSITX-A Time Division Multiplexed
FSITXA_TDM_D0 I 10, 19 51, 76 42, 63 34
Data Input
FSITX-A Time Division Multiplexed
FSITXA_TDM_D1 I 1 62 51 41
Additional Data Input
GPIO0 I/O General-Purpose Input Output 0 63 52 42
GPIO1 I/O General-Purpose Input Output 1 1 62 51 41
GPIO2 I/O General-Purpose Input Output 2 2 61 50 40
GPIO3 I/O General-Purpose Input Output 3 3 60 49 39
GPIO4 I/O General-Purpose Input Output 4 4 59 48 38
GPIO5 I/O General-Purpose Input Output 5 5 74 61 47
GPIO6 I/O General-Purpose Input Output 6 6 80 64 48
GPIO7 I/O General-Purpose Input Output 7 7 68 57 43
GPIO8 I/O General-Purpose Input Output 8 8 58 47
GPIO9 I/O General-Purpose Input Output 9 9 75 62
GPIO10 I/O General-Purpose Input Output 10 10 76 63
GPIO11 I/O General-Purpose Input Output 11 11 37 31
GPIO12 I/O General-Purpose Input Output 12 12 36 30 24
GPIO13 I/O General-Purpose Input Output 13 13 35 29 23
GPIO14 I/O General-Purpose Input Output 14 14 79
GPIO15 I/O General-Purpose Input Output 15 15 78
GPIO16 I/O General-Purpose Input Output 16 16 39 33 26
GPIO17 I/O General-Purpose Input Output 17 17 40 34
GPIO18_X2 I/O General-Purpose Input Output 18_X2 18 50 41 33
GPIO19_X1 I/O General-Purpose Input Output 19_X1 19 51 42 34
GPIO22 I/O General-Purpose Input Output 22 22 67 56
GPIO23 I/O General-Purpose Input Output 23 23 65 54
GPIO24 I/O General-Purpose Input Output 24 24 41 35 27
GPIO25 I/O General-Purpose Input Output 25 25 42
GPIO26 I/O General-Purpose Input Output 26 26 43
GPIO27 I/O General-Purpose Input Output 27 27 44
GPIO28 I/O General-Purpose Input Output 28 28 4 2 2
GPIO29 I/O General-Purpose Input Output 29 29 3 1 1
GPIO30 I/O General-Purpose Input Output 30 30 1
GPIO31 I/O General-Purpose Input Output 31 31 2
GPIO32 I/O General-Purpose Input Output 32 32 49 40 32
GPIO33 I/O General-Purpose Input Output 33 33 38 32 25
GPIO34 I/O General-Purpose Input Output 34 34 77
GPIO35 I/O General-Purpose Input Output 35 35 48 39 31

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Table 6-3. Digital Signals (continued)

PIN
SIGNAL NAME DESCRIPTION GPIO 80 QFP 64 QFP 48 QFP
TYPE
GPIO37 I/O General-Purpose Input Output 37 37 46 37 29
GPIO39 I/O General-Purpose Input Output 39 39 56 46
GPIO40 I/O General-Purpose Input Output 40 40 64 53
GPIO41 I/O General-Purpose Input Output 41 41 66 55
GPIO42 I/O General-Purpose Input Output 42 42 57
GPIO43 I/O General-Purpose Input Output 43 43 54
GPIO44 I/O General-Purpose Input Output 44 44 69
GPIO45 I/O General-Purpose Input Output 45 45 73
GPIO46 I/O General-Purpose Input Output 46 46 6
GPIO61 I/O General-Purpose Input Output 61 61
GPIO62 I/O General-Purpose Input Output 62 62
GPIO63 I/O General-Purpose Input Output 63 63
HIC_A0 I HIC Address 0 8 58 47
HIC_A1 I HIC Address 1 2, 26 43, 61 50 40
HIC_A2 I HIC Address 2 1 62 51 41
HIC_A3 I HIC Address 3 23 65 54
HIC_A4 I HIC Address 4 27, 41 44, 66 55
HIC_A5 I HIC Address 5 22 67 56
HIC_A6 I HIC Address 6 42, 7 57, 68 57 43
HIC_A7 I HIC Address 7 43, 5 54, 74 61 47
HIC_BASESEL0 I HIC Base Address Range Select 0 25, 9 42, 75 62
HIC_BASESEL1 I HIC Base Address Range Select 1 63 52 42
HIC_BASESEL2 I HIC Base Address Range Select 2 4 59 48 38
HIC_D0 I/O HIC Data 0 26, 33 38, 43 32 25
HIC_D1 I/O HIC Data 1 16, 27 39, 44 33 26
HIC_D2 I/O HIC Data 2 17, 42 40, 57 34
HIC_D3 I/O HIC Data 3 24, 43 41, 54 35 27
HIC_D4 I/O HIC Data 4 3, 5 60, 74 49, 61 39, 47
HIC_D5 I/O HIC Data 5 13, 40, 44 35, 64, 69 29, 53 23
HIC_D6 I/O HIC Data 6 11, 45 37, 73 31
HIC_D7 I/O HIC Data 7 39, 44 56, 69 46
HIC_D8 I/O HIC Data 8 30, 8 1, 58 47
HIC_D9 I/O HIC Data 9 2, 34 61, 77 50 40
HIC_D10 I/O HIC Data 10 1, 31 2, 62 51 41
HIC_D11 I/O HIC Data 11 13, 23 35, 65 29, 54 23
HIC_D12 I/O HIC Data 12 15, 41 66, 78 55
HIC_D13 I/O HIC Data 13 12, 22 36, 67 30, 56 24
HIC_D14 I/O HIC Data 14 6, 7 68, 80 57, 64 43, 48
HIC_D15 I/O HIC Data 15 14, 5 74, 79 61 47
HIC_INT O HIC Device Interrupt 12, 18, 32 36, 49, 50 30, 40, 41 24, 32, 33
HIC_NBE0 I HIC Byte Enable 0 11, 19 37, 51 31, 42 34
HIC_NBE1 I HIC Byte Enable 1 34, 40, 6 64, 77, 80 53, 64 48
HIC_NCS I HIC Chip Select 29 3 1 1
HIC_NOE O HIC Output Enable 28, 3 4, 60 2, 49 2, 39
HIC_NRDY O HIC Ready 37, 9 46, 75 37, 62 29

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Table 6-3. Digital Signals (continued)

PIN
SIGNAL NAME DESCRIPTION GPIO 80 QFP 64 QFP 48 QFP
TYPE
HIC_NWE I HIC Data Write Enable 10, 35, 4, 46 48, 59, 6, 76 39, 48, 63 31, 38
1, 18, 27, 33, 38, 44, 46, 32, 37, 41,
I2CA_SCL I/OD I2C-A Open-Drain Bidirectional Clock 25, 29, 33, 41
37, 43, 8 50, 54, 58, 62 47, 51
10, 19, 26, 43, 48, 49, 39, 40, 42,
I2CA_SDA I/OD I2C-A Open-Drain Bidirectional Data 31, 32, 34, 42
32, 35, 42 51, 57, 63, 76 52, 63
I2CB_SCL I/OD I2C-B Open-Drain Bidirectional Clock 15, 29, 3, 9 3, 60, 75, 78 1, 49, 62 1, 39
I2CB_SDA I/OD I2C-B Open-Drain Bidirectional Data 14, 2, 28, 34 4, 61, 77, 79 2, 50 2, 40
23, 29, 33, 3, 38, 48, 57,
LINA_RX I LIN-A Receive 1, 32, 39, 54 1, 25, 31
35, 42 65
22, 28, 32, 4, 46, 49, 6,
LINA_TX O LIN-A Transmit 2, 37, 40, 56 2, 29, 32
37, 46 67
11, 13, 15, 19, 35, 37, 51, 29, 31, 42,
LINB_RX I LIN-B Receive 23, 34
23, 41, 9 65, 66, 75, 78 54, 55, 62
10, 12, 14, 36, 41, 50, 30, 35, 41,
LINB_TX O LIN-B Transmit 24, 27, 33
18, 22, 24, 40 64, 67, 76, 79 53, 56, 63
OUTPUTXBAR1 O Output X-BAR Output 1 2, 24, 34 41, 61, 77 35, 50 27, 40
OUTPUTXBAR2 O Output X-BAR Output 2 25, 3, 37 42, 46, 60 37, 49 29, 39
OUTPUTXBAR3 O Output X-BAR Output 3 14, 26, 4, 5 43, 59, 74, 79 48, 61 38, 47
OUTPUTXBAR4 O Output X-BAR Output 4 15, 27, 33, 6 38, 44, 78, 80 32, 64 25, 48
OUTPUTXBAR5 O Output X-BAR Output 5 28, 42, 7 4, 57, 68 2, 57 2, 43
OUTPUTXBAR6 O Output X-BAR Output 6 29, 43, 9 3, 54, 75 1, 62 1
OUTPUTXBAR7 O Output X-BAR Output 7 11, 16, 30, 44 1, 37, 39, 69 31, 33 26
OUTPUTXBAR8 O Output X-BAR Output 8 17, 31, 45 2, 40, 73 34
PMBus-A Open-Drain Bidirectional 13, 19, 27, 35, 44, 46,
PMBUSA_ALERT I/OD 29, 37, 42 23, 29, 34
Alert 37, 43 51, 54
PMBus-A Control Signal - Slave 12, 18, 26, 36, 43, 48,
PMBUSA_CTL I/O 30, 39, 41 24, 31, 33
Input/Master Output 35, 42 50, 57
PMBus-A Open-Drain Bidirectional 15, 16, 24, 3, 39, 41, 48, 33, 35, 39,
PMBUSA_SCL I/OD 26, 27, 31, 39
Clock 35, 41 60, 66, 78 49, 55
PMBus-A Open-Drain Bidirectional 14, 17, 2, 25, 40, 42, 61,
PMBUSA_SDA I/OD 34, 50, 53 40
Data 34, 40 64, 77, 79
17, 25, 28, 3, 4, 40, 42, 48, 2, 34, 39, 49,
SCIA_RX I SCI-A Receive Data 2, 31, 39
35, 9 60, 75 62
16, 2, 24, 29, 3, 39, 41, 46, 1, 33, 35, 37, 1, 26, 27, 29,
SCIA_TX O SCI-A Transmit Data
37, 8 58, 61 47, 50 40
SPIA_CLK I/O SPI-A Clock 12, 18, 3, 9 36, 50, 60, 75 30, 41, 49, 62 24, 33, 39
SPIA_SIMO I/O SPI-A Slave In, Master Out (SIMO) 11, 16, 2, 8 37, 39, 58, 61 31, 33, 47, 50 26, 40
SPIA_SOMI I/O SPI-A Slave Out, Master In (SOMI) 1, 10, 13, 17 35, 40, 62, 76 29, 34, 51, 63 23, 41
SPIA_STE I/O SPI-A Slave Transmit Enable (STE) 11, 19, 5 37, 51, 63, 74 31, 42, 52, 61 34, 42, 47
14, 22, 26, 4, 43, 49, 59,
SPIB_CLK I/O SPI-B Clock 2, 40, 48, 56 2, 32, 38
28, 32, 4 67, 79
SPIB_SIMO I/O SPI-B Slave In, Master Out (SIMO) 24, 30, 40, 7 1, 41, 64, 68 35, 53, 57 27, 43
16, 25, 31, 2, 39, 42, 66,
SPIB_SOMI I/O SPI-B Slave Out, Master In (SOMI) 33, 55, 64 26, 48
41, 6 80
15, 23, 27, 3, 38, 44, 65,
SPIB_STE I/O SPI-B Slave Transmit Enable (STE) 1, 32, 54 1, 25
29, 33 78
External ePWM Synchronization
SYNCOUT O 39, 6 56, 80 46, 64 48
Pulse

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Table 6-3. Digital Signals (continued)

PIN
SIGNAL NAME DESCRIPTION GPIO 80 QFP 64 QFP 48 QFP
TYPE
JTAG Test Data Input (TDI) - TDI is
the default mux selection for the pin.
The internal pullup is disabled by
TDI I default. The internal pullup should be 35 48 39 31
enabled or an external pullup added
on the board if this pin is used as
JTAG TDI to avoid a floating input.
JTAG Test Data Output (TDO) - TDO
is the default mux selection for the
pin. The internal pullup is disabled by
default. The TDO function will tristate
TDO O when there is no JTAG activity, 37 46 37 29
leaving this pin floating; the internal
pullup should be enabled or an
external pullup added on the board to
avoid a floating GPIO input.
Crystal oscillator input or single-
ended clock input. The device
initialization software must configure
this pin before the crystal oscillator is
enabled. To use this oscillator, a
quartz crystal circuit must be
connected to X1 and X2. This pin can
also be used to feed a single-ended
X1 I 19 51 42 34
3.3-V level clock. For more
information about the ALT
functionality, see the table that is in
the External Oscillator (XTAL) section
of the System Control chapter in the
TMS320F28002x Real-Time
Microcontrollers Technical Reference
Manual.
Crystal oscillator output. For more
information about the ALT
functionality, see the table that is in
the External Oscillator (XTAL) section
X2 O 18 50 41 33
of the System Control chapter in the
TMS320F28002x Real-Time
Microcontrollers Technical Reference
Manual.
External Clock Output. This pin
outputs a divided-down version of a
XCLKOUT O 16, 18 39, 50 33, 41 26, 33
chosen clock signal from within the
device.

6.3.3 Power and Ground

Table 6-4. Power and Ground
PIN
SIGNAL NAME DESCRIPTION GPIO 80 QFP 64 QFP 48 QFP
TYPE
1.2-V Digital Logic Power Pins. TI
recommends placing a decoupling
capacitor near each VDD pin with a
VDD minimum total capacitance of 31, 53, 71, 8 27, 4, 44, 59 36, 45
approximately 10 µF. It is also
recommended that all VDD pins be
externally connected to each other.
3.3-V Analog Power Pins. Place a
VDDA minimum 2.2-µF decoupling capacitor 26 22 18
on each pin.

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Table 6-4. Power and Ground (continued)

PIN
SIGNAL NAME DESCRIPTION GPIO 80 QFP 64 QFP 48 QFP
TYPE
3.3-V Digital I/O Power Pins. Place a
minimum 0.1-µF decoupling capacitor
on each pin. It's recommended to
place an additional bulk cap of
VDDIO 32, 52, 7, 72 28, 43, 60 35, 46
around 20uF shared by all the pins.
However, the exact value of this bulk
cap will depend on the regulator
being used.
VSS Digital Ground 30, 55, 70, 9 26, 45, 5, 58 22, 37, 44
VSSA Analog Ground 25 21 17

6.3.4 Test, JTAG, and Reset

Table 6-5. Test, JTAG, and Reset
PIN
SIGNAL NAME DESCRIPTION GPIO 80 QFP 64 QFP 48 QFP
TYPE
Flash test pin 1. Reserved for TI.
FLT1 I/O 34
Must be left unconnected.
Flash test pin 2. Reserved for TI.
FLT2 I/O 33
Must be left unconnected.
TCK I JTAG test clock with internal pullup. 45 36 28
JTAG test-mode select (TMS) with
internal pullup. This serial control
input is clocked into the TAP
controller on the rising edge of TCK.
This device does not have a TRSTn
TMS I/O 47 38 30
pin. An external pullup resistor
(recommended 2.2 kΩ) on the TMS
pin to VDDIO should be placed on
the board to keep JTAG in reset
during normal operation.
Device Reset (in) and Watchdog
Reset (out). During a power-on
condition, this pin is driven low by the
device. An external circuit may also
drive this pin to assert a device reset.
This pin is also driven low by the
MCU when a watchdog reset occurs.
During watchdog reset, the XRSn pin
is driven low for the watchdog reset
duration of 512 OSCCLK cycles. A
resistor between 2.2 kΩ and 10 kΩ
should be placed between XRSn and
XRSn I/OD 5 3 3
VDDIO. If a capacitor is placed
between XRSn and VSS for noise
filtering, it should be 100 nF or
smaller. These values will allow the
watchdog to properly drive the XRSn
pin to VOL within 512 OSCCLK
cycles when the watchdog reset is
asserted. This pin is an open-drain
output with an internal pullup. If this
pin is driven by an external device, it
should be done using an open-drain
device.

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6.4 Pin Multiplexing

6.4.1 GPIO Muxed Pins
Table 6-6 lists the GPIO muxed pins. The default mode for each GPIO pin is the GPIO function, except GPIO35
and GPIO37, which default to TDI and TDO, respectively. Secondary functions can be selected by setting both
the GPyGMUXn.GPIOz and GPyMUXn.GPIOz register bits. The GPyGMUXn register should be configured
before the GPyMUXn to avoid transient pulses on GPIOs from alternate mux selections. Columns that are not
shown and blank cells are reserved GPIO Mux settings. GPIO ALT functions cannot be configured with the
GPyMUXn and GPyGMUXn registers. These are special functions that need to be configured from the module.

Note
GPIO20, GPIO21, GPIO36 and GPIO38 do not exist on this device. GPIO61 to GPIO63 exist but are
not pinned out on any packages. Boot ROM enables pullups on GPIO61 to GPIO63. For more details,
see Section 6.5.

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6.4.1.1 GPIO Muxed Pins Table

Table 6-6. GPIO Muxed Pins
0, 4, 8, 12 1 2 3 5 6 7 9 10 11 13 14 15 ALT
CLB_OUTPUTX
GPIO0 EPWM1_A I2CA_SDA SPIA_STE FSIRXA_CLK HIC_BASESEL1
BAR8
CLB_OUTPUTX FSITXA_TDM_D
GPIO1 EPWM1_B I2CA_SCL SPIA_SOMI HIC_A2 HIC_D10
BAR7 1
GPIO2 EPWM2_A OUTPUTXBAR1 PMBUSA_SDA SPIA_SIMO SCIA_TX FSIRXA_D1 I2CB_SDA HIC_A1 CANA_TX HIC_D9
GPIO3 EPWM2_B OUTPUTXBAR2 OUTPUTXBAR2 PMBUSA_SCL SPIA_CLK SCIA_RX FSIRXA_D0 I2CB_SCL HIC_NOE CANA_RX HIC_D4
EQEP2_STROB CLB_OUTPUTX
GPIO4 EPWM3_A OUTPUTXBAR3 CANA_TX SPIB_CLK FSIRXA_CLK HIC_BASESEL2 HIC_NWE
E BAR6
CLB_OUTPUTX
GPIO5 EPWM3_B OUTPUTXBAR3 CANA_RX SPIA_STE FSITXA_D1 HIC_A7 HIC_D4 HIC_D15
BAR5
CLB_OUTPUTX
GPIO6 EPWM4_A OUTPUTXBAR4 SYNCOUT EQEP1_A SPIB_SOMI FSITXA_D0 FSITXA_D1 HIC_NBE1 HIC_D14
BAR8
CLB_OUTPUTX
GPIO7 EPWM4_B OUTPUTXBAR5 EQEP1_B SPIB_SIMO FSITXA_CLK HIC_A6 HIC_D14
BAR2
EQEP1_STROB CLB_OUTPUTX FSITXA_TDM_C
GPIO8 EPWM5_A ADCSOCAO SCIA_TX SPIA_SIMO I2CA_SCL FSITXA_D1 HIC_A0 HIC_D8
E BAR5 LK
GPIO9 EPWM5_B OUTPUTXBAR6 EQEP1_INDEX SCIA_RX SPIA_CLK FSITXA_D0 LINB_RX HIC_BASESEL0 I2CB_SCL HIC_NRDY
FSITXA_TDM_D
GPIO10 EPWM6_A ADCSOCBO EQEP1_A SPIA_SOMI I2CA_SDA FSITXA_CLK LINB_TX HIC_NWE
0
GPIO11 EPWM6_B OUTPUTXBAR7 EQEP1_B SPIA_STE FSIRXA_D1 LINB_RX EQEP2_A SPIA_SIMO HIC_D6 HIC_NBE0
EQEP1_STROB
GPIO12 EPWM7_A PMBUSA_CTL FSIRXA_D0 LINB_TX SPIA_CLK CANA_RX HIC_D13 HIC_INT
E
PMBUSA_ALER
GPIO13 EPWM7_B EQEP1_INDEX FSIRXA_CLK LINB_RX SPIA_SOMI CANA_TX HIC_D11 HIC_D5
T
CLB_OUTPUTX
GPIO14 I2CB_SDA OUTPUTXBAR3 PMBUSA_SDA SPIB_CLK EQEP2_A LINB_TX EPWM3_A HIC_D15
BAR7
CLB_OUTPUTX
GPIO15 I2CB_SCL OUTPUTXBAR4 PMBUSA_SCL SPIB_STE EQEP2_B LINB_RX EPWM3_B HIC_D12
BAR6
EQEP1_STROB
GPIO16 SPIA_SIMO OUTPUTXBAR7 EPWM5_A SCIA_TX PMBUSA_SCL XCLKOUT EQEP2_B SPIB_SOMI HIC_D1
E
GPIO17 SPIA_SOMI OUTPUTXBAR8 EPWM5_B SCIA_RX EQEP1_INDEX PMBUSA_SDA CANA_TX HIC_D2
FSITXA_TDM_C
GPIO18_X2 SPIA_CLK CANA_RX EPWM6_A I2CA_SCL EQEP2_A PMBUSA_CTL XCLKOUT LINB_TX HIC_INT X2
LK
PMBUSA_ALER CLB_OUTPUTX FSITXA_TDM_D
GPIO19_X1 SPIA_STE CANA_TX EPWM6_B I2CA_SDA EQEP2_B LINB_RX HIC_NBE0 X1
T BAR1 0
EQEP1_STROB CLB_OUTPUTX
GPIO22 SPIB_CLK LINA_TX LINB_TX HIC_A5 EPWM4_A HIC_D13
E BAR1
GPIO23 EQEP1_INDEX SPIB_STE LINA_RX LINB_RX HIC_A3 EPWM4_B HIC_D11
GPIO24 OUTPUTXBAR1 EQEP2_A SPIB_SIMO LINB_TX PMBUSA_SCL SCIA_TX ERRORSTS HIC_D3
GPIO25 OUTPUTXBAR2 EQEP2_B EQEP1_A SPIB_SOMI FSITXA_D1 PMBUSA_SDA SCIA_RX HIC_BASESEL0
GPIO26 OUTPUTXBAR3 EQEP2_INDEX OUTPUTXBAR3 SPIB_CLK FSITXA_D0 PMBUSA_CTL I2CA_SDA HIC_D0 HIC_A1
EQEP2_STROB PMBUSA_ALER
GPIO27 OUTPUTXBAR4 OUTPUTXBAR4 SPIB_STE FSITXA_CLK I2CA_SCL HIC_D1 HIC_A4
E T

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TMS320F280023C TMS320F280021 TMS320F280021-Q1
TMS320F280025, TMS320F280025-Q1
TMS320F280025C, TMS320F280025C-Q1, TMS320F280023, TMS320F280023-Q1
TMS320F280023C, TMS320F280021, TMS320F280021-Q1
www.ti.com SPRSP45B – MARCH 2020 – REVISED DECEMBER 2020

Table 6-6. GPIO Muxed Pins (continued)

0, 4, 8, 12 1 2 3 5 6 7 9 10 11 13 14 15 ALT
EQEP2_STROB
GPIO28 SCIA_RX EPWM7_A OUTPUTXBAR5 EQEP1_A LINA_TX SPIB_CLK ERRORSTS I2CB_SDA HIC_NOE
E
GPIO29 SCIA_TX EPWM7_B OUTPUTXBAR6 EQEP1_B EQEP2_INDEX LINA_RX SPIB_STE ERRORSTS I2CB_SCL HIC_NCS
EQEP1_STROB
GPIO30 CANA_RX SPIB_SIMO OUTPUTXBAR7 FSIRXA_CLK EPWM1_A HIC_D8
E
GPIO31 CANA_TX SPIB_SOMI OUTPUTXBAR8 EQEP1_INDEX FSIRXA_D1 EPWM1_B HIC_D10
GPIO32 I2CA_SDA SPIB_CLK LINA_TX FSIRXA_D0 CANA_TX ADCSOCBO HIC_INT
GPIO33 I2CA_SCL SPIB_STE OUTPUTXBAR4 LINA_RX FSIRXA_CLK CANA_RX EQEP2_B ADCSOCAO HIC_D0
GPIO34 OUTPUTXBAR1 PMBUSA_SDA HIC_NBE1 I2CB_SDA HIC_D9
GPIO35 SCIA_RX I2CA_SDA CANA_RX PMBUSA_SCL LINA_RX EQEP1_A PMBUSA_CTL HIC_NWE TDI
PMBUSA_ALER
GPIO37 OUTPUTXBAR2 I2CA_SCL SCIA_TX CANA_TX LINA_TX EQEP1_B HIC_NRDY TDO
T
CLB_OUTPUTX
GPIO39 FSIRXA_CLK EQEP2_INDEX SYNCOUT EQEP1_INDEX HIC_D7
BAR2
GPIO40 SPIB_SIMO EPWM2_B PMBUSA_SDA FSIRXA_D0 EQEP1_A LINB_TX HIC_NBE1 HIC_D5
GPIO41 EPWM2_A PMBUSA_SCL FSIRXA_D1 EQEP1_B LINB_RX HIC_A4 SPIB_SOMI HIC_D12
EQEP1_STROB CLB_OUTPUTX
GPIO42 LINA_RX OUTPUTXBAR5 PMBUSA_CTL I2CA_SDA HIC_D2 HIC_A6
E BAR3
PMBUSA_ALER CLB_OUTPUTX
GPIO43 OUTPUTXBAR6 I2CA_SCL EQEP1_INDEX HIC_D3 HIC_A7
T BAR4
CLB_OUTPUTX
GPIO44 OUTPUTXBAR7 EQEP1_A FSITXA_CLK HIC_D7 HIC_D5
BAR3
CLB_OUTPUTX
GPIO45 OUTPUTXBAR8 FSITXA_D0 HIC_D6
BAR4
GPIO46 LINA_TX FSITXA_D1 HIC_NWE
GPIO61
GPIO62
GPIO63
AIO224 HIC_A3
AIO225 HIC_NWE
AIO226 HIC_A1
AIO227 HIC_NBE0
AIO228 HIC_A0
AIO230 HIC_BASESEL2
AIO231 HIC_BASESEL1
AIO232 HIC_BASESEL0
AIO233 HIC_A4
AIO237 HIC_A6
AIO238 HIC_NCS
AIO239 HIC_A5
AIO241 HIC_NBE1
AIO242 HIC_A2
AIO244 HIC_A7

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TMS320F280023C TMS320F280021 TMS320F280021-Q1
TMS320F280025, TMS320F280025-Q1
TMS320F280025C, TMS320F280025C-Q1, TMS320F280023, TMS320F280023-Q1
TMS320F280023C, TMS320F280021, TMS320F280021-Q1
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Table 6-6. GPIO Muxed Pins (continued)

0, 4, 8, 12 1 2 3 5 6 7 9 10 11 13 14 15 ALT
AIO245 HIC_NOE

Note
The analog pins that contain AIOs are in analog mode by default. AIO mode is enabled by configuring the AMSEL option of GPIOH for the
analog pin. In addition, if using the HIC mux options on the AIO pins, an external pullup is required.

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6.4.2 Digital Inputs on ADC Pins (AIOs)

GPIOs on port H (GPIO224–GPIO245) are multiplexed with analog pins. These are also referred to as AIOs.
These pins can only function in input mode. By default, these pins will function as analog pins and the GPIOs
are in a high-Z state. The GPHAMSEL register is used to configure these pins for digital or analog operation.

Note
If digital signals with sharp edges (high dv/dt) are connected to the AIOs, cross-talk can occur with
adjacent analog signals. The user should therefore limit the edge rate of signals connected to AIOs if
adjacent channels are being used for analog functions.

6.4.3 GPIO Input X-BAR

The Input X-BAR is used to route signals from a GPIO to many different IP blocks such as the ADCs, eCAPs,
ePWMs, and external interrupts (see Figure 6-4). Table 6-7 lists the input X-BAR destinations. For details on
configuring the Input X-BAR, see the Crossbar (X-BAR) chapter of the TMS320F28002x Real-Time
Microcontrollers Technical Reference Manual.

GPIO0 Asynchronous
Synchronous Input X-BAR
Sync. + Qual. Other Sources 127:16
GPIOx
eCAP
Modules
INPUT[16:1] 15:0
INPUT16
INPUT15
INPUT14
INPUT13
INPUT12

INPUT10
INPUT11

INPUT6
INPUT5
INPUT4
INPUT3
INPUT2
INPUT1
INPUT9
INPUT8
INPUT7

DCCx Clock Source-1 TZ1,TRIP1

TZ2,TRIP2
DCCx Clock Source-0 TZ3,TRIP3
TRIP6

XINT1 TRIP4
XINT2 TRIP5 ePWM
CPU PIE XINT3 Modules
XINT4 TRIP7
XINT5 TRIP8
ePWM TRIP9
X-BAR
TRIP10
TRIP11
TRIP12

Other
Sources
ADC ADCEXTSOC
EXTSYNCIN1 ePWM and eCAP
EXTSYNCIN2 Sync Scheme
Other Sources

Output X-BAR

Figure 6-4. Input X-BAR

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Table 6-7. Input X-BAR Destinations

INPUT 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
ECAP / HRCAP Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes
EPWM X-BAR Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes
CLB X-BAR Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes
OUTPUT X-BAR Yes Yes Yes Yes Yes Yes
CPU XINT XINT1 XINT2 XINT3 XINT4 XINT5
TZ1, TZ2, TZ3,
EPWM TRIP TRIP6
TRIP1 TRIP2 TRIP3
ADC START OF ADCEX
CONVERSION TSOC
EPWM / ECAP EXTSY EXTSY
SYNC NCIN1 NCIN2
DCCx CLK1 CLK0

6.4.4 GPIO Output X-BAR, CLB X-BAR, CLB Output X-BAR, and ePWM X-BAR
The Output X-BAR has eight outputs that can be selected on the GPIO mux as OUTPUTXBARx. The CLB X-
BAR has eight outputs that are connected to the CLB global mux as AUXSIGx. The CLB Output X-BAR has
eight outputs that can be selected on the GPIO mux as CLB_OUTPUTXBARx. The ePWM X-BAR has eight
outputs that are connected to the TRIPx inputs of the ePWM. The sources for the Output X-BAR, CLB X-BAR,
CLB Output X-BAR, and ePWM X-BAR are shown in Figure 6-5. For details on the Output X-BAR, CLB X-BAR,
CLB Output X-BAR, and ePWM X-BAR, see the Crossbar (X-BAR) chapter of the TMS320F28002x Real-Time
Microcontrollers Technical Reference Manual.

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CTRIPOUTH
CTRIPOUTL (Output X-BAR only)

CMPSSx
CTRIPH
CTRIPL (ePWM X-BAR only)

ePWM and eCAP

EXTSYNCOUT AUXSIG1
Sync Chain
AUXSIG2
AUXSIG3
ADCSOCA0 CLB AUXSIG4
CLB
ADCSOCA0
Select Circuit X-BAR AUXSIG5 Global
AUXSIG6 Mux
ADCSOCB0 AUXSIG7
ADCSOCB0 AUXSIG8
Select Circuit

eCAPx ECAPxOUT TRIP4

TRIP5
EVT1 TRIP7 All
ADCx EVT2 ePWM
TRIP8
EVT3 EPWM
EVT4 TRIP9 Modules
X-BAR TRIP10
TRIP11
INPUT1-6 TRIP12
Input X-BAR INPUT7-14
(ePWM X-BAR only)
eQEPx

OUTPUTXBAR1
OUTPUTXBAR2
OUTPUTXBAR3
Output OUTPUTXBAR4
X-BAR OUTPUTXBAR5
OUTPUTXBAR6
OUTPUTXBAR7
OUTPUTXBAR8

X-BAR Flags GPIO

(shared) Mux

CLB_OUTPUTXBAR1
CLB_OUTPUTXBAR2
CLB CLB_OUTPUTXBAR3
CLB_OUTPUTXBAR4
CLB Input X-BAR CLB TILEx Output CLB_OUTPUTXBAR5
X-BAR CLB_OUTPUTXBAR6
CLB_OUTPUTXBAR7
CLB_OUTPUTXBAR8

Figure 6-5. Output X-BAR, CLB X-BAR, CLB Output X-BAR, and ePWM X-BAR Sources

Copyright © 2020 Texas Instruments Incorporated Submit Document Feedback 45

6.5 Pins With Internal Pullup and Pulldown

Some pins on the device have internal pullups or pulldowns. Table 6-8 lists the pull direction and when it is
active. The pullups on GPIO pins are disabled by default and can be enabled through software. To avoid any
floating unbonded inputs, the Boot ROM will enable internal pullups on GPIO pins that are not bonded out in a
particular package. Other pins noted in Table 6-8 with pullups and pulldowns are always on and cannot be
disabled.
Table 6-8. Pins With Internal Pullup and Pulldown
RESET
PIN DEVICE BOOT APPLICATION
(XRSn = 0)
GPIOx Pullup disabled Pullup disabled(1) Application defined
GPIO35/TDI Pullup disabled Application defined
GPIO37/TDO Pullup disabled Application defined
TCK Pullup active
TMS Pullup active
XRSn Pullup active
Other pins (including AIOs) No pullup or pulldown present

(1) Pins not bonded out in a given package will have the internal pullups enabled by the Boot ROM.

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6.6 Connections for Unused Pins

For applications that do not need to use all functions of the device, Table 6-9 lists acceptable conditioning for any
unused pins. When multiple options are listed in Table 6-9, any option is acceptable. Pins not listed in Table 6-9
must be connected according to Section 6.
Table 6-9. Connections for Unused Pins
SIGNAL NAME ACCEPTABLE PRACTICE
ANALOG
VREFHI Tie to VDDA (applies only if ADC is not used in the application)
VREFLO Tie to VSSA
• No Connect
Analog input pins • Tie to VSSA
• Tie to VSSA through resistor

DIGITAL
• No Connect
FLT1 (Flash Test pin 1) • Tie to VSS through 4.7-kΩ or larger resistor

• No Connect
FLT2 (Flash Test pin 2) • Tie to VSS through 4.7-kΩ or larger resistor

• No connection (input mode with internal pullup enabled)

GPIOx • No connection (output mode with internal pullup disabled)
• Pullup or pulldown resistor (any value resistor, input mode, and with internal pullup disabled)

When TDI mux option is selected (default), the GPIO is in Input mode.
GPIO35/TDI • Internal pullup enabled
• External pullup resistor

When TDO mux option is selected (default), the GPIO is in Output mode only during JTAG activity;
otherwise, it is in a tri-state condition. The pin must be biased to avoid extra current on the input buffer.
GPIO37/TDO • Internal pullup enabled
• External pullup resistor

• No Connect
TCK • Pullup resistor

TMS Pullup resistor

Turn XTAL off and:
• Input mode with internal pullup enabled
GPIO19/X1 • Input mode with external pullup or pulldown resistor
• Output mode with internal pullup disabled

Turn XTAL off and:

• Input mode with internal pullup enabled
GPIO18/X2 • Input mode with external pullup or pulldown resistor
• Output mode with internal pullup disabled

POWER AND GROUND

VDD All VDD pins must be connected per Section 6.3. Pins should not be used to bias any external circuits.
VDDA If a dedicated analog supply is not used, tie to VDDIO.
VDDIO All VDDIO pins must be connected per Section 6.3.
VSS All VSS pins must be connected to board ground.
VSSA If an analog ground is not used, tie to VSS.

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7 Specifications
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
These are stress ratings only and functional operation of the device beyond the Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect
device reliability. All voltage values are with respect to VSS, unless otherwise noted.
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
VDDIO with respect to VSS –0.3 4.6
Supply voltage V
VDDA with respect to VSSA –0.3 4.6
Input voltage VIN (3.3 V) –0.3 4.6 V
Output voltage VO –0.3 4.6 V
Digital/analog input (per pin), IIK (VIN < VSS/VSSA or VIN >
–20 20
VDDIO/VDDA)(2)
Input clamp current mA
Total for all inputs, IIKTOTAL
–20 20
(VIN < VSS/VSSA or VIN > VDDIO/VDDA)
Output current Digital output (per pin), IOUT –20 20 mA
Free-Air temperature TA –40 125 °C
Operating junction temperature TJ –40 150 °C
Storage temperature(1) Tstg –65 150 °C

(1) Long-term high-temperature storage or extended use at maximum temperature conditions may result in a reduction of overall device
life. For additional information, see the Semiconductor and IC Package Thermal Metrics Application Report.
(2) Continuous clamp current per pin is ±2 mA. Do not operate in this condition continuously as VDDIO/VDDA voltage may internally rise and
impact other electrical specifications.

7.2 ESD Ratings – Commercial

VALUE UNIT
F280025, F280025C, F280023, F280023C in 80-pin PN package
Human-body model (HBM), per ANSI/ESDA/JEDEC ±2000
Electrostatic discharge JS-001(1)
V(ESD) V
(ESD) Charged-device model (CDM), per JEDEC specification ±500
JESD22-C101 or ANSI/ESDA/JEDEC JS-002(2)
F280025, F280025C, F280023, F280023C in 64-pin PM package
Human-body model (HBM), per ANSI/ESDA/JEDEC ±2000
Electrostatic discharge JS-001(1)
V(ESD) V
(ESD) Charged-device model (CDM), per JEDEC specification ±500
JESD22-C101 or ANSI/ESDA/JEDEC JS-002(2)
F280025, F280025C, F280023, F280023C, F280021 in 48-pin PT package
Human-body model (HBM), per ANSI/ESDA/JEDEC ±2000
Electrostatic discharge JS-001(1)
V(ESD) V
(ESD) Charged-device model (CDM), per JEDEC specification ±500
JESD22-C101 or ANSI/ESDA/JEDEC JS-002(2)

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

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7.3 ESD Ratings – Automotive

VALUE UNIT
F280025-Q1, F280025C-Q1, F280023-Q1 in 80-pin PN package
Human body model (HBM), per All pins ±2000
AEC Q100-002(1)
V(ESD) Electrostatic discharge Charged device model (CDM), All pins ±500 V
per AEC Q100-011
Corner pins on 80-pin PN: ±750
1, 20, 21, 40, 41, 60, 61, 80
F280025-Q1, F280025C-Q1, F280023-Q1 in 64-pin PM package
Human body model (HBM), per All pins ±2000
AEC Q100-002(1)
V(ESD) Electrostatic discharge Charged device model (CDM), All pins ±500 V
per AEC Q100-011
Corner pins on 64-pin PM: ±750
1, 16, 17, 32, 33, 48, 49, 64
F280025-Q1, F280025C-Q1, F280023-Q1, F280021-Q1 in 48-pin PT package
Human body model (HBM), per All pins ±2000
AEC Q100-002(1)
V(ESD) Electrostatic discharge Charged device model (CDM), All pins ±500 V
per AEC Q100-011
Corner pins on 48-pin PT: ±750
1, 12, 13, 24, 25, 36, 37, 48

(1) AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

7.4 Recommended Operating Conditions

MIN NOM MAX UNIT

Device supply voltage, VDDIO and Internal BOR enabled(3) VBOR-VDDIO(MAX) + VBOR-GB (2) 3.3 3.63
V
VDDA Internal BOR disabled 2.8 3.3 3.63
Device ground, VSS 0 V
Analog ground, VSSA 0 V
Supply ramp rate of VDDIO,
SRSUPPLY 20 100 mV/us
VDDA with respect to VSS.(4)
VDDIO supply ramp time from
tVDDIO-RAMP 10 ms
1 V to VBOR-VDDIO(MAX)
Digital input voltage VSS – 0.3 VDDIO + 0.3 V
VIN
Analog input voltage VSSA – 0.3 VDDA + 0.3 V
VBOR-GB VDDIO BOR guard band(5) 0.1 V
Junction temperature, TJ S version(1) –40 125 °C
Q version(1)
Free-Air temperature, TA –40 125 °C
(AEC Q100 qualification)

(1) Operation above TJ = 105°C for extended duration will reduce the lifetime of the device. See Calculating Useful Lifetimes of Embedded
Processors for more information.
(2) The VDDIO BOR voltage (VBOR-VDDIO[MAX]) in Electrical Characteristics table determines the lower voltage bound for device
operation. TI recommends that system designers budget an additional guard band (VBOR-GB) as shown in Supply Voltages figure.
(3) Internal BOR is enabled by default.
(4) Supply ramp rate faster than this can trigger the on-chip ESD protection.
(5) TI recommends VBOR-GB to avoid BOR resets due to normal supply noise or load-transient events on the 3.3-V VDDIO system
regulator. Good system regulator design and decoupling capacitance (following the system regulator specifications) are important to
prevent activation of the BOR during normal device operation. The value of VBOR-GB is a system-level design consideration; the voltage
listed here is typical for many applications.

Copyright © 2020 Texas Instruments Incorporated Submit Document Feedback 49

Supply Voltages

3.63 V +10%

Recommended
System Voltage
3.3 V 0% Regulator Range F28002x
VDDIO
Operating
Range
3.1 V –6.1%
VBOR-GB
BOR Guard Band
3.0 V –9.1%
VBOR-VDDIO
Internal BOR Threshold
2.81 V –14.8%
2.80 V –15.1%

Figure 7-1. Supply Voltages

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7.5 Power Consumption Summary

Current values listed in this section are representative for the test conditions given and not the absolute
maximum possible. The actual device currents in an application will vary with application code and pin
configurations. Section 7.5.1 lists the system current consumption values.
7.5.1 System Current Consumption
over operating free-air temperature range (unless otherwise noted).
TYP : Vnom, 30℃
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
OPERATING MODE
VDDIO current consumption during This is an estimation of current
IDDIO 35 72 mA
operational usage for a typical heavily loaded
application. Actual currents will
VDDA current consumption during vary depending on system
IDDA activity, I/O electrical loading and 3 5 mA
operational usage
switching frequency.
IDLE MODE
VDDIO current consumption while - CPU is in IDLE mode
IDDIO 16 33 mA
device is in Idle mode - Flash is powered down
VDDA current consumption while - XCLKOUT is turned off
IDDA - Pull up is enabled for IO pins 0.01 0.1 mA
device is in Idle mode
STANDBY MODE
VDDIO current consumption while - CPU is in STANDBY mode
IDDIO 8 22 mA
device is in Standby mode - Flash is powered down
VDDA current consumption while - XCLKOUT is turned off
IDDA - Pull up is enabled for IO pins 0.01 0.1 mA
device is in Standby mode
HALT MODE
VDDIO current consumption while - CPU is in HALT mode
IDDIO 1 16 mA
device is in Halt mode - Flash is powered down
VDDA current consumption while - XCLKOUT is turned off
IDDA - Pull up is enabled for IO pins 0.01 0.1 mA
device is in Halt mode
FLASH ERASE/PROGRAM
VDDIO current consumption during - CPU is running from RAM.
IDDIO 72 106 mA
Erase/Program cycle(1) - SYSCLK at 100 MHz.
- I/Os are inputs with pullups
enabled.
VDDA current consumption during - Peripheral clocks are turned off.
IDDA 0.1 2.5 mA
Erase/Program cycle

RESET MODE
VDDIO current consumption while
IDDIO 8.6 mA
reset is active(2)
VDDA current consumption while reset
IDDA 0.1 mA
is active(2)

(1) Brownout events during flash programming can corrupt flash data and permanently lock the device. Programming environments using
alternate power sources (such as a USB programmer) must be capable of supplying the rated current for the device and other system
components with sufficient margin to avoid supply brownout conditions.
(2) This is the current consumption while reset is active, i.e XRSn is low.

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7.5.2 Operating Mode Test Description

Section 7.5.1 and Section 7.5.4.1 list the current consumption values for the operational mode of the device. The
operational mode provides an estimation of what an application might encounter. The test condition for these
measurements has the following properties:
• Code is executing from RAM.
• FLASH is read and kept in active state.
• No external components are driven by I/O pins.
• All peripherals have clocks enabled.
• All CPUs are actively executing code.
• All analog peripherals are powered up. ADCs and DACs are periodically converting.
7.5.3 Current Consumption Graphs
Figure 7-2, Figure 7-3, Figure 7-4, Figure 7-5, and Figure 7-6 show a typical representation of the relationship
between frequency, temperature, core supply, and current consumption on the device. Actual results will vary
based on the system implementation and conditions.
Figure 7-3 shows the typical operating current profile across temperature and core supply voltage. Figure 7-4
shows the typical idle current profile across temperature and core supply voltage. Figure 7-5 shows the typical
standby current profile across temperature and core supply voltage. Figure 7-6 shows the typical halt current
profile across temperature and core supply voltage.

Figure 7-2. Operating Current Versus Frequency Figure 7-3. Operating Current Versus Temperature

Figure 7-4. Current Versus Temperature – Figure 7-5. Current Versus Temperature –
IDLE Mode STANDBY Mode

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Figure 7-6. Current Versus Temperature – HALT Mode

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7.5.4 Reducing Current Consumption

The F28002x devices provide some methods to reduce the device current consumption:
• One of the two low-power modes—IDLE or STANDBY—could be entered during idle periods in the
application.
• The flash module may be powered down if the code is run from RAM.
• Disable the pullups on pins that assume an output function.
• Each peripheral has an individual clock-enable bit (PCLKCRx). Reduced current consumption may be
achieved by turning off the clock to any peripheral that is not used in a given application. Section 7.5.4.1 lists
the typical current reduction that may be achieved by disabling the clocks using the PCLKCRx register.
• To realize the lowest VDDA current consumption in an LPM, see the Analog-to-Digital Converter (ADC)
chapter of the TMS320F28002x Real-Time Microcontrollers Technical Reference Manual to ensure each
module is powered down as well.
7.5.4.1 Typical Current Reduction per Disabled Peripheral
PERIPHERAL IDDIO CURRENT REDUCTION (mA)
ADC(1) 0.67
BGCRC 0.26
CAN 1.18
CLB 1.18
CMPSS(1) 0.34
CPU TIMER 0.02
CPUCRC 0.01
DCC 0.18
DMA 0.56
eCAP1 and eCAP2 0.22
eCAP3(2) 0.28
ePWM 0.78
eQEP 0.11
FSI 0.74
HIC 0.21
HRPWM 0.87
I2C 0.24
LIN 0.32
PBIST 0.19
PMBUS 0.26
SCI 0.16
SPI 0.08

(1) This current represents the current drawn by the digital portion of the each module.
(2) eCAP3 can also be configured as HRCAP.

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7.6 Electrical Characteristics

over recommended operating conditions (unless otherwise noted)
TEST
PARAMETER MIN TYP MAX UNIT
CONDITIONS
Digital and Analog IO
IOH = IOH MIN VDDIO * 0.8
VOH High-level output voltage V
IOH = –100 μA VDDIO – 0.2
IOL = IOL MAX 0.4
VOL Low-level output voltage V
IOL = 100 µA 0.2
IOH High-level output source current for all output pins –4 mA
IOL Low-level output sink current for all output pins 4 mA
ROH High-level output impedance for all output pins 45 65 100 Ω
ROL Low-level output impedance for all output pins 45 60 90 Ω
VIH High-level input voltage 2.0 V
VIL Low-level input voltage 0.8 V
VHYSTERESIS Input hysteresis 125 mV
VDDIO = 3.3 V
IPULLDOWN Input current Pins with pulldown 120 µA
VIN = VDDIO
Digital inputs with pullup VDDIO = 3.3 V
IPULLUP Input current 160 µA
enabled(1) VIN = 0 V
Pullups and outputs
Digital inputs disabled 0.1
0 V ≤ VIN ≤ VDDIO
ILEAK Pin leakage µA
Analog pins (except Analog drivers 0.1
ADCINA3/VDAC) disabled
ADCINA3/VDAC 0 V ≤ VIN ≤ VDDA 2 11
Digital inputs 2
CI Input capacitance pF
Analog pins(2)
VREG and BOR
VDDIO power on reset VDDIO power on reset
VPOR-VDDIO 2.3 V
voltage voltage
VBOR-VDDIO VDDIO brown out reset voltage(3) 2.81 3.0 V
VVREG Internal voltage regulator output 1.14 1.2 1.32 V

(1) See Pins With Internal Pullup and Pulldown table for a list of pins with a pullup or pulldown.
(2) The analog pins are specified separately; see Per-Channel Parasitic Capacitance table.
(3) See the Supply Voltages figure in the Recommended Operating Conditions section.

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7.7 Thermal Resistance Characteristics for PN Package

°C/W(1) AIR FLOW (lfm)(2)
RΘJC Junction-to-case thermal resistance 14.2 N/A
RΘJB Junction-to-board thermal resistance 21.9 N/A
49.9 0
38.3 150
RΘJA (High k PCB) Junction-to-free air thermal resistance
36.7 250
34.4 500
0.8 0
1.18 150
PsiJT Junction-to-package top
1.34 250
1.62 500
21.6 0
20.7 150
PsiJB Junction-to-board
20.5 250
20.1 500

(1) These values are based on a JEDEC-defined 2S2P system (with the exception of the Theta JC [RΘJC] value, which is based on a
JEDEC-defined 1S0P system) and will change based on environment as well as application. For more information, see these EIA/
JEDEC standards:
• JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions - Natural Convection (Still Air)
• JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
• JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
• JESD51-9, Test Boards for Area Array Surface Mount Package Thermal Measurements
(2) lfm = linear feet per minute

7.8 Thermal Resistance Characteristics for PM Package

°C/W(1) AIR FLOW (lfm)(2)
RΘJC Junction-to-case thermal resistance 12.4 N/A
RΘJB Junction-to-board thermal resistance 25.6 N/A
RΘJA (High k PCB) Junction-to-free air thermal resistance 51.8 0
42.2 150
RΘJMA Junction-to-moving air thermal resistance 39.4 250
36.5 500
0.5 0
0.9 150
PsiJT Junction-to-package top
1.1 250
1.4 500
25.1 0
23.8 150
PsiJB Junction-to-board
23.4 250
22.7 500

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7.9 Thermal Resistance Characteristics for PT Package

°C/W(1) AIR FLOW (lfm)(2)
RΘJC Junction-to-case thermal resistance 13.6 N/A
RΘJB Junction-to-board thermal resistance 30.6 N/A
64 0
50.4 150
RΘJA (High k PCB) Junction-to-free air thermal resistance
48.2 250
45 500
0.56 0
0.94 150
PsiJT Junction-to-package top
1.1 250
1.38 500
30.1 0
28.7 150
PsiJB Junction-to-board
28.4 250
28 500

7.10 Thermal Design Considerations

Based on the end application design and operational profile, the IDD and IDDIO currents could vary. Systems that
exceed the recommended maximum power dissipation in the end product may require additional thermal
enhancements. Ambient temperature (TA) varies with the end application and product design. The critical factor
that affects reliability and functionality is TJ, the junction temperature, not the ambient temperature. Hence, care
should be taken to keep TJ within the specified limits. Tcase should be measured to estimate the operating
junction temperature TJ. Tcase is normally measured at the center of the package top-side surface. The thermal
application report Semiconductor and IC Package Thermal Metrics helps to understand the thermal metrics and
definitions.

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7.11 System
7.11.1 Power Management
TMS320F28002x real-time MCUs use an internal 1.2-V LDO Voltage Regulator (VREG) to supply the required
1.2 V to the core (VDD).
7.11.1.1 Internal 1.2-V LDO Voltage Regulator (VREG)
The internal VREG is supplied by VDDIO and generates the 1.2 V required to power the VDD pins. The internal
VREG is always enabled and, as such, is the required supply source for the VDD pins. Although the internal
VREG eliminates the need to use an external power supply for VDD, decoupling capacitors are required on each
VDD pin for VREG stability. There are two recommended capacitor configurations (described in the list that
follows) for the VDD rail when using the internal VREG. The signal description for VDD can be found in Table
6-4.
• Configuration 1: Place a small decoupling capacitor to VSS on each pin as close to the device as possible. In
addition, a bulk capacitance must be placed on the VDD node to VSS (one 10-µF capacitor or two parallel
4.7-µF capacitors).
• Configuration 2: Distribute the total capacitance to VSS evenly across all VDD pins (total capacitance divided
by number of available VDD pins).
7.11.1.2 Power Sequencing
Signal Pin Requirements: Before powering the device, no voltage larger than 0.3 V above VDDIO can be
applied to any digital pin, and no voltage larger than 0.3 V above VDDA can be applied to any analog pin
(including VREFHI).
VDDIO and VDDA Requirements: The 3.3-V supplies VDDIO and VDDA should be powered up together and
kept within 0.3 V of each other during functional operation.
VDD Requirements: The VDD sequencing requirements are handled by the device.
7.11.1.3 Power-On Reset (POR)
An internal power-on reset (POR) circuit holds the device in reset and keeps the I/Os in a high-impedance state
during power up. The POR is in control and forces XRSn low internally until the voltage on VDDIO crosses the
POR threshold. When the voltage crosses the POR threshold, the internal brownout-reset (BOR) circuit takes
control and holds the device in reset until the voltage crosses the BOR threshold (for internal BOR details, see
Section 7.11.1.4).
7.11.1.4 Brownout Reset (BOR)
An internal BOR circuit monitors the VDDIO rail for dips in voltage which result in the supply voltage dropping out
of operational range. When the VDDIO voltage drops below the BOR threshold, the device is forced into reset,
and XRSn is pulled low. XRSn will remain in reset until the voltage returns to the operational range. The BOR is
enabled by default. To disable the BOR, set the BORLVMONDIS bit in the VMONCTL register. The internal BOR
circuit monitors only the VDDIO rail. See Section 7.6 for BOR characteristics. External supply voltage supervisor
(SVS) devices can be used to monitor the voltage on the 3.3-V rail and to drive XRSn low if supplies fall outside
operational specifications.

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7.11.2 Reset Timing

XRSn is the device reset pin. It functions as an input and open-drain output. The device has a built-in power-on
reset (POR). During power up, the POR circuit drives the XRSn pin low. A watchdog or NMI watchdog reset will
also drive the pin low. An external open-drain circuit may drive the pin to assert a device reset.
A resistor with a value from 2.2 kΩ to 10 kΩ should be placed between XRSn and VDDIO. A capacitor should be
placed between XRSn and VSS for noise filtering, it should be 100 nF or smaller. These values will allow the
watchdog to properly drive the XRSn pin to VOL within 512 OSCCLK cycles when the watchdog reset is
asserted. Figure 7-7 shows the recommended reset circuit.
VDDIO

2.2 kW to 10 kW

Optional open-drain
XRSn
Reset source
£100 nF

Figure 7-7. Reset Circuit

7.11.2.1 Reset Sources

Table 7-1 summarizes the various reset signals and their effect on the device.
Table 7-1. Reset Signals
CPU CORE JTAG/
PERIPHERALS
RESET SOURCE RESET DEBUG LOGIC I/Os XRSn OUTPUT
RESET
(C28x, FPU, VCU) RESET
POR Yes Yes Yes Hi-Z Yes
XRSn Pin Yes Yes No Hi-Z –
WDRS Yes Yes No Hi-Z Yes
NMIWDRS Yes Yes No Hi-Z Yes
SYSRS (Debugger Reset) Yes Yes No Hi-Z No
SCCRESET Yes Yes No Hi-Z No

The parameter th(boot-mode) must account for a reset initiated from any of these sources.
See the Resets section of the System Control chapter in the TMS320F28002x Real-Time Microcontrollers
Technical Reference Manual.

CAUTION
Some reset sources are internally driven by the device. Some of these sources will drive XRSn low,
use this to disable any other devices driving the boot pins. The SCCRESET and debugger reset
sources do not drive XRSn; therefore, the pins used for boot mode should not be actively driven by
other devices in the system. The boot configuration has a provision for changing the boot pins in
OTP; for more details, see the TMS320F28002x Real-Time Microcontrollers Technical Reference
Manual.

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7.11.2.2 Reset Electrical Data and Timing

Section 7.11.2.2.1 lists the reset (XRSn) timing requirements. Section 7.11.2.2.2 lists the reset (XRSn) switching
characteristics. Figure 7-8 shows the power-on reset. Figure 7-9 shows the warm reset.
7.11.2.2.1 Reset (XRSn) Timing Requirements

MIN MAX UNIT

th(boot-mode) Hold time for boot-mode pins 1.5 ms
All cases 3.2
Pulse duration, XRSn low on
tw(RSL2) Low-power modes used in µs
warm reset 3.2 * (SYSCLKDIV/16)
application and SYSCLKDIV > 16

7.11.2.2.2 Reset (XRSn) Switching Characteristics

over recommended operating conditions (unless otherwise noted)
PARAMETER MIN TYP MAX UNIT
Pulse duration, XRSn driven low by device after supplies are
tw(RSL1) 100 µs
stable
tw(WDRS) Pulse duration, reset pulse generated by watchdog 512tc(OSCCLK) cycles
tboot-flash Boot-ROM execution time to first instruction fetch in flash 900 µs

7.11.2.2.3 Reset Timing Diagrams

VDDIO VDDA
(3.3V)

VDD (1.2V)

tw(RSL1)

XRSn(A)
tboot-flash
Boot ROM

CPU
Execution
Phase
User code
th(boot-mode)(B) User code dependent

Boot-Mode GPIO pins as input

Pins
Boot-ROM execution starts Peripheral/GPIO function
Based on boot code

GPIO pins as input (pullups are disabled)

I/O Pins
User code dependent
A. The XRSn pin can be driven externally by a supervisor or an external pullup resistor, see Table 6-1. On-chip POR logic will hold this pin
low until the supplies are in a valid range.
B. After reset from any source (see Section 7.11.2.1), the boot ROM code samples Boot Mode pins. Based on the status of the Boot Mode
pin, the boot code branches to destination memory or boot code function. If boot ROM code executes after power-on conditions (in
debugger environment), the boot code execution time is based on the current SYSCLK speed. The SYSCLK will be based on user
environment and could be with or without PLL enabled.

Figure 7-8. Power-on Reset

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tw(RSL2)

XRSn

User code
CPU
Execution User code Boot ROM
Phase
Boot ROM execution starts
(initiated by any reset source) th(boot-mode)(A)

Boot-Mode Peripheral/GPIO function GPIO Pins as Input Peripheral/GPIO function

Pins
User-Code Execution Starts

I/O Pins User-Code Dependent GPIO Pins as Input (Pullups are Disabled)

User-Code Dependent
A. After reset from any source (see Section 7.11.2.1), the Boot ROM code samples BOOT Mode pins. Based on the status of the Boot
Mode pin, the boot code branches to destination memory or boot code function. If Boot ROM code executes after power-on conditions (in
debugger environment), the Boot code execution time is based on the current SYSCLK speed. The SYSCLK will be based on user
environment and could be with or without PLL enabled.

Figure 7-9. Warm Reset

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7.11.3 Clock Specifications

7.11.3.1 Clock Sources
Table 7-2 lists clock sources. Figure 7-10 shows the clocking system. Figure 7-11 shows the PLL.
Table 7-2. Possible Reference Clock Sources
CLOCK SOURCE DESCRIPTION
INTOSC1 Internal oscillator 1.
Zero-pin overhead 10-MHz internal oscillator.
INTOSC2(1) Internal oscillator 2.
Zero-pin overhead 10-MHz internal oscillator.
X1 (XTAL) External crystal or resonator connected between the X1 and X2 pins or single-ended clock connected to the X1
pin.

(1) On reset, internal oscillator 2 (INTOSC2) is the default clock source for the PLL (OSCCLK).

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SYSCLKDIVSEL PLLSYSCLK
Watchdog NMIWD
Timer
SYS
PLLRAWCLK Divider FPU
INTOSC1 SYSPLL CPUCLK TMU
OSCCLK Flash
INTOSC2 SYSPLLCLKEN
X1 (XTAL)

OSCCLKSRCSEL
CPU
ePIE Boot ROM
GPIO DCSM
SYSCLK SYSCLK Mx RAMs System Control
Lx RAMs WD
GSx RAMs XINT

CPUTIMERs I2C
One per SYSCLK peripheral CLB ADC
ECAP CMPSS
PCLKCRx PERx.SYSCLK EQEP CAN
EPWM HIC
HRCAL DCC
PMBUS HWBIST
LIN BGCRC
FSI ERAD

One per LSPCLK peripheral

LOSPCP
PCLKCRx
LSPCLK PERx.LSPCLK SCI
LSP
Divider SPI

CLKSRCCTL2.CANxBCLKSEL

CAN Bit Clock

Figure 7-10. Clocking System

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SYSPLL

OSCCLK ÷ INTCLK VCOCLK ÷ PLLRAWCLK

VCO
(REFDIV+1) (ODIV+1)

÷
IMULT

Figure 7-11. System PLL

In Figure 7-11,

f OSCCLK IMULT
f PLLRAWCLK REFDIV 1
u
ODIV 1

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7.11.3.2 Clock Frequencies, Requirements, and Characteristics

This section provides the frequencies and timing requirements of the input clocks, PLL lock times, frequencies of
the internal clocks, and the frequency and switching characteristics of the output clock.
7.11.3.2.1 Input Clock Frequency and Timing Requirements, PLL Lock Times
Section 7.11.3.2.1.1 lists the frequency requirements for the input clocks. Section 7.11.3.2.1.2 lists the XTAL
oscillator characteristics. Section 7.11.3.2.1.3 lists the X1 timing requirements. Section 7.11.3.2.1.4 lists the
APLL characteristics. Section 7.11.3.2.1.5 lists the switching characteristics of the output clock, XCLKOUT.
Section 7.11.3.2.1.6 provides the clock frequencies for the internal clocks.
7.11.3.2.1.1 Input Clock Frequency
MIN MAX UNIT
f(XTAL) Frequency, X1/X2, from external crystal or resonator 10 20 MHz
f(X1) Frequency, X1, from external oscillator 10 25 MHz

7.11.3.2.1.2 XTAL Oscillator Characteristics

over recommended operating conditions (unless otherwise noted)
PARAMETER MIN TYP MAX UNIT
X1 VIL Valid low-level input voltage –0.3 0.3 * VDDIO V
X1 VIH Valid high-level input voltage 0.7 * VDDIO VDDIO + 0.3 V

7.11.3.2.1.3 X1 Timing Requirements

MIN MAX UNIT

tf(X1) Fall time, X1 6 ns
tr(X1) Rise time, X1 6 ns
tw(X1L) Pulse duration, X1 low as a percentage of tc(X1) 45% 55%
tw(X1H) Pulse duration, X1 high as a percentage of tc(X1) 45% 55%

7.11.3.2.1.4 APLL Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETER MIN TYP MAX UNIT
PLL Lock time
SYS PLL Lock Time(1) 5µs + (1024 * (REFDIV + 1) * tc(OSCCLK)) us

(1) The PLL lock time here defines the typical time that takes for the PLL to lock once PLL is enabled (SYSPLLCTL1[PLLENA]=1).
Additional time to verify the PLL clock using Dual Clock Comparator (DCC) is not accounted here. TI recommends using the latest
example software from C2000Ware for initializing the PLLs. For the system PLL, see InitSysPll() or SysCtl_setClock().

7.11.3.2.1.5 XCLKOUT Switching Characteristics

over recommended operating conditions (unless otherwise noted)
PARAMETER(1) MIN MAX UNIT
tf(XCO) Fall time, XCLKOUT 5 ns
tr(XCO) Rise time, XCLKOUT 5 ns
tw(XCOL) Pulse duration, XCLKOUT low H – 2(2) H + 2(2) ns
tw(XCOH) Pulse duration, XCLKOUT high H – 2(2) H + 2(2) ns
f(XCO) Frequency, XCLKOUT 50 MHz

(1) A load of 40 pF is assumed for these parameters.

(2) H = 0.5tc(XCO)

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7.11.3.2.1.6 Internal Clock Frequencies

MIN NOM MAX UNIT
f(SYSCLK) Frequency, device (system) clock 2 100 MHz
tc(SYSCLK) Period, device (system) clock 10 500 ns
Frequency, system PLL going into VCO (after
f(INTCLK) 10 20 MHz
REFDIV)
f(VCOCLK) Frequency, system PLL VCO (before ODIV) 220 600 MHz
Frequency, system PLL output (before SYSCLK
f(PLLRAWCLK) 6 200 MHz
divider)
f(PLL) Frequency, PLLSYSCLK 2 100 MHz
f(PLL_LIMP) Frequency, PLL Limp Frequency (1) 45/(ODIV+1) MHz
f(LSP) Frequency, LSPCLK 2 100 MHz
tc(LSPCLK) Period, LSPCLK 10 500 ns
Frequency, OSCCLK (INTOSC1 or INTOSC2 or
f(OSCCLK) See respective clock MHz
XTAL or X1)
f(EPWM) Frequency, EPWMCLK 100 MHz
f(HRPWM) Frequency, HRPWMCLK 60 100 MHz

(1) PLL output frequency when OSCCLK is dead (Loss of OSCCLK causes PLL to Limp).

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7.11.3.3 Input Clocks and PLLs

In addition to the internal 0-pin oscillators, three types of external clock sources are supported:
• A single-ended 3.3-V external clock. The clock signal should be connected to X1, as shown in Figure 7-12,
with the XTALCR.SE bit set to 1.
• An external crystal. The crystal should be connected across X1 and X2 with its load capacitors connected to
VSS as shown in Figure 7-13.
• An external resonator. The resonator should be connected across X1 and X2 with its ground connected to
VSS as shown in Figure 7-14.

Microcontroller Microcontroller

GPIO19 GPIO18* GPIO19 GPIO18

VSS X1 X2 VSS X1 X2

* Available as a
+3.3 V
GPIO when X1 is
used as a clock

VDD Out

3.3-V Oscillator

Gnd

Figure 7-12. Single-ended 3.3-V External Clock Figure 7-13. External Crystal
Microcontroller

GPIO19 GPIO18
VSS X1 X2

Figure 7-14. External Resonator

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7.11.3.4 Crystal Oscillator

When using a quartz crystal, it may be necessary to include a damping resistor (RD) in the crystal circuit to
prevent overdriving the crystal (drive level can be found in the crystal data sheet). In higher-frequency
applications (10 MHz or greater), RD is generally not required. If a damping resistor is required, RD should be as
small as possible because the size of the resistance affects start-up time (smaller RD = faster start-up time). TI
recommends that the crystal manufacturer characterize the crystal with the application board. Section 7.11.3.4.1
lists the crystal oscillator parameters. Table 7-3 lists the crystal equivalent series resistance (ESR) requirements.
Section 7.11.3.4.2 lists the crystal oscillator electrical characteristics.
7.11.3.4.1 Crystal Oscillator Parameters

MIN MAX UNIT

CL1, CL2 Load capacitance 12 24 pF
C0 Crystal shunt capacitance 7 pF

For Table 7-3:

1. Crystal shunt capacitance (C0) should be less than or equal to 7 pF.
2. ESR = Negative Resistance/3
Table 7-3. Crystal Equivalent Series Resistance (ESR) Requirements
MAXIMUM ESR (Ω) MAXIMUM ESR (Ω)
CRYSTAL FREQUENCY (MHz)
(CL1 = CL2 = 12 pF) (CL1 = CL2 = 24 pF)
10 55 110
12 50 95
14 50 90
16 45 75
18 45 65
20 45 50

7.11.3.4.2 Crystal Oscillator Electrical Characteristics

over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
f = 20 MHz
ESR MAX = 50 Ω
Start-up time(1) 2 ms
CL1 = CL2 = 24 pF
C0 = 7 pF
Crystal drive level (DL) 1 mW

(1) Start-up time is dependent on the crystal and tank circuit components. TI recommends that the crystal vendor characterize the
application with the chosen crystal.

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7.11.3.5 Internal Oscillators

To reduce production board costs and application development time, all F28002x devices contain two
independent internal oscillators, referred to as INTOSC1 and INTOSC2. By default, INTOSC2 is set as the
source for the system reference clock (OSCCLK) and INTOSC1 is set as the backup clock source.
Applications requiring tighter clock tolerance can use the SCI baud tuning example available in C2000Ware
(C2000Ware_3_03_00_00\driverlib\f28002x\examples\sci\baud_tune_via_uart) to enable baud matching better
than 1% accuracy.
Section 7.11.3.5.1 provides the electrical characteristics of the internal oscillators.
7.11.3.5.1 INTOSC Characteristics
over recommended operating conditions (unless otherwise noted)
TEST
PARAMETER MIN TYP MAX UNIT
CONDITIONS

Frequency, INTOSC1 and -40°C to 125°C 9.8 (–2.0%) 10 10.15 (1.5%) MHz
fINTOSC
INTOSC2 -30°C to 90°C 9.85 (–1.5%) 10 10.15 (1.5%) MHz
30°C, Nominal
fINTOSC-STABILITY Frequency stability ±0.1 %
VDDIO
tINT0SC-ST Start-up and settling time 20 µs

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7.11.4 Flash Parameters

Table 7-4 lists the minimum required Flash wait states with different clock sources and frequencies. Wait state is
the value set in register FRDCNTL[RWAIT].
Table 7-4. Minimum Required Flash Wait States with Different Clock Sources and Frequencies
EXTERNAL OSCILLATOR OR CRYSTAL INTOSC1 OR INTOSC2
CPUCLK (MHz) BANK OR PUMP BANK OR PUMP
NORMAL OPERATION NORMAL OPERATION
SLEEP(1) SLEEP(1)
97 < CPUCLK ≤ 100 5
4 4
80 < CPUCLK ≤ 97 4
77 < CPUCLK ≤ 80 4
3 3
60 < CPUCLK ≤ 77 3
58 < CPUCLK ≤ 60 3
2 2
40 < CPUCLK ≤ 58 2
38 < CPUCLK ≤ 40 2
1 1
20 < CPUCLK ≤ 38 1
19 < CPUCLK ≤ 20 1
0 0
CPUCLK ≤ 19 0

(1) Flash SLEEP operations require an extra wait state when using INTOSC as the clock source for the frequency ranges indicated. Any
wait state FRDCNTL[RWAIT] change must be made before beginning a SLEEP mode operation. This setting impacts both flash banks.

The F28002x devices have an improved 128-bit prefetch buffer that provides high flash code execution efficiency
across wait states. Figure 7-15 and Figure 7-16 illustrate typical efficiency across wait-state settings compared to
previous-generation devices with a 64-bit prefetch buffer. Wait-state execution efficiency with a prefetch buffer
will depend on how many branches are present in application software. Two examples of linear code and if-then-
else code are provided.

100% 100%

95%
90%
90%
80%
Efficiency (%)

Efficiency (%)

85%
70% 80%

60% 75%

Flash with 64-Bit Prefetch 70% Flash with 64-Bit Prefetch

50% Flash with 128-Bit Prefetch
Flash with 128-Bit Prefetch
65%
40%
60%

30% 55%
0 1 2 3 4 5 0 1 2 3 4 5
Wait State D005 Wait State D006

Figure 7-15. Application Code With Heavy 32-Bit Figure 7-16. Application Code With 16-Bit If-Else
Floating-Point Math Instructions Instructions

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Table 7-5 lists the Flash parameters.

Table 7-5. Flash Parameters
PARAMETER MIN TYP MAX UNIT
128 data bits + 16 ECC bits 150 300 µs
Program Time(1)
8KB sector 50 100 ms
EraseTime(2) (3) at < 25 cycles 8KB sector 15 100 ms
EraseTime(2) (3) at 1000 cycles 8KB sector 25 350 ms
EraseTime(2) (3) at 2000 cycles 8KB sector 30 600 ms
EraseTime(2) (3) at 20K cycles 8KB sector 120 4000 ms
Nwec Write/Erase Cycles per sector 20000 cycles
Nwec Write/Erase Cycles for entire Flash (combined all
100000 cycles
sectors)
tretention Data retention duration at TJ = 85oC 20 years

(1) Program time is at the maximum device frequency. Program time includes overhead of the flash state machine but does not include
the time to transfer the following into RAM:
• Code that uses flash API to program the flash
• Flash API itself
• Flash data to be programmed
In other words, the time indicated in this table is applicable after all the required code/data is available in the device RAM, ready for
programming. The transfer time will significantly vary depending on the speed of the JTAG debug probe used.
Program time calculation is based on programming 144 bits at a time at the specified operating frequency. Program time includes
Program verify by the CPU. The program time does not degrade with write/erase (W/E) cycling, but the erase time does.
Erase time includes Erase verify by the CPU and does not involve any data transfer.
(2) Erase time includes Erase verify by the CPU.
(3) The on-chip flash memory is in an erased state when the device is shipped from TI. As such, erasing the flash memory is not required
prior to programming, when programming the device for the first time. However, the erase operation is needed on all subsequent
programming operations.

Note
The Main Array flash programming must be aligned to 64-bit address boundaries and each 64-bit
word may only be programmed once per write/erase cycle.
The DCSM OTP programming must be aligned to 128-bit address boundaries and each 128-bit word
may only be programmed once. The exceptions are:
1. The DCSM Zx-LINKPOINTER1 and Zx-LINKPOINTER2 values in the DCSM OTP should be
programmed together, and may be programmed 1 bit at a time as required by the DCSM operation.
2. The DCSM Zx-LINKPOINTER3 values in the DCSM OTP may be programmed 1 bit at a time on a
64-bit boundary to separate it from Zx-PSWDLOCK, which must only be programmed once.

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7.11.5 Emulation/JTAG
The JTAG (IEEE Standard 1149.1-1990 Standard Test Access Port and Boundary Scan Architecture) port has
four dedicated pins: TMS, TDI, TDO, and TCK. The cJTAG (IEEE Standard 1149.7-2009 for Reduced-Pin and
Enhanced-Functionality Test Access Port and Boundary-Scan Architecture) port is a compact JTAG interface
requiring only two pins (TMS and TCK), which allows other device functionality to be muxed to the traditional
GPIO35 (TDI) and GPIO37 (TDO) pins.
Typically, no buffers are needed on the JTAG signals when the distance between the MCU target and the JTAG
header is smaller than 6 inches (15.24 cm), and no other devices are present on the JTAG chain. Otherwise,
each signal should be buffered. Additionally, for most JTAG debug probe operations at 10 MHz, no series
resistors are needed on the JTAG signals. However, if high emulation speeds are expected (35 MHz or so), 22-Ω
resistors should be placed in series on each JTAG signal.
The PD (Power Detect) terminal of the JTAG debug probe header should be connected to the board's 3.3-V
supply. Header GND terminals should be connected to board ground. TDIS (Cable Disconnect Sense) should
also be connected to board ground. The JTAG clock should be looped from the header TCK output terminal back
to the RTCK input terminal of the header (to sense clock continuity by the JTAG debug probe). This MCU does
not support the EMU0 and EMU1 signals that are present on 14-pin and 20-pin emulation headers. These
signals should always be pulled up at the emulation header through a pair of board pullup resistors ranging from
2.2 kΩ to 4.7 kΩ (depending on the drive strength of the debugger ports). Typically, a 2.2-kΩ value is used.
Header terminal RESET is an open-drain output from the JTAG debug probe header that enables board
components to be reset through JTAG debug probe commands (available only through the 20-pin header).
Figure 7-17 shows how the 14-pin JTAG header connects to the MCU’s JTAG port signals. Figure 7-18 shows
how to connect to the 20-pin JTAG header. The 20-pin JTAG header terminals EMU2, EMU3, and EMU4 are not
used and should be grounded.
For more information about hardware breakpoints and watchpoints, see Hardware Breakpoints and Watchpoints
for C28x in CCS.
For more information about JTAG emulation, see the XDS Target Connection Guide.

Note
JTAG Test Data Input (TDI) is the default mux selection for the pin. The internal pullup is disabled by
default. If this pin is used as JTAG TDI, the internal pullup should be enabled or an external pullup
added on the board to avoid a floating input. In the cJTAG option, this pin can be used as GPIO.
JTAG Test Data Output (TDO) is the default mux selection for the pin. The internal pullup is disabled
by default. The TDO function will be in a tri-state condition when there is no JTAG activity, leaving this
pin floating. The internal pullup should be enabled or an external pullup added on the board to avoid a
floating GPIO input. In the cJTAG option, this pin can be used as GPIO.

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Distance between the header and the target

should be less than 6 inches (15.24 cm).
3.3 V

4.7 kΩ
1 2
TMS TMS TRST
3.3 V

10 kΩ
(A) 3 4
TDI TDI TDIS GND
MCU 3.3 V 100 Ω
5 6
3.3 V PD KEY
10 kΩ
(A) 7 8
TDO TDO GND
9 RTCK GND 10

TCK 11 TCK GND 12

4.7 kΩ 4.7 kΩ
13 14
3.3 V EMU0 EMU1 3.3 V

A. TDI and TDO connections are not required for cJTAG option and these pins can be used as GPIOs instead.

Figure 7-17. Connecting to the 14-Pin JTAG Header

Distance between the header and the target

should be less than 6 inches (15.24 cm).

3.3 V

4.7 kΩ
1 2
TMS TMS TRST
3.3 V

10 kΩ
(A) 3 4
MCU TDI TDI TDIS GND
3.3 V 100 Ω
3.3V 5 PD 6
KEY
10 kΩ
(A) 7 8
TDO TDO GND
9 10
RTCK GND
11 12
TCK TCK GND
4.7 kΩ 4.7 kΩ
13 14
3.3 V EMU0 EMU1 3.3 V
15 16
RESET GND
Open
Drain 17 18
EMU2 EMU3

A low pulse from the JTAG debug probe 19 20

EMU4 GND
can be tied with other reset sources
to reset the board. GND GND
A. TDI and TDO connections are not required for cJTAG option and these pins can be used as GPIOs instead.

Figure 7-18. Connecting to the 20-Pin JTAG Header

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7.11.5.1 JTAG Electrical Data and Timing

Section 7.11.5.1.1 lists the JTAG timing requirements. Section 7.11.5.1.2 lists the JTAG switching characteristics.
Figure 7-19 shows the JTAG timing.
7.11.5.1.1 JTAG Timing Requirements
NO. MIN MAX UNIT
1 tc(TCK) Cycle time, TCK 66.66 ns
1a tw(TCKH) Pulse duration, TCK high (40% of tc) 26.66 ns
1b tw(TCKL) Pulse duration, TCK low (40% of tc) 26.66 ns
tsu(TDI-TCKH) Input setup time, TDI valid to TCK high 13
3 ns
tsu(TMS-TCKH) Input setup time, TMS valid to TCK high 13
th(TCKH-TDI) Input hold time, TDI valid from TCK high 7
4 ns
th(TCKH-TMS) Input hold time, TMS valid from TCK high 7

7.11.5.1.2 JTAG Switching Characteristics

over recommended operating conditions (unless otherwise noted)
NO. PARAMETER MIN MAX UNIT
2 td(TCKL-TDO) Delay time, TCK low to TDO valid 6 25 ns

7.11.5.1.3 JTAG Timing Diagram

1
1a 1b

TCK

TDO

3 4

TDI/TMS

Figure 7-19. JTAG Timing

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7.11.5.2 cJTAG Electrical Data and Timing

Section 7.11.5.2.1 lists the cJTAG timing requirements. Section 7.11.5.2.2 lists the cJTAG switching
characteristics. Figure 7-20 shows the cJTAG timing.
7.11.5.2.1 cJTAG Timing Requirements
NO. MIN MAX UNIT
1 tc(TCK) Cycle time, TCK 100 ns
1a tw(TCKH) Pulse duration, TCK high (40% of tc) 40 ns
1b tw(TCKL) Pulse duration, TCK low (40% of tc) 40 ns
tsu(TMS-TCKH) Input setup time, TMS valid to TCK high 15 ns
3
tsu(TMS-TCKL) Input setup time, TMS valid to TCK low 15 ns
th(TCKH-TMS) Input hold time, TMS valid from TCK high 2 ns
4
th(TCKL-TMS) Input hold time, TMS valid from TCK low 2 ns

7.11.5.2.2 cJTAG Switching Characteristics

over recommended operating conditions (unless otherwise noted)
NO. PARAMETER MIN MAX UNIT
2 td(TCKL-TMS) Delay time, TCK low to TMS valid 6 20 ns
5 tdis(TCKH-TMS) Delay time, TCK high to TMS disable 20 ns

7.11.5.2.3 cJTAG Timing Diagram

1
1a 1b
2
3 4 3 4 5
TCK

TMS TMS Input TMS Input TMS Output

Figure 7-20. cJTAG Timing

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7.11.6 GPIO Electrical Data and Timing

The peripheral signals are multiplexed with general-purpose input/output (GPIO) signals. On reset, GPIO pins
are configured as inputs. For specific inputs, the user can also select the number of input qualification cycles to
filter unwanted noise glitches.
The GPIO module contains an Output X-BAR which allows an assortment of internal signals to be routed to a
GPIO in the GPIO mux positions denoted as OUTPUTXBARx. The GPIO module also contains an Input X-BAR
which is used to route signals from any GPIO input to different IP blocks such as the ADCs, eCAPs, ePWMs,
and external interrupts. For more details, see the X-BAR chapter in the TMS320F28002x Real-Time
Microcontrollers Technical Reference Manual.
7.11.6.1 GPIO – Output Timing
Section 7.11.6.1.1 lists the general-purpose output switching characteristics. Figure 7-21 shows the general-
purpose output timing.
7.11.6.1.1 General-Purpose Output Switching Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER MIN MAX UNIT
tr(GPIO) Rise time, GPIO switching low to high All GPIOs 8(1) ns
tf(GPIO) Fall time, GPIO switching high to low All GPIOs 8(1) ns
fGPIO Toggling frequency, all GPIOs 25 MHz

(1) Rise time and fall time vary with load. These values assume a 40-pF load.

GPIO

tr(GPIO)
tf(GPIO)

Figure 7-21. General-Purpose Output Timing

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7.11.6.2 GPIO – Input Timing

Section 7.11.6.2.1 lists the general-purpose input timing requirements. Figure 7-22 shows the sampling mode.
7.11.6.2.1 General-Purpose Input Timing Requirements

MIN MAX UNIT

QUALPRD = 0 1tc(SYSCLK)
tw(SP) Sampling period cycles
QUALPRD ≠ 0 2tc(SYSCLK) * QUALPRD
tw(IQSW) Input qualifier sampling window tw(SP) * (n(1) – 1) cycles
Synchronous mode 2tc(SYSCLK)
tw(GPI) (2) Pulse duration, GPIO low/high cycles
With input qualifier tw(IQSW) + tw(SP) + 1tc(SYSCLK)

(1) "n" represents the number of qualification samples as defined by GPxQSELn register.
(2) For tw(GPI), pulse width is measured from VIL to VIL for an active low signal and VIH to VIH for an active high signal.

7.11.6.2.2 Sampling Mode

(A)
GPIO Signal GPxQSELn = 1,0 (6 samples)

1 1 0 0 0 0 0 0 0 1 0 0 0 1 1 1 1 1 1 1 1 1

tw(SP) Sampling Period determined

(B)
by GPxCTRL[QUALPRD]
tw(IQSW)
(C)
Sampling Window (SYSCLK cycle * 2 * QUALPRD) * 5

SYSCLK

QUALPRD = 1
(SYSCLK/2)
(D)
Output From
Qualifier
A. This glitch will be ignored by the input qualifier. The QUALPRD bit field specifies the qualification sampling period. It can vary from 00 to
0xFF. If QUALPRD = 00, then the sampling period is 1 SYSCLK cycle. For any other value "n", the qualification sampling period in 2n
SYSCLK cycles (that is, at every 2n SYSCLK cycles, the GPIO pin will be sampled).
B. The qualification period selected through the GPxCTRL register applies to groups of eight GPIO pins.
C. The qualification block can take either three or six samples. The GPxQSELn Register selects which sample mode is used.
D. In the example shown, for the qualifier to detect the change, the input should be stable for 10 SYSCLK cycles or greater. In other words,
the inputs should be stable for (5 × QUALPRD × 2) SYSCLK cycles. This would ensure 5 sampling periods for detection to occur.
Because external signals are driven asynchronously, an 13-SYSCLK-wide pulse ensures reliable recognition.

Figure 7-22. Sampling Mode

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7.11.6.3 Sampling Window Width for Input Signals

The following section summarizes the sampling window width for input signals for various input qualifier
configurations.
Sampling frequency denotes how often a signal is sampled with respect to SYSCLK.
Sampling frequency = SYSCLK/(2 × QUALPRD), if QUALPRD ≠ 0
Sampling frequency = SYSCLK, if QUALPRD = 0
Sampling period = SYSCLK cycle × 2 × QUALPRD, if QUALPRD ≠ 0
In the previous equations, SYSCLK cycle indicates the time period of SYSCLK.
Sampling period = SYSCLK cycle, if QUALPRD = 0
In a given sampling window, either 3 or 6 samples of the input signal are taken to determine the validity of the
signal. This is determined by the value written to GPxQSELn register.
Case 1:
Qualification using 3 samples
Sampling window width = (SYSCLK cycle × 2 × QUALPRD) × 2, if QUALPRD ≠ 0
Sampling window width = (SYSCLK cycle) × 2, if QUALPRD = 0
Case 2:
Qualification using 6 samples
Sampling window width = (SYSCLK cycle × 2 × QUALPRD) × 5, if QUALPRD ≠ 0
Sampling window width = (SYSCLK cycle) × 5, if QUALPRD = 0
Figure 7-23 shows the general-purpose input timing.

SYSCLK

GPIOxn

tw(GPI)

Figure 7-23. General-Purpose Input Timing

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7.11.7 Interrupts
The C28x CPU has fourteen peripheral interrupt lines. Two of them (INT13 and INT14) are connected directly to
CPU timers 1 and 2, respectively. The remaining twelve are connected to peripheral interrupt signals through the
enhanced Peripheral Interrupt Expansion (ePIE) module. The ePIE multiplexes up to sixteen peripheral
interrupts into each CPU interrupt line. It also expands the vector table to allow each interrupt to have its own
ISR. This allows the CPU to support a large number of peripherals.
An interrupt path is divided into three stages—the peripheral, the ePIE, and the CPU. Each stage has its own
enable and flag registers. This system allows the CPU to handle one interrupt while others are pending,
implement and prioritize nested interrupts in software, and disable interrupts during certain critical tasks.
Figure 7-24 shows the interrupt architecture for this device.
TINT0
TIMER0

LPM Logic LPMINT WAKEINT

WDINT NMI module NMI
WD
ERAD RTOSINT
INPUTXBAR4 XINT1 Control CPU
GPIO0 INPUTXBAR5 XINT2 Control ePIE INT1
Input
to INPUTXBAR6 XINT3 Control to
X-BAR
GPIOx INPUTXBAR13 XINT4 Control INT12
INPUTXBAR14 XINT5 Control

TIMER1 INT13

Peripherals TIMER2 INT14

See ePIE Table

Figure 7-24. Device Interrupt Architecture

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7.11.7.1 External Interrupt (XINT) Electrical Data and Timing

Section 7.11.7.1.1 lists the external interrupt timing requirements. Section 7.11.7.1.2 lists the external interrupt
switching characteristics. Figure 7-25 shows the external interrupt timing. For an explanation of the input qualifier
parameters, see Section 7.11.6.2.1.
7.11.7.1.1 External Interrupt Timing Requirements

MIN MAX UNIT

Synchronous 2tc(SYSCLK)
tw(INT) Pulse duration, INT input low/high cycles
With qualifier tw(IQSW) + tw(SP) + 1tc(SYSCLK)

7.11.7.1.2 External Interrupt Switching Characteristics

over recommended operating conditions (unless otherwise noted)
PARAMETER MIN MAX UNIT
td(INT) Delay time, INT low/high to interrupt-vector fetch(1) tw(IQSW) + 14tc(SYSCLK) tw(IQSW) + tw(SP) + 14tc(SYSCLK) cycles

(1) This assumes that the ISR is in a single-cycle memory.

7.11.7.1.3 External Interrupt Timing

tw(INT)
XINT1, XINT2, XINT3,
XINT4, XINT5

td(INT)

Address bus
Interrupt Vector
(internal)

Figure 7-25. External Interrupt Timing

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7.11.8 Low-Power Modes

This device has HALT, IDLE and STANDBY as clock-gating low-power modes.
Further details, as well as the entry and exit procedure, for all of the low-power modes can be found in the Low
Power Modes section of the TMS320F28002x Real-Time Microcontrollers Technical Reference Manual.
7.11.8.1 Clock-Gating Low-Power Modes
IDLE and HALT modes on this device are similar to those on other C28x devices. Table 7-6 describes the effect
on the system when any of the clock-gating low-power modes are entered.
Table 7-6. Effect of Clock-Gating Low-Power Modes on the Device
MODULES/
IDLE STANDBY HALT
CLOCK DOMAIN
SYSCLK Active Gated Gated
CPUCLK Gated Gated Gated
Clock to modules connected Active Gated Gated
to PERx.SYSCLK
WDCLK Active Active Gated if CLKSRCCTL1.WDHALTI = 0
PLL Powered Powered Software must power down PLL before entering HALT.
INTOSC1 Powered Powered Powered down if CLKSRCCTL1.WDHALTI = 0
INTOSC2 Powered Powered Powered down if CLKSRCCTL1.WDHALTI = 0
Flash(1) Powered Powered Powered
XTAL(2) Powered Powered Powered

(1) The Flash module is not powered down by hardware in any LPM. It may be powered down using software if required by the
application. For more information, see the Flash and OTP Memory section of the System Control chapter in the TMS320F28002x Real-
Time Microcontrollers Technical Reference Manual.
(2) The XTAL is not powered down by hardware in any LPM. It may be powered down by software setting the XTALCR.OSCOFF bit to 1.
This can be done at any time during the application if the XTAL is not required.

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7.11.8.2 Low-Power Mode Wake-up Timing

Section 7.11.8.2.1 lists the IDLE mode timing requirements, Section 7.11.8.2.2 lists the IDLE mode switching
characteristics, and Figure 7-26 shows the timing diagram for IDLE mode. For an explanation of the input
qualifier parameters, see Section 7.11.6.2.1.
7.11.8.2.1 IDLE Mode Timing Requirements
MIN MAX UNIT
Without input qualifier 2tc(SYSCLK)
tw(WAKE) Pulse duration, external wake-up signal cycles
With input qualifier 2tc(SYSCLK) + tw(IQSW)

7.11.8.2.2 IDLE Mode Switching Characteristics

over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN MAX UNIT

From Flash (active Without input qualifier 40tc(SYSCLK) cycles

state) With input qualifier 40tc(SYSCLK) + tw(WAKE) cycles
Without input qualifier 6700tc(SYSCLK) (2) cycles
Delay time, external wake signal to From Flash (sleep
td(WAKE-IDLE) 6700tc(SYSCLK) (2) +
program execution resume(1) state) With input qualifier cycles
tw(WAKE)
Without input qualifier 25tc(SYSCLK) cycles
From RAM
With input qualifier 25tc(SYSCLK) + tw(WAKE) cycles

(1) This is the time taken to begin execution of the instruction that immediately follows the IDLE instruction. Execution of an ISR (triggered
by the wake-up signal) involves additional latency.
(2) This value is based on the flash power-up time, which is a function of the SYSCLK frequency, flash wait states (RWAIT), and
FPAC1[PSLEEP]. This value can be realized when SYSCLK is 200 MHz, RWAIT is 3, and FPAC1[PSLEEP] is 0x860.

7.11.8.2.3 IDLE Entry and Exit Timing Diagram

td(WAKE-IDLE)
Address/Data
(internal)

XCLKOUT

tw(WAKE)
(A)
WAKE
A. WAKE can be any enabled interrupt, WDINT or XRSn. After the IDLE instruction is executed, a delay of five OSCCLK cycles (minimum)
is needed before the wake-up signal could be asserted.

Figure 7-26. IDLE Entry and Exit Timing Diagram

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Section 7.11.8.2.4 lists the STANDBY mode timing requirements, Section 7.11.8.2.5 lists the STANDBY mode
switching characteristics, and Figure 7-27 shows the timing diagram for STANDBY mode.
7.11.8.2.4 STANDBY Mode Timing Requirements
MIN MAX UNIT
QUALSTDBY = 0 | 2tc(OSCCLK) 3tc(OSCCLK)
Pulse duration, external
tw(WAKE-INT) QUALSTDBY > 0 | cycles
wake-up signal (2 + QUALSTDBY) * tc(OSCCLK)
(2 + QUALSTDBY)tc(OSCCLK) (1)

(1) QUALSTDBY is a 6-bit field in the LPMCR register.

7.11.8.2.5 STANDBY Mode Switching Characteristics

over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN MAX UNIT
Delay time, IDLE instruction executed to
td(IDLE-XCOS) 16tc(INTOSC1) cycles
XCLKOUT stop
Wakeup from flash
td(WAKE-STBY) (Flash module in 175tc(SYSCLK) + tw(WAKE-INT) cycles
active state)
Delay time, external wake signal to program
Wakeup from flash
execution resume(1)
td(WAKE-STBY) (Flash module in 6700tc(SYSCLK) (2) + tw(WAKE-INT) cycles
sleep state)
td(WAKE-STBY) Wakeup from RAM 3tc(OSC) + 15tc(SYSCLK) + tw(WAKE-INT) cycles

7.11.8.2.6 STANDBY Entry and Exit Timing Diagram

(A) (C) (F)
(B) (D)(E) (G)

Device STANDBY STANDBY Normal Execution

Status
Flushing Pipeline

Wake-up
Signal

tw(WAKE-INT)

td(WAKE-STBY)

OSCCLK

XCLKOUT

td(IDLE-XCOS)

A. IDLE instruction is executed to put the device into STANDBY mode.

B. The LPM block responds to the STANDBY signal, SYSCLK is held for a maximum 16 INTOSC1 clock cycles before being turned off.
This delay enables the CPU pipeline and any other pending operations to flush properly.
C. Clock to the peripherals are turned off. However, the PLL and watchdog are not shut down. The device is now in STANDBY mode. After
the IDLE instruction is executed, a delay of five OSCCLK cycles (minimum) is needed before the wake-up signal could be asserted.
D. The external wake-up signal is driven active.
E. The wake-up signal fed to a GPIO pin to wake up the device must meet the minimum pulse width requirement. Furthermore, this signal
must be free of glitches. If a noisy signal is fed to a GPIO pin, the wakeup behavior of the device will not be deterministic and the device
may not exit low-power mode for subsequent wakeup pulses.
F. After a latency period, the STANDBY mode is exited.
G. Normal execution resumes. The device will respond to the interrupt (if enabled).

Figure 7-27. STANDBY Entry and Exit Timing Diagram

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Section 7.11.8.2.7 lists the HALT mode timing requirements, Section 7.11.8.2.8 lists the HALT mode switching
characteristics, and Figure 7-28 shows the timing diagram for HALT mode.
7.11.8.2.7 HALT Mode Timing Requirements
MIN MAX UNIT
tw(WAKE-GPIO) Pulse duration, GPIO wake-up signal(1) toscst + 2tc(OSCCLK) cycles
tw(WAKE-XRS) Pulse duration, XRS wake-up signal(1) toscst + 8tc(OSCCLK) cycles

(1) For applications using X1/X2 for OSCCLK, the user must characterize their specific oscillator start-up time as it is dependent on circuit/
layout external to the device. See Crystal Oscillator Electrical Characteristics table for more information. For applications using
INTOSC1 or INTOSC2 for OSCCLK, see Internal Oscillators section for toscst. Oscillator start-up time does not apply to applications
using a single-ended crystal on the X1 pin, as it is powered externally to the device.

7.11.8.2.8 HALT Mode Switching Characteristics

over recommended operating conditions (unless otherwise noted)
PARAMETER MIN MAX UNIT
Delay time, IDLE instruction executed to XCLKOUT
td(IDLE-XCOS) 16tc(INTOSC1) cycles
stop
Delay time, external wake signal end to CPU1 program
execution resume

td(WAKE-HALT) Wakeup from Flash - Flash module in active state 75tc(OSCCLK) cycles
Wakeup from Flash - Flash module in sleep state 17500tc(OSCCLK) (1)
Wakeup from RAM 75tc(OSCCLK)

(1) This value is based on the flash power-up time, which is a function of the SYSCLK frequency, flash wait states (RWAIT), and
FPAC1[PSLEEP]. This value can be realized when SYSCLK is 200 MHz, RWAIT is 3, and FPAC1[PSLEEP] is 0x860.

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7.11.8.2.9 HALT Entry and Exit Timing Diagram

(A) (C) (F)
(B) (D)(E) (G)

Device
HALT HALT
Status

Flushing Pipeline Normal

Execution

GPIOn

td(WAKE-HALT)
tw(WAKE-GPIO)

OSCCLK

Oscillator Start-up Time

XCLKOUT

td(IDLE-XCOS)

A. IDLE instruction is executed to put the device into HALT mode.

B. The LPM block responds to the HALT signal, SYSCLK is held for a maximum 16 INTOSC1 clock cycles before being turned off. This
delay enables the CPU pipeline and any other pending operations to flush properly.
C. Clocks to the peripherals are turned off and the PLL is shut down. If a quartz crystal or ceramic resonator is used as the clock source,
the internal oscillator is shut down as well. The device is now in HALT mode and consumes very little power. It is possible to keep the
zero-pin internal oscillators (INTOSC1 and INTOSC2) and the watchdog alive in HALT MODE. This is done by writing 1 to
CLKSRCCTL1.WDHALTI. After the IDLE instruction is executed, a delay of five OSCCLK cycles (minimum) is needed before the wake-
up signal could be asserted.
D. When the GPIOn pin (used to bring the device out of HALT) is driven low, the oscillator is turned on and the oscillator wake-up sequence
is initiated. The GPIO pin should be driven high only after the oscillator has stabilized. This enables the provision of a clean clock signal
during the PLL lock sequence. Because the falling edge of the GPIO pin asynchronously begins the wake-up procedure, care should be
taken to maintain a low noise environment before entering and during HALT mode.
E. The wake-up signal fed to a GPIO pin to wake up the device must meet the minimum pulse width requirement. Furthermore, this signal
must be free of glitches. If a noisy signal is fed to a GPIO pin, the wake-up behavior of the device will not be deterministic and the device
may not exit low-power mode for subsequent wake-up pulses.
F. When CLKIN to the core is enabled, the device will respond to the interrupt (if enabled), after some latency. The HALT mode is now
exited.
G. Normal operation resumes.
H. The user must relock the PLL upon HALT wakeup to ensure a stable PLL lock.

Figure 7-28. HALT Entry and Exit Timing Diagram

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7.12 Analog Peripherals

The analog subsystem module is described in this section.
The analog modules on this device include the ADC, temperature sensor, and CMPSS.
The analog subsystem has the following features:
• Flexible voltage references
– The ADCs are referenced to VREFHI and VSSA pins
• VREFHI pin voltage can be driven in externally or can be generated by an internal bandgap voltage
reference
• The internal voltage reference range can be selected to be 0V to 3.3V or 0V to 2.5V
– The comparator DACs are referenced to VDDA and VSSA
• Alternately, these DACs can be referenced to the VDAC pin and VSSA
• Flexible pin usage
– Comparator subsystem inputs and digital inputs are multiplexed with ADC inputs
– Internal connection to VREFLO on all ADCs for offset self-calibration
Figure 7-29 shows the Analog Subsystem Block Diagram for the 80-pin PN and 64-pin PM LQFPs.
Figure 7-30 shows the Analog Subsystem Block Diagram for the 48-pin PT LQFP.
Table 7-7 lists the analog pins and internal connections. Table 7-8 lists descriptions of analog signals.Figure 7-31
shows the analog group connections.

Figure 7-29. Analog Subsystem Block Diagram (80-Pin PN and 64-Pin PM LQFPs)

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Figure 7-30. Analog Subsystem Block Diagram (48-Pin PT LQFP)

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CMPSSx Input MUX

CMPxHPMX
CMPx_HP0
0
CMPx_HP1
1
CMPx_HP2
2 CMPx_HP
CMPx_HP3
3
CMPx_HP4
4

CMPxHNMX
CMPx_HN0 0

To CMPSSx
CMPx_HN1 CMPx_HN
1

CMPxLNMX
CMPx_LN0 0
CMPx_LN1 CMPx_LN
1

CMPxLPMX
CMPx_LP0
0
CMPx_LP1
1
CMPx_LP2
2 CMPx_LP
CMPx_LP3
3
CMPx_LP4
4

Gx_ADCA Gx_ADCA

AIO

To ADCs
Gx_ADCC Gx_ADCC

AIO

Figure 7-31. Analog Group Connections

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Analog Pins and Internal Connections

Table 7-7. Analog Pins and Internal Connections
Package Pin ADC Comparator Subsystem (MUX)
Pin Name High High Low Low AIO Input
80 QFP 64 QFP 48 QFN A C
Positive Negative Positive Negative
VREFHI 20 16 12
VREFLO 21 17 13 A13 C13
Analog Group 1 CMP1
A6 10 6 4(3) A6 - CMP1 (HPMXSEL=2) CMP1 (LPMXSEL=2) AIO228
A2/C9 13 9 6 A2 C9 CMP1 (HPMXSEL=0) CMP1 (LPMXSEL=0) AIO224
A15/C7 14 10 7 A15 C7 CMP1 (HPMXSEL=3) CMP1 (HNMXSEL=0) CMP1 (LPMXSEL=3) CMP1 (LNMXSEL=0) AIO233
A11/C0 16 12 8 A11 C0 CMP1 (HPMXSEL=1) CMP1 (HNMXSEL=1) CMP1 (LPMXSEL=1) CMP1 (LNMXSEL=1) AIO237
A1 18 14 10 A1 - CMP1 (HPMXSEL=4) CMP1 (LPMXSEL=4) AIO232
Analog Group 2 CMP2
A10/C10 29 25 21 A10 C10 CMP2 (HPMXSEL=3) CMP2 (HNMXSEL=0) CMP2 (LPMXSEL=3) CMP2 (LNMXSEL=0) AIO230
Analog Group 3 CMP3
C6 11 7 4(3) - C6 CMP3 (HPMXSEL=0) CMP3 (LPMXSEL=0) AIO226
A3/C5/VDAC(1) 12 8 5 A3 C5 CMP3 (HPMXSEL=3) CMP3 (HNMXSEL=0) CMP3 (LPMXSEL=3) CMP3 (LNMXSEL=0) AIO242
A14/C4 15 11 - A14 C4 CMP3 (HPMXSEL=4) CMP3 (LPMXSEL=4) AIO239
A5/C2 17 13 9 A5 C2 CMP3 (HPMXSEL=1) CMP3 (HNMXSEL=1) CMP3 (LPMXSEL=1) CMP3 (LNMXSEL=1) AIO244
A0/C15 19 15 11 A0 C15 CMP3 (HPMXSEL=2) CMP3 (LPMXSEL=2) AIO231
Analog Group 4 CMP4
A7/C3 23 19 15 A7 C3 CMP4 (HPMXSEL=1) CMP4 (HNMXSEL=1) CMP4 (LPMXSEL=1) CMP4 (LNMXSEL=1) AIO245
Combined Analog Group 2/4 CMP2/4
CMP2 (HPMXSEL=1) CMP2 (LPMXSEL=1)
A12/C1 22 18 14 A12 C1 CMP2 (HNMXSEL=1) CMP2 (LNMXSEL=1) AIO238
CMP4 (HPMXSEL=2) CMP4 (LPMXSEL=2)
CMP2 (HPMXSEL=4) CMP2 (LPMXSEL=4)
A8/C11 24 20 16 A8 C11 AIO241
CMP4 (HPMXSEL=4) CMP4 (LPMXSEL=4)
CMP2 (HPMXSEL=0) CMP2 (LPMXSEL=0)
A4/C14 27 23 19 A4 C14 CMP4 (HNMXSEL=0) CMP4 (LNMXSEL=0) AIO225
CMP4 (HPMXSEL=3) CMP4 (LPMXSEL=3)
CMP2 (HPMXSEL=2) CMP2 (LPMXSEL=2)
A9/C8 28 24 20 A9 C8 AIO227
CMP4 (HPMXSEL=0) CMP4 (LPMXSEL=0)

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Table 7-7. Analog Pins and Internal Connections (continued)

Package Pin ADC Comparator Subsystem (MUX)
Pin Name High High Low Low AIO Input
80 QFP 64 QFP 48 QFN A C
Positive Negative Positive Negative
Other Analog
TempSensor(2) - - - - C12

(1) Optional external reference voltage for on-chip COMPDACs. There is an internal capacitance to VSSA on this pin whether used for ADC input or COMPDAC reference. If used as a
VDAC reference, place at least a 1-µF capacitor on this pin.
(2) Internal connection only; does not come to a device pin.
(3) A6 and C6 is double bonded as pin # 4.

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Analog Signal Descriptions

Table 7-8. Analog Signal Descriptions
SIGNAL NAME DESCRIPTION
AIOx Digital input on ADC pin
Ax ADC A Input
Cx ADC C Input
CMPx_HNy Comparator subsystem high comparator negative input
CMPx_HPy Comparator subsystem high comparator positive input
CMPx_LNy Comparator subsystem low comparator negative input
CMPx_LPy Comparator subsystem low comparator positive input
TempSensor Internal temperature sensor
Optional external reference voltage for on-chip COMPDACs. There is an internal capacitance to VSSA on this
VDAC pin whether used for ADC input or COMPDAC reference which cannot be disabled. If this pin is being used as
a reference for the on-chip COMPDACs, place at least a 1-uF capacitor on this pin.

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7.12.1 Analog-to-Digital Converter (ADC)

The ADC module described here is a successive approximation (SAR) style ADC with resolution of 12 bits. This
section refers to the analog circuits of the converter as the “core,” and includes the channel-select MUX, the
sample-and-hold (S/H) circuit, the successive approximation circuits, voltage reference circuits, and other analog
support circuits. The digital circuits of the converter are referred to as the “wrapper” and include logic for
programmable conversions, result registers, interfaces to analog circuits, interfaces to the peripheral buses,
post-processing circuits, and interfaces to other on-chip modules.
Each ADC module consists of a single sample-and-hold (S/H) circuit. The ADC module is designed to be
duplicated multiple times on the same chip, allowing simultaneous sampling or independent operation of multiple
ADCs. The ADC wrapper is start-of-conversion (SOC)-based (see the SOC Principle of Operation section of the
Analog-to-Digital Converter (ADC) chapter in the TMS320F28002x Real-Time Microcontrollers Technical
Reference Manual).
Each ADC has the following features:
• Resolution of 12 bits
• Ratiometric external reference set by VREFHI/VREFLO
• Selectable internal reference of 2.5 V or 3.3 V
• Single-ended signaling
• Input multiplexer with up to 16 channels
• 16 configurable SOCs
• 16 individually addressable result registers
• Multiple trigger sources
– S/W: software immediate start
– All ePWMs: ADCSOC A or B
– GPIO XINT2
– CPU Timers 0/1/2
– ADCINT1/2
• Four flexible PIE interrupts
• Burst-mode triggering option
• Four post-processing blocks, each with:
– Saturating offset calibration
– Error from setpoint calculation
– High, low, and zero-crossing compare, with interrupt and ePWM trip capability
– Trigger-to-sample delay capture

Note
Not every channel may be pinned out from all ADCs. See Section 6 to determine which channels are
available.

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The block diagram for the ADC core and ADC wrapper are shown in Figure 7-32.
Analog-to-Digital Core Analog-to-Digital Wrapper Logic

Input Circuit
SOCx (0-15)

TRIGSEL
Triggers
CHSEL [15:0]

SOC Arbitration [15:0]

ACQPS
ADCIN0 0 & Control
ADCIN1 1 ADCSOC [15:0]
CHSEL
ADCIN2 2
ADCIN3 3

...
...
ADCIN4 4

SOCxSTART[15:0]
ADCIN5 5

EOCx[15:0]
ADCIN6 6 ADCCOUNTER TRIGGER[15:0]
xV
1
IN+
ADCIN7 7 u
ADCIN8 8 DOUT1
xV
2
IN-
ADCIN9 9
ADCIN10 10
ADCIN11 11 SOC Delay Trigger
ADCIN12 12 Timestamp Timestamp
S/H Circuit Converter
ADCIN13 13
ADCIN14 14
ADCIN15 15 RESULT + -
ADCPPBxOFFCAL

ADCRESULT
0±15 Regs
saturate

ADCPPBxOFFREF
+ -
ADCPPBxRESULT

VREFHI ADCEVT
CONFIG Event
Logic ADCEVTINT
Bandgap
Reference Circuit
1.65-V Output 1
Post Processing Block (1-4)
(3.3-V Range)
0
or
2.5-V Output
(2.5-V Range) Interrupt Block (1-4)
ADCINT1-4
VREFLO

Analog System Control

ANAREFSEL

ANAREFx2PSSEL

Reference Voltage Levels

Figure 7-32. ADC Module Block Diagram

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7.12.1.1 ADC Configurability

Some ADC configurations are individually controlled by the SOCs, while others are globally controlled per ADC
module. Table 7-9 summarizes the basic ADC options and their level of configurability.
Table 7-9. ADC Options and Configuration Levels
OPTIONS CONFIGURABILITY
Clock Per module(1)
Resolution Not configurable (12-bit resolution only)
Signal mode Not configurable (single-ended signal mode only)
Reference voltage source Common for both ADC modules
Trigger source Per SOC(1)
Converted channel Per SOC
Acquisition window duration Per SOC(1)
EOC location Per module
Burst mode Per module(1)

(1) Writing these values differently to different ADC modules could cause the ADCs to operate
asynchronously. For guidance on when the ADCs are operating synchronously or asynchronously,
see the Ensuring Synchronous Operation section of the Analog-to-Digital Converter (ADC) chapter
in the TMS320F28002x Real-Time Microcontrollers Technical Reference Manual.

7.12.1.1.1 Signal Mode

The ADC supports single-ended signaling. The input voltage to the converter is sampled through a single pin
(ADCINx), referenced to VREFLO. Figure 7-33 shows the single-ended signaling mode.

Pin Voltage
VREFHI
VREFHI

ADCINx ADCINx

VREFHI/2 ADC

VREFLO
VREFLO
(VSSA)

Digital Output
2n - 1

ADC Vin

Figure 7-33. Single-ended Signaling Mode

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7.12.1.2 ADC Electrical Data and Timing

Section 7.12.1.2.1 lists the ADC operating conditions. Section 7.12.1.2.2 lists the ADC electrical characteristics.

Note
The ADC inputs should be kept below VDDA + 0.3 V during operation. If an ADC input exceeds this
level, the VREF internal to the device may be disturbed, which can impact results for other ADC inputs
using the same VREF.

Note
The VREFHI pin must be kept below VDDA + 0.3 V to ensure proper functional operation. If the
VREFHI pin exceeds this level, a blocking circuit may activate, and the internal value of VREFHI may
float to 0 V internally, giving improper ADC conversion.

7.12.1.2.1 ADC Operating Conditions

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ADCCLK (derived from PERx.SYSCLK) 5 50 MHz
Sample rate 100-MHz SYSCLK 3.45 MSPS
Sample window duration (set by ACQPS and
With 50 Ω or less Rs 75 ns
PERx.SYSCLK)(1)
VREFHI External Reference 2.4 2.5 or 3.0 VDDA V
Internal Reference = 3.3V Range 1.65 V
VREFHI(2)
Internal Reference = 2.5V Range 2.5 V
VREFLO VSSA VSSA V
VREFHI - VREFLO 2.4 VDDA V
Internal Reference = 3.3 V Range 0 3.3 V
Conversion range Internal Reference = 2.5 V Range 0 2.5 V
External Reference VREFLO VREFHI V

(1) The sample window must also be at least as long as 1 ADCCLK cycle for correct ADC operation.
(2) In internal reference mode, the reference voltage is driven out of the VREFHI pin by the device. The user should not drive a voltage
into the pin in this mode.

7.12.1.2.2 ADC Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
General
ADCCLK Conversion Cycles 100-MHz SYSCLK 10.1 11 ADCCLKs
External Reference mode 500 µs
Internal Reference mode 5000 µs
Power Up Time
Internal Reference mode, when switching between
5000 µs
2.5-V range and 3.3-V range.
VREFHI input current(1) 130 µA
Internal Reference Capacitor
2.2 µF
Value(2)
External Reference Capacitor
2.2 µF
Value(2)

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7.12.1.2.2 ADC Characteristics (continued)

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
DC Characteristics
Internal reference –45 45
Gain Error LSB
External reference –5 ±3 5
Offset Error –5 ±2 5 LSB
Channel-to-Channel Gain Error(4) 2 LSB
Channel-to-Channel Offset
2 LSB
Error(4)
ADC-to-ADC Gain Error(5) Identical VREFHI and VREFLO for all ADCs 4 LSB
ADC-to-ADC Offset Error(5) Identical VREFHI and VREFLO for all ADCs 2 LSB
DNL Error >–1 ±0.5 1 LSB
INL Error –2 ±1.0 2 LSB
ADC-to-ADC Isolation VREFHI = 2.5 V, synchronous ADCs –1 1 LSBs
AC Characteristics
VREFHI = 2.5 V, fin = 100 kHz, SYSCLK from X1 68.8
SNR(3) VREFHI = 2.5 V, fin = 100 kHz, SYSCLK from dB
60.1
INTOSC
THD(3) VREFHI = 2.5 V, fin = 100 kHz –80.6 dB
SFDR(3) VREFHI = 2.5 V, fin = 100 kHz 79.2 dB
VREFHI = 2.5 V, fin = 100 kHz, SYSCLK from X1 68.5
SINAD(3) VREFHI = 2.5 V, fin = 100 kHz, SYSCLK from dB
60.0
INTOSC
VREFHI = 2.5 V, fin = 100 kHz, SYSCLK from
11.0
X1, Single ADC
VREFHI = 2.5 V, fin = 100 kHz, SYSCLK from
ENOB(3) 11.0 bits
X1, synchronous ADCs
VREFHI = 2.5 V, fin = 100 kHz, SYSCLK from Not
X1, asynchronous ADCs Supported
VDD = 1.2-V DC + 100mV
60
DC up to Sine at 1 kHz
VDD = 1.2-V DC + 100 mV
57
DC up to Sine at 300 kHz
PSRR dB
VDDA = 3.3-V DC + 200 mV
60
DC up to Sine at 1 kHz
VDDA = 3.3-V DC + 200 mV
57
Sine at 900 kHz

(1) Load current on VREFHI increases when ADC input is greater than VDDA. This causes inaccurate conversions.
(2) A ceramic capacitor with package size of 0805 or smaller is preferred. Up to ±20% tolerance is acceptable.
(3) IO activity is minimized on pins adjacent to ADC input and VREFHI pins as part of best practices to reduce capacitive coupling and
crosstalk.
(4) Variation across all channels belonging to the same ADC module.
(5) Worst case variation compared to other ADC modules.

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7.12.1.2.3 ADC Input Model

The ADC input characteristics are given by Table 7-10 and Figure 7-34.
Table 7-10. Input Model Parameters
DESCRIPTION REFERENCE MODE VALUE
Cp Parasitic input capacitance All See Table 7-11
External Reference, 2.5-V Internal
500 Ω
Ron Sampling switch resistance Reference
3.3-V Internal Reference 860 Ω
External Reference, 2.5-V Internal
12.5 pF
Ch Sampling capacitor Reference
3.3-V Internal Reference 7.5 pF
Rs Nominal source impedance All 50 Ω

ADC
ADCINx
Rs
Switch Ron
AC Cp Ch

VREFLO

Figure 7-34. Input Model

This input model should be used with actual signal source impedance to determine the acquisition window
duration. For more information, see the Choosing an Acquisition Window Duration section of the Analog-to-
Digital Converter (ADC) chapter in the TMS320F28002x Real-Time Microcontrollers Technical Reference
Manual.
Table 7-11 lists the parasitic capacitance on each channel.
Table 7-11. Per-Channel Parasitic Capacitance
Cp (pF)
ADC CHANNEL
COMPARATOR DISABLED COMPARATOR ENABLED
ADCINA0/ADCINC15 3.3 15.8
ADCINA1 2.4 4.9
ADCINA2/ADCINC9 2.9 5.4
ADCINA3/ADCINC5(1) 71.4 73.9
ADCINA4/ADCINC14 4.5 7
ADCINA5/ADCINC2 2.7 5.2
ADCINA6 2.6 5.1
ADCINA7/ADCINC3 4.2 6.7
ADCINA8/ADCINC11 4.5 7
ADCINA9/ADCINC8 3.4 5.9
ADCINA10/ADCINC10 2.9 5.4
ADCINA11/ADCINC0 2.9 5.4
ADCINA12/ADCINC1 4.7 7.2
ADCINA14/ADCINC4 2.5 5
ADCINA15/ADCINC7 3.3 5.8
ADCINC6 2.9 5.4

(1) Pin also used to supply reference voltage for COMPDAC and includes an internal decoupling
capacitor.

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7.12.1.2.4 ADC Timing Diagrams

Figure 7-35 shows the ADC conversion timings for two SOCs given the following assumptions:
• SOC0 and SOC1 are configured to use the same trigger.
• No other SOCs are converting or pending when the trigger occurs.
• The round-robin pointer is in a state that causes SOC0 to convert first.
• ADCINTSEL is configured to set an ADCINT flag upon end of conversion for SOC0 (whether this flag
propagates through to the CPU to cause an interrupt is determined by the configurations in the PIE module).
Table 7-12 lists the descriptions of the ADC timing parameters. Table 7-13 lists the ADC timings.

Sample n
Input on SOC0.CHSEL

Input on SOC1.CHSEL
Sample n+1

ADC S+H SOC0 SOC1

SYSCLK

ADCCLK

ADCTRIG

ADCSOCFLG.SOC0

ADCSOCFLG.SOC1

ADCRESULT0 (old data) Sample n

ADCRESULT1 (old data) Sample n+1

ADCINTFLG.ADCINTx

tSH tLAT

tEOC

tINT

Figure 7-35. ADC Timings

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Table 7-12. ADC Timing Parameters

PARAMETER DESCRIPTION
The duration of the S+H window.

At the end of this window, the value on the S+H capacitor becomes the voltage to be converted into a digital
value. The duration is given by (ACQPS + 1) SYSCLK cycles. ACQPS can be configured individually for each
tSH
SOC, so tSH will not necessarily be the same for different SOCs.

Note: The value on the S+H capacitor will be captured approximately 5 ns before the end of the S+H window
regardless of device clock settings.
The time from the end of the S+H window until the ADC results latch in the ADCRESULTx register.
tLAT
If the ADCRESULTx register is read before this time, the previous conversion results will be returned.
The time from the end of the S+H window until the S+H window for the next ADC conversion can begin. The
tEOC
subsequent sample can start before the conversion results are latched.
The time from the end of the S+H window until an ADCINT flag is set (if configured).

If the INTPULSEPOS bit in the ADCCTL1 register is set, tINT will coincide with the conversion results being
latched into the result register.

If the INTPULSEPOS bit is 0, tINT will coincide with the end of the S+H window. If tINT triggers a read of the
tINT
ADC result register (directly through DMA or indirectly by triggering an ISR that reads the result), care must be
taken to ensure the read occurs after the results latch (otherwise, the previous results will be read).

If the INTPULSEPOS bit is 0, and the OFFSET field in the ADCINTCYCLE register is not 0, then there will be a
delay of OFFSET SYSCLK cycles before the ADCINT flag is set. This delay can be used to enter the ISR or
trigger the DMA at exactly the time the sample is ready.

Table 7-13. ADC Timings

ADCCLK PRESCALE SYSCLK CYCLES ADCCLK CYCLES
RATIO (1) (2)
ADCCTL2 [PRESCALE] tEOC tLAT tINT(EARLY) tINT(LATE) tEOC
ADCCLK:SYSCLK
0 1 11 13 1 11 11
2 2 21 23 1 21 10.5
4 3 31 34 1 31 10.3
6 4 41 44 1 41 10.3
8 5 51 55 1 51 10.2
10 6 61 65 1 61 10.2
12 7 71 76 1 71 10.1
14 8 81 86 1 81 10.1

(1) Refer to the "ADC: DMA Read of Stale Result" advisory in the TMS320F28002x Real-Time MCUs Silicon Errata.
(2) By default, tINT occurs one SYSCLK cycle after the S+H window if INTPULSEPOS is 0. This can be changed by writing to the OFFSET
field in the ADCINTCYCLE register.

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7.12.2 Temperature Sensor

7.12.2.1 Temperature Sensor Electrical Data and Timing
The temperature sensor can be used to measure the device junction temperature. The temperature sensor is
sampled through an internal connection to the ADC and translated into a temperature through TI-provided
software. When sampling the temperature sensor, the ADC must meet the acquisition time in Section 7.12.2.1.1.
7.12.2.1.1 Temperature Sensor Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Tacc Temperature Accuracy External reference ±15 °C
Start-up time
tstartup (TSNSCTL[ENABLE] to 500 µs
sampling temperature sensor)
tacq ADC acquisition time 450 ns

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7.12.3 Comparator Subsystem (CMPSS)

Each CMPSS contains two comparators, two reference 12-bit DACs, two digital filters, and one ramp generator.
Comparators are denoted "H" or "L" within each module, where “H” and “L” represent high and low, respectively.
Each comparator generates a digital output that indicates whether the voltage on the positive input is greater
than the voltage on the negative input. The positive input of the comparator can be driven from an external pin or
by the PGA . The negative input can be driven by an external pin or by the programmable reference 12-bit DAC.
Each comparator output passes through a programmable digital filter that can remove spurious trip signals. An
unfiltered output is also available if filtering is not required. A ramp generator circuit is optionally available to
control the reference 12-bit DAC value for the high comparator in the subsystem. There are two outputs from
each CMPSS module. These two outputs pass through the digital filters and crossbar before connecting to the
ePWM modules or GPIO pin. Figure 7-36 shows the CMPSS connectivity.

CMP1_ HP Comparator Subsystem 1 CTRIP1H

CMP1_HN Digital CTRIP1H
VDDA or VDAC Filter CTRIPOUT1H CTRIP1L

DAC12 CTRIP2H
DAC12
Digital CTRIP1L
CMP1_LN CTRIP2L
Filter CTRIPOUT1L
CMP1_LP
ePWM X- BAR ePWMs

CMP2_HP Comparator Subsystem 2

CMP2_HN Digital CTRIP2H
VDDA or VDAC Filter CTRIPOUT2H
DAC12 CTRIP4H
DAC12
Digital CTRIP2L
CMP2_LN CTRIP4L
Filter CTRIPOUT2L
CMP2_LP

CTRIPOUT1H

CTRIPOUT1L

CTRIPOUT2H
CMP4_ HP Comparator Subsystem 4
CTRIPOUT2L
CMP4_ HN Digital CTRIP4H
VDDA or VDAC Filter CTRIPOUT4H Output X- BAR GPIO Mux
DAC12
DAC12 Digital CTRIP4L
CMP4_LN
Filter CTRIPOUT4L
CMP4_ LP
CTRIPOUT4H

CTRIPOUT4L

Figure 7-36. CMPSS Connectivity

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7.12.3.1 CMPSS Electrical Data and Timing

Section 7.12.3.1.1 lists the comparator electrical characteristics. Figure 7-37 shows the CMPSS comparator
input referred offset. Figure 7-38 shows the CMPSS comparator hysteresis.
7.12.3.1.1 Comparator Electrical Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
TPU Power-up time 500 µs
Comparator input (CMPINxx) range 0 VDDA V
Low common mode, inverting
Input referred offset error –20 20 mV
input set to 50mV
1x 12
2x 24
Hysteresis(1) LSB
3x 36
4x 48
Step response 21 60
Response time (delay from CMPINx input ns
change to output on ePWM X-BAR or Output Ramp response (1.65V/µs) 26
X-BAR)
Ramp response (8.25mV/µs) 30 ns
PSRR Power Supply Rejection Ratio Up to 250 kHz 46 dB
Common Mode Rejection
CMRR 40 dB
Ratio

(1) The CMPSS DAC is used as the reference to determine how much hysteresis to apply. Therefore, hysteresis will scale with the
CMPSS DAC reference voltage. Hysteresis is available for all comparator input source configurations.

CMPSS Comparator Input Referred Offset and Hysteresis

Note
The CMPSS inputs must be kept below VDDA + 0.3 V to ensure proper functional operation. If a
CMPSS input exceeds this level, an internal blocking circuit isolates the internal comparator from the
external pin until the external pin voltage returns below VDDA + 0.3 V. During this time, the internal
comparator input is floating and can decay below VDDA within approximately 0.5 µs. After this time,
the comparator could begin to output an incorrect result depending on the value of the other
comparator input.

Input Referred Offset

CTRIPx
Logic Level CTRIPx = 1

CTRIPx = 0

COMPINxP
Voltage
0 CMPINxN or
DACxVAL

Figure 7-37. CMPSS Comparator Input Referred Offset

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Hysteresis

CTRIPx
Logic Level CTRIPx = 1

CTRIPx = 0

COMPINxP
Voltage
0 CMPINxN or
DACxVAL

Figure 7-38. CMPSS Comparator Hysteresis

Section 7.12.3.1.2 lists the CMPSS DAC static electrical characteristics.

7.12.3.1.2 CMPSS DAC Static Electrical Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Internal reference 0 VDDA
CMPSS DAC output range V
External reference 0 VDAC(4)
Static offset error(1) –25 25 mV
Static gain error(1) –2 2 % of FSR
Static DNL Endpoint corrected >–1 4 LSB
Static INL Endpoint corrected –16 16 LSB
Settling to 1LSB after full-scale output
Settling time 1 µs
change
Resolution 12 bits
Error induced by comparator trip or
CMPSS DAC output disturbance(2) CMPSS DAC code change within the –100 100 LSB
same CMPSS module
CMPSS DAC disturbance time(2) 200 ns
VDAC reference voltage When VDAC is reference 2.4 2.5 or 3.0 VDDA V
VDAC load(3) When VDAC is reference 6 8 10 kΩ

(1) Includes comparator input referred errors.

(2) Disturbance error may be present on the CMPSS DAC output for a certain amount of time after a comparator trip.
(3) Per active CMPSS module.
(4) The maximum output voltage is VDDA when VDAC > VDDA.

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7.12.3.1.3 CMPSS Illustrative Graphs

Figure 7-39 shows the CMPSS DAC static offset. Figure 7-40 shows the CMPSS DAC static gain. Figure 7-41
shows the CMPSS DAC static linearity.

Offset Error

Figure 7-39. CMPSS DAC Static Offset

Ideal Gain

Actual Gain

Actual Linear Range

Figure 7-40. CMPSS DAC Static Gain

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Linearity Error

Figure 7-41. CMPSS DAC Static Linearity

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7.13 Control Peripherals

7.13.1 Enhanced Pulse Width Modulator (ePWM)
The ePWM peripheral is a key element in controlling many of the power electronic systems found in both
commercial and industrial equipment. The ePWM type-4 module is able to generate complex pulse width
waveforms with minimal CPU overhead by building the peripheral up from smaller modules with separate
resources that can operate together to form a system. Some of the highlights of the ePWM type-4 module
include complex waveform generation, dead-band generation, a flexible synchronization scheme, advanced trip-
zone functionality, and global register reload capabilities.
Figure 7-42 shows the ePWM module. Figure 7-43 shows the ePWM trip input connectivity.

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Time-Base (TB)

TBPRD Shadow (24) EXTSYNCIN ePWM EXTSYNCOUT

TBPRDHR (8) SYNC
TBPRD Active (24)
Scheme

CTR=PRD
EPWMxSYNCI
TBCTL[PHSEN]
TBCTL[SWFSYNC]
Counter
DCAEVT1/sync(A)
Up/Down
(16 bit) DCBEVT1/sync(A)
CTR=ZERO
TBCTR
Active (16) CTR_Dir CTR=PRD EPWMx_INT
CTR=ZERO
TBPHSHR (8)
CTR=PRD or ZERO EPWMxSOCA
16 8
CTR=CMPA Event On-chip
Phase EPWMxSOCB
TBPHS Active (24) Trigger ADC
Control CTR=CMPB
And
CTR=CMPC
Interrupt
CTR=CMPD (ET) ADCSOCOUTSELECT
Counter Compare (CC)
CTR_Dir
Action
CTR=CMPA Qualifier DCAEVT1.soc(A) Select and pulse stretch
(AQ) DCBEVT1.soc(A) for external ADC
CMPAHR (8)
16 HiRes PWM (HRPWM)
CMPAHR (8)
CMPA Active (24) ADCSOCAO
ADCSOCBO
CMPA Shadow (24) EPWMA ePWMxA

CTR=CMPB Dead PWM Trip

Band Chopper Zone
(DB) (DB) (TZ)
CMPBHR (8)
16
CMPB Active (16) EPWMB ePWMxB
CMPB Shadow (16)
CMPBHR (8)
EPWMx_TZ_INT
TBCNT (16) CTR=CMPC CTR=ZERO
TZ1 to TZ3
DCAEVT1.inter
EMUSTOP
CMPC[15-0] 16 DCBEVT1.inter
CLOCKFAIL
DCAEVT2.inter
CMPC Active (16) EQEPxERR
DCBEVT2.inter
CMPC Shadow (16) DCAEVT1.force(A)
DCBEVT1.force(A)
TBCNT (16) CTR=CMPD DCAEVT2.force(A)
DCBEVT2.force(A)
CMPD[15-0] 16

CMPD Active (16)

CMPD Shadow (16)

A. These events are generated by the ePWM digital compare (DC) submodule based on the levels of the TRIPIN inputs.

Figure 7-42. ePWM Submodules and Critical Internal Signal Interconnects

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GPIO0 Async/
Sync/ Input X-Bar
Sync+Filter
GPIOx
Other Sources 16:127

INPUT15
INPUT16
INPUT13
INPUT14
INPUT10

INPUT12
INPUT11
INPUT1
INPUT2
INPUT3
INPUT4
INPUT5
INPUT6
INPUT7
INPUT8
INPUT9
eCAPx
INPUT[1:16] 0:15

XINT1
XINT2
ADC
XINT3
Wrapper(s)
XINT4 PIE
ePWM XINT5
eCAP
EXTSYNCIN1
Sync Mux EXTSYNCIN2
TZ1 EPWMINT
TZ2 TZINT
TZ3
TRIP1
TRIP2 EPWMx.EPWMCLK
TRIP3 PCLKCR2[EPWMx]
TRIP6
TBCLKSYNC
INPUT[1:14] TRIP4 PCLKCR0[TBCLKSYNC]
CMPSSx.TRIPH
TRIP5
TRIP7
CMPSSx.TRIPHORL TRIP8
CMPSSx.TRIPL TRIP9 All
ADCx.EVT1-4 TRIP10
ePWM ePWM
ECAPx.OUT TRIP11 Modules
X-Bar
TRIP12 ADCSOCAO Select
ADCSOCBO Select
EXTSYNCOUT
ADCSOCx
SOCA ADC
Reserved Wrapper(s)
TRIP13 SOCB
ECCERR TRIP14
PIEVECTERROR TRIP15
EQEPERR TZ4 EPWMSYNCPER
CLKFAIL TZ5 CMPSS
EMUSTOP TZ6 Blanking Window

Figure 7-43. ePWM Trip Input Connectivity

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7.13.1.1 Control Peripherals Synchronization

The ePWM and eCAP synchronization scheme on the device provides flexibility in partitioning the ePWM and
eCAP modules and allows localized synchronization within the modules. Like the other peripherals, the
partitioning of the ePWM and eCAP modules needs to be done using the CPUSELx registers. Figure 7-44 shows
the synchronization scheme.
TBCTL

TBCTL2[OSHTSYNC]

TBCTL3[OSSFRCEN]
GLDCTL2[OSHTLD]
SWFSYNC

:ULWH ³1´ WR

:ULWH ³1´ WR
CTR=ZERO

CTR=CMPB
CTR=CMPC

TBCTL2[OSHTSYNCMODE]
CTR=CMPD
CLR
DCAEVT1.sync One Shot
DCBEVT1.sync Latch
0
Set Q
EPWMSYNCOUTEN
1

SWEN

ZEROEN
0 0
CMPBEN
1 EPWMxSYNCOUT
CMPCEN OR 1
0
CMPDEN

DCARVT1EN
TBCTL2[SELFCLRTRREM]
DCBEVT1EN

Disable Clear
Register
EPWM1SYNCOUT 0
|
|
|
EPWMxSYNCOUT
EPWMxSYNCIN HRPCTL[PWMSYNCSELX]
ECAP1SYNCOUT CTR=CMPC UP
|
|
|
CTR=CMPC DOWN
ECAPySYNCOUT CTR=CMPD UP EPWMxSYNCPER
Other Sources CTR=CMPD DOWN CMPSS
DAC
HRPCTL[PWMSYNCSEL]

EPWMSYNCINSEL CTR=PRD
CTR=ZERO
Note: SYNCO and SYNCOUT are used interchangeably

Figure 7-44. Synchronization Chain Architecture

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7.13.1.2 ePWM Electrical Data and Timing

Section 7.13.1.2.1 lists the ePWM timing requirements and Section 7.13.1.2.2 lists the ePWM switching
characteristics. For an explanation of the input qualifier parameters, see Section 7.11.6.2.1.
7.13.1.2.1 ePWM Timing Requirements
MIN MAX UNIT
Asynchronous 2tc(EPWMCLK)
tw(SYNCIN) Sync input pulse width Synchronous 2tc(EPWMCLK) cycles
With input qualifier 1tc(EPWMCLK) + tw(IQSW)

7.13.1.2.2 ePWM Switching Characteristics

over recommended operating conditions (unless otherwise noted)
PARAMETER MIN MAX UNIT
tw(PWM) Pulse duration, PWMx output high/low 20 ns
tw(SYNCOUT) Sync output pulse width 8tc(SYSCLK) cycles
Delay time, trip input active to PWM forced high
td(TZ-PWM) Delay time, trip input active to PWM forced low 25 ns
Delay time, trip input active to PWM Hi-Z

7.13.1.2.3 Trip-Zone Input Timing

Section 7.13.1.2.3.1 lists the trip-zone input timing requirements. Figure 7-45 shows the PWM Hi-Z
characteristics. For an explanation of the input qualifier parameters, see Section 7.11.6.2.1.
7.13.1.2.3.1 Trip-Zone Input Timing Requirements

MIN MAX UNIT

Asynchronous 1tc(EPWMCLK) cycles
tw(TZ) Pulse duration, TZx input low Synchronous 2tc(EPWMCLK) cycles
With input qualifier 1tc(EPWMCLK) + tw(IQSW) cycles

EPWMCLK

tw(TZ)
(A)
TZ

td(TZ-PWM)

(B)
PWM

A. TZ: TZ1, TZ2, TZ3, TRIP1–TRIP12

B. PWM refers to all the PWM pins in the device. The state of the PWM pins after TZ is taken high depends on the PWM recovery software.

Figure 7-45. PWM Hi-Z Characteristics

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7.13.1.3 External ADC Start-of-Conversion Electrical Data and Timing

Section 7.13.1.3.1 lists the external ADC start-of-conversion switching characteristics. Figure 7-46 shows the
ADCSOCAO or ADCSOCBO timing.
7.13.1.3.1 External ADC Start-of-Conversion Switching Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER MIN MAX UNIT
tw(ADCSOCL) Pulse duration, ADCSOCxO low 32tc(SYSCLK) cycles

tw(ADCSOCL)
ADCSOCAO
or
ADCSOCBO

Figure 7-46. ADCSOCAO or ADCSOCBO Timing

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7.13.2 High-Resolution Pulse Width Modulator (HRPWM)

The HRPWM combines multiple delay lines in a single module and a simplified calibration system by using a
dedicated calibration delay line. For each ePWM module, there are two HR outputs:
• HR Duty and Deadband control on Channel A
• HR Duty and Deadband control on Channel B
The HRPWM module offers PWM resolution (time granularity) that is significantly better than what can be
achieved using conventionally derived digital PWM methods. The key points for the HRPWM module are:
• Significantly extends the time resolution capabilities of conventionally derived digital PWM
• This capability can be used in both single edge (duty cycle and phase-shift control) as well as dual edge
control for frequency/period modulation.
• Finer time granularity control or edge positioning is controlled through extensions to the Compare A, B,
phase, period and deadband registers of the ePWM module.

Note
The minimum HRPWMCLK frequency allowed for HRPWM is 60 MHz.

7.13.2.1 HRPWM Electrical Data and Timing

Section 7.13.2.1.1 lists the high-resolution PWM switching characteristics.
7.13.2.1.1 High-Resolution PWM Characteristics

PARAMETER MIN TYP MAX UNIT

Micro Edge Positioning (MEP) step size(1) 150 310 ps

(1) The MEP step size will be largest at high temperature and minimum voltage on VDD. MEP step size will increase with higher
temperature and lower voltage and decrease with lower temperature and higher voltage.
Applications that use the HRPWM feature should use MEP Scale Factor Optimizer (SFO) estimation software functions. See the TI
software libraries for details of using SFO functions in end applications. SFO functions help to estimate the number of MEP steps per
SYSCLK period dynamically while the HRPWM is in operation.

7.13.3 Enhanced Capture and High-Resolution Capture (eCAP, HRCAP)

The eCAP module can be used in systems where accurate timing of external events is important. eCAP/HRCAP
on this device is Type-2.
Applications for eCAP include:
• Speed measurements of rotating machinery (for example, toothed sprockets sensed through Hall sensors)
• Elapsed time measurements between position sensor pulses
• Period and duty cycle measurements of pulse train signals
• Decoding current or voltage amplitude derived from duty cycle encoded current/voltage sensors
The eCAP module includes the following features:
• 4-event time-stamp registers (each 32 bits)
• Edge-polarity selection for up to four sequenced time-stamp capture events
• Interrupt on either of the four events
• Single shot capture of up to four event timestamps
• Continuous mode capture of timestamps in a four-deep circular buffer
• Absolute time-stamp capture
• Difference (Delta) mode time-stamp capture
• All of the above resources dedicated to a single input pin
• When not used in capture mode, the eCAP module can be configured as a single-channel PWM output
(APWM).

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The capture functionality of the Type-1 eCAP is enhanced from the Type-0 eCAP with the following added
features:
• Event filter reset bit
– Writing a 1 to ECCTL2[CTRFILTRESET] will clear the event filter, the modulo counter, and any pending
interrupts flags. Resetting the bit is useful for initialization and debug.
• Modulo counter status bits
– The modulo counter (ECCTL2 [MODCTRSTS]) indicates which capture register will be loaded next. In the
Type-0 eCAP, it was not possible to know current state of modulo counter.
• DMA trigger source
– eCAPxDMA is added as a DMA trigger. CEVT[1–4] can be configured as the source for eCAPxDMA.
• Input multiplexer
– ECCTL0 [INPUTSEL] selects one of 128 input signals.
• EALLOW protection
– EALLOW protection is added to critical registers. To maintain software compatibility with the Type-0 eCAP,
configure DEV_CFG_REGS.ECAPTYPE to make these registers unprotected.
The capture functionality of the Type-2 eCAP is enhanced from the Type-1 eCAP with the following added
features:
• ECAPxSYNCINSEL register
– The ECAPSxYNCINSEL register is added for each eCAP to select an external SYNCIN. Every eCAP can
have a separate SYNCIN signal.
The eCAP inputs connect to any GPIO input through the Input X-BAR. The APWM outputs connect to GPIO pins
through the Output X-BAR to OUTPUTx positions in the GPIO mux. See Section 6.4.3 and Section 6.4.4.
The eCAP module is clocked by PERx.SYSCLK.
The clock enable bits (ECAP1–ECAP3) in the PCLKCR3 register turn off the eCAP module individually (for low-
power operation). Upon reset, ECAP1ENCLK is set to low, indicating that the peripheral clock is off.
7.13.3.1 High-Resolution Capture (HRCAP)
The eCAP3 module can be configured as high-resolution capture (HRCAP) submodules. The HRCAP
submodule measures the difference, in time, between pulses asynchronously to the system clock. This
submodule is new to the eCAP Type 1 module, and features many enhancements over the Type 0 HRCAP
module.
Applications for the HRCAP include:
• Capacitive touch applications
• High-resolution period and duty-cycle measurements of pulse train cycles
• Instantaneous speed measurements
• Instantaneous frequency measurements
• Voltage measurements across an isolation boundary
• Distance/sonar measurement and scanning
• Flow measurements
The HRCAP submodule includes the following features:
• Pulse-width capture in either non-high-resolution or high-resolution modes
• Absolute mode pulse-width capture
• Continuous or "one-shot" capture
• Capture on either falling or rising edge
• Continuous mode capture of pulse widths in 4-deep buffer
• Hardware calibration logic for precision high-resolution capture
• All of the resources in this list are available on any pin using the Input X-BAR.

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The HRCAP submodule includes one high-resolution capture channel in addition to a calibration block. The
calibration block allows the HRCAP submodule to be continually recalibrated, at a set interval, with no “down
time”. Because the HRCAP submodule now uses the same hardware as its respective eCAP, if the HRCAP is
used, the corresponding eCAP will be unavailable.
Each high-resolution-capable channel has the following independent key resources.
• All hardware of the respective eCAP
• High-resolution calibration logic
• Dedicated calibration interrupt
eCAP and HRCAP Block Diagram
Figure 7-47 shows the eCAP and HRCAP block diagram.

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ECCTL2 [ SYNCI_EN, SYNCOSEL, SWSYNC]

ECCTL2[CAP/APWM]
CTRPHS
(phase register−32 bit) APWM Mode

SYNC
ECAPxSYNCIN
OVF CTR_OVF CTR [0−31]
ECAPxSYNCOUT TSCTR
PWM
(counter−32 bit) Output
Delta−Mode PRD [0−31] Compare
RST X-Bar
Logic
CMP [0−31]
32

CTR=PRD
CTR [0−31]
CTR=CMP
32
PRD [0−31]
HRCTRL[HRE] ECCTL1 [ CAPLDEN, CTRRSTx]

32
32 CAP1 LD1
Polarity
(APRD Active) LD
Select

APRD
32
shadow CMP [0−31]
HRCTRL[HRE] 32

32 HRCTRL[HRE]
32
CAP2 LD2 Polarity
(ACMP Active) LD Select Other
Event [127:16]
Sources
Prescale
Event
32 ACMP
qualifier 16
shadow ECCTL1[PRESCALE] Input
HRCTRL[HRE] [15:0]
X-Bar
32
Polarity
32 CAP3 LD3
LD Select
(APRD Shadow)

HRCTRL[HRE]
32
32 CAP4 LD4 Polarity
(ACMP Shadow) LD
Select

4 Edge Polarity Select

Capture Events ECCTL1[CAPxPOL]
4

CEVT[1:4]
ECAPxDMA_INT
ECCTL2[CTRFILTRESET]
Interrupt Continuous /
Trigger Oneshot MODCNTRSTS
and CTR_OVF Capture Control
ECCTL2[DMAEVTSEL]
Flag
CTR=PRD
ECAPx Control
(to ePIE) CTR=CMP
ECCTL2 [ REARM, CONT_ONESHT, STOP_WRAP]
Registers: ECEINT, ECFLG, ECCLR, ECFRC

SYSCLK Capture Pulse

(A)
HRCLK HR Submodule
ECAPx_HRCAL HR Input
(to ePIE)
Copyright © 2018, Texas Instruments Incorporated

A. The HRCAP submodule is not available on all eCAP modules; in this case, the high-resolution muxes and hardware are not
implemented.

Figure 7-47. eCAP and HRCAP Block Diagram

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7.13.3.2 eCAP/HRCAP Synchronization

The eCAP modules can be synchronized with each other by selecting a common SYNCIN source. SYNCIN
source for eCAP can be either software sync-in or external sync-in. The external sync-in signal can come from
EPWM, eCAP, or X-Bar. The SYNC signal is defined by the selection in the ECAPxSYNCINSEL[SEL] bit for
ECAPx as shown in Figure 7-48.

ECAPx

Disable 0x0
EPWM[1..7]SYNCOUT 0x1 ECAPxSYNCIN
EPWMxSYNCOUT
ECCTL2[SWSYNC] EXTSYNCOUT
ECAP[1..3]SYNCOUT CTR=PRD ECAPxSYNCOUT
Disable
INPUT5 (Input X-Bar) Disable

INPUT6 (Input X-Bar) 0x19 SYNCSELECT[SYNCOUT]

ECCTL2[SYNCOSEL]

ECAPSYNCINSEL[SEL]

Figure 7-48. eCAPSynchronization Scheme

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7.13.3.3 eCAP Electrical Data and Timing

Section 7.13.3.3.1 lists the eCAP timing requirements and Section 7.13.3.3.2 lists the eCAP switching
characteristics.
7.13.3.3.1 eCAP Timing Requirements
MIN NOM MAX UNIT
Asynchronous 2tc(SYSCLK)
tw(CAP) Capture input pulse width Synchronous 2tc(SYSCLK) ns
With input qualifier 1tc(SYSCLK) + tw_(IQSW)

7.13.3.3.2 eCAP Switching Characteristics

over recommended operating conditions (unless otherwise noted)
PARAMETER MIN TYP MAX UNIT
tw(APWM) Pulse duration, APWMx output high/low 20 ns

7.13.3.4 HRCAP Electrical Data and Timing

Section 7.13.3.4.1 lists the HRCAP switching characteristics. Figure 7-49 shows the HRCAP accuracy precision
and resolution. Figure 7-50 shows the HRCAP standard deviation characteristics.
7.13.3.4.1 HRCAP Switching Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Input pulse width 110 ns
Measurement length ≤ 5 µs ±390 540 ps
Accuracy(1) (2) (3) (4)
Measurement length > 5 µs ±450 1450 ps
See HRCAP
Standard
Standard deviation Deviation
Characteristics
figure
Resolution 300 ps

(1) Value obtained using an oscillator of 100 PPM, oscillator accuracy directly affects the HRCAP accuracy.
(2) Measurement is completed using rising-rising or falling-falling edges
(3) Opposite polarity edges will have an additional inaccuracy due to the difference between VIH and VIL. This effect is dependent on the
signal’s slew rate.
(4) Accuracy only applies to time-converted measurements.

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HRCAP Figure and Graph

HRCAP’s Mean
Accuracy

HRCAP Result
Probability Resolution
(Step Size)

Precision
Actual (Standard Deviation)
Input Signal
A. The HRCAP has some variation in performance, this results in a probability distribution which is described using the following terms:
• Accuracy: The time difference between the input signal and the mean of the HRCAP’s distribution.
• Precision: The width of the HRCAP’s distribution, this is given as a standard deviation.
• Resolution: The minimum measurable increment.

Figure 7-49. HRCAP Accuracy Precision and Resolution

2 7.4
Typical Core Conditions
Noisy Core Supply

1.8 6.66

1.6 5.92

1.4 5.18

Standard Deviation (Steps)

Standard Deviation (nS)

1.2 4.44

1 3.7

0.8 2.96

0.6 2.22

0.4 1.48

0.2 0.74
0 1000 2000 3000 4000 5000 6000 7000 8000 9000 10000
Time Between Edges(nS)
A. Typical core conditions: All peripheral clocks are enabled.
B. Noisy core supply: All core clocks are enabled and disabled with a regular period during the measurement.
C. Fluctuations in current and voltage on the 1.2-V rail cause the standard deviation of the HRCAP to rise. Care should be taken to ensure
that the 1.2-V supply is clean, and that noisy internal events, such as enabling and disabling clock trees, have been minimized while
using the HRCAP.

Figure 7-50. HRCAP Standard Deviation Characteristics

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7.13.4 Enhanced Quadrature Encoder Pulse (eQEP)

The eQEP module on this device is Type-2. The eQEP interfaces directly with linear or rotary incremental
encoders to obtain position, direction, and speed information from rotating machines used in high-performance
motion and position control systems.
The eQEP peripheral contains the following major functional units (see Figure 7-51):
• Programmable input qualification for each pin (part of the GPIO MUX)
• Quadrature decoder unit (QDU)
• Position counter and control unit for position measurement (PCCU)
• Quadrature edge-capture unit for low-speed measurement (QCAP)
• Unit time base for speed/frequency measurement (UTIME)
• Watchdog timer for detecting stalls (QWDOG)
• Quadrature Mode Adapter (QMA)
System
control registers
To CPU
EQEPxENCLK
SYSCLK

Data bus
QCPRD
Enhanced QEP (eQEP) peripheral
QCAPCTL QCTMR
16 16

16
Quadrature
capture unit
QCTMRLAT (QCAP)
QCPRDLAT

Registers QUTMR QWDTMR

used by QUPRD QWDPRD
multiple units
32 16
QEPCTL QDECCTL
QEPSTS UTOUT 16
UTIME QWDOG
QFLG EQEPxAIN EQEPx_A
WDTOUT QMA EQEPxBIN EQEPx_B
EQEPxINT QCLK
PIE
QDIR EQEPxIIN
32 Quadrature
Position counter/ QI decoder EQEPxIOUT GPIO EQEPx_INDEX
control unit QS (QDU) MUX
EQEPxIOE
QPOSLAT (PCCU) PHE
QPOSSLAT PCSOUT EQEPxSIN
QPOSILAT EQEPxSOUT EQEPx_STROBE
EQEPxSOE
32 32 16

QPOSCNT QPOSCMP QEINT

QPOSINIT QFRC
QPOSMAX QCLR
QPOSCTL

Copyright © 2017, Texas Instruments Incorporated

Figure 7-51. eQEP Block Diagram

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7.13.4.1 eQEP Electrical Data and Timing

Section 7.13.4.1.1 lists the eQEP timing requirements and Section 7.13.4.1.2 lists the eQEP switching
characteristics. For an explanation of the input qualifier parameters, see Section 7.11.6.2.1.
7.13.4.1.1 eQEP Timing Requirements
MIN MAX UNIT
Synchronous(1) 2tc(SYSCLK)
tw(QEPP) QEP input period cycles
Synchronous with input qualifier 2[1tc(SYSCLK) + tw(IQSW)]
Synchronous(1) 2tc(SYSCLK)
tw(INDEXH) QEP Index Input High time cycles
Synchronous with input qualifier 2tc(SYSCLK) + tw(IQSW)
Synchronous(1) 2tc(SYSCLK)
tw(INDEXL) QEP Index Input Low time cycles
Synchronous with input qualifier 2tc(SYSCLK) + tw(IQSW)
Synchronous(1) 2tc(SYSCLK)
tw(STROBH) QEP Strobe High time cycles
Synchronous with input qualifier 2tc(SYSCLK) + tw(IQSW)
Synchronous(1) 2tc(SYSCLK)
tw(STROBL) QEP Strobe Input Low time cycles
Synchronous with input qualifier 2tc(SYSCLK) + tw(IQSW)

(1) The GPIO GPxQSELn Asynchronous mode should not be used for eQEP module input pins.

7.13.4.1.2 eQEP Switching Characteristics

over recommended operating conditions (unless otherwise noted)
PARAMETER MIN MAX UNIT
td(CNTR)xin Delay time, external clock to counter increment 5tc(SYSCLK) cycles
td(PCS-OUT)QEP Delay time, QEP input edge to position compare sync output 7tc(SYSCLK) cycles

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7.14 Communications Peripherals

7.14.1 Controller Area Network (CAN)

Note
The CAN module uses the IP known as DCAN. This document uses the names CAN and DCAN
interchangeably to reference this peripheral.

The CAN module implements the following features:

• Complies with ISO11898-1 ( Bosch® CAN protocol specification 2.0 A and B)
• Bit rates up to 1 Mbps
• Multiple clock sources
• 32 message objects (mailboxes), each with the following properties:
– Configurable as receive or transmit
– Configurable with standard (11-bit) or extended (29-bit) identifier
– Supports programmable identifier receive mask
– Supports data and remote frames
– Holds 0 to 8 bytes of data
– Parity-checked configuration and data RAM
• Individual identifier mask for each message object
• Programmable FIFO mode for message objects
• Programmable loopback modes for self-test operation
• Suspend mode for debug support
• Software module reset
• Automatic bus on after bus-off state by a programmable 32-bit timer
• Two interrupt lines
• DMA support

Note
For a CAN bit clock of 100 MHz, the smallest bit rate possible is 3.90625 kbps.

Note
The accuracy of the on-chip zero-pin oscillator is in Section 7.11.3.5.1. Depending on parameters
such as the CAN bit timing settings, bit rate, bus length, and propagation delay, the accuracy of this
oscillator may not meet the requirements of the CAN protocol. In this situation, an external clock
source must be used.

Figure 7-52 shows the CAN block diagram.

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CAN_H
CAN Bus
CAN_L

External connections 3.3V CAN Transceiver

Device CANx RX pin CANx TX pin

CAN

CAN Core

Message RAM

Message Handler
Message
RAM
Interface
32 Register and Message
Message Object Access (IFx)
Objects Test Modes
(Mailboxes) Only

Module Interface

CANINT0 CANINT1 DMA

CPU Bus

Figure 7-52. CAN Block Diagram

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7.14.2 Inter-Integrated Circuit (I2C)

The I2C module has the following features:
• Compliance with the NXP Semiconductors I2C-bus specification (version 2.1):
– Support for 8-bit format transfers
– 7-bit and 10-bit addressing modes
– General call
– START byte mode
– Support for multiple master-transmitters and slave-receivers
– Support for multiple slave-transmitters and master-receivers
– Combined master transmit/receive and receive/transmit mode
– Data transfer rate from 10 kbps up to 400 kbps (Fast-mode)
• One 16-byte receive FIFO and one 16-byte transmit FIFO
• Supports two ePIE interrupts
– I2Cx interrupt – Any of the below conditions can be configured to generate an I2Cx interrupt:
• Transmit Ready
• Receive Ready
• Register-Access Ready
• No-Acknowledgment
• Arbitration-Lost
• Stop Condition Detected
• Addressed-as-Slave
– I2Cx_FIFO interrupts:
• Transmit FIFO interrupt
• Receive FIFO interrupt
• Module enable and disable capability
• Free data format mode
Figure 7-53 shows how the I2C peripheral module interfaces within the device.

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I2C module

I2CXSR I2CDXR

TX FIFO
FIFO Interrupt
SDA
to CPU/PIE
RX FIFO

Peripheral bus

I2CRSR I2CDRR

Control/status
Clock registers CPU
SCL synchronizer

Prescaler

Noise filters Interrupt to

I2C INT CPU/PIE
Arbitrator

Figure 7-53. I2C Peripheral Module Interfaces

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7.14.2.1 I2C Electrical Data and Timing

Section 7.14.2.1.1 lists the I2C timing requirements. Section 7.14.2.1.2 lists the I2C switching characteristics.
Figure 7-54 shows the I2C timing diagram.

Note
To meet all of the I2C protocol timing specifications, the I2C module clock must be configured in the
range from 7 MHz to 12 MHz.

7.14.2.1.1 I2C Timing Requirements

NO. MIN MAX UNIT
Standard mode
T0 fmod I2C module frequency 7 12 MHz
Hold time, START condition, SCL fall delay after
T1 th(SDA-SCL)START 4.0 µs
SDA fall
Setup time, Repeated START, SCL rise before SDA
T2 tsu(SCL-SDA)START 4.7 µs
fall delay
T3 th(SCL-DAT) Hold time, data after SCL fall 0 µs
T4 tsu(DAT-SCL) Setup time, data before SCL rise 250 ns
T5 tr(SDA) Rise time, SDA 1000 ns
T6 tr(SCL) Rise time, SCL 1000 ns
T7 tf(SDA) Fall time, SDA 300 ns
T8 tf(SCL) Fall time, SCL 300 ns
Setup time, STOP condition, SCL rise before SDA
T9 tsu(SCL-SDA)STOP 4.0 µs
rise delay
Pulse duration of spikes that will be suppressed by
T10 tw(SP) 0 50 ns
filter
T11 Cb capacitance load on each bus line 400 pF
Fast mode
T0 fmod I2C module frequency 7 12 MHz
Hold time, START condition, SCL fall delay after
T1 th(SDA-SCL)START 0.6 µs
SDA fall
Setup time, Repeated START, SCL rise before SDA
T2 tsu(SCL-SDA)START 0.6 µs
fall delay
T3 th(SCL-DAT) Hold time, data after SCL fall 0 µs
T4 tsu(DAT-SCL) Setup time, data before SCL rise 100 ns
T5 tr(SDA) Rise time, SDA 20 300 ns
T6 tr(SCL) Rise time, SCL 20 300 ns
T7 tf(SDA) Fall time, SDA 11.4 300 ns
T8 tf(SCL) Fall time, SCL 11.4 300 ns
Setup time, STOP condition, SCL rise before SDA
T9 tsu(SCL-SDA)STOP 0.6 µs
rise delay
Pulse duration of spikes that will be suppressed by
T10 tw(SP) 0 50 ns
filter
T11 Cb capacitance load on each bus line 400 pF

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7.14.2.1.2 I2C Switching Characteristics

over recommended operating conditions (unless otherwise noted)
NO. PARAMETER TEST CONDITIONS MIN MAX UNIT
Standard mode
S1 fSCL SCL clock frequency 0 100 kHz
S2 TSCL SCL clock period 10 µs
S3 tw(SCLL) Pulse duration, SCL clock low 4.7 µs
S4 tw(SCLH) Pulse duration, SCL clock high 4.0 µs
Bus free time between STOP and START
S5 tBUF 4.7 µs
conditions
S6 tv(SCL-DAT) Valid time, data after SCL fall 3.45 µs
S7 tv(SCL-ACK) Valid time, Acknowledge after SCL fall 3.45 µs
S8 II Input current on pins 0.1 Vbus < Vi < 0.9 Vbus –10 10 µA
Fast mode
S1 fSCL SCL clock frequency 0 400 kHz
S2 TSCL SCL clock period 2.5 µs
S3 tw(SCLL) Pulse duration, SCL clock low 1.3 µs
S4 tw(SCLH) Pulse duration, SCL clock high 0.6 µs
Bus free time between STOP and START
S5 tBUF 1.3 µs
conditions
S6 tv(SCL-DAT) Valid time, data after SCL fall 0.9 µs
S7 tv(SCL-ACK) Valid time, Acknowledge after SCL fall 0.9 µs
S8 II Input current on pins 0.1 Vbus < Vi < 0.9 Vbus –10 10 µA

7.14.2.1.3 I2C Timing Diagram

STOP START

SDA
ACK Contd...

S6 T10 S7
T5 T7 S3

SCL S4 Contd...

9th
T6 T8 clock
S2
Repeated
START STOP
S5

SDA
ACK
T2
T9
T1

SCL

9th
clock

Figure 7-54. I2C Timing Diagram

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7.14.3 Power Management Bus (PMBus) Interface

The PMBus module has the following features:
• Compliance with the SMI Forum PMBus Specification (Part I v1.0 and Part II v1.1)
• Support for master and slave modes
• Support for I2C mode
• Support for two speeds:
– Standard Mode: Up to 100 kHz
– Fast Mode: 400 kHz
• Packet error checking
• CONTROL and ALERT signals
• Clock high and low time-outs
• Four-byte transmit and receive buffers
• One maskable interrupt, which can be generated by several conditions:
– Receive data ready
– Transmit buffer empty
– Slave address received
– End of message
– ALERT input asserted
– Clock low time-out
– Clock high time-out
– Bus free
Figure 7-55 shows the PMBus block diagram.

PCLKCR20

SYSCLK

Div PMBCTRL
ALERT DMA

Bit clock
CTL Other registers

GPIO Mux CPU

PMBTXBUF
SCL

Shift register PMBRXBUF

SDA PMBUSA_INT PIE

PMBus Module

Figure 7-55. PMBus Block Diagram

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7.14.3.1 PMBus Electrical Data and Timing

Section 7.14.3.1.1 lists the PMBus electrical characteristics. Section 7.14.3.1.2 lists the PMBUS fast mode
switching characteristics. Section 7.14.3.1.3 lists the PMBUS standard mode switching characteristics.
7.14.3.1.1 PMBus Electrical Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VIL Valid low-level input voltage 0.8 V
VIH Valid high-level input voltage 2.1 VDDIO V
VOL Low-level output voltage At Ipullup = 4 mA 0.4 V
IOL Low-level output current VOL ≤ 0.4 V 4 mA
Pulse width of spikes that must be
tSP 0 50 ns
suppressed by the input filter
Ii Input leakage current on each pin 0.1 Vbus < Vi < 0.9 Vbus –10 10 µA
Ci Capacitance on each pin 10 pF

7.14.3.1.2 PMBus Fast Mode Switching Characteristics

over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
fSCL SCL clock frequency 10 400 kHz
Bus free time between STOP and
tBUF 1.3 µs
START conditions
START condition hold time -- SDA fall
tHD;STA 0.6 µs
to SCL fall delay
Repeated START setup time -- SCL
tSU;STA 0.6 µs
rise to SDA fall delay
STOP condition setup time -- SCL rise
tSU;STO 0.6 µs
to SDA rise delay
tHD;DAT Data hold time after SCL fall 300 ns
tSU;DAT Data setup time before SCL rise 100 ns
tTimeout Clock low time-out 25 35 ms
tLOW Low period of the SCL clock 1.3 µs
tHIGH High period of the SCL clock 0.6 50 µs
Cumulative clock low extend time
tLOW;SEXT From START to STOP 25 ms
(slave device)
Cumulative clock low extend time
tLOW;MEXT Within each byte 10 ms
(master device)
tr Rise time of SDA and SCL 5% to 95% 20 300 ns
tf Fall time of SDA and SCL 95% to 5% 20 300 ns

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7.14.3.1.3 PMBus Standard Mode Switching Characteristics

over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
fSCL SCL clock frequency 10 100 kHz
Bus free time between STOP and
tBUF 4.7 µs
START conditions
START condition hold time -- SDA fall
tHD;STA 4 µs
to SCL fall delay
Repeated START setup time -- SCL
tSU;STA 4.7 µs
rise to SDA fall delay
STOP condition setup time -- SCL rise
tSU;STO 4 µs
to SDA rise delay
tHD;DAT Data hold time after SCL fall 300 ns
tSU;DAT Data setup time before SCL rise 250 ns
tTimeout Clock low time-out 25 35 ms
tLOW Low period of the SCL clock 4.7 µs
tHIGH High period of the SCL clock 4 50 µs
Cumulative clock low extend time
tLOW;SEXT From START to STOP 25 ms
(slave device)
Cumulative clock low extend time
tLOW;MEXT Within each byte 10 ms
(master device)
tr Rise time of SDA and SCL 1000 ns
tf Fall time of SDA and SCL 300 ns

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7.14.4 Serial Communications Interface (SCI)

The SCI is a 2-wire asynchronous serial port, commonly known as a UART. The SCI module supports digital
communications between the CPU and other asynchronous peripherals that use the standard non-return-to-zero
(NRZ) format
The SCI receiver and transmitter each have a 16-level-deep FIFO for reducing servicing overhead, and each has
its own separate enable and interrupt bits. Both can be operated independently for half-duplex communication,
or simultaneously for full-duplex communication. To specify data integrity, the SCI checks received data for break
detection, parity, overrun, and framing errors. The bit rate is programmable to different speeds through a 16-bit
baud-select register.
Features of the SCI module include:
• Two external pins:
– SCITXD: SCI transmit-output pin
– SCIRXD: SCI receive-input pin
– Baud rate programmable to 64K different rates
• Data-word format
– 1 start bit
– Data-word length programmable from 1 to 8 bits
– Optional even/odd/no parity bit
– 1 or 2 stop bits
• Four error-detection flags: parity, overrun, framing, and break detection
• Two wake-up multiprocessor modes: idle-line and address bit
• Half- or full-duplex operation
• Double-buffered receive and transmit functions
• Transmitter and receiver operations can be accomplished through interrupt-driven or polled algorithms with
status flags.
– Transmitter: TXRDY flag (transmitter-buffer register is ready to receive another character) and TX EMPTY
flag (transmitter-shift register is empty)
– Receiver: RXRDY flag (receiver-buffer register is ready to receive another character), BRKDT flag (break
condition occurred), and RX ERROR flag (monitoring four interrupt conditions)
• Separate enable bits for transmitter and receiver interrupts (except BRKDT)
• NRZ format
• Auto baud-detect hardware logic
• 16-level transmit and receive FIFO

Note
All registers in this module are 8-bit registers. When a register is accessed, the register data is in the
lower byte (bits 7–0), and the upper byte (bits 15–8) is read as zeros. Writing to the upper byte has no
effect.

Figure 7-56 shows the SCI block diagram.

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TXENA
SCICTL1.1

TXSHF
SCITXD
Register

Frame 8
Format and Mode

Parity
Even/Odd TXEMPTY
0 1
SCICCR.6 8 SCICTL2.6

Enable
TX FIFO_0
TXINT
SCICCR.5 To CPU
TX FIFO_1 TX FIFO Interrupts TX Interrupt
88
Logic

TX FIFO_N
TXINTENA

TXRDY SCICTL2.0
8
TXWAKE 0 1 SCICTL2.7
SCICTL1.3

SCI TX Interrupt Select Logic

WUT 8

Transmit Data
Buffer Register
SCITXBUF.7-0 Auto Baud Detect Logic
RXENA
Baud Rate
MSB/LSB SCICTL1.0
LSPCLK Registers
RXSHF
SCIRXD
Register
SCIHBAUD.15-8
RXWAKE
SCILBAUD.7-0 8
SCIRXST.1

0 1
8

SCIFFENA
SCIFFTX.14 RX FIFO_0 RXINT
8 RX FIFO_1 To CPU
RX FIFO Interrupts RX Interrupt
Logic

RX FIFO_N
RXFFOVF
8 SCIFFRX.15
0 1
RXBKINTENA
SCICTL2.1
RXRDY
SCIRXST.6

RXENA BRKDT
RXERRINTENA
SCICTL1.0
SCIRXST.5 SCICTL1.6

SCI RX Interrupt Select Logic

SCIRXST.5-2
Receive Data BRKDT FE OE PE
Buffer Register
RXERROR
SCIRXBUF.7-0
SCIRXST.7

Figure 7-56. SCI Block Diagram

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7.14.5 Serial Peripheral Interface (SPI)

The serial peripheral interface (SPI) is a high-speed synchronous serial input and output (I/O) port that allows a
serial bit stream of programmed length (1 to 16 bits) to be shifted into and out of the device at a programmed bit-
transfer rate. The SPI is normally used for communications between the MCU controller and external peripherals
or another controller. Typical applications include external I/O or peripheral expansion through devices such as
shift registers, display drivers, and analog-to-digital converters (ADCs). Multidevice communications are
supported by the master or slave operation of the SPI. The port supports a 16-level, receive and transmit FIFO
for reducing CPU servicing overhead.
The SPI module features include:
• SPISOMI: SPI slave-output/master-input pin
• SPISIMO: SPI slave-input/master-output pin
• SPISTE: SPI slave transmit-enable pin
• SPICLK: SPI serial-clock pin
• Two operational modes: Master and Slave
• Baud rate: 125 different programmable rates. The maximum baud rate that can be employed is limited by the
maximum speed of the I/O buffers used on the SPI pins.
• Data word length: 1 to 16 data bits
• Four clocking schemes (controlled by clock polarity and clock phase bits) include:
– Falling edge without phase delay: SPICLK active-high. SPI transmits data on the falling edge of the
SPICLK signal and receives data on the rising edge of the SPICLK signal.
– Falling edge with phase delay: SPICLK active-high. SPI transmits data one half-cycle ahead of the falling
edge of the SPICLK signal and receives data on the falling edge of the SPICLK signal.
– Rising edge without phase delay: SPICLK inactive-low. SPI transmits data on the rising edge of the
SPICLK signal and receives data on the falling edge of the SPICLK signal.
– Rising edge with phase delay: SPICLK inactive-low. SPI transmits data one half-cycle ahead of the rising
edge of the SPICLK signal and receives data on the rising edge of the SPICLK signal.
• Simultaneous receive and transmit operation (transmit function can be disabled in software)
• Transmitter and receiver operations are accomplished through either interrupt-driven or polled algorithm
• 16-level transmit/receive FIFO
• DMA support
• High-speed mode
• Delayed transmit control
• 3-wire SPI mode
• SPISTE inversion for digital audio interface receive mode on devices with two SPI modules
Figure 7-57 shows the SPI CPU interfaces.

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PCLKCR8
Low-Speed
LSPCLK SYSCLK CPU
Prescaler

Bit Clock

SYSRS

Peripheral Bus
SPISIMO

SPISOMI
GPIO MUX SPI
SPIINT
SPICLK PIE
SPITXINT
SPISTE

SPIRXDMA
DMA
SPITXDMA

Figure 7-57. SPI CPU Interface

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7.14.5.1 SPI Master Mode Timings

The following section contains the SPI Master Mode Timings. For more information about the SPI in High-Speed
mode, see the Serial Peripheral Interface (SPI) chapter of the TMS320F28002x Real-Time Microcontrollers
Technical Reference Manual.
Section 7.14.5.1.1 lists the SPI master mode timing requirements.
Section 7.14.5.1.2 lists the SPI master mode switching characteristics where the clock phase = 0. Figure 7-58
shows the SPI master mode external timing where the clock phase = 0.
Section 7.14.5.1.3 lists the SPI master mode switching characteristics where the clock phase = 1. Figure 7-59
shows the SPI master mode external timing where the clock phase = 1.

Note
All timing parameters for SPI High-Speed Mode assume a load capacitance of 5 pF on SPICLK,
SPISIMO, and SPISOMI.

7.14.5.1.1 SPI Master Mode Timing Requirements

NO. (BRR + 1) (1) MIN MAX UNIT
High-Speed Mode
8 tsu(SOMI)M Setup time, SPISOMI valid before SPICLK Even, Odd 1 ns
9 th(SOMI)M Hold time, SPISOMI valid after SPICLK Even, Odd 5 ns
Normal Mode
8 tsu(SOMI)M Setup time, SPISOMI valid before SPICLK Even, Odd 15 ns
9 th(SOMI)M Hold time, SPISOMI valid after SPICLK Even, Odd 0 ns

(1) The (BRR + 1) condition is Even when (SPIBRR + 1) is even or SPIBRR is 0 or 2. It is Odd when (SPIBRR + 1) is odd and SPIBRR is
greater than 3.

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7.14.5.1.2 SPI Master Mode Switching Characteristics (Clock Phase = 0)

over recommended operating conditions (unless otherwise noted)
NO. PARAMETER (BRR + 1)(1) MIN MAX UNIT
General
Even 4tc(LSPCLK) 128tc(LSPCLK)
1 tc(SPC)M Cycle time, SPICLK ns
Odd 5tc(LSPCLK) 127tc(LSPCLK)
Even 0.5tc(SPC)M – 1 0.5tc(SPC)M + 1
2 tw(SPC1)M Pulse duration, SPICLK, first pulse 0.5tc(SPC)M + ns
Odd 0.5tc(SPC)M + 0.5tc(LSPCLK) – 1
0.5tc(LSPCLK) + 1
Even 0.5tc(SPC)M – 1 0.5tc(SPC)M + 1
3 tw(SPC2)M Pulse duration, SPICLK, second pulse 0.5tc(SPC)M – ns
Odd 0.5tc(SPC)M – 0.5tc(LSPCLK) – 1
0.5tc(LSPCLK) + 1
1.5tc(SPC)M –
Even 1.5tc(SPC)M – 3tc(SYSCLK) – 3
3tc(SYSCLK) + 3
23 td(SPC)M Delay time, SPISTE active to SPICLK ns
1.5tc(SPC)M –
Odd 1.5tc(SPC)M – 4tc(SYSCLK) – 3
4tc(SYSCLK) + 3
Even 0.5tc(SPC)M – 3 0.5tc(SPC)M + 3
24 tv(STE)M Valid time, SPICLK to SPISTE inactive 0.5tc(SPC)M – ns
Odd 0.5tc(SPC)M – 0.5tc(LSPCLK) – 3
0.5tc(LSPCLK) + 3
High-Speed Mode
4 td(SIMO)M Delay time, SPICLK to SPISIMO valid Even, Odd 1 ns

Valid time, SPISIMO valid after Even 0.5tc(SPC)M – 3

5 tv(SIMO)M ns
SPICLK Odd 0.5tc(SPC)M – 0.5tc(LSPCLK) – 3
Normal Mode
4 td(SIMO)M Delay time, SPICLK to SPISIMO valid Even, Odd 1 ns

Valid time, SPISIMO valid after Even 0.5tc(SPC)M – 3

5 tv(SIMO)M ns
SPICLK Odd 0.5tc(SPC)M – 0.5tc(LSPCLK) – 3

(1) The (BRR + 1) condition is Even when (SPIBRR + 1) is even or SPIBRR is 0 or 2. It is Odd when (SPIBRR + 1) is odd and SPIBRR is
greater than 3.

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7.14.5.1.3 SPI Master Mode Switching Characteristics (Clock Phase = 1)

over recommended operating conditions (unless otherwise noted)
NO. PARAMETER (BRR + 1) MIN MAX UNIT
General
Even 4tc(LSPCLK) 128tc(LSPCLK)
1 tc(SPC)M Cycle time, SPICLK ns
Odd 5tc(LSPCLK) 127tc(LSPCLK)
Even 0.5tc(SPC)M – 1 0.5tc(SPC)M + 1
2 tw(SPCH)M Pulse duration, SPICLK, first pulse 0.5tc(SPC)M – ns
Odd 0.5tc(SPC)M – 0.5tc(LSPCLK) – 1
0.5tc(LSPCLK) + 1
Even 0.5tc(SPC)M – 1 0.5tc(SPC)M + 1
3 tw(SPC2)M Pulse duration, SPICLK, second pulse 0.5tc(SPC)M + ns
Odd 0.5tc(SPC)M + 0.5tc(LSPCLK) – 1
0.5tc(LSPCLK) + 1
2tc(SPC)M –
23 td(SPC)M Delay time, SPISTE valid to SPICLK Even, Odd 2tc(SPC)M – 3tc(SYSCLK) – 3 ns
3tc(SYSCLK) + 2
Even –3 2
24 td(STE)M Delay time, SPICLK to SPISTE invalid ns
Odd –3 2
High-Speed Mode
Even 0.5tc(SPC)M – 2
4 td(SIMO)M Delay time, SPISIMO valid to SPICLK ns
Odd 0.5tc(SPC)M + 0.5tc(LSPCLK) – 2

Valid time, SPISIMO valid after Even 0.5tc(SPC)M – 3

5 tv(SIMO)M ns
SPICLK Odd 0.5tc(SPC)M – 0.5tc(LSPCLK) – 3
Normal Mode
Even 0.5tc(SPC)M – 2
4 td(SIMO)M Delay time, SPISIMO valid to SPICLK ns
Odd 0.5tc(SPC)M + 0.5tc(LSPCLK) – 2

Valid time, SPISIMO valid after Even 0.5tc(SPC)M – 3

5 tv(SIMO)M ns
SPICLK Odd 0.5tc(SPC)M – 0.5tc(LSPCLK) – 3

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7.14.5.1.4 SPI Master Mode Timing Diagrams

SPICLK
(clock polarity = 0)

SPICLK
(clock polarity = 1)

4
5

SPISIMO Master Out Data Is Valid

Master In Data
SPISOMI
Must Be Valid

23 24

(A)
SPISTE

A. On the trailing end of the word, SPISTE will go inactive except between back-to-back transmit words in both FIFO and non-FIFO modes.

Figure 7-58. SPI Master Mode External Timing (Clock Phase = 0)

1
SPICLK
(clock polarity = 0)
2

SPICLK
(clock polarity = 1)
4
5

SPISIMO Master Out Data Is Valid

SPISOMI Master In Data Must

Be Valid
24
(A) 23
SPISTE

A. On the trailing end of the word, SPISTE will go inactive except between back-to-back transmit words in both FIFO and non-FIFO modes.

Figure 7-59. SPI Master Mode External Timing (Clock Phase = 1)

7.14.5.2 SPI Slave Mode Timings

The following section contains the SPI Slave Mode Timings. For more information about the SPI in High-Speed
mode, see the Serial Peripheral Interface (SPI) chapter of the TMS320F28002x Real-Time Microcontrollers
Technical Reference Manual.
Section 7.14.5.2.1 lists the SPI slave mode timing requirements. Section 7.14.5.2.2 lists the SPI slave mode
switching characteristics.
Figure 7-60 shows the SPI slave mode external timing where the clock phase = 0. Figure 7-61 shows the SPI
slave mode external timing where the clock phase = 1.
7.14.5.2.1 SPI Slave Mode Timing Requirements
NO. MIN MAX UNIT
12 tc(SPC)S Cycle time, SPICLK 4tc(SYSCLK) ns
13 tw(SPC1)S Pulse duration, SPICLK, first pulse 2tc(SYSCLK) – 1 ns
14 tw(SPC2)S Pulse duration, SPICLK, second pulse 2tc(SYSCLK) – 1 ns
19 tsu(SIMO)S Setup time, SPISIMO valid before SPICLK 1.5tc(SYSCLK) ns
20 th(SIMO)S Hold time, SPISIMO valid after SPICLK 1.5tc(SYSCLK) ns
Setup time, SPISTE valid before SPICLK
2tc(SYSCLK) + 3 ns
(Clock Phase = 0)
25 tsu(STE)S
Setup time, SPISTE valid before SPICLK
2tc(SYSCLK) + 23 ns
(Clock Phase = 1)
26 th(STE)S Hold time, SPISTE invalid after SPICLK 1.5tc(SYSCLK) ns

7.14.5.2.2 SPI Slave Mode Switching Characteristics

over recommended operating conditions (unless otherwise noted)
NO. PARAMETER MIN MAX UNIT
15 td(SOMI)S Delay time, SPICLK to SPISOMI valid 12 ns
16 tv(SOMI)S Valid time, SPISOMI valid after SPICLK 0 ns

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7.14.5.2.3 SPI Slave Mode Timing Diagrams

SPICLK
(clock polarity = 0)

SPICLK
(clock polarity = 1)

15
16

SPISOMI SPISOMI Data Is Valid

SPISIMO Data
SPISIMO
Must Be Valid

25 26

SPISTE

Figure 7-60. SPI Slave Mode External Timing (Clock Phase = 0)

SPICLK
(clock polarity = 0)

13 14

SPICLK
(clock polarity = 1)

SPISOMI SPISOMI Data Is Valid Data Valid Data Valid

19 16

SPISIMO SPISIMO Data

Must Be Valid

25 26

SPISTE

Figure 7-61. SPI Slave Mode External Timing (Clock Phase = 1)

7.14.6 Local Interconnect Network (LIN)

This device contains one Local Interconnect Network (LIN) module. The LIN module adheres to the LIN 2.1
standard as defined by the LIN Specification Package Revision 2.1. The LIN is a low-cost serial interface
designed for applications where the CAN protocol may be too expensive to implement, such as small
subnetworks for cabin comfort functions like interior lighting or window control in an automotive application.
The LIN standard is based on the SCI (UART) serial data link format. The communication concept is single-
master and multiple-slave with a message identification for multicast transmission between any network nodes.
The LIN module can be programmed to work either as an SCI or as a LIN as the core of the module is an SCI.
The hardware features of the SCI are augmented to achieve LIN compatibility. The SCI module is a universal
asynchronous receiver-transmitter (UART) that implements the standard non-return-to-zero format.
Though the registers are common for LIN and SCI, the register descriptions have notes to identify the register/bit
usage in different modes. Because of this, code written for this module cannot be directly ported to the stand-
alone SCI module and vice versa.
The LIN module has the following features:
• Compatibility with LIN 1.3, 2.0 and 2.1 protocols
• Configurable baud rate up to 20 kbps (as per LIN 2.1 protocol)
• Two external pins: LINRX and LINTX
• Multibuffered receive and transmit units
• Identification masks for message filtering
• Automatic master header generation
– Programmable synchronization break field
– Synchronization field
– Identifier field
• Slave automatic synchronization
– Synchronization break detection
– Optional baud rate update
– Synchronization validation
• 231 programmable transmission rates with 7 fractional bits
• Wakeup on LINRX dominant level from transceiver
• Automatic wakeup support
– Wakeup signal generation
– Expiration times on wakeup signals
• Automatic bus idle detection
• Error detection
– Bit error
– Bus error
– No-response error
– Checksum error
– Synchronization field error
– Parity error
• Capability to use direct memory access (DMA) for transmit and receive data
• Two interrupt lines with priority encoding for:
– Receive
– Transmit
– ID, error, and status
• Support for LIN 2.0 checksum
• Enhanced synchronizer finite state machine (FSM) support for frame processing
• Enhanced handling of extended frames

Product Folder Links: TMS320F280025 TMS320F280025-Q1 TMS320F280025C TMS320F280025C-Q1

• Enhanced baud rate generator

• Update wakeup/go to sleep
Figure 7-62 shows the LIN block diagram.

READ DATA BUS

WRITE DATA BUS

ADDRESS BUS

CHECKSUM
CALCULATOR INTERFACE

ID PARTY
CHECKER

BIT
MONITOR

TXRX ERROR
DETECTOR (TED)

TIME-OUT
CONTROL

COUNTER

LINRX/
SCIRX COMPARE

LINTX/ MASK 8 RECEIVE DMA

SCITX FSM
FILTER BUFFERS CONTROL
8 TRANSMIT
SYNCHRONIZER
BUFFERS

Figure 7-62. LIN Block Diagram

7.14.7 Fast Serial Interface (FSI)

The Fast Serial Interface (FSI) module is a serial communication peripheral capable of reliable and robust high-
speed communications. The FSI is designed to ensure data robustness across many system conditions such as
chip-to-chip as well as board-to-board across an isolation barrier. Payload integrity checks such as CRC, start-
and end-of-frame patterns, and user-defined tags, are encoded before transmit and then verified after receipt
without additional CPU interaction. Line breaks can be detected using periodic transmissions, all managed and
monitored by hardware. The FSI is also tightly integrated with other control peripherals on the device. To ensure
that the latest sensor data or control parameters are available, frames can be transmitted on every control loop
period. An integrated skew-compensation block has been added on the receiver to handle skew that may occur
between the clock and data signals due to a variety of factors, including trace-length mismatch and skews
induced by an isolation chip. With embedded data robustness checks, data-link integrity checks, skew
compensation, and integration with control peripherals, the FSI can enable high-speed, robust communication in
any system. These and many other features of the FSI follow.
The FSI module includes the following features:
• Independent transmitter and receiver cores
• Source-synchronous transmission
• Dual data rate (DDR)
• One or two data lines
• Programmable data length
• Skew adjustment block to compensate for board and system delay mismatches
• Frame error detection
• Programmable frame tagging for message filtering
• Hardware ping to detect line breaks during communication (ping watchdog)
• Two interrupts per FSI core
• Externally triggered frame generation
• Hardware- or software-calculated CRC
• Embedded ECC computation module
• Register write protection
• DMA support
• SPI compatibility mode (limited features available)
Operating the FSI at maximum speed (50 MHz) at dual data rate (100 Mbps) may require the integrated skew
compensation block to be configured according to the specific operating conditions on a case-by-case basis.
The Fast Serial Interface (FSI) Skew Compensation Application Report provides example software on how to
configure and set up the integrated skew compensation block on the Fast Serial Interface.
The FSI consists of independent transmitter (FSITX) and receiver (FSIRX) cores. The FSITX and FSIRX cores
are configured and operated independently. The features available on the FSITX and FSIRX are described in
Section 7.14.7.1 and Section 7.14.7.2, respectively.

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7.14.7.1 FSI Transmitter

The FSI transmitter module handles the framing of data, CRC generation, signal generation of TXCLK, TXD0,
and TXD1, as well as interrupt generation. The operation of the transmitter core is controlled and configured
through programmable control registers. The transmitter control registers let the CPU program, control, and
monitor the operation of the FSI transmitter. The transmit data buffer is accessible by the CPU and the DMA.
The transmitter has the following features:
• Automated ping frame generation
• Externally triggered ping frames
• Externally triggered data frames
• Software-configurable frame lengths
• 16-word data buffer
• Data buffer underrun and overrun detection
• Hardware-generated CRC on data bits
• Software ECC calculation on select data
• DMA support
Figure 7-63 shows the FSITX CPU interface. Figure 7-64 shows the high-level block diagram of the FSITX. Not
all data paths and internal connections are shown. This diagram provides a high-level overview of the internal
modules present in the FSITX.
PLLRAWCLK

PCLKCR18

SYSCLK

SYSRSN

C28x ePIE

FSITXyINT1

FSITXyINT2
Register Interface

Registers

FSITXyCLK
GPIO MUX

FSITXyD0
DMA FSITX
FSITXyD1
FSITXyDMA
Trigger Muxes(A)

A. The signals connected to the trigger muxes are described in the External Frame Trigger Mux section of the Fast Serial Interface (FSI)
chapter in the TMS320F28002x Real-Time Microcontrollers Technical Reference Manual.

Figure 7-63. FSITX CPU Interface

FSITX
PLLRAWCLK

SYSRSN

SYSCLK
FSI Mode:
Transmit Clock TXCLKIN
TXCLK = TXCLKIN/2
Generator SPI Signaling Mode:
Register Interface TXCLK = TXCLKIN

Core Reset
FSITXINT1
Control Registers, TXCLK
FSITXINT2 Interrupt Management
FSITX_DMA_EVT Ping Time-out Counter
TXD0
Transmitter Core

External Frame Triggers TXD1

Transmit Data
Buffer

ECC Logic

Figure 7-64. FSITX Block Diagram

7.14.7.1.1 FSITX Electrical Data and Timing

Section 7.14.7.1.1.1 lists the FSITX switching characteristics. Figure 7-65 shows the FSITX timings.
7.14.7.1.1.1 FSITX Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
NO. PARAMETER MIN MAX UNIT
1 tc(TXCLK) Cycle time, TXCLK 20 ns
2 tw(TXCLK) Pulse width, TXCLK low or TXCLK high (0.5tc(TXCLK)) – 1 (0.5tc(TXCLK)) + 1 ns
Delay time, TXCLK rising or falling toTXD
3 td(TXCLK–TXD) (0.25tc(TXCLK)) – 2 (0.25tc(TXCLK)) + 2 ns
valid
Delay skew introduced between TXCLK-
TDM1 tskew(TDM_CLK-TDM_Dx ) -2 2 ns
TDM_CLK delay and TXDx-TDM_Dx delays

7.14.7.1.1.2 FSITX Timings

FSITXCLK 2

FSITXD0

FSITXD1
3

Figure 7-65. FSITX Timings

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7.14.7.2 FSI Receiver

The receiver module interfaces to the FSI clock (RXCLK), and data lines (RXD0 and RXD1) after they pass
through an optional programmable delay line. The receiver core handles the data framing, CRC computation,
and frame-related error checking. The receiver bit clock and state machine are run by the RXCLK input, which is
asynchronous to the device system clock.
The receiver control registers let the CPU program, control, and monitor the operation of the FSIRX. The receive
data buffer is accessible by the CPU, HIC, and the DMA.
The receiver core has the following features:
• 16-word data buffer
• Multiple supported frame types
• Ping frame watchdog
• Frame watchdog
• CRC calculation and comparison in hardware
• ECC detection
• Programmable delay line control on incoming signals
• DMA support
• SPI compatibility mode
Figure 7-66 shows the FSIRX CPU interface. Figure 7-67 provides a high-level overview of the internal modules
present in the FSIRX. Not all data paths and internal connections are shown.
PCLKCR18

SYSCLK

SYSRSN

C28x ePIE

FSIRXyINT1
FSIRXyINT2
Register Interface

Registers

FSIRXyCLK
GPIO MUX

FSIRXyD0
DMA FSIRX
FSIRXyD1

FSIRXyDMA

Figure 7-66. FSIRX CPU Interface

FSIRX
SYSRSn

SYSCLK

Frame Watchdog

Register Interface
Core Reset
FSIRXINT1 Control Registers,
FSIRXINT2 Interrupt Management
RXCLK
FSIRX_DMA_EVT Ping Watchdog
Receiver Core Skew
RXD0
Control

RXD1

Receive Data
Buffer
ECC Check
Logic

Figure 7-67. FSIRX Block Diagram

7.14.7.2.1 FSIRX Electrical Data and Timing

Section 7.14.7.2.1.1 lists the FSIRX timing requirements. Section 7.14.7.2.1.2 lists the FSIRX switching
characteristics. Figure 7-68 shows the FSIRX Timings.
7.14.7.2.1.1 FSIRX Timing Requirements
NO. MIN MAX UNIT
1 tc(RXCLK) Cycle time, RXCLK 20 ns
2 tw(RXCLK) Pulse width, RXCLK low or RXCLK high. 0.35tc(RXCLK) 0.65tc(RXCLK) ns
Setup time with respect to RXCLK, applies to
3 tsu(RXCLK–RXD) 1.7 ns
both edges of the clock
Hold time with respect to RXCLK, applies to
4 th(RXCLK–RXD) 2 ns
both edges of the clock

7.14.7.2.1.2 FSIRX Switching Characteristics

NO. PARAMETER MIN MAX UNIT
RXCLK delay compensation at
1 td(RXCLK) 10 30 ns
RX_DLYLINE_CTRL[RXCLK_DLY]=31
RXD0 delay compensation at
2 td(RXD0) 10 30 ns
RX_DLYLINE_CTRL[RXD0_DLY]=31
RXD1 delay compensation
3 td(RXD1) 10 30 ns
at RX_DLYLINE_CTRL[RXD1_DLY]=31
Incremental delay of each delay line element
4 td(DELAY_ELEMENT) 0.3 1 ns
for RXCLK, RXD0, and RXD1

Product Folder Links: TMS320F280025 TMS320F280025-Q1 TMS320F280025C TMS320F280025C-Q1

7.14.7.2.1.3 FSIRX Timings

FSIRXCLK 2

FSIRXD0

FSIRXD1
3

Figure 7-68. FSIRX Timings

7.14.7.3 FSI SPI Compatibility Mode

The FSI supports a SPI compatibility mode to enable communication with programmable SPI devices. In this
mode, the FSI transmits its data in the same manner as a SPI in a single clock configuration mode. While the
FSI is able to physically interface with a SPI in this mode, the external device must be able to encode and
decode an FSI frame to communicate successfully. This is because the FSI transmits all SPI frame phases with
the exception of the preamble and postamble. The FSI provides the same data validation and frame checking as
if it was in standard FSI mode, allowing for more robust communication without consuming CPU cycles. The
external SPI is required to send all relevant information and can access standard FSI features such as the ping
frame watchdog on the FSIRX, frame tagging, or custom CRC values. The list of features of SPI compatibility
mode follows:
• Data will transmit on rising edge and receive on falling edge of the clock.
• Only 16-bit word size is supported.
• TXD1 will be driven like an active-low chip-select signal. The signal will be low for the duration of the full
frame transmission.
• No receiver chip-select input is required. RXD1 is not used. Data is shifted into the receiver on every active
clock edge.
• No preamble or postamble clocks will be transmitted. All signals return to the idle state after the frame phase
is finished.
• It is not possible to transmit in the SPI slave configuration because the FSI TXCLK cannot take an external
clock source.
7.14.7.3.1 FSITX SPI Signaling Mode Electrical Data and Timing
Section 7.14.7.3.1.1 lists the FSITX SPI signaling mode switching characteristics. Figure 7-69 shows the FSITX
SPI signaling mode timings. Special timings are not required for the FSIRX in SPI signaling mode. FSIRX
timings listed in Section 7.14.7.2.1.1 are applicable in SPI compatibility mode. Setup and Hold times are only
valid on the falling edge of FSIRXCLK because this is the active edge in SPI signaling mode.
7.14.7.3.1.1 FSITX SPI Signaling Mode Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
NO. PARAMETER MIN MAX UNIT
1 tc(TXCLK) Cycle time, TXCLK 20 ns
2 tw(TXCLK) Pulse width, TXCLK low or TXCLK high (0.5tc(TXCLK)) – 1 (0.5tc(TXCLK)) + 1 ns
3 td(TXCLKH–TXD0) Delay time, TXD0 valid after TXCLK high 3 ns
4 td(TXD1-TXCLK) Delay time, TXCLK high after TXD1 low tw(TXCLK) – 3 ns
5 td(TXCLK-TXD1) Delay time, TXD1 high after TXCLK low tw(TXCLK) ns

7.14.7.3.1.2 FSITX SPI Signaling Mode Timings

2
FSITXCLK
3

FSITXD0

5
4
FSITXD1

Figure 7-69. FSITX SPI Signaling Mode Timings

Product Folder Links: TMS320F280025 TMS320F280025-Q1 TMS320F280025C TMS320F280025C-Q1

7.14.8 Host Interface Controller (HIC)

The HIC module allows an external host controller to directly access resources of the device by emulating the
ASRAM protocol. It has two modes of operation: direct access and mailbox access. In direct access mode,
device resources is written to and read from directly by the external host. In mailbox access mode, external host
and device write to and read from a buffer and notify each other when the buffer write/read is complete. For
security reasons, the HIC has to be enabled by the device before the external host can access it. Figure 7-70
shows the block diagram of the HIC.
Features of the HIC include:
• Configurable I/O data lines of 8 bits and 16 bits
• Direct and mailbox access modes
• 8 address lines and 8 configurable base addresses for a total of 2048 possible addressable regions
• Two 64-byte buffers for external host and device when using mailbox access mode
• Interrupt generation on buffer full/empty
• High throughput
• Trigger HIC activity from other peripherals
• Error indicators to the system or interface
Legend
HIC Pins
HIC Registers
HIC
I/O Interface

A[7:0] A[31:0]

D[15:0] H2DINT to PIE D2HINT to Pin WDATA[31:0]

Memory Mapped HIC

nBE[1:0] Configuration Interface RDATA[31:0]
Host Device
nCS To To
CTRL Regs
Device Host
STATUS Regs
nWE
BASE_ADDR0
nOE BASE_ADDR1
.
Mailbox Mailbox
.
BASESEL[2:0] Buffer Buffer
BASE_ADDRn

nRDY

EVT_TRIGGER[15:0]

Figure 7-70. HIC Block Diagram

7.14.8.1 HIC Electrical Data and Timing

Section 7.14.8.1.1 lists the HIC timing requirements. Section 7.14.8.1.2 lists the HIC switching characteristics.
Figure 7-71 shows the read/write operation with nOE and nWE pins. Figure 7-72 shows the read/write operation
with RnW pin.
7.14.8.1.1 HIC Timing Requirements
over operating free-air temperature range (unless otherwise noted)
REFID MIN MAX UNIT
Read/Write Parameters with nOE and nWE pins - Dual Read/Write pins
T1 tsu(ABBV-OEV) Setup time, A/BASESEL/nBE before nOE active 0 ns
T2 tsu(ABBV-WEV) Setup time, A/BASESEL/nBE before nWE active 0 ns
T3 tsu(CSV-OEV) Setup time, nCS active before nOE active 0.5tc(SYSCLK) ns
T4 tsu(CSV-WEV) Setup time, nCS active before nWE active 0.5tc(SYSCLK) ns
T5 th(ABBV-OEIV) Hold time, A/BASESEL/nBE/nCS after nOE inactive 6 ns
T6 th(ABBV-WEIV) Hold time, A/BASESEL/nBE/nCS after nWE inactive 6 ns
T7 tw(OEV) Active pulse width of nOE (Read)(1) 4tc(SYSCLK) ns
T8 tw(WEV) Active pulse width of nWE (Write) 4tc(SYSCLK) ns
T9 tw(CSIV) Inactive pulse width of nCS(2) 3tc(SYSCLK) ns
T10 tw(OEIV) Inactive Read pulse width of nOE(2) 3tc(SYSCLK) ns
T11 tw(WEIV) Inactive Write pulse width of nWE(2) 3tc(SYSCLK) ns
T12 tsu(DV-WEV) Setup time, D before nWE active 0 ns
T13 th(DV-WEIV) Hold time, D after nWE inactive 6 ns
Read/Write Parameters with RnW pin - Single Read/Write pin
T14 tsu(ABBV-CSV) Setup time, A/BASESEL/nBE before nCS active 0 ns
T15 tsu(RNWV-CSV) Setup time, RnW before nCS active 0.5tc(SYSCLK) ns
T16 th(ABBV-CSIV) Hold time, A/BASESEL/nBE/RnW after nCS inactive 6 ns
T17 tw(CSV_RD) Active pulse width of nCS for read operation(1) 4tc(SYSCLK) ns
T18 tw(CSV_WR) Active pulse width of nCS for write operation 4tc(SYSCLK) ns
T19 tw(CSIV) Inactive pulse width of nCS(2) 3tc(SYSCLK) ns
T20 tw(RNWIV) Inactive pulse width of RnW(2) 3tc(SYSCLK) ns
T21 tsu(DV-CSV) Setup time, D before nCS active 0 ns
T22 th(DV-CSIV) Hold time, D after nCS inactive 5 ns

(1) For accesses to the device region, additional 2 SYSCLK cycles are required.
(2) For accesses to the device region with nRDY pin, additional SYSCLK cycle is required.

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7.14.8.1.2 HIC Switching Characteristics

over operating free-air temperature range (unless otherwise noted)
REFID PARAMETER MIN MAX UNIT
Read/Write Parameters with nOE and nWE pins
S1 td(OEV-DV) Output data delay time : nOE to D output valid (1) 3tc(SYSCLK) 4tc(SYSCLK) + 14 ns
S2 td(OEIV-DIV) Output data hold time : nOE invalid to D output invalid (tri-state) 1tc(SYSCLK) 2tc(SYSCLK) + 14 ns
S3 td(OEV-RDYV) Read Ready delay time : nOE to nRDY output valid 0 11 ns
S4 td(WEV-RDYV) Write Ready delay time : nWE to nRDY output valid 0 11 ns
S5 td(RDYV-DV) Ready to Data delay time : nRDY output valid to D output valid -3 3 ns
S6 tw(RDYACT) Active pulse width of nRDY output 2tc(SYSCLK) ns
Read/Write Parameters with RnW pin
S7 td(CSV-DV) Output delay time : nCS active to D output valid (1) 3tc(SYSCLK) 4tc(SYSCLK) + 14 ns
S8 td(CSIV-DIV) Output hold time : nCS inactive to D output invalid (tri-state) 1tc(SYSCLK) 2tc(SYSCLK) + 14 ns
S9 td(CSV-RDYV) Output delay time : nCS to nRDY output valid 0 11 ns
S10 td(RDYV-DV) Ready to Data delay time : nRDY output valid to D output valid -3 3 ns
S11 tw(RDYACT) Active pulse width of nRDY output 2tc(SYSCLK) ns

(1) Applicable to mailbox accesses only. Direct memory map (Device) accesses are qualified with nRDY pin.

7.14.8.1.3 HIC Timing Diagrams

SETUP SIGNALS
nCS T9

A[7:0]
BASESEL[2:0]
nBE[3:0]
READ SIGNALS
T1 T5
T3 T10
nOE
T7

S1 S2
D[15:0]

7
WRITE SIGNALS
T2 T6
T4 T11
nWE T8

T12 T13
D[15:0]

READY/WAIT SIGNAL
S5
nRDY S3
S6
S4

Figure 7-71. Read/Write Operation With nOE and nWE Pins

SETUP SIGNALS

nCS T19
T17 or T18

T14 T16
A[7:0]
BASESEL[2:0]
nBE[3:0]
READ SIGNALS

T15 T20
RnW
(Read)
S7 S8
D[15:0]

S10
WRITE SIGNALS
T15 T20
RnW
(Write)
T21 T22
D[15:0]

READY/WAIT SIGNAL
S9
nRDY
S11

Figure 7-72. Read/Write Operation With RnW Pin

Product Folder Links: TMS320F280025 TMS320F280025-Q1 TMS320F280025C TMS320F280025C-Q1

8 Detailed Description
8.1 Overview
C2000™ 32-bit microcontrollers are optimized for processing, sensing, and actuation to improve closed-loop
performance in real-time control applications such as industrial motor drives; solar inverters and digital power;
electrical vehicles and transportation; motor control; and sensing and signal processing.
The TMS320F28002x (F28002x) is a powerful 32-bit floating-point microcontroller unit (MCU) that lets designers
incorporate crucial control peripherals, differentiated analog, and nonvolatile memory on a single device.
The real-time control subsystem is based on TI’s 32-bit C28x CPU, which provides 100 MHz of signal processing
performance. The C28x CPU is further boosted by the new TMU extended instruction set, which enables fast
execution of algorithms with trigonometric operations commonly found in transforms and torque loop
calculations; and the VCRC extended instruction set, which reduces the latency for complex math operations
commonly found in encoded applications.
The F28002x supports up to 128KB (64KW) of flash memory in one bank. Up to 24KB (12KW) of on-chip SRAM
is also available in blocks of 4KB (2KW) for efficient system partitioning. Flash ECC, SRAM ECC/parity, and
dual-zone security are also supported.
High-performance analog blocks are integrated on the F28002x real-time MCU to further enable system
consolidation. Two separate 12-bit ADCs provide precise and efficient management of multiple analog signals,
which ultimately boosts system throughput. Four analog comparator modules provide continuous monitoring of
input voltage levels for trip conditions.
The TMS320C2000™ devices contain industry-leading control peripherals with frequency-independent ePWM/
HRPWM and eCAP allow for a best-in-class level of control to the system.
Connectivity is supported through various industry-standard communication ports (such as SPI, SCI, I2C,
PMBus, LIN, and CAN) and offers multiple muxing options for optimal signal placement in a variety of
applications. New to the C2000™ platform is Host Interface Controller (HIC), a high throughput interface that
allows an external host to access resources of the TMS320F28002x. Additionally, in an industry first, the FSI
enables high-speed, robust communication to complement the rich set of peripherals that are embedded in the
device.
A specially enabled device variant, TMS320F28002xC, allows access to the Configurable Logic Block (CLB) for
additional interfacing features and allows access to the secure ROM, which includes a library to enable
InstaSPIN-FOC™. See Table 5-1 for more information.
The Embedded Real-Time Analysis and Diagnostic (ERAD) module enhances the debug and system analysis
capabilities of the device by providing additional hardware breakpoints and counters for profiling.
To learn more about the C2000 real-time MCUs, visit the C2000™ real-time control MCUs page.

8.2 Functional Block Diagram

Figure 8-1 shows the CPU system and associated peripherals.

Boot ROM Secure Memories

shown in Red
C28x CPU Secure ROM

FPU32 Bus Legend

FINTDIV Flash Bank0
16 Sectors CPU
TMU
VCRC 64 KW (128 KB) DMA
HIC

CPU Timers BGCRC

DCC
DCSM M0-M1 RAM
ePIE 2 KW (4 KB)
ERAD
BGCRC
LS4-LS7 RAM
8 KW (16 KB)
Crystal Oscillator HIC
INTOSC1, INTOSC2
GS0 RAM
PLL DMA
2 KW (4 KB)
6 Channles

PF1 PF3 PF4 PF2 PF7 PF8 PF9

Figure 8-1. Functional Block Diagram

Product Folder Links: TMS320F280025 TMS320F280025-Q1 TMS320F280025C TMS320F280025C-Q1

8.3 Memory
8.3.1 Memory Map
The Memory Map table describes the memory map. See the Memory Controller Module section of the System
Control chapter in the TMS320F28002x Real-Time Microcontrollers Technical Reference Manual.
Table 8-1. Memory Map
START HIC DMA ECC/ ACCESS
MEMORY SIZE END ADDRESS SECURITY
ADDRESS ACCESS ACCESS PARITY PROTECTION
M0 RAM 1K x 16 0x0000 0000 0x0000 03FF - - ECC Yes -
M1 RAM 1K x 16 0x0000 0400 0x0000 07FF - - ECC Yes -
PieVectTable 512 x 16 0x0000 0D00 0x0000 0EFF - - - - -
LS4 RAM 2K x 16 0x0000 A000 0x0000 A7FF - - ECC Yes Yes
LS5 RAM 2K x 16 0x0000 A800 0x0000 AFFF - - ECC Yes Yes
LS6 RAM 2K x 16 0x0000 B000 0x0000 B7FF - - ECC Yes Yes
LS7 RAM 2K x 16 0x0000 B800 0x0000 BFFF - - ECC Yes Yes
GS0 RAM 2K x 16 0x0000 C000 0x0000 C7FF Yes Yes Parity Yes -
CAN A Message RAM 2K x 16 0x0004 9000 0x0004 97FF - - Parity - -
TI OTP(1) 1K x 16 0x0007 0000 0x0007 03FF - - ECC - -
User OTP 1K x 16 0x0007 8000 0x0007 83FF - - ECC - Yes
Flash 64K x 16 0x0008 0000 0x0008 FFFF - - ECC - Yes
Secure ROM 32K x 16 0x003E 8000 0x003E FFFF - - Parity - Yes
Boot ROM 64K x 16 0x003F 0000 0x003F FFFF - - Parity - -
Pie Vector Fetch Error
1 x 16 0x003F FFBE 0x003F FFBF - - Parity - -
(part of Boot ROM)
Default Vectors
64 x 16 0x003F FFC0 0x003F FFFF - - Parity - -
(part of Boot ROM)

(1) TI OTP is for TI internal use only.

8.3.1.1 Dedicated RAM (Mx RAM)

The CPU subsystem has two dedicated ECC-capable RAM blocks: M0 and M1. These memories are small
nonsecure blocks that are tightly coupled with the CPU (that is, only the CPU has access to them).
8.3.1.2 Local Shared RAM (LSx RAM)
Local shared RAMs (LSx RAMs) are accessible to the CPU, HIC, and BGCRC. All LSx RAM blocks have ECC.
These memories are secure and have CPU access protection (CPU write/CPU fetch).
8.3.1.3 Global Shared RAM (GSx RAM)
Global shared RAMs (GSx RAMs) are accessible from the CPU, HIC, and DMA. The CPU, HIC, and DMA have
full read and write access to these memories. All GSx RAM blocks have parity. The GSx RAMs have access
protection (CPU write/CPU fetch/DMA write/HIC write).

8.3.2 Flash Memory Map

On the F28002x devices one flash bank (128KB [64KW]) is available. Code to program the flash should be
executed out of RAM, there should not be any kind of access to the flash bank when an erase or program
operation is in progress. Table 8-2 lists the addresses of flash sectors available for each part number.
8.3.2.1 Addresses of Flash Sectors
Table 8-2. Addresses of Flash Sectors
ADDRESS ECC ADDRESS
PART NUMBER SECTOR
SIZE START END SIZE START END
OTP Sectors
TI OTP 1K x 16 0x0007 0000 0x0007 03FF 128 x 16 0x0107 0000 0x0107 007F
All F28002x
DCSM OTP 1K x 16 0x0007 8000 0x0007 83FF 128 x 16 0x0107 1000 0x0107 107F
Bank 0 Sectors
Sector 0 4K x 16 0x0008 0000 0x0008 0FFF 512 x 16 0x0108 0000 0x0108 01FF
Sector 1 4K x 16 0x0008 1000 0x0008 1FFF 512 x 16 0x0108 0200 0x0108 03FF
All F28002x
Sector 2 4K x 16 0x0008 2000 0x0008 2FFF 512 x 16 0x0108 0400 0x0108 05FF
Sector 3 4K x 16 0x0008 3000 0x0008 3FFF 512 x 16 0x0108 0600 0x0108 07FF
Sector 4 4K x 16 0x0008 4000 0x0008 4FFF 512 x 16 0x0108 0800 0x0108 09FF

F280025, Sector 5 4K x 16 0x0008 5000 0x0008 5FFF 512 x 16 0x0108 0A00 0x0108 0BFF
F280023 Sector 6 4K x 16 0x0008 6000 0x0008 6FFF 512 x 16 0x0108 0C00 0x0108 0DFF
Sector 7 4K x 16 0x0008 7000 0x0008 7FFF 512 x 16 0x0108 0E00 0x0108 0FFF
Sector 8 4K x 16 0x0008 8000 0x0008 8FFF 512 x 16 0x0108 1000 0x0108 11FF
Sector 9 4K x 16 0x0008 9000 0x0008 9FFF 512 x 16 0x0108 1200 0x0108 13FF
Sector 10 4K x 16 0x0008 A000 0x0008 AFFF 512 x 16 0x0108 1400 0x0108 15FF
Sector 11 4K x 16 0x0008 B000 0x0008 BFFF 512 x 16 0x0108 1600 0x0108 17FF
F280025
Sector 12 4K x 16 0x0008 C000 0x0008 CFFF 512 x 16 0x0108 1800 0x0108 19FF
Sector 13 4K x 16 0x0008 D000 0x0008 DFFF 512 x 16 0x0108 1A00 0x0108 1BFF
Sector 14 4K x 16 0x0008 E000 0x0008 EFFF 512 x 16 0x0108 1C00 0x0108 1DFF
Sector 15 4K x 16 0x0008 F000 0x0008 FFFF 512 x 16 0x0108 1E00 0x0108 1FFF

Product Folder Links: TMS320F280025 TMS320F280025-Q1 TMS320F280025C TMS320F280025C-Q1

8.3.3 Peripheral Registers Memory Map

The Peripheral Registers Memory Map (C28x) table lists the peripheral registers.
Table 8-3. Peripheral Registers Memory Map (C28x)
Bit Field Name Pipeline DMA HIC
DriverLib Name Base Address
Instance Structure Protected Access Access

Peripheral Frame 0 (PF0)

AdcaResultRegs ADC_RESULT_REGS ADCARESULT_BASE 0x0000_0B00 - YES YES
AdccResultRegs ADC_RESULT_REGS ADCCRESULT_BASE 0x0000_0B40 - YES YES
CpuTimer0Regs CPUTIMER_REGS CPUTIMER0_BASE 0x0000_0C00 - - -
CpuTimer1Regs CPUTIMER_REGS CPUTIMER1_BASE 0x0000_0C08 - - -
CpuTimer2Regs CPUTIMER_REGS CPUTIMER2_BASE 0x0000_0C10 - - -
PieCtrlRegs PIE_CTRL_REGS PIECTRL_BASE 0x0000_0CE0 - - -
DmaRegs DMA_REGS DMA_BASE 0x0000_1000 - - -
Dmach1Regs DMA_CH_REGS DMA_CH1_BASE 0x0000_1020 - - -
Dmach2Regs DMA_CH_REGS DMA_CH2_BASE 0x0000_1040 - - -
Dmach3Regs DMA_CH_REGS DMA_CH3_BASE 0x0000_1060 - - -
Dmach4Regs DMA_CH_REGS DMA_CH4_BASE 0x0000_1080 - - -
Dmach5Regs DMA_CH_REGS DMA_CH5_BASE 0x0000_10A0 - - -
Dmach6Regs DMA_CH_REGS DMA_CH6_BASE 0x0000_10C0 - - -
Peripheral Frame 1 (PF1)
Clb1LogicCfgRegs CLB_LOGIC_CONFIG_REGS CLB1_LOGICCFG_BASE 0x0000_3000 - YES YES
Clb1LogicCtrlRegs CLB_LOGIC_CONTROL_REGS CLB1_LOGICCTRL_BASE 0x0000_3100 - YES YES
Clb1DataExchRegs CLB_DATA_EXCHANGE_REGS CLB1_DATAEXCH_BASE 0x0000_3180 - YES YES
Clb2LogicCfgRegs CLB_LOGIC_CONFIG_REGS CLB2_LOGICCFG_BASE 0x0000_3200 - YES YES
Clb1DataExchRegs CLB_DATA_EXCHANGE_REGS CLB1_DATAEXCH_BASE 0x0000_3300 - YES YES
Clb2LogicCfgRegs CLB_LOGIC_CONFIG_REGS CLB2_LOGICCFG_BASE 0x0000_3380 - YES YES
EPwm1Regs EPWM_REGS EPWM1_BASE 0x0000_4000 YES YES YES
EPwm2Regs EPWM_REGS EPWM2_BASE 0x0000_4100 YES YES YES
EPwm3Regs EPWM_REGS EPWM3_BASE 0x0000_4200 YES YES YES
EPwm4Regs EPWM_REGS EPWM4_BASE 0x0000_4300 YES YES YES
EPwm5Regs EPWM_REGS EPWM5_BASE 0x0000_4400 YES YES YES
EPwm6Regs EPWM_REGS EPWM6_BASE 0x0000_4500 YES YES YES
EPwm7Regs EPWM_REGS EPWM7_BASE 0x0000_4600 YES YES YES
EQep1Regs EQEP_REGS EQEP1_BASE 0x0000_5100 YES YES YES
EQep2Regs EQEP_REGS EQEP2_BASE 0x0000_5140 YES YES YES
ECap1Regs ECAP_REGS ECAP1_BASE 0x0000_5200 YES YES YES
ECap2Regs ECAP_REGS ECAP2_BASE 0x0000_5240 YES YES YES
ECap3Regs ECAP_REGS ECAP3_BASE 0x0000_5280 YES YES YES
Hrcap3Regs HRCAP_REGS HRCAP3_BASE 0x0000_52A0 YES YES YES
Cmpss1Regs CMPSS_REGS CMPSS1_BASE 0x0000_5C80 YES YES YES
Cmpss2Regs CMPSS_REGS CMPSS2_BASE 0x0000_5CA0 YES YES YES
Cmpss3Regs CMPSS_REGS CMPSS3_BASE 0x0000_5CC0 YES YES YES
Cmpss4Regs CMPSS_REGS CMPSS4_BASE 0x0000_5CE0 YES YES YES
Peripheral Frame 2 (PF2)
SpiaRegs SPI_REGS SPIA_BASE 0x0000_6100 YES YES YES
SpibRegs SPI_REGS SPIB_BASE 0x0000_6110 YES YES YES
BgcrcCpuRegs BGCRC_REGS BGCRC_CPU_BASE 0x0000_6340 YES YES YES
PmbusaRegs PMBUS_REGS PMBUSA_BASE 0x0000_6400 YES YES YES
HicRegs HIC_CFG_REGS HIC_BASE 0x0000_6500 YES YES YES
FsiTxaRegs FSI_TX_REGS FSITXA_BASE 0x0000_6600 YES YES YES
FsiRxaRegs FSI_RX_REGS FSIRXA_BASE 0x0000_6680 YES YES YES

Table 8-3. Peripheral Registers Memory Map (C28x) (continued)

Bit Field Name Pipeline DMA HIC
DriverLib Name Base Address
Instance Structure Protected Access Access

Peripheral Frame 3 (PF3)

AdcaRegs ADC_REGS ADCA_BASE 0x0000_7400 YES - -
AdccRegs ADC_REGS ADCC_BASE 0x0000_7500 YES - -
Peripheral Frame 4 (PF4)
InputXbarRegs INPUT_XBAR_REGS INPUTXBAR_BASE 0x0000_7900 YES - -
XbarRegs XBAR_REGS XBAR_BASE 0x0000_7920 YES - -
SyncSocRegs SYNC_SOC_REGS SYNCSOC_BASE 0x0000_7940 YES - -
InputXbar2Regs INPUT_XBAR_REGS INPUTXBAR2_BASE 0x0000_7960 YES - -
DmaClaSrcSelRegs DMA_CLA_SRC_SEL_REGS DMACLASRCSEL_BASE 0x0000_7980 YES - -
EPwmXbarRegs EPWM_XBAR_REGS EPWMXBAR_BASE 0x0000_7A00 YES - -
ClbXbarRegs CLB_XBAR_REGS CLBXBAR_BASE 0x0000_7A40 YES - -
OutputXbarRegs OUTPUT_XBAR_REGS OUTPUTXBAR_BASE 0x0000_7A80 YES - -
OutputXbar2Regs OUTPUT_XBAR_REGS OUTPUTXBAR2_BASE 0x0000_7BC0 YES - -
GpioCtrlRegs GPIO_CTRL_REGS GPIOCTRL_BASE 0x0000_7C00 YES - -
GpioDataRegs GPIO_DATA_REGS GPIODATA_BASE 0x0000_7F00 YES - -
GpioDataReadRegs GPIO_DATA_READ_REGS GPIODATAREAD_BASE 0x0000_7F80 YES - YES
Peripheral Frame 5 (PF5)
DevCfgRegs DEV_CFG_REGS DEVCFG_BASE 0x0005_D000 YES - -
ClkCfgRegs CLK_CFG_REGS CLKCFG_BASE 0x0005_D200 YES - -
CpuSysRegs CPU_SYS_REGS CPUSYS_BASE 0x0005_D300 YES - -
PeriphAcRegs PERIPH_AC_REGS PERIPHAC_BASE 0x0005_D500 YES - -
AnalogSubsysRegs ANALOG_SUBSYS_REGS ANALOGSUBSYS_BASE 0x0005_D700 YES - -
DcsmBank0Z1Regs DCSM_BANK0_Z1_REGS DCSM_BANK0_Z1_BASE 0x0005_F000 YES - -
DcsmBank0Z2Regs DCSM_BANK0_Z2_REGS DCSM_BANK0_Z2_BASE 0x0005_F040 YES - -
DcsmCommonRegs DCSM_COMMON_REGS DCSMCOMMON_BASE 0x0005_F070 YES - -
DcsmCommon2Regs DCSM_COMMON2_REGS DCSMCOMMON2_BASE 0x0005_F080 YES - -
Peripheral Frame 6 (PF6)
MemCfgRegs MEM_CFG_REGS MEMCFG_BASE 0x0005_F400 YES - -
AccessProtectionRegs ACCESSPROTECTION_REGS ACCESSPROTECTION_BASE 0x0005_F500 YES - -
MemoryErrorRegs MEMORY_ERROR_REGS MEMORYERROR_BASE 0x0005_F540 YES - -
RomWaitStateRegs ROM_WAIT_STATE_REGS ROMWAITSTATE_BASE 0x0005_F580 YES - -
RomPrefetchRegs ROM_PREFETCH_REGS ROMPREFETCH_BASE 0x0005_F588 YES - -
Flash0CtrlRegs FLASH_CTRL_REGS FLASH0CTRL_BASE 0x0005_F800 YES - -
Flash0EccRegs FLASH_ECC_REGS FLASH0ECCREGS_BASE 0x0005_FB00 YES - -
Peripheral Frame 7 (PF7)
CanaRegs CAN_REGS CANA_BASE 0x0004_8000 YES YES YES
CanaMboxRegs CAN_MBOX CANAMBOX_BASE 0x0004_9000 YES YES YES
HwbistRegs HWBIST_REGS HWBIST_BASE 0x0005_E000 YES - -
MpostRegs MPOST_REGS MPOST_BASE 0x0005_E200 YES - -
Dcc0Regs DCC_REGS DCC0_BASE 0x0005_E700 YES - -
Dcc1Regs DCC_REGS DCC1_BASE 0x0005_E740 YES - -
EradGlobalRegs ERAD_GLOBAL_REGS ERADGLOBAL_BASE 0x0005_E800 YES - -
EradHWBP1Regs ERAD_HWBP_REGS ERADHWBP1_BASE 0x0005_E900 YES - -
EradHWBP2Regs ERAD_HWBP_REGS ERADHWBP2_BASE 0x0005_E908 YES - -
EradHWBP3Regs ERAD_HWBP_REGS ERADHWBP3_BASE 0x0005_E910 YES - -
EradHWBP4Regs ERAD_HWBP_REGS ERADHWBP4_BASE 0x0005_E918 YES - -
EradHWBP5Regs ERAD_HWBP_REGS ERADHWBP5_BASE 0x0005_E920 YES - -
EradHWBP6Regs ERAD_HWBP_REGS ERADHWBP6_BASE 0x0005_E928 YES - -
EradHWBP7Regs ERAD_HWBP_REGS ERADHWBP7_BASE 0x0005_E930 YES - -

Product Folder Links: TMS320F280025 TMS320F280025-Q1 TMS320F280025C TMS320F280025C-Q1

Table 8-3. Peripheral Registers Memory Map (C28x) (continued)

Bit Field Name Pipeline DMA HIC
DriverLib Name Base Address
Instance Structure Protected Access Access

EradHWBP8Regs ERAD_HWBP_REGS ERADHWBP8_BASE 0x0005_E938 YES - -

EradCounter1Regs ERAD_COUNTER_REGS ERADCOUNTER1_BASE 0x0005_E980 YES - -
EradCounter2Regs ERAD_COUNTER_REGS ERADCOUNTER2_BASE 0x0005_E990 YES - -
EradCounter3Regs ERAD_COUNTER_REGS ERADCOUNTER3_BASE 0x0005_E9A0 YES - -
EradCounter4Regs ERAD_COUNTER_REGS ERADCOUNTER4_BASE 0x0005_E9B0 YES - -
EradCRCGlobalRegs ERAD_CRC_GLOBAL_REGS ERADCRCGLOBAL_BASE 0x0005_EA00 YES - -
EradCRC1Regs ERAD_CRC_REGS ERADCRC1_BASE 0x0005_EA10 YES - -
EradCRC2Regs ERAD_CRC_REGS ERADCRC2_BASE 0x0005_EA20 YES - -
EradCRC3Regs ERAD_CRC_REGS ERADCRC3_BASE 0x0005_EA30 YES - -
EradCRC4Regs ERAD_CRC_REGS ERADCRC4_BASE 0x0005_EA40 YES - -
EradCRC5Regs ERAD_CRC_REGS ERADCRC5_BASE 0x0005_EA50 YES - -
EradCRC6Regs ERAD_CRC_REGS ERADCRC6_BASE 0x0005_EA60 YES - -
EradCRC7Regs ERAD_CRC_REGS ERADCRC7_BASE 0x0005_EA70 YES - -
EradCRC8Regs ERAD_CRC_REGS ERADCRC8_BASE 0x0005_EA80 YES - -
Peripheral Frame 8 (PF8)
LinaRegs LIN_REGS LINA_BASE 0x0000_6A00 YES YES YES
LinbRegs LIN_REGS LINB_BASE 0x0000_6B00 YES YES YES
Peripheral Frame 9 (PF9)
WdRegs WD_REGS WD_BASE 0x0000_7000 YES - YES
NmiIntruptRegs NMI_INTRUPT_REGS NMI_BASE 0x0000_7060 YES - YES
XintRegs XINT_REGS XINT_BASE 0x0000_7070 YES - YES
SciaRegs SCI_REGS SCIA_BASE 0x0000_7200 YES - YES
I2caRegs I2C_REGS I2CA_BASE 0x0000_7300 YES - YES
I2cbRegs I2C_REGS I2CB_BASE 0x0000_7340 YES - YES

8.4 Identification
Table 8-4 lists the Device Identification Registers. Additional information on these device identification registers
can be found in the TMS320F28002x Real-Time Microcontrollers Technical Reference Manual.
Table 8-4. Device Identification Registers
NAME ADDRESS SIZE (x16) DESCRIPTION
Device part identification number
TMS320F280025 0x04FF 0500
TMS320F280025C 0x04FF 0500
PARTIDH 0x0005 D00A 2
TMS320F280023 0x04FD 0500
TMS320F280023C 0x04FD 0500
TMS320F280021 0x04FB 0500
Silicon revision number
REVID 0x0005 D00C 2 Revision 0 0x0000 0000
Revision A 0x0000 0001
Unique identification number. This number is different on each
individual device with the same PARTIDH. This unique number
UID_UNIQUE 0x0007 01F4 2
can be used as a serial number in the application. This number
is present only on TMS devices.

Product Folder Links: TMS320F280025 TMS320F280025-Q1 TMS320F280025C TMS320F280025C-Q1

8.5 Bus Architecture – Peripheral Connectivity

The Peripheral Connectivity table lists a broad view of the peripheral and configuration register accessibility from
each bus master.
Table 8-5. Peripheral Connectivity
PERIPHERAL C28 DMA HIC BGCRC
SYSTEM PERIPHERALS
CPU Timers Y
ERAD Y
GPIO Data Y Y
GPIO Pin Mapping and Configuration Y
XBAR Configuration Y
System Configuration Y
DCC Y
MEMORY
M0/M1 Y Y
LSx Y Y
GS0 Y Y Y Y
ROM Y Y
FLASH Y
CONTROL PERIPHERALS
ePWM/HRPWM Y Y Y
eCAP Y Y Y
eQEP(1) Y Y Y
ANALOG PERIPHERALS
CMPSS(1) Y Y Y
ADC Configuration Y
ADC Results(1) Y Y Y
COMMUNICATION PERIPHERALS
CAN Y Y Y
FSITX/FSIRX Y Y Y
I2C Y Y
LIN Y Y Y
PMBus Y Y Y
SCI Y Y
SPI Y Y Y

(1) These modules are accessible from DMA but cannot trigger a DMA transfer.

8.6 C28x Processor

The CPU is a 32-bit fixed-point processor. This device draws from the best features of digital signal processing;
reduced instruction set computing (RISC); and microcontroller architectures, firmware, and tool sets.
The CPU features include a modified Harvard architecture and circular addressing. The RISC features are
single-cycle instruction execution, register-to-register operations, and modified Harvard architecture. The
microcontroller features include ease of use through an intuitive instruction set, byte packing and unpacking, and
bit manipulation. The modified Harvard architecture of the CPU enables instruction and data fetches to be
performed in parallel. The CPU can read instructions and data while it writes data simultaneously to maintain the
single-cycle instruction operation across the pipeline. The CPU does this over six separate address/data buses.
For more information on CPU architecture and instruction set, see the TMS320C28x CPU and Instruction Set
Reference Guide. For more information on the C28x Floating Point Unit (FPU), Trigonometric Math Unit, and
Cyclic Redundancy Check (VCRC) instruction sets, see the TMS320C28x Extended Instruction Sets Technical
Reference Manual. A brief overview of the FPU, TMU, and VCRC are provided here.
8.6.1 Floating-Point Unit (FPU)
The C28x plus floating-point (C28x+FPU) processor extends the capabilities of the C28x fixed-point CPU by
adding registers and instructions to support IEEE single-precision floating-point operations.
Devices with the C28x+FPU include the standard C28x register set plus an additional set of floating-point unit
registers. The additional floating-point unit registers are the following:
• Eight floating-point result registers, RnH (where n = 0–7)
• Floating-point Status Register (STF)
• Repeat Block Register (RB)
All of the floating-point registers, except the RB, are shadowed. This shadowing can be used in high-priority
interrupts for fast context save and restore of the floating-point registers.
8.6.2 Fast Integer Division Unit
The Fast Integer Division (FINTDIV) unit of the C28x CPU uniquely supports three types of integer division
(Truncated, Modulus, Euclidean) of varying data type sizes (16/16, 32/16, 32/32, 64/32, 64/64) in unsigned or
signed formats.
• Truncated integer division is naturally supported by C language (/, % operators).
• Modulus and Euclidean divisions are variants that are more efficient for control algorithms and are supported
by C intrinsics.
All three types of integer division produce both a quotient and remainder component, are interruptible, and
execute in a minimum number of deterministic cycles (10 cycles for a 32/32 division). In addition, the Fast
Division capabilities of the C28x CPU uniquely support fast execution of floating-point 32-bit (in 5 cycles) and 64-
bit (in 20 cycles) division.
For more information about fast integer division, see the Fast Integer Division – A Differentiated Offering From
C2000™ Product Family Application Report.

Product Folder Links: TMS320F280025 TMS320F280025-Q1 TMS320F280025C TMS320F280025C-Q1

8.6.3 Trigonometric Math Unit (TMU)

The TMU extends the capabilities of a C28x+FPU by adding instructions and leveraging existing FPU
instructions to speed up the execution of common trigonometric and arithmetic operations listed in Table 8-6.
Table 8-6. TMU Supported Instructions
INSTRUCTIONS C EQUIVALENT OPERATION PIPELINE CYCLES
MPY2PIF32 RaH,RbH a = b * 2pi 2/3
DIV2PIF32 RaH,RbH a = b / 2pi 2/3
DIVF32 RaH,RbH,RcH a = b/c 5
SQRTF32 RaH,RbH a = sqrt(b) 5
SINPUF32 RaH,RbH a = sin(b*2pi) 4
COSPUF32 RaH,RbH a = cos(b*2pi) 4
ATANPUF32 RaH,RbH a = atan(b)/2pi 4
QUADF32 RaH,RbH,RcH,RdH Operation to assist in calculating ATANPU2 5

No changes have been made to existing instructions, pipeline or memory bus architecture. All TMU instructions
use the existing FPU register set (R0H to R7H) to carry out their operations.
Exponent instruction IEXP2F32 and logarithmic instruction LOG2F32 have been added to support computation
of floating-point power function for the non-linear proportional integral derivative control (NLPID) component of
the C2000 Digital Control Library. These two added instructions reduce the power function calculations from a
typical of 300 cycles using library emulation to less than 10 cycles.
8.6.4 VCRC Unit
Cyclic redundancy check (CRC) algorithms provide a straightforward method for verifying data integrity over
large data blocks, communication packets, or code sections. The C28x+VCRC can perform 8-bit, 16-bit, 24-bit,
and 32-bit CRCs. For example, the VCRC can compute the CRC for a block length of 10 bytes in 10 cycles. A
CRC result register contains the current CRC, which is updated whenever a CRC instruction is executed.
The following are the CRC polynomials used by the CRC calculation logic of the VCRC:
• CRC8 polynomial = 0x07
• CRC16 polynomial 1 = 0x8005
• CRC16 polynomial 2 = 0x1021
• CRC24 polynomial = 0x5d6dcb
• CRC32 polynomial 1 = 0x04c11db7
• CRC32 polynomial 2 = 0x1edc6f41
This module can calculate CRCs for a byte of data in a single cycle. The CRC calculation for CRC8, CRC16,
CRC24, and CRC32 is done byte-wise (instead of computing on a complete 16-bit or 32-bit data read by the
C28x core) to match the byte-wise computation requirement mandated by various standards.
The VCRC Unit also allows the user to provide the size (1b-32b) and value of any polynomial to fit custom CRC
requirements. The CRC execution time increases to three cycles when using a custom polynomial.

8.7 Embedded Real-Time Analysis and Diagnostic (ERAD)

The ERAD module enhances the debug and system-analysis capabilities of the device. The debug and system-
analysis enhancements provided by the ERAD module is done outside of the CPU. The ERAD module consists
of the Enhanced Bus Comparator units and the System Event Counter units. The Enhanced Bus Comparator
units are used to generate hardware breakpoints, hardware watch points, and other output events. The System
Event Counter units are used to analyze and profile the system. The ERAD module is accessible by the
debugger and by the application software, which significantly increases the debug capabilities of many real-time
systems, especially in situations where debuggers are not connected. In the TMS320F28002x devices, the
ERAD module contains eight Enhanced Bus Comparator units (which increases the number of Hardware
breakpoints from two to ten) and four Benchmark System Event Counter units.
8.8 Background CRC-32 (BGCRC)
The Background CRC (BGCRC) module computes a CRC-32 on a configurable block of memory. It
accomplishes this by fetching the specified block of memory during idle cycles (when the CPU, HIC, or DMA is
not accessing the memory block). The calculated CRC-32 value is compared against a golden CRC-32 value to
indicate a pass or fail. In essence, the BGCRC helps identify memory faults and corruption.
The BGCRC module has the following features:
• One cycle CRC-32 computation on 32 bits of data
• No CPU bandwidth impact for zero wait state memory
• Minimal CPU bandwidth impact for non-zero wait state memory
• Dual operation modes (CRC-32 mode and scrub mode)
• Watchdog timer to time CRC-32 completion
• Ability to pause and resume CRC-32 computation

Product Folder Links: TMS320F280025 TMS320F280025-Q1 TMS320F280025C TMS320F280025C-Q1

8.9 Direct Memory Access (DMA)

The DMA module provides a hardware method of transferring data between peripherals and/or memory without
intervention from the CPU, thereby freeing up bandwidth for other system functions. Additionally, the DMA has
the capability to orthogonally rearrange the data as it is transferred as well as “ping-pong” data between buffers.
These features are useful for structuring data into blocks for optimal CPU processing. Figure 8-2 shows a
device-level block diagram of the DMA.
DMA features include:
• Six channels with independent PIE interrupts
• Peripheral interrupt trigger sources
– ADC interrupts and EVT signals
– External Interrupts
– ePWM SOC signals
– CPU timers
– eCAP
– SPI transmit and receive
– CAN transmit and receive
– LIN transmit and receive
• Data sources and destinations:
– GSx RAM
– ADC result registers
– Control peripheral registers (ePWM, eQEP, eCAP)
– SPI, LIN, CAN, and PMBus registers
• Word Size: 16-bit or 32-bit (SPI limited to 16-bit)
• Throughput: Four cycles per word without arbitration

ADC ADC Global Shared

CAN LIN XINT TIMER
WRAPPER RESULTS (GS0) RAM

C28x bus
DMA bus
TINT(0-2) DMA_CHx(1-6)
XINT(1-5) DMA Trigger
ADCx.INT(1-5), ADCx.EVT Source Selection
CANxIF(1-3) C28x
DMACHSRCSEL1.CHx DMA
ECAP(1-3)DMA
DMACHSRCSEL2.CHx
EPWM(1-7).SOCA, EPWM(1-7.SOCB PIE
CHx.MODE.PERINTSEL
SPITXDMA(A-B), SPIRXDMA(A-B) (x = 1 to 6)
FSITXADMA, FSIRXADMA
CMPSS
eQEP

eCAP EPWM SPI PMBUS FSI

Figure 8-2. DMA Block Diagram

8.10 Device Boot Modes

This section explains the default boot modes, as well as all the available boot modes supported on this device.
The boot ROM uses the boot mode select, general-purpose input/output (GPIO) pins to determine the boot
mode configuration.
Table 8-7 shows the boot mode options available for selection by the default boot mode select pins. Users have
the option to program the device to customize the boot modes selectable in the boot-up table as well as the boot
mode select pin GPIOs used.
All the peripheral boot modes that are supported use the first instance of the peripheral module (SCIA, SPIA,
I2CA, CANA, and so forth). Whenever these boot modes are referred to in this chapter, such as SCI boot, it is
actually referring to the first module instance, which means the SCI boot on the SCIA port. The same applies to
the other peripheral boots.
See Section 7.11.2.2.2 and Figure 7-8 for tboot-flash, the boot ROM execution time to first instruction fetch in flash.
Table 8-7. Device Default Boot Modes
GPIO24 GPIO32
BOOT MODE
(DEFAULT BOOT MODE SELECT PIN 1) (DEFAULT BOOT MODE SELECT PIN 0)
Parallel IO 0 0
SCI / Wait Boot(1) 0 1
CAN 1 0
Flash 1 1

(1) SCI boot mode can be used as a wait boot mode as long as SCI continues to wait for an 'A' or 'a' during the SCI autobaud lock
process.

8.10.1 Device Boot Configurations

This section details what boot configurations are available and how to configure them. This device supports from
0 boot mode select pins up to 3 boot mode select pins as well as from 1 configured boot mode up to 8
configured boot modes.
To change and configure the device from the default settings to custom settings for your application, use the
following process:
1. Determine all the various ways you want application to be able to boot. (For example: Primary boot option of
Flash boot for your main application, secondary boot option of CAN boot for firmware updates, tertiary boot
option of SCI boot for debugging, etc)
2. Based on the number of boot modes needed, determine how many boot mode select pins (BMSPs) are
required to select between your selected boot modes. (For example: 2 BMSPs are required to select between
3 boot mode options)
3. Assign the required BMSPs to a physical GPIO pin. (For example, BMSP0 to GPIO10, BMSP1 to GPIO51,
and BMSP2 left as default which is disabled). Refer to Section 8.10.1.1 for all the details on performing these
configurations.
4. Assign the determined boot mode definitions to indexes in your custom boot table that correlate to the
decoded value of the BMSPs. For example, BOOTDEF0=Boot to Flash, BOOTDEF1=CAN Boot,
BOOTDEF2=SCI Boot; all other BOOTDEFx are left as default/nothing). Refer to Section 8.10.1.2 for all the
details on setting up and configuring the custom boot mode table.
Additionally, the Boot Mode Example Use Cases section of the TMS320F28002x Real-Time Microcontrollers
Technical Reference Manual provides some example use cases on how to configure the BMSPs and custom
boot tables.

Note
The CAN boot mode turns on the XTAL. Be sure an XTAL is installed in the application before using
CAN boot mode.

Product Folder Links: TMS320F280025 TMS320F280025-Q1 TMS320F280025C TMS320F280025C-Q1

8.10.1.1 Configuring Boot Mode Pins

This section explains how the boot mode select pins can be customized by the user, by programming the
BOOTPIN-CONFIG location (refer to Table 8-8) in the user-configurable dual-zone security module (DCSM)
OTP. The location in the DCSM OTP is Z1-OTP-BOOTPIN-CONFIG or Z2-OTP-BOOTPIN-CONFIG. When
debugging, EMU-BOOTPIN-CONFIG is the emulation equivalent of Z1-OTP-BOOTPIN-CONFIG/Z2-OTP-
BOOTPIN-CONFIG, and can be programmed to experiment with different boot modes without writing to OTP.
The device can be programmed to use 0, 1, 2, or 3 boot mode select pins as needed.

Note
When using Z2-OTP-BOOTPIN-CONFIG, the configurations programmed in this location will take
priority over the configurations in Z1-OTP-BOOTPIN-CONFIG. It is recommended to use Z1-OTP-
BOOTPIN-CONFIG first and then if OTP configurations need to be altered, switch to using Z2-OTP-
BOOTPIN-CONFIG.

Table 8-8. BOOTPIN-CONFIG Bit Fields

BIT NAME DESCRIPTION
31:24 Key Write 0x5A to these 8-bits to indicate the bits in this register are valid
23:16 Boot Mode Select Pin 2 (BMSP2) Refer to BMSP0 description except for BMSP2
15:8 Boot Mode Select Pin 1 (BMSP1) Refer to BMSP0 description except for BMSP1
Set to the GPIO pin to be used during boot (up to 255):
- 0x0 = GPIO0
- 0x01 = GPIO1
7:0 Boot Mode Select Pin 0 (BMSP0)
- and so on
Writing 0xFF disables BMSP0 and this pin is no longer used to select
the boot mode.

The following GPIOs cannot be used as a BMSP. If selected for a particular BMSP, the boot ROM automatically
selects the factory default GPIO (the factory default for BMSP2 is 0xFF, which disables the BMSP).
• GPIO 20 and GPIO 21
• GPIO 36 and GPIO 38
• GPIO 47 to GPIO 60
• GPIO 63 to GPIO 223

Table 8-9. Standalone Boot Mode Select Pin Decoding

BOOTPIN_CONFIG
BMSP0 BMSP1 BMSP2 REALIZED BOOT MODE
KEY
!= 0x5A Don’t Care Don’t Care Don’t Care Boot as defined by the factory default BMSPs
Boot as defined in the boot table for boot mode
0xFF 0xFF 0xFF 0
(All BMSPs disabled)
Boot as defined by the value of BMSP0
Valid GPIO 0xFF 0xFF
(BMSP1 and BMSP2 disabled)
Boot as defined by the value of BMSP1
0xFF Valid GPIO 0xFF
(BMSP0 and BMSP2 disabled)
Boot as defined by the value of BMSP2
0xFF 0xFF Valid GPIO
(BMSP0 and BMSP1 disabled)
Boot as defined by the values of BMSP0 and
Valid GPIO Valid GPIO 0xFF BMSP1
(BMSP2 disabled)
Boot as defined by the values of BMSP0 and
Valid GPIO 0xFF Valid GPIO BMSP2
(BMSP1 disabled)
= 0x5A Boot as defined by the values of BMSP1 and
0xFF Valid GPIO Valid GPIO BMSP2
(BMSP0 disabled)
Boot as defined by the values of BMSP0,
Valid GPIO Valid GPIO Valid GPIO
BMSP1, and BMSP2
BMSP0 is reset to the factory default BMSP0
GPIO
Invalid GPIO Valid GPIO Valid GPIO
Boot as defined by the values of BMSP0,
BMSP1, and BMSP2
BMSP1 is reset to the factory default BMSP1
GPIO
Valid GPIO Invalid GPIO Valid GPIO
Boot as defined by the values of BMSP0,
BMSP1, and BMSP2
BMSP2 is reset to the factory default state,
which is disabled
Valid GPIO Valid GPIO Invalid GPIO
Boot as defined by the values of BMSP0 and
BMSP1

Note
When decoding the boot mode, BMSP0 is the least-significant-bit and BMSP2 is the most-significant-
bit of the boot table index value. It is recommended when disabling BMSPs to start with disabling
BMSP2. For example, in an instance when only using BMSP2 (BMSP1 and BMSP0 are disabled),
then only the boot table indexes of 0 and 4 will be selectable. In the instance when using only BMSP0,
then the selectable boot table indexes are 0 and 1.

Product Folder Links: TMS320F280025 TMS320F280025-Q1 TMS320F280025C TMS320F280025C-Q1

8.10.1.2 Configuring Boot Mode Table Options

This section explains how to configure the boot definition table, BOOTDEF, for the device and the associated
boot options. The 64-bit location is located in user-configurable DCSM OTP in the Z1-OTP-BOOTDEF-LOW and
Z1-OTP-BOOTDEF-HIGH locations. When debugging, EMU-BOOTDEF-LOW and EMU-BOOTDEF-HIGH are
the emulation equivalents of Z1-OTP-BOOTDEF-LOW and Z1-OTP-BOOTDEF-HIGH, and can be programmed
to experiment with different boot mode options without writing to OTP. The range of customization to the boot
definition table depends on how many boot mode select pins (BMSP) are being used. For example, 0 BMSPs
equals to 1 table entry, 1 BMSP equals to 2 table entries, 2 BMSPs equals to 4 table entries, and 3 BMSPs
equals to 8 table entries. Refer to the TMS320F28002x Real-Time Microcontrollers Technical Reference Manual
for examples on how to set up the BOOTPIN_CONFIG and BOOTDEF values.

Note
The locations Z2-OTP-BOOTDEF-LOW and Z2-OTP-BOOTDEF-HIGH will be used instead of Z1-
OTP-BOOTDEF-LOW and Z1-OTP-BOOTDEF-HIGH locations when Z2-OTP-BOOTPIN-CONFIG is
configured. Refer to Configuring Boot Mode Pins for more details on BOOTPIN_CONFIG usage.

Table 8-10. BOOTDEF Bit Fields

BYTE
BOOTDEF NAME NAME DESCRIPTION
POSITION
Set the boot mode for index 0 of the boot table.

Different boot modes and their options can include,

for example, a boot mode that uses different GPIOs
for a specific bootloader or a different flash entry
BOOT_DEF0 7:0 BOOT_DEF0 Mode/Options point address. Any unsupported boot mode will
cause the device to either go to wait boot or boot to
flash.

Refer to GPIO Assignments for valid BOOTDEF

values to set in the table.
BOOT_DEF1 15:8 BOOT_DEF1 Mode/Options
BOOT_DEF2 23:16 BOOT_DEF2 Mode/Options
BOOT_DEF3 31:24 BOOT_DEF3 Mode/Options
BOOT_DEF4 39:32 BOOT_DEF4 Mode/Options Refer to BOOT_DEF0 description
BOOT_DEF5 47:40 BOOT_DEF5 Mode/Options
BOOT_DEF6 55:48 BOOT_DEF6 Mode/Options
BOOT_DEF7 63:56 BOOT_DEF7 Mode/Options

8.10.2 GPIO Assignments

This section details the GPIOs and boot option values used for boot mode set in the BOOT_DEF memory
location located at Z1-OTP-BOOTDEF-LOW/ Z2-OTP-BOOTDEF-LOW and Z1-OTP-BOOTDEF-HIGH/ Z2-OTP-
BOOTDEF-HIGH. Refer to Configuring Boot Mode Table Options on how to configure BOOT_DEF. When
selecting a boot mode option, make sure to verify that the necessary pins are available in the pin mux options for
the specific device package being used.
Table 8-11. SCI Boot Options
OPTION BOOTDEF VALUE SCITXDA GPIO SCIRXDA GPIO
0 (default) 0x01 GPIO29 GPIO28
1 0x21 GPIO16 GPIO17
2 0x41 GPIO8 GPIO9
3 0x61 GPIO2 GPIO3
4 0x81 GPIO16 GPIO3

Table 8-12. CAN Boot Options

OPTION BOOTDEF VALUE CANTXA GPIO CANRXA GPIO
0 (default) 0x02 GPIO4 GPIO5
1 0x22 GPIO32 GPIO33
2 0x42 GPIO2 GPIO3

Table 8-13. I2C Boot Options

OPTION BOOTDEF VALUE SDAA GPIO SCLA GPIO
0 0x07 GPIO32 GPIO33
1 0x27 GPIO0 GPIO1
2 0x47 GPIO10 GPIO8

Table 8-14. RAM Boot Options

RAM ENTRY POINT
OPTION BOOTDEF VALUE
(ADDRESS)
0 0x05 0x0000 0000

Table 8-15. Flash Boot Options

FLASH ENTRY POINT
OPTION BOOTDEF VALUE FLASH SECTOR
(ADDRESS)
0 (default) 0x03 0x0008 0000 Bank0 Sector 0
1 0x23 0x0008 4000 Bank 0 Sector 4
2 0x43 0x0008 8000 Bank 0 Sector 8
3 0x63 0x0008 EFF0 Bank 0, End of Sector 14

Table 8-16. Wait Boot Options

OPTION BOOTDEF VALUE WATCHDOG
0 0x04 Enabled
1 0x24 Disabled

Product Folder Links: TMS320F280025 TMS320F280025-Q1 TMS320F280025C TMS320F280025C-Q1

Table 8-17. SPI Boot Options

OPTION BOOTDEF VALUE SPISIMOA SPISOMIA SPICLKA SPISTEA
0 0x06 GPIO2 GPIO1 GPIO3 GPIO5
1 0x26 GPIO16 GPIO1 GPIO3 GPIO0
2 0x46 GPIO8 GPIO10 GPIO9 GPIO11
3 0x66 GPIO8 GPIO17 GPIO9 GPIO11

Table 8-18. Parallel Boot Options

28x(DSP) CONTROL
OPTION BOOTDEF VALUE D0-D7 GPIO HOST CONTROL GPIO
GPIO
0 (default) 0x00 D0 - GPIO28 GPIO16 GPIO29
D1 - GPIO1
D2 - GPIO2
D3 - GPIO3
D4 - GPIO4
D5 - GPIO5
D6 - GPIO6
D7 - GPIO7
1 0x20 D0 - GPIO0 GPIO16 GPIO11
D1 - GPIO1
D2 - GPIO2
D3 - GPIO3
D4 - GPIO4
D5 - GPIO5
D6 - GPIO6
D7 - GPIO7

8.11 Dual Code Security Module

The dual code security module (DCSM) prevents access to on-chip secure memories. The term “secure” means
access to secure memories and resources is blocked. The term “unsecure” means access is allowed; for
example, through a debugging tool such as Code Composer Studio™ (CCS).
The code security mechanism offers protection for two zones, Zone 1 (Z1) and Zone 2 (Z2). The security
implementation for both the zones is identical. Each zone has its own dedicated secure resource (OTP memory
and secure ROM) and allocated secure resource (LSx RAM and flash sectors).
The security of each zone is ensured by its own 128-bit password (CSM password). The password for each zone
is stored in an OTP memory location based on a zone-specific link pointer. The link pointer value can be
changed to program a different set of security settings (including passwords) in OTP.

Code Security Module Disclaimer

THE CODE SECURITY MODULE (CSM) INCLUDED ON THIS DEVICE WAS DESIGNED TO
PASSWORD PROTECT THE DATA STORED IN THE ASSOCIATED MEMORY AND IS
WARRANTED BY TEXAS INSTRUMENTS (TI), IN ACCORDANCE WITH ITS STANDARD TERMS
AND CONDITIONS, TO CONFORM TO TI'S PUBLISHED SPECIFICATIONS FOR THE WARRANTY
PERIOD APPLICABLE FOR THIS DEVICE.
TI DOES NOT, HOWEVER, WARRANT OR REPRESENT THAT THE CSM CANNOT BE
COMPROMISED OR BREACHED OR THAT THE DATA STORED IN THE ASSOCIATED MEMORY
CANNOT BE ACCESSED THROUGH OTHER MEANS. MOREOVER, EXCEPT AS SET FORTH
ABOVE, TI MAKES NO WARRANTIES OR REPRESENTATIONS CONCERNING THE CSM OR
OPERATION OF THIS DEVICE, INCLUDING ANY IMPLIED WARRANTIES OF MERCHANTABILITY
OR FITNESS FOR A PARTICULAR PURPOSE.
IN NO EVENT SHALL TI BE LIABLE FOR ANY CONSEQUENTIAL, SPECIAL, INDIRECT,
INCIDENTAL, OR PUNITIVE DAMAGES, HOWEVER CAUSED, ARISING IN ANY WAY OUT OF
YOUR USE OF THE CSM OR THIS DEVICE, WHETHER OR NOT TI HAS BEEN ADVISED OF THE
POSSIBILITY OF SUCH DAMAGES. EXCLUDED DAMAGES INCLUDE, BUT ARE NOT LIMITED
TO LOSS OF DATA, LOSS OF GOODWILL, LOSS OF USE OR INTERRUPTION OF BUSINESS OR
OTHER ECONOMIC LOSS.

Product Folder Links: TMS320F280025 TMS320F280025-Q1 TMS320F280025C TMS320F280025C-Q1

8.12 Watchdog
The watchdog module is the same as the one on previous TMS320C2000 devices, but with an optional lower
limit on the time between software resets of the counter. This windowed countdown is disabled by default, so the
watchdog is fully backward-compatible.
The watchdog generates either a reset or an interrupt. It is clocked from the internal oscillator with a selectable
frequency divider.
Figure 8-3 shows the various functional blocks within the watchdog module.
WDCR.WDPRECLKDIV WDCR.WDPS WDCR.WDDIS

WDCNTR

WDCLK
(INTOSC1) Overflow 1-count
delay
8-bit
WDCLK Watchdog Watchdog
Divider Prescaler Counter

SYSRSn
Clear
Count

WDWCR.MIN
WDKEY (7:0)
Out of Window Watchdog
Watchdog Good Key
Window
Key Detector Detector
WDCR(WDCHK(2:0))
55 + AA

Bad Key

WDRSTn Generate
1 0 1 512-WDCLK Watchdog Time-out
WDINTn Output Pulse

SCSR.WDENINT

Figure 8-3. Windowed Watchdog

8.13 C28x Timers

CPU-Timers 0, 1, and 2 are identical 32-bit timers with presettable periods and with 16-bit clock prescaling. The
timers have a 32-bit count-down register that generates an interrupt when the counter reaches zero. The counter
is decremented at the CPU clock speed divided by the prescale value setting. When the counter reaches zero, it
is automatically reloaded with a 32-bit period value.
CPU-Timer 0 is for general use and is connected to the PIE block. CPU-Timer 1 is also for general use and is
connected to INT13 of the CPU. CPU-Timer 2 is reserved for TI-RTOS. It is connected to INT14 of the CPU. If
TI-RTOS is not being used, CPU-Timer 2 is available for general use.
CPU-Timer 2 can be clocked by any one of the following:
• SYSCLK (default)
• Internal zero-pin oscillator 1 (INTOSC1)
• Internal zero-pin oscillator 2 (INTOSC2)
• X1 (XTAL)
8.14 Dual-Clock Comparator (DCC)
There are three Dual-Clock Comparators (DCC0 and DCC1) on the device. All three DCCs are only accessible
through CPU1. The DCC module is used for evaluating and monitoring the clock input based on a second clock,
which can be a more accurate and reliable version. This instrumentation is used to detect faults in clock source
or clock structures, thereby enhancing the system's safety metrics.
8.14.1 Features
The DCC has the following features:
• Allows the application to ensure that a fixed ratio is maintained between frequencies of two clock signals.
• Supports the definition of a programmable tolerance window in terms of the number of reference clock cycles.
• Supports continuous monitoring without requiring application intervention.
• Supports a single-sequence mode for spot measurements.
• Allows the selection of a clock source for each of the counters, resulting in several specific use cases.
8.14.2 Mapping of DCCx (DCC0 and DCC1) Clock Source Inputs
Table 8-19. DCCx Clock Source0 Table
DCCxCLKSRC0[3:0] CLOCK NAME
0x0 XTAL/X1
0x1 INTOSC1
0x2 INTOSC2
0x5 CPU1.SYSCLK
0xC INPUT XBAR (Output16 of input-xbar)
others Reserved

Product Folder Links: TMS320F280025 TMS320F280025-Q1 TMS320F280025C TMS320F280025C-Q1

Table 8-20. DCCx Clock Source1 Table

DCCxCLKSRC1[4:0] CLOCK NAME
0x0 PLLRAWCLK
0x2 INTOSC1
0x3 INTOSC2
0x6 CPU1.SYSCLK
0x9 Input XBAR (Output15 of the input-xbar)
0xB EPWMCLK
0xC LSPCLK
0xD ADCCLK
0xE WDCLK
0xF CAN0BITCLK
others Reserved

8.15 Configurable Logic Block (CLB)

The C2000 configurable logic block (CLB) is a collection of blocks that can be interconnected using software to
implement custom digital logic functions or enhance existing on-chip peripherals. The CLB is able to enhance
existing peripherals through a set of crossbar interconnections, which provide a high level of connectivity to
existing control peripherals such as enhanced pulse width modulators (ePWM), enhanced capture modules
(eCAP), and enhanced quadrature encoder pulse modules (eQEP). The crossbars also allow the CLB to be
connected to external GPIO pins. In this way, the CLB can be configured to interact with device peripherals to
perform small logical functions such as comparators, or to implement custom serial data exchange protocols.
Through the CLB, functions that would otherwise be accomplished using external logic devices can now be
implemented inside the MCU.
The CLB peripheral is configured through the CLB tool. For more information on the CLB tool, available
examples, application reports and users guide, please refer to the following location in your C2000Ware package
(C2000Ware_2_00_00_03 and higher):
C2000WARE_INSTALL_LOCATION\utilities\clb_tool\clb_syscfg\doc
CLB Tool User Guide
How to Design with the C2000™ CLB Application Report
How to Migrate Custom Logic From an FPGA/CPLD to C2000™ CLB Application Report
The CLB module and its interconnections are shown in Figure 8-4.

Product Folder Links: TMS320F280025 TMS320F280025-Q1 TMS320F280025C TMS320F280025C-Q1

Figure 8-4. CLB Overview

Absolute encoder protocol interfaces are now provided as Position Manager solutions in the C2000Ware
MotorControl SDK. Configuration files, application programmer interface (API), and use examples for such
solutions are provided with C2000Ware MotorControl SDK. In some solutions, the TI-configured CLB is used
with other on-chip resources, such as the SPI port or the C28x CPU, to perform more complex functionality.

9 Applications, Implementation, and Layout

Note
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.

9.1 TI Reference Design

The TI Reference Design Library is a robust reference design library spanning analog, embedded processor,
and connectivity. Created by TI experts to help you jump start your system design, all reference designs include
schematic or block diagrams, BOMs, and design files to speed your time to market.
Check out our latest reference design based on F28002x, targeted for digital power applications: Two Phase
Interleaved LLC Resonant Converter Reference Design Using C2000™ MCUs.
Search and download other TI reference designs at Select TI reference designs.

Product Folder Links: TMS320F280025 TMS320F280025-Q1 TMS320F280025C TMS320F280025C-Q1

10 Device and Documentation Support

10.1 Getting Started and Next Steps
For a quick overview of the device, features, roadmap, comparisons to other devices, and package details, see
Texas Instruments C2000™ F28002x Real-Time Controller Series.
10.2 Device and Development Support Tool Nomenclature
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all TMS320
MCU devices and support tools. Each TMS320™ MCU commercial family member has one of three prefixes:
TMX, TMP, or TMS (for example, TMS320F280025C). Texas Instruments recommends two of three possible
prefix designators for its support tools: TMDX and TMDS. These prefixes represent evolutionary stages of
product development from engineering prototypes (with TMX for devices and TMDX for tools) through fully
qualified production devices and tools (with TMS for devices and TMDS for tools).
Device development evolutionary flow:

TMX Experimental device that is not necessarily representative of the final device's electrical specifications and
may not use production assembly flow.
TMP Prototype device that is not necessarily the final silicon die and may not necessarily meet final electrical
specifications.
TMS Production version of the silicon die that is fully qualified.

Support tool development evolutionary flow:

TMDX Development-support product that has not yet completed Texas Instruments internal qualification testing.
TMDS Fully-qualified development-support product.

TMX and TMP devices and TMDX development-support tools are shipped against the following disclaimer:
"Developmental product is intended for internal evaluation purposes."
Production devices and TMDS development-support tools have been characterized fully, and the quality and
reliability of the device have been demonstrated fully. TI's standard warranty applies.
Predictions show that prototype devices (X or P) have a greater failure rate than the standard production
devices. Texas Instruments recommends that these devices not be used in any production system because their
expected end-use failure rate still is undefined. Only qualified production devices are to be used.
TI device nomenclature also includes a suffix with the device family name. This suffix indicates the package type
(for example, PN) and temperature range (for example, S).
For device part numbers and further ordering information, see the TI website (www.ti.com) or contact your TI
sales representative.
For additional description of the device nomenclature markings on the die, see the TMS320F28002x Real-Time
MCUs Silicon Errata.

Generic Part Number: TMS 320 F 280025C -Q1

Orderable Part Number: X (blank) F 280025C PN Q R
(A)
PREFIX SHIPPING OPTIONS
TMX (X) = experimental device (blank) = Tray
TMS (blank) = qualified device R = Tape and Reel

QUALIFICATION (in Generic Part Number)

blank = Non-Automotive
DEVICE FAMILY -Q1 = Q1 refers to Automotive AEC Q100 Grade 1 qualification.
320 = TMS320 MCU Family
TEMPERATURE RANGE (in Orderable Part Number)
S = −40°C to 125°C (TJ)
TECHNOLOGY Q = −40°C to 125°C (T )A
F = Flash

PACKAGE TYPE
80-Pin PN Low-Profile Quad Flatpack (LQFP)
64-Pin PM LQFP
48-Pin PT LQFP

DEVICE
280025 280025C
280023 280023C
280021
A. Prefix X is used in orderable part numbers.

Figure 10-1. Device Nomenclature

10.3 Markings
Figure 10-2 and Figure 10-3 show the package symbolization. Table 10-1 lists the silicon revision codes.

F280025CPMS F280025CPNS
$$#−YMLLLLS $$#−YMLLLLS
G4 G4
Package Package
Pin 1 Pin 1

YMLLLLS = Lot Trace Code

YM = 2-Digit Year/Month Code

LLLL = Assembly Lot
S = Assembly Site Code
$$ = Wafer Fab Code (one or two characters) as applicable
# = Silicon Revision Code

G4 = Green (Low Halogen and RoHS-compliant)

Figure 10-2. Package Symbolization for PM and PN Packages

Product Folder Links: TMS320F280025 TMS320F280025-Q1 TMS320F280025C TMS320F280025C-Q1

YMLLLLS = Lot Trace Code

980 PTS YM = 2-Digit Year/Month Code

LLLL = Assembly Lot
F280025C S = Assembly Site Code
980 = TI E.I.A. Code
YMLLLLS $$ = Wafer Fab Code (one or two characters) as applicable
# = Silicon Revision Code
$$# G4
G4 = Green (Low Halogen and RoHS-compliant)

Package
Pin 1

Figure 10-3. Package Symbolization for PT Package

Table 10-1. Revision Identification

REVID(1)
SILICON REVISION CODE SILICON REVISION COMMENTS
ADDRESS: 0x5D00C
Blank 0 0x0000 0000 This silicon revision is available as TMX.
This silicon revision is available as TMX and
A A 0x0000 0001
TMS.

(1) Silicon Revision ID

10.4 Tools and Software

TI offers an extensive line of development tools. Some of the tools and software to evaluate the performance of
the device, generate code, and develop solutions follow. To view all available tools and software for C2000™
real-time control MCUs, visit the C2000 real-time control MCUs – Design & development page.
Development Tools
LAUNCHXL-F280025C
LAUNCHXL-F280025C is a low-cost development board for TI C2000™ Real-Time Controllers series of F28002x
devices. Ideal for initial evaluation and prototyping, it provides a standardized and easy-to-use platform to
develop your next application. This extended version LaunchPad™ development kit offers extra pins for
evaluation and supports the connection of two BoosterPack™ plug-in modules.
F280025 controlCARD
The F280025 controlCARD is an HSEC180 controlCARD based evaluation and development tool for the
C2000™ F28002x series of microcontroller products. controlCARDs are ideal to use for initial evaluation and
system prototyping. controlCARDs are complete board-level modules that utilize one of two standard form
factors (100-pin DIMM or 180-pin HSEC ) to provide a low-profile single-board controller solution. For first
evaluation controlCARDs are typically purchased bundled with a baseboard or bundled in an application kit.
TI Resource Explorer
To enhance your experience, be sure to check out the TI Resource Explorer to browse examples, libraries, and
documentation for your applications.
Software Tools
C2000Ware for C2000 MCUs
C2000Ware for C2000™ MCUs is a cohesive set of software and documentation created to minimize
development time. It includes device-specific drivers, libraries, and peripheral examples.
Digital Power SDK
Digital Power SDK is a cohesive set of software infrastructure, tools, and documentation designed to minimize
C2000 MCU-based digital power system development time targeted for various AC-DC, DC-DC and DC-AC
power supply applications. The software includes firmware that runs on C2000 digital power evaluation modules
(EVMs) and TI designs (TIDs), which are targeted for solar, telecom, server, electric vehicle chargers and
industrial power delivery applications. Digital Power SDK provides all the needed resources at every stage of
development and evaluation in a digital power applications.
Motor Control SDK
Motor Control SDK is a cohesive set of software infrastructure, tools, and documentation designed to minimize
C2000 MCU-based motor control system development time targeted for various three-phase motor control
applications. The software includes firmware that runs on C2000 motor control evaluation modules (EVMs) and
TI designs (TIDs), which are targeted for industrial drive and other motor control, Motor Control SDK provides all
the needed resources at every stage of development and evaluation for high-performance motor control
applications.
Code Composer Studio™ (CCS) Integrated Development Environment (IDE) for C2000 microcontrollers
Code Composer Studio is an integrated development environment (IDE) that supports TI's Microcontroller and
Embedded Processors portfolio. Code Composer Studio comprises a suite of tools used to develop and debug
embedded applications. It includes an optimizing C/C++ compiler, source code editor, project build environment,
debugger, profiler, and many other features. The intuitive IDE provides a single user interface taking the user
through each step of the application development flow. Familiar tools and interfaces allow users to get started
faster than ever before. Code Composer Studio combines the advantages of the Eclipse software framework
with advanced embedded debug capabilities from TI resulting in a compelling feature-rich development
environment for embedded developers.

Product Folder Links: TMS320F280025 TMS320F280025-Q1 TMS320F280025C TMS320F280025C-Q1

SysConfig System configuration tool

SysConfig is a comprehensive collection of graphical utilities for configuring pins, peripherals, radios,
subsystems, and other components. SysConfig helps you manage, expose and resolve conflicts visually so that
you have more time to create differentiated applications. The tool's output includes C header and code files that
can be used with software development kit (SDK) examples or used to configure custom software. The
SysConfig tool automatically selects the pinmux settings that satisfy the entered requirements. The SysConfig
tool is delivered integrated in CCS, as a standalone installer, or can be used via the dev.ti.com cloud tools portal.
For more information about the SysConfig system configuration tool, visit the System configuation tool page.
Models
Various models are available for download from the product Design & development pages. These models
include I/O Buffer Information Specification (IBIS) Models and Boundary-Scan Description Language (BSDL)
Models. To view all available models, visit the Design tools & simulation section of the Design & development
page for each device.
Training
To help assist design engineers in taking full advantage of the C2000 microcontroller features and performance,
TI has developed a variety of training resources. Utilizing the online training materials and downloadable hands-
on workshops provides an easy means for gaining a complete working knowledge of the C2000 microcontroller
family. These training resources have been designed to decrease the learning curve, while reducing
development time, and accelerating product time to market. For more information on the various training
resources, visit the C2000™ real-time control MCUs – Support & training site.
The architecture and many of the peripherals of the F28002x are similar to those of the F28004x. The following
Workshop material and the Migration Between TMS320F28004x and TMS320F28002x Application Report will
cover the technical details of the TMS320F28004x architecture and highlight the device differences, which will be
helpful to users of the F28002x device.
Specific TMS320F28004x hands-on training resources can be found at C2000™ MCU Device Workshops.
Technical Introduction to the New C2000 TMS320F28004x Device Family
Many of the peripherals and architecture of the F28002x are similar to the F28004x. This presentation will cover
the technical details of the TMS320F28004x architecture and highlight the new improvements to various key
peripherals which will be helpful to users of the F28002x device.
10.5 Documentation Support
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
The current documentation that describes the processor, related peripherals, and other technical collateral
follows.
Errata
TMS320F28002x Real-Time MCUs Silicon Errata describes known advisories on silicon and provides
workarounds.
Technical Reference Manual
TMS320F28002x Real-Time Microcontrollers Technical Reference Manual details the integration, the
environment, the functional description, and the programming models for each peripheral and subsystem in the
F28002x real-time microcontrollers.

CPU User's Guides

TMS320C28x CPU and Instruction Set Reference Guide describes the central processing unit (CPU) and the
assembly language instructions of the TMS320C28x fixed-point digital signal processors (DSPs). This Reference
Guide also describes emulation features available on these DSPs.
TMS320C28x Extended Instruction Sets Technical Reference Manual describes the architecture, pipeline, and
instruction set of the TMU, VCU-II, and FPU accelerators.
Peripheral Guides
C2000 Real-Time Control Peripherals Reference Guide describes the peripheral reference guides of the 28x
DSPs.
Tools Guides
TMS320C28x Assembly Language Tools v20.8.0.STS User's Guide describes the assembly language tools
(assembler and other tools used to develop assembly language code), assembler directives, macros, common
object file format, and symbolic debugging directives for the TMS320C28x device.
TMS320C28x Optimizing C/C++ Compiler v20.8.0.STS User's Guide describes the TMS320C28x C/C++
compiler. This compiler accepts ANSI standard C/C++ source code and produces TMS320 DSP assembly
language source code for the TMS320C28x device.
Application Reports
The SMT & packaging application notes website lists documentation on TI’s surface mount technology (SMT)
and application notes on a variety of packaging-related topics.
Semiconductor Packing Methodology describes the packing methodologies employed to prepare semiconductor
devices for shipment to end users.
Calculating Useful Lifetimes of Embedded Processors provides a methodology for calculating the useful lifetime
of TI embedded processors (EPs) under power when used in electronic systems. It is aimed at general
engineers who wish to determine if the reliability of the TI EP meets the end system reliability requirement.
An Introduction to IBIS (I/O Buffer Information Specification) Modeling discusses various aspects of IBIS
including its history, advantages, compatibility, model generation flow, data requirements in modeling the input/
output structures, and future trends.
Serial Flash Programming of C2000™ Microcontrollers discusses using a flash kernel and ROM loaders for
serial programming a device.
Fast Integer Division – A Differentiated Offering From C2000™ Product Family provides an overview of the
different division and modulo (remainder) functions and its associated properties.
C2000™ Key Technology Guide provides a deeper look into the components that differentiate the C2000
Microcontroller Unit (MCU) as it pertains to Real-Time Control Systems.
Migration Between TMS320F28004x and TMS320F28002x describes the hardware and software differences to
be aware of when moving between F28004x and F28002x C2000™ MCUs.
TMS320F2802x/TMS320F2803x to TMS320F28002x Migration Overview describes the differences between the
Texas Instruments TMS320F2802x/TMS320F2803x and the TMS320F28002x microcontrollers for the purpose
of assisting with application migration.
10.6 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.

Product Folder Links: TMS320F280025 TMS320F280025-Q1 TMS320F280025C TMS320F280025C-Q1

10.7 Trademarks
C2000™, TMS320C2000™, InstaSPIN-FOC™, Code Composer Studio™, TMS320™, LaunchPad™,
BoosterPack™, TI E2E™ are trademarks of Texas Instruments.
Bosch® is a registered trademark of Robert Bosch GmbH Corporation.
All trademarks are the property of their respective owners.
10.8 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.

10.9 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.

11 Mechanical, Packaging, and Orderable Information

11.1 Packaging Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
To learn more about TI packaging, visit the Packaging information website.

Product Folder Links: TMS320F280025 TMS320F280025-Q1 TMS320F280025C TMS320F280025C-Q1

TMS320F280023 TMS320F280023-Q1 TMS320F280023C TMS320F280021 TMS320F280021-Q1
PACKAGE OPTION ADDENDUM

www.ti.com 29-Jan-2021

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

F280021PTQR ACTIVE LQFP PT 48 1000 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 125 F280021
PTQ
F280021PTSR ACTIVE LQFP PT 48 1000 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 125 F280021
PTS
F280023CPMSR ACTIVE LQFP PM 64 1000 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 125 F280023CPMS

F280023CPNSR ACTIVE LQFP PN 80 1000 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 125 F280023CPNS

F280023CPTSR ACTIVE LQFP PT 48 1000 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 125 F280023C
PTS
F280023PMQR ACTIVE LQFP PM 64 1000 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 125 F280023PMQ

F280023PMSR ACTIVE LQFP PM 64 1000 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 125 F280023PMS

F280023PNQR ACTIVE LQFP PN 80 1000 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 125 F280023PNQ

F280023PNSR ACTIVE LQFP PN 80 1000 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 125 F280023PNS

F280023PTQR ACTIVE LQFP PT 48 1000 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 125 F280023
PTQ
F280023PTSR ACTIVE LQFP PT 48 1000 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 125 F280023
PTS
F280025CPMQR ACTIVE LQFP PM 64 1000 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 125 F280025CPMQ

F280025CPMS ACTIVE LQFP PM 64 160 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 125 F280025CPMS

F280025CPMSR ACTIVE LQFP PM 64 1000 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 125 F280025CPMS

F280025CPNQR ACTIVE LQFP PN 80 1000 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 125 F280025CPNQ

F280025CPNSR ACTIVE LQFP PN 80 1000 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 125 F280025CPNS

F280025CPTQR ACTIVE LQFP PT 48 1000 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 125 F280025C
PTQ
F280025CPTSR ACTIVE LQFP PT 48 1000 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 125 F280025C
PTS

Addendum-Page 1
PACKAGE OPTION ADDENDUM

www.ti.com 29-Jan-2021

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

F280025PMQR ACTIVE LQFP PM 64 1000 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 125 F280025PMQ

F280025PMS ACTIVE LQFP PM 64 160 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 125 F280025PMS

F280025PMSR ACTIVE LQFP PM 64 1000 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 125 F280025PMS

F280025PNQR ACTIVE LQFP PN 80 1000 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 125 F280025PNQ

F280025PNS ACTIVE LQFP PN 80 119 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 125 F280025PNS

F280025PNSR ACTIVE LQFP PN 80 1000 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 125 F280025PNS

F280025PTQR ACTIVE LQFP PT 48 1000 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 125 F280025
PTQ
F280025PTS ACTIVE LQFP PT 48 250 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 125 F280025
PTS
F280025PTSR ACTIVE LQFP PT 48 1000 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 125 F280025
PTS

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

Addendum-Page 2
PACKAGE OPTION ADDENDUM

www.ti.com 29-Jan-2021

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 3
PACKAGE MATERIALS INFORMATION

www.ti.com 2-Jul-2021

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
F280021PTQR LQFP PT 48 1000 330.0 16.4 9.6 9.6 1.9 12.0 16.0 Q2
F280021PTSR LQFP PT 48 1000 330.0 16.4 9.6 9.6 1.9 12.0 16.0 Q2
F280023CPMSR LQFP PM 64 1000 330.0 24.4 13.0 13.0 2.1 16.0 24.0 Q2
F280023CPNSR LQFP PN 80 1000 330.0 24.4 16.0 16.0 2.0 24.0 24.0 Q2
F280023CPTSR LQFP PT 48 1000 330.0 16.4 9.6 9.6 1.9 12.0 16.0 Q2
F280023PMQR LQFP PM 64 1000 330.0 24.4 13.0 13.0 2.1 16.0 24.0 Q2
F280023PMSR LQFP PM 64 1000 330.0 24.4 13.0 13.0 2.1 16.0 24.0 Q2
F280023PNQR LQFP PN 80 1000 330.0 24.4 16.0 16.0 2.0 24.0 24.0 Q2
F280023PNSR LQFP PN 80 1000 330.0 24.4 16.0 16.0 2.0 24.0 24.0 Q2
F280023PTQR LQFP PT 48 1000 330.0 16.4 9.6 9.6 1.9 12.0 16.0 Q2
F280023PTSR LQFP PT 48 1000 330.0 16.4 9.6 9.6 1.9 12.0 16.0 Q2
F280025CPMQR LQFP PM 64 1000 330.0 24.4 13.0 13.0 2.1 16.0 24.0 Q2
F280025CPMSR LQFP PM 64 1000 330.0 24.4 13.0 13.0 2.1 16.0 24.0 Q2
F280025CPNQR LQFP PN 80 1000 330.0 24.4 16.0 16.0 2.0 24.0 24.0 Q2
F280025CPNSR LQFP PN 80 1000 330.0 24.4 16.0 16.0 2.0 24.0 24.0 Q2
F280025CPTQR LQFP PT 48 1000 330.0 16.4 9.6 9.6 1.9 12.0 16.0 Q2
F280025CPTSR LQFP PT 48 1000 330.0 16.4 9.6 9.6 1.9 12.0 16.0 Q2
F280025PMQR LQFP PM 64 1000 330.0 24.4 13.0 13.0 2.1 16.0 24.0 Q2

Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION

www.ti.com 2-Jul-2021

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1

Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
F280025PMSR LQFP PM 64 1000 330.0 24.4 13.0 13.0 2.1 16.0 24.0 Q2
F280025PNQR LQFP PN 80 1000 330.0 24.4 16.0 16.0 2.0 24.0 24.0 Q2
F280025PNSR LQFP PN 80 1000 330.0 24.4 16.0 16.0 2.0 24.0 24.0 Q2
F280025PTQR LQFP PT 48 1000 330.0 16.4 9.6 9.6 1.9 12.0 16.0 Q2
F280025PTSR LQFP PT 48 1000 330.0 16.4 9.6 9.6 1.9 12.0 16.0 Q2

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
F280021PTQR LQFP PT 48 1000 336.6 336.6 31.8
F280021PTSR LQFP PT 48 1000 336.6 336.6 31.8
F280023CPMSR LQFP PM 64 1000 336.6 336.6 41.3
F280023CPNSR LQFP PN 80 1000 367.0 367.0 55.0
F280023CPTSR LQFP PT 48 1000 336.6 336.6 31.8
F280023PMQR LQFP PM 64 1000 336.6 336.6 41.3
F280023PMSR LQFP PM 64 1000 336.6 336.6 41.3
F280023PNQR LQFP PN 80 1000 367.0 367.0 55.0
F280023PNSR LQFP PN 80 1000 367.0 367.0 55.0
F280023PTQR LQFP PT 48 1000 336.6 336.6 31.8
F280023PTSR LQFP PT 48 1000 336.6 336.6 31.8
F280025CPMQR LQFP PM 64 1000 336.6 336.6 41.3

Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION

www.ti.com 2-Jul-2021

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
F280025CPMSR LQFP PM 64 1000 336.6 336.6 41.3
F280025CPNQR LQFP PN 80 1000 367.0 367.0 55.0
F280025CPNSR LQFP PN 80 1000 367.0 367.0 55.0
F280025CPTQR LQFP PT 48 1000 336.6 336.6 31.8
F280025CPTSR LQFP PT 48 1000 336.6 336.6 31.8
F280025PMQR LQFP PM 64 1000 336.6 336.6 41.3
F280025PMSR LQFP PM 64 1000 336.6 336.6 41.3
F280025PNQR LQFP PN 80 1000 367.0 367.0 55.0
F280025PNSR LQFP PN 80 1000 367.0 367.0 55.0
F280025PTQR LQFP PT 48 1000 336.6 336.6 31.8
F280025PTSR LQFP PT 48 1000 336.6 336.6 31.8

Pack Materials-Page 3
MECHANICAL DATA

MTQF003A – OCTOBER 1994 – REVISED DECEMBER 1996

PT (S-PQFP-G48) PLASTIC QUAD FLATPACK

0,27
0,50 0,08 M
0,17

36 25

37 24

48 13

0,13 NOM
1 12

5,50 TYP
7,20
SQ
6,80 Gage Plane
9,20
SQ
8,80
0,25
1,45 0,05 MIN 0°– 7°
1,35

0,75
Seating Plane 0,45

1,60 MAX 0,10

4040052 / C 11/96

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
D. This may also be a thermally enhanced plastic package with leads conected to the die pads.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1

MECHANICAL DATA

MTQF010A – JANUARY 1995 – REVISED DECEMBER 1996

PN (S-PQFP-G80) PLASTIC QUAD FLATPACK

0,27
0,50 0,08 M
0,17

60 41

61 40

0,13 NOM
80 21

1 20 Gage Plane

9,50 TYP
12,20 0,25
SQ
11,80 0,05 MIN 0°– 7°
14,20
SQ
13,80
1,45 0,75
1,35 0,45

Seating Plane

1,60 MAX 0,08

4040135 / B 11/96

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1

PACKAGE OUTLINE
PM0064A SCALE 1.400
LQFP - 1.6 mm max height
PLASTIC QUAD FLATPACK

10.2
B
9.8
NOTE 3
64 49
PIN 1 ID

1 48

10.2 12.2
TYP
9.8 11.8
NOTE 3

16 33

17 32
A
0.27
60X 0.5 64X
0.17
4X 7.5 0.08 C A B

C
(0.13) TYP
SEATING PLANE

0.08
SEE DETAIL A

0.25 (1.4) 1.6 MAX

GAGE PLANE

0 -7 0.75 0.05 MIN

0.45
DETAIL A
DETAIL A
SCALE: 14

TYPICAL
4215162/A 03/2017

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. Reference JEDEC registration MS-026.

www.ti.com
EXAMPLE BOARD LAYOUT
PM0064A LQFP - 1.6 mm max height
PLASTIC QUAD FLATPACK

SYMM
64 49

64X (1.5)

1
48

64X (0.3)

SYMM
60X (0.5) (11.4)

(R0.05) TYP

16 33

17 32
(11.4)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE:8X

0.05 MAX
EXPOSED METAL ALL AROUND EXPOSED METAL 0.05 MIN
ALL AROUND

METAL SOLDER MASK SOLDER MASK METAL UNDER

OPENING SOLDER MASK
NON SOLDER MASK SOLDER MASK
DEFINED DEFINED
SOLDER MASK DETAILS

4215162/A 03/2017
NOTES: (continued)

5. Publication IPC-7351 may have alternate designs.

6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
7. For more information, see Texas Instruments literature number SLMA004 (www.ti.com/lit/slma004).

www.ti.com
EXAMPLE STENCIL DESIGN
PM0064A LQFP - 1.6 mm max height
PLASTIC QUAD FLATPACK

SYMM

64 49

64X (1.5)

1
48

64X (0.3)

SYMM

60X (0.5) (11.4)

(R0.05) TYP

16 33

17 32
(11.4)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE:8X

4215162/A 03/2017

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

www.ti.com
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
permission to use these resources only for development of an application that uses the TI products described in the resource. Other
reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party
intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages,
costs, losses, and liabilities arising out of your use of these resources.
TI’s products are provided subject to TI’s Terms of Sale (https:www.ti.com/legal/termsofsale.html) or other applicable terms available either
on ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s
applicable warranties or warranty disclaimers for TI products.IMPORTANT NOTICE

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