Describe register organization of 8085:

Accumulator
It is an 8-bit register used to perform arithmetic, logical, I/O & LOAD/STORE
operations. It is connected to internal data bus & ALU.
General purpose register
There are 6 general purpose registers in 8085 processor, i.e. B, C, D, E, H & L. Each
register can hold 8-bit data.
These registers can work in pair to hold 16-bit data and their pairing combination is like
B-C, D-E & H-L.
Program counter
It is a 16-bit register used to store the memory address location of the next instruction
to be executed. Microprocessor increments the program whenever an instruction is
being executed, so that the program counter points to the memory address of the next
instruction that is going to be executed.
Stack pointer
It is also a 16-bit register works like stack, which is always incremented/decremented
by 2 during push & pop operations.
Temporary register
It is an 8-bit register, which holds the temporary data of arithmetic and logical
operations.
Flag register
It is an 8-bit register having five 1-bit flip-flops, which holds either 0 or 1 depending
upon the result stored in the accumulator.

1. Sign Flag (S) – After any operation if the MSB (B(7)) of the result is 1, it indicates
the number is negative and the sign flag becomes set, i.e. 1. If the MSB is 0, it
indicates the number is positive and the sign flag becomes reset i.e. 0.
 2. Zero Flag (Z) – After any arithmetical or logical operation if the result is 0 (00)H,
the zero flag becomes set i.e. 1, otherwise it becomes reset i.e. 0.

3. Auxiliary Carry Flag (AC) – This flag is used in BCD number system(0-9). If after
any arithmetic or logical operation D(3) generates any carry and passes on to B(4)
this flag becomes set i.e. 1, otherwise it becomes reset i.e. 0.

4. Parity Flag (P) – If after any arithmetic or logical operation the result has even
parity, an even number of 1 bits, the parity regist er becomes set i.e. 1, otherwise it
becomes reset i.e. 0.
.

5. Carry Flag (CY) – Carry is generated when performing n bit operations and the
result is more than n bits, then this flag becomes set i.e. 1, otherwise it becomes
reset i.e. 0.

Describe architecture of 8085:

Instruction register and decoder

It is an 8-bit register. When an instruction is fetched from memory then it is stored in
the Instruction register. Instruction decoder decodes the information present in the
Instruction register.
Timing and control unit
It provides timing and control signal to the microprocessor to perform operations.
Following are the timing and control signals, which control external and internal circuits
−
 Control Signals: READY, RD’, WR’, ALE
 Status Signals: S0, S1, IO/M’
 DMA Signals: HOLD, HLDA
 RESET Signals: RESET IN, RESET OUT
Interrupt control
As the name suggests it controls the interrupts during a process. When a
microprocessor is executing a main program and whenever an interrupt occurs, the
microprocessor shifts the control from the main program to process the incoming
request. After the request is completed, the control goes back to the main program.
There are 5 interrupt signals in 8085 microprocessor: INTR, RST 7.5, RST 6.5, RST
5.5, TRAP.
Serial Input/output control
It controls the serial data communication by using these two instructions: SID (Serial
input data) and SOD (Serial output data).
Address buffer and address-data buffer
The content stored in the stack pointer and program counter is loaded into the address
buffer and address-data buffer to communicate with the CPU. The memory and I/O
chips are connected to these buses; the CPU can exchange the desired data with the
memory and I/O chips.

Interrupts in 8085
What is interrupt?
Interrupts are the signals generated by the external devices to request the
microprocessor to perform a task. There are 5 interrupt signals, i.e. TRAP, RST 7.5,
RST 6.5, RST 5.5, and INTR.
Types of interrupt:
Interrupt are classified into following groups based on their parameter −
 Vector interrupt − In this type of interrupt, the interrupt address is known to the
processor. For example: RST7.5, RST6.5, RST5.5, TRAP.
  Non-Vector interrupt − In this type of interrupt, the interrupt address is not known to the
processor so, the interrupt address needs to be sent externally by the device to perform
interrupts. For example: INTR.
 Maskable interrupt − In this type of interrupt, we can disable the interrupt by writing some
instructions into the program. For example: RST7.5, RST6.5, RST5.5.
 Non-Maskable interrupt − In this type of interrupt, we cannot disable the interrupt by writing
some instructions into the program. For example: TRAP.
 Software interrupt − In this type of interrupt, the programmer has to add the instructions
into the program to execute the interrupt. There are 8 software interrupts in 8085, i.e. RST0,
RST1, RST2, RST3, RST4, RST5, RST6, and RST7.
 Hardware interrupt − There are 5 interrupt pins in 8085 used as hardware interrupts, i.e.
TRAP, RST7.5, RST6.5, RST5.5, INTA.

What is Interrupt Service Routine (ISR)?

A small program or a routine that when executed, services the corresponding
interrupting source is called an ISR.
What is TRAP?
It is a non-maskable interrupt, having the highest priority among all interrupts.
Bydefault, it is enabled until it gets acknowledged. In case of failure, it executes as ISR
and sends the data to backup memory. This interrupt transfers the control to the
location 0024H.

Explain Addressing modes in 8085 microprocessor

with example:
The way of specifying data to be operated by an instruction is called addressing mode.

Types of addressing modes –

In 8085 microprocessor there are 5 types of addressing modes:

1. Immediate Addressing Mode –
In immediate addressing mode the source operand is always data. If the data is 8-bit, then
the instruction will be of 2 bytes, if the data is of 16-bit then the instruction will be of 3
bytes.

Examples:
MVI B 45H (move the data 45H immediately to register B)

2. Register Addressing Mode –

In register addressing mode, the data to be operated is available inside the register(s) and
register(s) is(are) operands. Therefore the operation is performed within various registers
of the microprocessor.
 Examples:
MOV A, B (move the contents of register B to register A)

3. Direct Addressing Mode –

In direct addressing mode, the data to be operated is available inside a memory location
and that memory location is directly specified as an operand. The operand is directly
available in the instruction itself.
Examples:
LDA 2050H (load the contents of memory location into accumulator A)

4. Register Indirect Addressing Mode –

IN register indirect addressing mode, the data to be operated is available inside a memory
location and that memory location is indirectly specified b a register pair.
Examples:
MOV A, M (move the contents of the memory location pointed by the H-L pair to
the accumulator)

5. Implied/Implicit Addressing Mode –

In implied/implicit addressing mode the operand is hidden and the data to be operated is
available in the instruction itself.
Examples:
CMA (finds and stores the 1’s complement of the contains of accumultor A in A)

Describe different mode of operation of 8255 PPI:

There are two different modes of 8255. These modes are:

 Bit Set Reset (BSR) Mode
 Input/ Output Mode

Bit Set Reset (BSR) Mode

This mode is used to set or reset the bits of the Port-C only. For BSR mode always D7
will be 0.
In this mode it affects only one bit of Port C at a time. When user set the bit, it remains
set until user unset it. The user needs to load the bit pattern in control register to change
the bit.

Input/ Output Mode

This mode is selected when the D7 bit of the control register is 1.
This mode has also three different modes. These modes are Mode 0 and Mode 1 and
Mode 3.
Mode 0 – Simple or basic I/O Mode
In this mode all of the ports A, B and C can be used as input or output mode. The
outputs are latched, but inputs are not latched. This mode has interrupt handling
capability.
Mode 1 – Handshake or Strobed I/O
In this mode the Port A and Port B can be used as input or output ports, the port C are
used for handshaking. In this mode the inputs and outputs are latched. This mode also
has the interrupt handling capability, and signal control to match the speed of CPU and
IO devices.
Mode 3 – Bidirectional I/O
In this mode only Port A can work, and port B can either be in mode 0 or mode 1, and
the port C are used for handshaking. In this mode the inputs and outputs are latched.

Explain Control word format of 8255 in I/O mode:

Explain SIM and RIM instruction:

Describe the function of 8259A (programmable interrupt

controller)
1. Data bus buffer –
This Block is used as a mediator between 8259 and 8085/8086 microprocessor by
acting as a buffer. It takes the control word from the 8085 (let say) microprocessor
and transfer it to the control logic of 8259 microprocessor. Also, after selection of
Interrupt by 8259 microprocessor, it transfer the opcode of the selected Interrupt
and address of the Interrupt service sub routine to the other connected
microprocessor.
2. Read/Write logic –
This block works only when the value of pin CS is low (as this pin is active low).
This block is responsible for the flow of data depending upon the inputs of RD and
WR. These two pins are active low pins used for read and write operations.
3. Control logic –
It is the centre of the microprocessor and controls the functioning of every block. It
 has pin INTR which is connected with other microprocessor for taking interrupt
request and pin INT for giving the output.
4. Interrupt request register (IRR) –
It stores all the interrupt level which are requesting for Interrupt services.
5. Interrupt service register (ISR) –
It stores the interrupt level which are currently being executed.
6. Interrupt mask register (IMR) –
It stores the interrupt level which have to be masked by storing the masking bits of
the interrupt level.
7. Priority resolver –
It examines all the three registers and set the priority of interrupts and according to
the priority of the interrupts, interrupt with highest priority is set in ISR register.
Also, it reset the interrupt level which is already been serviced in IRR.
8. Cascade buffer –
To increase the Interrupt handling capability, we can further cascade more number
of pins by using cascade buffer. So, during increment of interrupt capability, CSA
lines are used to control multiple interrupt structure.