Subject: ECE3004

Microprocessors and Microcontrollers

Dr. Om Prakash Pahari

Course type: LTP

Credits: 4
COMPUTER SYSTEM COMPONENTS
Memory
Stores instructions and data

Input/Output
Called peripherals
Used to input and output instructions and data

Arithmetic and Logic Unit

– Performs arithmetic operations (addition, subtraction)
– Performs logical operations (AND, OR, XOR, SHIFT, ROTATE)
COMPUTER SYSTEM
COMPONENTS
Control Unit
– Coordinates the operation of the computer
System Interconnection and Interaction
Bus—A group of lines used to transfer bits between the
microprocessor and other components of the computer system. Bus is
used to communicate between parts of the computer. There is only
one transmitter at a time and only the addressed device can respond.
Types
» Address
» Data
» Control signals
CPU COMPONENTS
Registers
Hold data, instructions, or other items.
Various sizes.
Program counter and memory address registers must be of
same size/width as address bus.
Registers which hold data must be of same size/width
as memory words.
CPU COMPONENTS
Control Unit
Generates control signals which are
necessary for execution of an instruction.
Connect registers to the bus.
Controls the data flow between CPU
and peripherals (including memory).
Provides status, control & timing signals
required for the operation of memory and
I/O devices to the system.
Acts as a brain of computer system
All actions of the control unit are
associated with the decoding and
executions of instructions (fetch and
CPU COMPONENTS
Arithmetic and Logic Unit
Executes arithmetic and logical operations.
Accumulator is a special 8-bit register
associated with ALU.Register ‘A’ in 8085 is an
accumulator.
Source of one of the operands of an arithmetic
or logical operation.
serves as one input to ALU.
Final result of an arithmetic or logical
operation is placed in accumulator.
ARITHMETIC AND
LOGIC UNIT
ALU performs the following arithmetic & logical
operations:
Addition
Subtraction
Logical AND
Logical OR
Logical EXCLUSIVE OR
Complement(logical NOT)
Increment (add 1)
Decrement (subtract 1)
Left shift, Rotate Left, Rotate right
Clear etc.
Data and instructions are stored in a single set o f
read-write memory. Contents of memory are addressable
by memory address, without regard to the type of data
contained.Execution occurs in a sequential fashion, unless
explicitly altered, from one instruction to the other.
Performance metrics of CPU:

Short response time for a given piece of work

High throughput (rate of processing work)
Low utilization of computing resource(s)
High availability of the computing system or application
Fast (or highly compact) data compression and decompression
High bandwidth
Short data transmission time.
Microprocessor and microcontrollers:

https://www.youtube.com/watch?v=_Cdf68NMTZ0.
MICROPROCESSO
R
is a semiconductor device consisting
of electronic logic circuits
manufactured by using various
fabrication schemes
capable of performing computing
functions
capable of transporting data/information
can be divided into 3 segments:
Arithmetic and Logic Unit
Register Unit
History: https://spectrum.ieee.org/the-surprising-story-of-the-first-microprocessors
Control Unit
 HISTORY OF INTEL
MICROPROCESSORS

1
CONTENTS

Introduction
4-Bit Microprocessors
8-Bit Microprocessors
16-Bit Microprocessors
32-Bit Microprocessors
64-Bit Microprocessors
2
 INTRODUCTION
Fairchild Semiconductors (founded in 1957) invented the first
IC in 1959.
In 1968, Robert Noyce, Gordan Moore, Andrew Grove
resigned from Fairchild Semiconductors.

They founded their own company Intel (Integrated

Electronics).

Intel grown from 3 man start-up in 1968 to industrial giant by

1981.

It had 20,000 employees and $188 million revenue

3
4-BIT MICROPROCESSORS

4
INTEL Introduced in 1971.
4004
It was the first microprocessor by
Intel.

It was a 4-bit µP.

Its clock speed was 740KHz.

It had 2,300 transistors.

It could execute around 60,000

instructions per second.

4-bit microprocessor
4 KB main memory
45 instructions
PMOS technology 5

was first programmable device which was used in calculators

INTEL
4040
Introduced in 1974.
It was also 4-bit µP.

6
8-BIT MICROPROCESSORS

7
INTEL
8008
Introduced in 1972.
It was first 8-bit µP.
Its clock speed was 500 KHz.
Could execute 50,000 instructions
per second.

8-bit version of 4004

16 KB main memory
48 instructions
PMOS technology 8
Slow
INTEL
8080 Introduced in 1974.
It was also 8-bit µP.
Its clock speed was
2 MHz.
8-bit microprocessor
64 KB main memory It had 6,000 transistors.
2 microseconds clock cycle time
500,000 instructions/sec Was 10 times faster
10X faster than 8008 than 8008.
NMOS technology
Drawback was that it needed Could execute
three power supplies. 5,00,000 instructions
Small computers (Microcomputers) per second.
were designed in mid 1970’s using 9
8080 as CPU.
 Introduced in 1976.
INTEL 8085
It was also 8-bit µP.
Its clock speed was 3 MHz.

Its data bus is 8-bit and

address bus is 16-bit.
It had 6,500 transistors.
8-bit microprocessor-upgraded
version of 8080
Could execute 7,69,230
64 KB main memory instructions per second.
1.3 microseconds clock cycle It could access 64 KB of
time
memory.
246 instructions
Intel sold 100 million It had 246 instructions.
copies of this 8-bit Over 100 million copies were 10
microprocessor sold.
uses only one +5v power supply.
16-BIT MICROPROCESSORS

1
1
 Introduced in 1978.

It was first 16-bit µP.

INTEL 8086
Its clock speed is 4.77 MHz, 8 MHz and
10 MHz, depending on the version.

Its data bus is 16-bit and

address bus is 20-bit.

It had 29,000 transistors.

Could execute 2.5 million

instructions per second.

It could access 1 MB of memory.

It had 22,000 instructions.

It had Multiply and Divide

instructions. 12
INTEL
8088 Introduced in 1979.

It was also 16-bit µP.

It was created as a cheaper

version of Intel’s 8086.

It was a 16-bit processor with an

8-bit external bus.

Could execute 2.5 million

instructions per second.

This chip became the most popular in

the computer industry when IBM used
it for its first PC

13
.
Intel 8086/8088

Year of introduction 1978 for 8086 and 1979 for

8088
16-bit microprocessors
Data bus width of 8086 is 16 bit and 8 bit for 8088
1 MB main memory
400 nanoseconds clock cycle time
6 byte instruction cache for 8086 and 4 byte for 8088
Other improvements included more registers and
additional instructions
In 1981 IBM decided to use 8088 in its personal computer
INTEL 80186 & 80188
Introduced in 1982.
They were 16-bit µPs.
Clock speed was 6 MHz.
80188 was a cheaper version of
80186 with an 8- bit external
data bus.
They had additional components
like:
Interrupt Controller
Clock Generator
Local Bus Controller
14
Counters
Intel 80186

Year of introduction 1982

16-bit microprocessor-upgraded version of 8086
1 MB main memory
Contained special hardware like
programmable counters, interrupt controller
etc.
Never used in the PC
But was ideal for systems that required a minimum
of hardware
INTEL
80286 Introduced in 1982.

It was 16-bit µP.

Its clock speed was 8

MHz.

Its data bus is 16-bit

and address bus is
24-bit.

It could address 16 MB of
memory.

It had 1,34,000 transistors.

It could execute 4 million 15

instructions per second.
HISTORICAL BACKGROUND OF
INTEL MICROPROCESSORS
Intel 80286

Year of introduction 1983

16-bit high performance microprocessor with
memory management & protection
16 MB main memory
Few additional instructions to handle extra 15 MB
Instruction execution time is as little as 250 ns
Concentrates on the features needed to
implement MULTITASKING
32-BIT MICROPROCESSORS

16
 Introduced in 1986.
INTEL It was first 32-bit µP.
80386 Its data bus is 32-bit and
address bus is 32-bit.
It could address 4 GB of
memory.
It had 2,75,000 transistors.
Its clock speed varied from 16
MHz to 33 MHz depending upon
the various versions.
Different versions:
80386 DX
80386 SX
80386 SL

Intel 80386 became the best 17

selling microprocessor in
history.
Intel 80386

Year of introduction 1986

Intel’s first practical 32-bit microprocessor
4 GB main memory
Improvements include page handling in
virtual environment
Includes hardware circuitry for memory
management and memory assignment
Memory paging and enhanced I/O permissions
INTEL Introduced in 1989.
80486 It was also 32-bit µP.
It had 1.2 million transistors.
Its clock speed varied from 16
MHz to 100 MHz depending
upon the various versions.
It had five different versions:

80486 DX
80486 SX
80486 DX2
80486 SL
80486 DX4
8 KB of cache memory was
18
introduced.
Intel 80486

Year of introduction 1989

32-bit high performance microprocessor
4 GB main memory
Incorporates 80387-like floating point coprocessor
and
8 K byte cache on one package
About half of the instructions executed in 1
clock instead of 2 on the 80386
INTEL Introduced in 1993.
PENTIUM It was also 32-bit
µP.
It was originally named 80586.

Its clock speed was 66 MHz.

Its data bus is 32-bit and

address bus is 32-bit.

It could address 4 GB of
memory.

Could execute 110 million

instructions per second.

Cache memory:
8 KB for instructions.
19
8 KB for data.
Pentium
Year of introduction 1993
32-bit microprocessor, 64-bit data bus and
32-bit address bus
4 GB main memory
Double clocked 120 and 133MHz versions
Fastest version is the 233MHz, Dual integer
processor
16 KB L1 cache (split instruction and data: 8 KB
each)
INTEL PENTIUM
PRO
Introduced in 1995.
It was also 32-bit µP.
It had L2 cache of 256 KB.
It had 21 million transistors.

It was primarily used in

server systems.
Cache memory:
8 KB for instructions.

8 KB for data.
20

It had L2 cache of 256 KB.

Pentium Pro
Year of introduction 1995
32-bit microprocessor, formerly code-named P6
64 GB main memory, 64-bit data bus and
36-bit address bus
16 KB L1 cache (split instruction/data: 8 KB each),
256 KB L2 cache
Uses three execution engines
Intel launched this processor for the server market
INTEL
PENTIUM II
Introduced in 1997.
It was also 32-bit µP.
Its clock speed was 233 MHz
to 500 MHz.

Could execute 333 million

instructions per second.

MMX technology was

supported.

L2 cache & processor were 21

on one circuit.
Pentium II
Year of introduction 1997
32-bit microprocessor, 64-bit data bus and
36-bit address bus, MMX
64 GB main memory
32 KB split instruction/data L1 caches (16 KB
each)
Module integrated 512KB L2 cache (133MHz)
A version of P2 called Xeon; specifically designed
for high-end applications
INTEL PENTIUM II
XEON
Introduced in 1998.

It was also 32-bit µP.

It was designed for servers.

Its clock speed was 400 MHz

to 450 MHz.

L1 cache of 32 KB & L2 cache

of 512 KB, 1MB or 2 MB.

It could work with 4 Xeons in

same system.
22
INTEL Introduced in 1999.
PENTIUM III It was also 32-bit µP.
Its clock speed varied from 500
MHz to 1.4 GHz.
It had 9.5 million
transistors.
32-bit microprocessor, 64-bit
data bus and 36-bit address bus
64 GB main memory
Dual Independent Bus
(simultaneous L2 and system
memory access)
23
On-chip 256 KB L2 cache
P3 was available in clock frequencies
of up to 1 GHz
 Introduced in 2000.
INTEL PENTIUM
It was also 32-bit µP.
IV
Its clock speed was from
1.3 GHz to 3.8 GHz.

L1 cache was of 32 KB & L2 cache

of 256 KB.

It had 42 million transistors.

All internal connections were made

from aluminium to copper.

32-bit microprocessor, 64-bit data bus and 36-bit address bus

64 GB main memory
1.4 to 1.9 GHz and the latest at 3.20 GHz and 3.46GHz (Hyper-Threading)
1MB/512KB/256KB L2 cache 24

Specialized for streaming video, game and DVD applications

INTEL DUAL
Introduced in 2006.
CORE
It is 32-bit or 64-bit µP.
It has two cores.
Both the cores have there own
internal bus and L1 cache, but
share the external bus and L2
cache.
It supported SMT
technology.

SMT: Simultaneously Multi-

Threading
E.g.: Adobe Photoshop supported
25
SMT.
45
64-BIT MICROPROCESSORS

46
INTEL CORE
2 Introduced in 2006.
It is a 64-bit µP.

Its clock speed is from 1.2 GHz to 3

GHz.
It has 291 million transistors.
It has 64 KB of L1 cache per core and 4
MB of L2 cache.
It is launched in three different versions:
Intel Core 2 Duo
Intel Core 2 Quad
Intel Core 2 Extreme
28
INTEL CORE
I7
Introduced in 2008.

It is a 64-bit µP.

It has 4 physical cores.

Its clock speed is from 2.66 GHz to

3.33 GHz.

It has 230 billion transistors.

It has 64 KB of L1 cache per

core, 256 KB of L2 cache and 8
MB of L3 cache.
29
INTEL CORE
I5
Introduced in 2009.

It is a 64-bit µP.

It has 4 physical cores.

Its clock speed is from 2.40 GHz to

3.60 GHz.

It has 781 million transistors.

It has 64 KB of L1 cache per

core, 256 KB of L2 cache and 8
MB of L3 cache.

30
INTEL CORE
I3
Introduced in 2010.

It is a 64-bit µP.

It has 2 physical cores.

Its clock speed is from 2.93 GHz to

3.33 GHz.

It has 781 million transistors.

It has 64 KB of L1 cache per core,

512 KB of L2 cache and 4 MB of
L3 cache.
31
INTEL CORE I9
Introduced in 2017.

It is a 64-bit µP.

It has 10 physical cores.

Its clock speed is from

3.33 GHz to 5.2 GHz.

It has 430 billion

transistors.

It has 64 KB of L1
cache per core, 1 MB
of L2 cache per core
and 13.75 MB of L3
cache.
Assembly language, high level language, low level language,
machine language:
http://www.itrelease.com/2018/07/difference-between-assembly-language-and-high
-level-language/.
MOV A, M : Assembly language
7E (0111 1110): Machine language

▪ Assembly language and machine language are treated as low level languages.

▪ Assembly language vs high-level language :

▪ In assembly language programs written for one processor will not run on another type of
processor. In high-level language programs run independently of processor type.
▪ Performance and accuracy of assembly language code are better than a high-level.
▪ High-level languages have to give extra instructions to run code on the computer.
▪ Code of assembly language is difficult to understand and debug than a high-level.
▪ One or two statements of high-level language expand into many assembly language
codes.
▪ Assembly language can communicate better than a high-level. Some type
of hardware actions can only be performed by assembly language.
▪ In assembly language, we can directly read pointers at a physical address which is not
possible in high-level
▪ Working with bits is easier in assembly language.
▪ Assembler is used to translate code in assembly language while the compiler is used to
compile code in the high-level.
▪ The executable code of high-level language is larger than assembly language code so it
takes a longer time to execute.
▪ Due to long executable code, high-level programs are less efficient than assembly
language programs.
▪ High-level language programmer does not need to know details about hardware
like registers in the processor as compared to assembly programmers.
▪ The most high-level language code is first automatically converted into assembly code.
 Assembly Programming
• Machine Language
• binary
• hexadecimal
• machine code or object code

• Assembly Language
• mnemonics
• assembler

• High-Level Language
• Pascal, Basic, C
• compiler
Assembly Language Programming
Microprocessor development tools:
https://csenotesforyou.blogspot.com/2016/12/assembly-language-program-develo
pment.html.
Hardware Tools :
Software Tools !
In Circuit Emulator (ICE)
Assembler !
Logic Analyzer
Linker !
Emulator
Loader !
Compiler ! ▪ A debugger is a computer program used by programmers to test
Libraries ! and debug a target program. Debuggers may use instruction-set
Simulator ! simulators, rather than running a program directly on the
Debugger ! processor to achieve a higher level of control over its execution.
Locator ! This allows debuggers to stop or halt the program according to
specific conditions. However, use of simulators decreases
execution speed. When a program crashes, debuggers show the
position of the error in the target program. Most debuggers also
are capable of running programs in a step-by-step mode, besides
stopping on specific points. They also can often modify the state
of programs while they are running.
5. Debugger: - A debugger is a program which allows you to load your object code
program into system memory, execute the program and troubleshoot or debug it.

The debugger allows you to look at the contents of registers and memory locations
after your program runs.

- It allows you to change the contents of registers and memory locations and re-run
the program.

- Some debuggers allow you to stop execution after each instruction so that you can
check or alter after each register contents.

- A debugger also allows you to set a breakpoint at any point in your program. If you
insert a breakpoint at any point in your program, the debugger will run the program
up to the instruction where you put the breakpoint and then stop the execution.

6. Emulator: - An emulator is a mixture of hardware and software.

- It is used to test and debug the hardware and software of an external system, such as
the prototype of a microprocessor based instrument. Part of the hardware of an
emulator is a multi wire cable which connects the host system to the system being
developed. Ex: FPGAs, USRPs.
Logic analysers:
https://www.radio-electronics.com/info/t_and_m/logic_analyzer/logic_analyzer.php.
Debugging, Simulator, Emulator, In-circuit
emulator:
https://www.youtube.com/watch?v=4wmDsd53ibE.

ICE:
Embedded systems pose unique debugging challenges. With neither terminal nor
display (in most cases), there's no natural way to probe these devices, to extract the
behavioural information needed to find what's wrong. They let us connect an external
computer to the system being debugged to enable single stepping, breakpoints, and all
of the debug resources enjoyed by programmers of desktop computers.

In-circuit emulation (ICE) is the use of a hardware device or in-circuit emulator used
to debug the software of an embedded system. It operates by using a processor with the
additional ability to support debugging operations, as well as to carry out the main function of
the system. Particularly for older systems, with limited processors, this usually involved
replacing the processor temporarily with a hardware emulator: a more powerful although more
expensive version. It was historically in the form of bond-out processor which has many
internal signals brought out for the purpose of debugging. These signals provide information
about the state of the processor.
An in-circuit emulator (ICE) provides a window into the embedded system. The
programmer uses the emulator to load programs into the embedded system, run
them, step through them slowly, and view and change data used by the system's
software.
WHAT DOES IT MEAN TO
DISASSEMBLE CODE?
Preprocessing
& Compiling
Source Code Assembly Code

Assembly

Executable Code Object Code

Linking

DLLs
WHAT DOES IT MEAN TO
DISASSEMBLE CODE?
Preprocessing
& Compiling
Source Code Assembly Code

L Y
MB
S E
A S Assembly
S
DI

Executable Code Object Code

Linking

DLLs
1. Linker :

A linker is special program that combines the object files, generated by

compiler/assembler, and other pieces of codes to originate an executable file have.
exe extension. In the object file, linker searches and append all libraries needed for
execution of file. It regulates the memory space that will hold the code from each
module. It also merges two or more separate object programs and establishes link
among them.

2. Loader :

The loader is special program that takes input of object code from linker, loads it to
main memory, and prepares this code for execution by computer. Loader allocates
memory space to program. Even it settles down symbolic reference between objects.
It is in charge of loading programs and libraries in operating system.
A locator is a program used to assign the specific addresses of where the
segments of object code are to be loaded into memory.
 Subject: ECE3004

Microprocessors and Microcontrollers

Dr. Anveshkumar Nella

Course type: LTP

Credits: 4
 Microprocessor Fifth Generation Pentium

Fourth Generation
During 1980s
Low power version of HMOS technology
(HCMOS)
Third Generation 32 bit processors
During 1978 Physical memory space 224 bytes = 16 Mb
HMOS technology ⇒ Faster speed, Higher Virtual memory space 240 bytes = 1 Tb
packing density Floating point hardware
16 bit processors ⇒ 40/ 48/ 64 pins Supports increased number of addressing
Easier to program modes
Dynamically relatable programs
Processor has multiply/ divide arithmetic Intel 80386
hardware
More powerful interrupt handling
capabilities Second Generation
Flexible I/O port addressing During 1973
NMOS technology ⇒ Faster speed, Higher
Intel 8086 (16 bit processor) density, Compatible with TTL
4 / 8/ 16 bit processors ⇒ 40 pins
First Generation Ability to address large memory spaces
Between 1971 – 1973 and I/O ports
PMOS technology, non compatible with TTL Greater number of levels of subroutine
4 bit processors ⇒ 16 pins nesting
8 and 16 bit processors ⇒ 40 pins Better interrupt handling capabilities
Due to limitations of pins, signals are 2
multiplexed Intel 8085 (8 bit processor)
General Microprocessor Functional blocks

Various conditions of the

Computational Unit;
results are stored as
performs arithmetic and Internal storage of data
status bits called flags in
logic operations
flag register

Register array or Data Bus

internal memory
ALU
Generates the
address of the
Instruction
Flag instructions to be
decoding unit
Register fetched from the
memory and send
through address
bus to the
Timing and memory
control unit PC/ IP

Control Bus Address Bus

Generates control signals for Decodes instructions; sends

internal and external operations information to the timing and
of the microprocessor control unit 3
8086 Microprocessor

Overview
First 16- bit processor released by
INTEL in the year 1978

Originally HMOS, now manufactured

using HMOS III technique

Approximately 29, 000 transistors, 40

pin DIP, 5V supply

Does not have internal clock; external

asymmetric clock source with 33% duty
cycle

20-bit address to access memory ⇒ can

address up to 220 = 1 megabytes of
memory space.

4
8086 Microprocessor
Common signals

Pins and Signals AD0-AD15 (Bidirectional)

Address/Data bus

Low order address bus; these are

multiplexed with data.

When AD lines are used to transmit

memory address the symbol A is used
instead of AD, for example A0-A15.

When data are transmitted over AD lines

the symbol D is used in place of AD, for
example D0-D7, D8-D15 or D0-D15.

A16/S3, A17/S4, A18/S5, A19/S6

High order address bus. These are

multiplexed with status signals

https://www.geeksforgeeks.org/pin-diagram-8086-microprocessor/ 5
8086 Microprocessor
Common signals

Pins and Signals BHE (Active Low)/S7 (Output)

Bus High Enable/Status

It is used to enable data onto the most

significant half of data bus, D8-D15. 8-bit
device connected to upper half of the
data bus use BHE (Active Low) signal. It
is multiplexed with status signal S7.

MN/ MX

MINIMUM / MAXIMUM

This pin signal indicates what mode the

processor is to operate in.

RD (Read) (Active Low)

The signal is used for read operation.

It is an output signal.
It is active when low.
6
8086 Microprocessor
Common signals

Pins and Signals

READY

This is the acknowledgement from the

slow device or memory that they have
completed the data transfer.

The signal made available by the devices

is synchronized by the 8284A clock
generator to provide ready input to the
8086.

The signal is active high. 7

 8086 Microprocessor
Common signals

Pins and Signals RESET (Input)

Causes the processor to immediately

terminate its present activity.

The signal must be active HIGH for at

least four clock cycles.

CLK

The clock input provides the basic timing

for processor operation and bus control
activity. Its an asymmetric square wave
with 33% duty cycle.

INTR Interrupt Request

This is a triggered input. This is sampled

during the last clock cycles of each
instruction to determine the availability
of the request. If any interrupt request is
pending, the processor enters the
The 8086 does not have on-chip clock
interrupt acknowledge cycle.
generation circuit. Hence the clock
generator chip, 8284 is connected to the This signal is active high and internally
synchronized. 8
CLK pin of 8086.
8086 Microprocessor
Min/ Max Pins

Pins and Signals

The 8086 microprocessor can work in two
modes of operations : Minimum mode and
Maximum mode.

In the minimum mode of operation the

microprocessor do not associate with any
co-processors and can not be used for
multiprocessor systems.

In the maximum mode the 8086 can work

in multi-processor or co-processor
configuration.

Minimum or maximum mode operations

are decided by the pin MN/ MX(Active low).

When this pin is high 8086 operates in

minimum mode otherwise it operates in
Maximum mode.

9
8086 Microprocessor
Minimum mode signals

Pins and Signals

(Data Transmit/ Receive) Output signal from the

processor to control the direction of data flow
through the data transceivers

(Data Enable) Output signal from the processor

used as out put enable for the transceivers.

ALE (Address Latch Enable) Used to demultiplex the

address and data lines using external latches

Used to differentiate memory access and I/O

access. For memory reference instructions, it is
high. For IN and OUT instructions, it is low.

Write control signal; asserted low Whenever

processor writes data to memory or I/O port

(Interrupt Acknowledge) When the interrupt

request is accepted by the processor, the output is
low on this line.
10
DEN

It stands for Data Enable and is available at pin 26. It is used to enable Transreceiver 8286.
The transreceiver is a device used to separate data from the address/data bus.

ALE

It stands for address enable latch and is available at pin 25. A positive pulse is generated
each time the processor begins any operation. This signal indicates the availability of a valid
address on the address/data lines.
8086 Microprocessor
Minimum mode signals

Pins and Signals

HOLD Input signal to the processor from the bus masters

as a request to grant the control of the bus.

Usually used by the DMA controller to get the

control of the bus.

HLDA (Hold Acknowledge) Acknowledge signal by the

processor to the bus master requesting the control
of the bus through HOLD.

The acknowledge is asserted high, when the

processor accepts HOLD.

12
8086 Microprocessor
Maximum mode signals

Pins and Signals

Status signals; used by the 8086 bus controller to

generate bus timing and control signals. These are
decoded as shown.

13
8086 Microprocessor
Maximum mode signals

Pins and Signals

(Queue Status) The processor provides the status

of queue in these lines.

The queue status can be used by external device to

track the internal status of the queue in 8086.

The output on QS0 and QS1 can be interpreted as

shown in the table.

▪ These signals provide the status of instruction queue. 14

8086 Microprocessor
Maximum mode signals

Pins and Signals

15
 Inside The 8088/8086

Concepts important to the internal

operation of 8088/8086

• Pipelining
• Registers
 Inside The 8088/8086…pipelining
• Pipelining
– Two ways to make CPU process information faster:
• Increase the working frequency – technology dependent
• Change the internal architecture of the CPU

– Pipelining is to allow CPU to fetch and execute at the

same time
 Inside The 8088/8086…pipelining

Intel implemented the concept of pipelining by splitting

the internal structure of the 8088/8086 into two
sections that works simultaneously:

• Execution Unit (EU) – Executes instructions previously fetched

• Bus Interface Unit (BIU) – Accesses memory and peripherals

8086 Microprocessor
Architecture

Execution Unit (EU) Bus Interface Unit (BIU)

EU executes instructions that have BIU fetches instructions, reads data

already been fetched by the BIU. from memory and I/O ports, writes
data to memory and I/ O ports.
BIU and EU functions separately.
19
8086 Microprocessor
Bus Interface Unit (BIU)

Dedicated Adder to generate

20 bit address

Four 16-bit segment

registers

Code Segment (CS)

Data Segment (DS)
Stack Segment (SS)
Extra Segment (ES)

Architecture
Segment Registers >> 20
 8086 Microprocessor
Bus Interface Unit (BIU)
Architecture
Segment
Registers

• 8086’s 1-megabyte • The 8086 can directly • Programs obtain access to

memory is divided address four segments (256 code and data in the
into segments of up K bytes within the 1 M byte segments by changing the
to 64K bytes each. of memory) at a particular segment register content
time. to point to the desired
segments.
21
8086 Microprocessor
Bus Interface Unit (BIU)

Architecture
Segment Code Segment Register
Registers
• 16-bit

• CS contains the base or start of the current code segment; IP contains the
distance or offset from this address to the next instruction byte to be fetched.

• BIU computes the 20-bit physical address by logically shifting the contents of CS
4-bits to the left and then adding the 16-bit contents of IP.

• That is, all instructions of a program are relative to the contents of the CS
register multiplied by 16 and then offset is added provided by the IP.

23
8086 Microprocessor
Bus Interface Unit (BIU)
Architecture
Segment Data Segment Register
Registers
• 16-bit

• Points to the current data segment; operands for most instructions are fetched
from this segment.

• The 16-bit contents of the Source Index (SI) or Destination Index (DI) or a
16-bit displacement are used as offset for computing the 20-bit physical
address.

24
8086 Microprocessor
Bus Interface Unit (BIU)
Architecture
Segment Stack Segment Register
Registers
• 16-bit

• Points to the current stack.

• The 20-bit physical stack address is calculated from the Stack Segment (SS) and
the Stack Pointer (SP) for stack instructions such as PUSH and POP.

• In based addressing mode, the 20-bit physical stack address is calculated from
the Stack segment (SS) and the Base Pointer (BP).

25
8086 Microprocessor
Bus Interface Unit (BIU)

Architecture
Segment
Registers
Extra Segment Register

• 16-bit

• Points to the extra segment in which data (in excess of 64K pointed to by the
DS) is stored.

• String instructions use the ES and DI to determine the 20-bit physical address
for the destination.

26
8086 Microprocessor
Bus Interface Unit (BIU)

Architecture
Segment Instruction Pointer
Registers
• 16-bit

• Always points to the next instruction to be executed within

the currently executing code segment.

• So, this register contains the 16-bit offset address pointing

to the next instruction code within the 64KB of the code
segment area.

• Its content is automatically incremented as the execution

of the next instruction takes place.

27
8086 Microprocessor
Bus Interface Unit (BIU)

Instruction queue

• A group of First-In-First-Out (FIFO) in

which up to 6 bytes of instruction
code are pre fetched from the
memory ahead of time.

• This is done in order to speed up the

execution by overlapping instruction
fetch with execution.

• This mechanism is known as

pipelining.

Architecture
28
8086 Microprocessor
Execution Unit (EU)

EU decodes and Architecture

executes instructions.

A decoder in the EU
control system
translates instructions.

16-bit ALU for

performing arithmetic
and logic operation

Four general purpose

registers(AX, BX, CX, DX);

Pointer registers (Stack

Pointer, Base Pointer);

and
Some of the 16 bit registers can be
Index registers (Source used as two 8 bit registers as :
Index, Destination Index)
each of 16-bits AX can be used as AH and AL
BX can be used as BH and BL
CX can be used as CH and CL 29
DX can be used as DH and DL
8086 Microprocessor
Execution Unit (EU)

Architecture
EU Accumulator Register (AX)
Registers

• Consists of two 8-bit registers AL and AH, which can be

combined together and used as a 16-bit register AX.

• AL in this case contains the low order byte of the word,

and AH contains the high-order byte.

• The I/O instructions use the AX or AL for inputting /

outputting 16 or 8 bit data to or from an I/O port.

• Multiplication and Division instructions also use the AX or

AL.

30
8086 Microprocessor
Execution Unit (EU)
Architecture
EU Base Register (BX)
Registers
• Consists of two 8-bit registers BL and BH, which can be
combined together and used as a 16-bit register BX.

• BL in this case contains the low-order byte of the word,

and BH contains the high-order byte.

• This is the only general purpose register whose contents

can be used for addressing the 8086 memory.

• All memory references utilizing this register content for

addressing use DS as the default segment register.

31
8086 Microprocessor
Execution Unit (EU)

Architecture
EU Counter Register (CX)
Registers
• Consists of two 8-bit registers CL and CH, which can be
combined together and used as a 16-bit register CX.

• When combined, CL register contains the low order byte of

the word, and CH contains the high-order byte.

• Instructions such as SHIFT, ROTATE and LOOP use the

contents of CX as a counter.

Example:

The instruction LOOP START automatically decrements

CX by 1 without affecting flags and will check if [CX] =
0.

If it is zero, 8086 executes the next instruction;

otherwise the 8086 branches to the label START.

32
8086 Microprocessor
Execution Unit (EU)
Architecture
EU
Registers

33
8086 Microprocessor
Execution Unit (EU)

Architecture
EU Stack Pointer (SP) and Base Pointer (BP)
Registers
• SP and BP are used to access data in the stack segment.

• SP is used as an offset from the current SS during

execution of instructions that involve the stack segment in
the external memory.

• SP contents are automatically updated (incremented/

decremented) due to execution of a POP or PUSH
instruction.

• BP contains an offset address in the current SS, which is

used by instructions utilizing the based addressing mode.

34
8086 Microprocessor
Execution Unit (EU)
Architecture
EU Source Index (SI) and Destination Index (DI)
Registers
• Used in indexed addressing.

• Instructions that process data strings use the SI and DI

registers together with DS and ES respectively in order to
distinguish between the source and destination addresses.

35
8086 Microprocessor
Architecture Execution Unit (EU)
Auxiliary Carry Flag
Carry Flag
Flag Register This is set, if there is a carry from the
This flag is set, when there is
lowest nibble, i.e, bit three during
addition, or borrow for the lowest a carry out of MSB in case of
nibble, i.e, bit three, during addition or a borrow in case
subtraction. of subtraction.

Sign Flag Zero Flag Parity Flag

This flag is set, when the This flag is set, if the result of This flag is set to 1, if the lower
result of any computation the computation or comparison byte of the result contains even
is negative performed by an instruction is number of 1’s ; for odd number
zero of 1’s set to zero.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

OF DF IF TF SF ZF AF PF CF

Tarp Flag
Over flow Flag If this flag is set, the processor
This flag is set, if an overflow occurs, i.e, if the result of a signed enters the single step execution
operation is large enough to accommodate in a destination
mode by generating internal
register. The result is of more than 7-bits in size in case of 8-bit
signed operation and more than 15-bits in size in case of 16-bit interrupts after the execution of
sign operations, then the overflow will be set. each instruction

Direction Flag Interrupt Flag

This is used by string manipulation instructions. If this flag bit
is ‘0’, the string is processed beginning from the lowest Causes the 8086 to recognize
address to the highest address, i.e., auto incrementing mode. external mask interrupts; clearing IF
Otherwise, the string is processed from the highest address disables these interrupts.
towards the lowest address, i.e., auto incrementing mode. 36
8086 Microprocessor
Architecture

8086 registers
categorized 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

into 4 groups OF DF IF TF SF ZF AF PF CF

Sl.No. Type Register width Name of register

1 General purpose register 16 bit AX, BX, CX, DX

8 bit AL, AH, BL, BH, CL, CH, DL, DH

2 Pointer register 16 bit SP, BP

3 Index register 16 bit SI, DI

4 Instruction Pointer 16 bit IP

5 Segment register 16 bit CS, DS, SS, ES

6 Flag (PSW) 16 bit Flag register

37
8086 Microprocessor
Architecture Registers and Special Functions

Register Name of the Register Special Function

AX 16-bit Accumulator Stores the 16-bit results of arithmetic and logic operations

AL 8-bit Accumulator Stores the 8-bit results of arithmetic and logic operations

BX Base register Used to hold base value in base addressing mode to access
memory data

CX Count Register Used to hold the count value in SHIFT, ROTATE and LOOP
instructions

DX Data Register Used to hold data for multiplication and division operations

SP Stack Pointer Used to hold the offset address of top stack memory

BP Base Pointer Used to hold the base value in base addressing using SS
register to access data from stack memory

SI Source Index Used to hold index value of source operand (data) for string
instructions

DI Data Index Used to hold the index value of destination operand (data)
for string operations 38
 8086 Microprocessor
Addressing Modes
• Every instruction of a program has to operate on a data.
• The different ways in which a source operand is denoted
in an instruction are known as addressing modes.

1. Register Addressing
Group I : Addressing modes for register and
2. Immediate Addressing immediate data

3. Direct Addressing

4. Register Indirect Addressing

5. Based Addressing
Group II : Addressing modes for memory data
6. Indexed Addressing

7. Based Index Addressing

8. String Addressing

9. Direct I/O port Addressing

Group III : Addressing modes for I/O ports
10. Indirect I/O port Addressing

11. Relative Addressing Group IV : Relative Addressing mode

12. Implied Addressing Group V : Implied Addressing mode

39
 8086 Microprocessor Group I : Addressing modes for register and

1. Register Addressing
Addressing Modes
The instruction will specify the name of the
immediate data

register which holds the data to be operated by

2. Immediate Addressing the instruction.
3. Direct Addressing Example:
4. Register Indirect Addressing
MOV CL, DH
5. Based Addressing
The content of 8-bit register DH is moved to
6. Indexed Addressing another 8-bit register CL

7. Based Index Addressing (CL) ← (DH)

8. String Addressing

9. Direct I/O port Addressing

10. Indirect I/O port Addressing

11. Relative Addressing

12. Implied Addressing

40
 8086 Microprocessor Group I : Addressing modes for register and
immediate data

1. Register Addressing
Addressing Modes
In immediate addressing mode, an 8-bit or 16-bit
2. Immediate Addressing data is specified as part of the instruction
3. Direct Addressing
Example:
4. Register Indirect Addressing
MOV DL, 08H
5. Based Addressing
The 8-bit data (08H) given in the instruction is
6. Indexed Addressing moved to DL

7. Based Index Addressing (DL) ← 08H

8. String Addressing
MOV AX, 0A9FH
9. Direct I/O port Addressing
The 16-bit data (0A9FH) given in the instruction is
10. Indirect I/O port Addressing
moved to AX register
11. Relative Addressing
(AX) ← 0A9FH
12. Implied Addressing

41
8086 Microprocessor

Addressing Modes : Memory Access

Offset Value (16 bits)

Segment Register (16 bits) 0000

Adder

Physical Address (20 Bits)

42
8086 Microprocessor

Addressing Modes : Memory Access

• 20 Address lines ⇒ 8086 can address up to 220 = 1M bytes
of memory

• However, the largest register is only 16 bits

• Physical Address will have to be calculated Physical Address :

Actual address of a byte in memory. i.e. the value which goes out
onto the address bus.

• Memory Address represented in the form – Seg : Offset (Eg

- 89AB:F012)

• Each time the processor wants to access memory, it takes the

contents of a segment register, shifts it one hexadecimal place to
the left (same as multiplying by 1610), then add the required
offset to form the 20- bit address
16 bytes of contiguous
memory

89AB : F012 → 89AB → 89AB0 (Paragraph to byte → 89AB x 10 = 89AB0)

F012 → 0F012 (Offset is already in byte unit)
+ -------
98AC2 (The absolute address)
43
8086 Microprocessor

Addressing Modes : Memory Access

• To access memory we use these four registers: BX, SI, DI, BP

• Combining these registers inside [ ] symbols, we can get different

memory locations (Effective Address, EA)

• Supported combinations:

[BX + SI] [BX + SI + d8]

[SI]
[BX + DI] [BX + DI + d8]
[DI]
[BP + SI] [BP + SI + d8]
d16 (variable offset only)
[BP + DI] [BP + DI + d8]
[BX]

[SI + d8] [BX + SI + d16] [SI + d16]

[DI + d8] [BX + DI + d16] [DI + d16]
[BP + d8] [BP + SI + d16] [BP + d16]
[BX + d8] [BP + DI + d16] [BX + d16]

BX SI
+ disp
BP DI 44
 8086 Microprocessor Group II : Addressing modes for memory data

1. Register Addressing Addressing Modes

2. Immediate Addressing
Here, the effective address of the memory
3. Direct Addressing
location at which the data operand is stored is
4. Register Indirect Addressing given in the instruction.

5. Based Addressing The effective address is just a 16-bit number

written directly in the instruction.
6. Indexed Addressing
Example:
7. Based Index Addressing
MOV BX, [1354H]
8. String Addressing MOV BL, [0400H]
9. Direct I/O port Addressing
The square brackets around the 1354H denotes
the contents of the memory location. When
10. Indirect I/O port Addressing
executed, this instruction will copy the contents of
11. Relative Addressing the memory location into BX register.

12. Implied Addressing This addressing mode is called direct because the
displacement of the operand from the segment
base is specified directly in the instruction.

45
 8086 Microprocessor Group II : Addressing modes for memory

Addressing Modes data

1. Register Addressing In Register indirect addressing, name of the

register which holds the effective address (EA)
2. Immediate Addressing will be specified in the instruction.

3. Direct Addressing Registers used to hold EA are any of the following

registers:
4. Register Indirect Addressing
BX, BP, DI and SI.
5. Based Addressing
Content of the DS register is used for base
6. Indexed Addressing
address calculation.
7. Based Index Addressing
Example:
8. String Addressing Note : Register/ memory
MOV CX, [BX] enclosed in brackets refer to
9. Direct I/O port Addressing content of register/ memory
Operations:
10. Indirect I/O port Addressing
EA = (BX)
11. Relative Addressing BA = (DS) x 1610
MA = BA + EA
12. Implied Addressing
(CX) ← (MA) or,

(CL) ← (MA)
(CH) ← (MA +1)
46
 8086 Microprocessor Group II : Addressing modes for memory

Addressing Modes
In Based Addressing, BX or BP is used to hold the
data

1. Register Addressing
base value for effective address and a signed 8-bit
2. Immediate Addressing or unsigned 16-bit displacement will be specified
in the instruction.
3. Direct Addressing
In case of 8-bit displacement, it is sign extended
4. Register Indirect Addressing to 16-bit before adding to the base value.

5. Based Addressing When BX holds the base value of EA, 20-bit

physical address is calculated from BX and DS.
6. Indexed Addressing
When BP holds the base value of EA, BP and SS is
7. Based Index Addressing
used.
8. String Addressing
Example:
9. Direct I/O port Addressing
MOV AX, [BX + 08H]
10. Indirect I/O port Addressing
Operations:
11. Relative Addressing
0008H ← 08H (Sign extended)
12. Implied Addressing EA = (BX) + 0008H
BA = (DS) x 1610
MA = BA + EA

(AX) ← (MA) or,

(AL) ← (MA)
47
(AH) ← (MA + 1)
 8086 Microprocessor Group II : Addressing modes for memory

Addressing Modes data

1. Register Addressing SI or DI register is used to hold an index value for

memory data and a signed 8-bit or unsigned
2. Immediate Addressing 16-bit displacement will be specified in the
instruction.
3. Direct Addressing
Displacement is added to the index value in SI or
4. Register Indirect Addressing DI register to obtain the EA.

5. Based Addressing In case of 8-bit displacement, it is sign extended

to 16-bit before adding to the base value.
6. Indexed Addressing

7. Based Index Addressing

Example:
8. String Addressing
MOV CX, [SI + 0A2H]
9. Direct I/O port Addressing
Operations:
10. Indirect I/O port Addressing
FFA2H ← A2H (Sign extended)
11. Relative Addressing
EA = (SI) + FFA2H
12. Implied Addressing BA = (DS) x 1610
MA = BA + EA

(CX) ← (MA) or,

(CL) ← (MA)
(CH) ← (MA + 1)
48
 8086 Microprocessor Group II : Addressing modes for memory

Addressing Modes data

1. Register Addressing In Based Index Addressing, the effective address

is computed from the sum of a base register (BX
2. Immediate Addressing or BP), an index register (SI or DI) and a
displacement.
3. Direct Addressing
Example:
4. Register Indirect Addressing
MOV DX, [BX + SI + 0AH]
5. Based Addressing
Operations:
6. Indexed Addressing
000AH ← 0AH (Sign extended)
7. Based Index Addressing

8. String Addressing EA = (BX) + (SI) + 000AH

BA = (DS) x 1610
9. Direct I/O port Addressing MA = BA + EA

10. Indirect I/O port Addressing (DX) ← (MA) or,

11. Relative Addressing (DL) ← (MA)

(DH) ← (MA + 1)
12. Implied Addressing

49
 8086 Microprocessor Group II : Addressing modes for memory

Addressing Modes Employed in string operations to operate on string

data

1. Register Addressing
data.
2. Immediate Addressing
The effective address (EA) of source data is stored
3. Direct Addressing in SI register and the EA of destination is stored in
DI register.
4. Register Indirect Addressing
Segment register for calculating base address of
5. Based Addressing source data is DS and that of the destination data
is ES
6. Indexed Addressing

7. Based Index Addressing

Example: MOVS BYTE
8. String Addressing
Operations:
9. Direct I/O port Addressing
Calculation of source memory location:
10. Indirect I/O port Addressing EA = (SI) BA = (DS) x 1610 MA = BA + EA

11. Relative Addressing Calculation of destination memory location:

EAE = (DI) BAE = (ES) x 1610 MAE = BAE + EAE
12. Implied Addressing

Note : Effective address of the (MAE) ← (MA)

Extra segment register
If DF = 1, then (SI) ← (SI) – 1 and (DI) = (DI) - 1
If DF = 0, then (SI) ← (SI) +1 and (DI) = (DI)50+ 1
 8086 Microprocessor Group III : Addressing modes for I/O

Addressing Modes
These addressing modes are used to access data
ports

1. Register Addressing
from standard I/O mapped devices or ports.
2. Immediate Addressing
In direct port addressing mode, an 8-bit port
3. Direct Addressing address is directly specified in the instruction.

4. Register Indirect Addressing Example: IN AL, [09H]

5. Based Addressing Operations: PORTaddr = 09H

(AL) ← (PORT)
6. Indexed Addressing
Content of port with address 09H is
7. Based Index Addressing
moved to AL register
8. String Addressing
In indirect port addressing mode, the instruction
9. Direct I/O port Addressing will specify the name of the register which holds
the port address. In 8086, the 16-bit port address
10. Indirect I/O port Addressing is stored in the DX register.

11. Relative Addressing Example: OUT [DX], AX

12. Implied Addressing Operations: PORTaddr = (DX)

(PORT) ← (AX)

Content of AX is moved to port

whose address is specified by DX
register. 51
 8086 Microprocessor Group IV : Relative Addressing
mode

1. Register Addressing Addressing Modes

2. Immediate Addressing

3. Direct Addressing In this addressing mode, the effective address of

a program instruction is specified relative to
4. Register Indirect Addressing Instruction Pointer (IP) by an 8-bit signed
displacement.
5. Based Addressing
Example: JZ 0AH
6. Indexed Addressing
Operations:
7. Based Index Addressing

8. String Addressing 000AH ← 0AH (sign extend)

9. Direct I/O port Addressing If ZF = 1, then

10. Indirect I/O port Addressing EA = (IP) + 000AH

BA = (CS) x 1610
11. Relative Addressing MA = BA + EA

12. Implied Addressing If ZF = 1, then the program control jumps to

new address calculated above.

If ZF = 0, then next instruction of the

program is executed.
52
 8086 Microprocessor Group IV : Implied Addressing
mode

1. Register Addressing
Addressing Modes
2. Immediate Addressing

3. Direct Addressing

4. Register Indirect Addressing

5. Based Addressing

6. Indexed Addressing
Instructions using this mode have no operands.
The instruction itself will specify the data to be
7. Based Index Addressing
operated by the instruction.
8. String Addressing
Example: CLC
9. Direct I/O port Addressing
This clears the carry flag to zero.
10. Indirect I/O port Addressing

11. Relative Addressing

12. Implied Addressing

53
8086 Microprocessor

Instruction Set
8086 supports 6 types of instructions.

1. Data Transfer Instructions

2. Arithmetic Instructions

3. Logical Instructions

4. String manipulation Instructions

5. Process Control Instructions

6. Control Transfer Instructions

https://www.tutorialspoint.com/assembly_programming/assembly_logical_instructions.ht
m

54
8086 Microprocessor

Instruction Set
1. Data Transfer Instructions

Instructions that are used to transfer data/ address in to registers, memory

locations and I/O ports.

Generally involve two operands: Source operand and Destination operand of the
same size.

Source: Register or a memory location or an immediate data

Destination : Register or a memory location.

The size should be a either a byte or a word.

A 8-bit data can only be moved to 8-bit register/ memory and a 16-bit data can be
moved to 16-bit register/ memory.

55
8086 Microprocessor
Instruction Set
1. Data Transfer Instructions

Mnemonics: MOV, XCHG, PUSH, POP, IN, OUT …

MOV reg2/ mem, reg1/ mem

MOV reg2, reg1 (reg2) ← (reg1)

MOV mem, reg1 (mem) ← (reg1)
MOV reg2, mem (reg2) ← (mem)

MOV reg/ mem, data

MOV reg, data (reg) ← data

MOV mem, data (mem) ← data

XCHG reg2/ mem, reg1

XCHG reg2, reg1 (reg2) ↔ (reg1)

XCHG mem, reg1 (mem) ↔ (reg1)

56
8086 Microprocessor
Instruction Set
1. Data Transfer Instructions

Mnemonics: MOV, XCHG, PUSH, POP, IN, OUT …

PUSH reg16/ mem

PUSH reg16 (SP) ← (SP) – 2

MA S = (SS) x 16 10 + SP
(MA S ; MA S + 1) ← (reg16)

PUSH mem (SP) ← (SP) – 2

MA S = (SS) x 16 10 + SP
(MA S ; MA S + 1) ← (mem)

POP reg16/ mem

POP reg16 MA S = (SS) x 16 10 + SP

(reg16) ← (MA S ; MA S + 1)
(SP) ← (SP) + 2

POP mem MA S = (SS) x 16 10 + SP

(mem) ← (MA S ; MA S + 1)
(SP) ← (SP) + 2
57
8086 Microprocessor
Instruction Set
1. Data Transfer Instructions

Mnemonics: MOV, XCHG, PUSH, POP, IN, OUT …

IN A, [DX] OUT [DX], A

IN AL, [DX] PORT addr = (DX) OUT [DX], AL PORT addr = (DX)
(AL) ← (PORT) (PORT) ← (AL)

IN AX, [DX] PORT addr = (DX) OUT [DX], AX PORT addr = (DX)
(AX) ← (PORT) (PORT) ← (AX)

IN A, addr8 OUT addr8, A

IN AL, addr8 (AL) ← (addr8) OUT addr8, AL (addr8) ← (AL)

IN AX, addr8 (AX) ← (addr8) OUT addr8, AX (addr8) ← (AX)

58
8086 Microprocessor
Instruction Set
2. Arithmetic Instructions
Mnemonics: ADD, ADC, SUB, SBB, INC, DEC, MUL, DIV, CMP…

ADD reg2/ mem, reg1/mem

ADD reg2, reg1 (reg2) ← (reg1) + (reg2)

ADD reg2, mem (reg2) ← (reg2) + (mem)
ADD mem, reg1 (mem) ← (mem)+(reg1)

ADD reg/mem, data

ADD reg, data (reg) ← (reg)+ data

ADD mem, data (mem) ← (mem)+data

ADD A, data

ADD AL, data8 (AL) ← (AL) + data8

ADD AX, data16 (AX) ← (AX) +data16

59
8086 Microprocessor
Instruction Set
2. Arithmetic Instructions
Mnemonics: ADD, ADC, SUB, SBB, INC, DEC, MUL, DIV, CMP…

ADC reg2/ mem, reg1/mem

ADC reg2, reg1 (reg2) ← (reg1) + (reg2)+CF

ADC reg2, mem (reg2) ← (reg2) + (mem)+CF
ADC mem, reg1 (mem) ← (mem)+(reg1)+CF

ADC reg/mem, data

ADC reg, data (reg) ← (reg)+ data+CF

ADC mem, data (mem) ← (mem)+data+CF

ADD A, data

ADD AL, data8 (AL) ← (AL) + data8+CF

ADD AX, data16 (AX) ← (AX) +data16+CF

60
8086 Microprocessor
Instruction Set
2. Arithmetic Instructions
Mnemonics: ADD, ADC, SUB, SBB, INC, DEC, MUL, DIV, CMP…

SUB reg2/ mem, reg1/mem

SUB reg2, reg1 (reg2) ← (reg1) - (reg2)

SUB reg2, mem (reg2) ← (reg2) - (mem)
SUB mem, reg1 (mem) ← (mem) - (reg1)

SUB reg/mem, data

SUB reg, data (reg) ← (reg) - data

SUB mem, data (mem) ← (mem) - data

SUB A, data

SUB AL, data8 (AL) ← (AL) - data8

SUB AX, data16 (AX) ← (AX) - data16

61
8086 Microprocessor
Instruction Set
2. Arithmetic Instructions
Mnemonics: ADD, ADC, SUB, SBB, INC, DEC, MUL, DIV, CMP…

SBB reg2/ mem, reg1/mem

SBB reg2, reg1 (reg2) ← (reg1) - (reg2) - CF

SBB reg2, mem (reg2) ← (reg2) - (mem)- CF
SBB mem, reg1 (mem) ← (mem) - (reg1) –CF

SBB reg/mem, data

SBB reg, data (reg) ← (reg) – data - CF

SBB mem, data (mem) ← (mem) - data - CF

SBB A, data

SBB AL, data8 (AL) ← (AL) - data8 - CF

SBB AX, data16 (AX) ← (AX) - data16 - CF

62
8086 Microprocessor
Instruction Set
2. Arithmetic Instructions
Mnemonics: ADD, ADC, SUB, SBB, INC, DEC, MUL, DIV, CMP…

INC reg/ mem

INC reg8 (reg8) ← (reg8) + 1

INC reg16 (reg16) ← (reg16) + 1

INC mem (mem) ← (mem) + 1

DEC reg/ mem

DEC reg8 (reg8) ← (reg8) - 1

DEC reg16 (reg16) ← (reg16) - 1

DEC mem (mem) ← (mem) - 1

63
8086 Microprocessor
Instruction Set
2. Arithmetic Instructions
Mnemonics: ADD, ADC, SUB, SBB, INC, DEC, MUL, DIV, CMP…

MUL reg/ mem

MUL reg For byte : (AX) ← (AL) x (reg8)

For word : (DX)(AX) ← (AX) x (reg16)

MUL mem For byte : (AX) ← (AL) x (mem8)

For word : (DX)(AX) ← (AX) x (mem16)

IMUL reg/ mem

IMUL reg For byte : (AX) ← (AL) x (reg8)

For word : (DX)(AX) ← (AX) x (reg16)

IMUL mem For byte : (AX) ← (AX) x (mem8)

For word : (DX)(AX) ← (AX) x (mem16)

64
8086 Microprocessor

Instruction Set
2. Arithmetic Instructions
Mnemonics: ADD, ADC, SUB, SBB, INC, DEC, MUL, DIV, CMP…

DIV reg/ mem

DIV reg For 16-bit :- 8-bit :

(AL) ← (AX) :- (reg8) Quotient
(AH) ← (AX) MOD(reg8) Remainder

For 32-bit :- 16-bit :

(AX) ← (DX)(AX) :- (reg16) Quotient
(DX) ← (DX)(AX) MOD(reg16) Remainder

DIV mem For 16-bit :- 8-bit :

(AL) ← (AX) :- (mem8) Quotient
(AH) ← (AX) MOD(mem8) Remainder

For 32-bit :- 16-bit :

(AX) ← (DX)(AX) :- (mem16) Quotient
(DX) ← (DX)(AX) MOD(mem16) Remainder

65
8086 Microprocessor
Instruction Set
2. Arithmetic Instructions
Mnemonics: ADD, ADC, SUB, SBB, INC, DEC, MUL, DIV, CMP…

IDIV reg/ mem

IDIV reg For 16-bit :- 8-bit :

(AL) ← (AX) :- (reg8) Quotient
(AH) ← (AX) MOD(reg8) Remainder

For 32-bit :- 16-bit :

(AX) ← (DX)(AX) :- (reg16) Quotient
(DX) ← (DX)(AX) MOD(reg16) Remainder

IDIV mem For 16-bit :- 8-bit :

(AL) ← (AX) :- (mem8) Quotient
(AH) ← (AX) MOD(mem8) Remainder

For 32-bit :- 16-bit :

(AX) ← (DX)(AX) :- (mem16) Quotient
(DX) ← (DX)(AX) MOD(mem16) Remainder

66
8086 Microprocessor
Instruction Set
2. Arithmetic Instructions
Mnemonics: ADD, ADC, SUB, SBB, INC, DEC, MUL, DIV, CMP…

CMP reg2/mem, reg1/ mem

CMP reg2, reg1 Modify flags ← (reg2) – (reg1)

If (reg2) > (reg1) then CF=0, ZF=0, SF=0

If (reg2) < (reg1) then CF=1, ZF=0, SF=1
If (reg2) = (reg1) then CF=0, ZF=1, SF=0

CMP reg2, mem Modify flags ← (reg2) – (mem)

If (reg2) > (mem) then CF=0, ZF=0, SF=0

If (reg2) < (mem) then CF=1, ZF=0, SF=1
If (reg2) = (mem) then CF=0, ZF=1, SF=0

CMP mem, reg1 Modify flags ← (mem) – (reg1)

If (mem) > (reg1) then CF=0, ZF=0, SF=0

If (mem) < (reg1) then CF=1, ZF=0, SF=1
If (mem) = (reg1) then CF=0, ZF=1, SF=0

67
8086 Microprocessor

Instruction Set
2. Arithmetic Instructions
Mnemonics: ADD, ADC, SUB, SBB, INC, DEC, MUL, DIV, CMP…

CMP reg/mem, data

CMP reg, data Modify flags ← (reg) – (data)

If (reg) > data then CF=0, ZF=0, SF=0

If (reg) < data then CF=1, ZF=0, SF=1
If (reg) = data then CF=0, ZF=1, SF=0

CMP mem, data Modify flags ← (mem) – (mem)

If (mem) > data then CF=0, ZF=0, SF=0

If (mem) < data then CF=1, ZF=0, SF=1
If (mem) = data then CF=0, ZF=1, SF=0

68
8086 Microprocessor
Instruction Set
2. Arithmetic Instructions
Mnemonics: ADD, ADC, SUB, SBB, INC, DEC, MUL, DIV, CMP…

CMP A, data

CMP AL, data8 Modify flags ← (AL) – data8

If (AL) > data8 then CF=0, ZF=0, SF=0

If (AL) < data8 then CF=1, ZF=0, SF=1
If (AL) = data8 then CF=0, ZF=1, SF=0

CMP AX, data16 Modify flags ← (AX) – data16

If (AX) > data16 then CF=0, ZF=0, SF=0

If (mem) < data16 then CF=1, ZF=0, SF=1
If (mem) = data16 then CF=0, ZF=1, SF=0

69
8086 Microprocessor

Instruction Set
3. Logical Instructions
Mnemonics: AND, OR, XOR, TEST, SHR, SHL, RCR, RCL … ROR, ROL

70
8086 Microprocessor

Instruction Set
3. Logical Instructions
Mnemonics: AND, OR, XOR, TEST, SHR, SHL, RCR, RCL … ROR, ROL

71
8086 Microprocessor
Instruction Set
3. Logical Instructions
Mnemonics: AND, OR, XOR, TEST, SHR, SHL, RCR, RCL … ROR, ROL

72
8086 Microprocessor
Instruction Set
3. Logical Instructions
Mnemonics: AND, OR, XOR, TEST, SHR, SHL, RCR, RCL … ROR, ROL
The TEST instruction
works same as the AND
operation, but unlike
AND instruction, it does
not change the first
operand. So, if we need
to check whether a
number in a register is
even or odd, we can also
do this using the TEST
instruction without
changing the original
number.

73
8086 Microprocessor

Instruction Set
3. Logical Instructions
Mnemonics: AND, OR, XOR, TEST, SHR, SHL, RCR, RCL … ROR, ROL

74
8086 Microprocessor
Instruction Set
3. Logical Instructions
Mnemonics: AND, OR, XOR, TEST, SHR, SHL, RCR, RCL … ROR, ROL

75
8086 Microprocessor
Instruction Set
3. Logical Instructions
Mnemonics: AND, OR, XOR, TEST, SHR, SHL, RCR, RCL … ROR, ROL

76
8086 Microprocessor
Instruction Set
3. Logical Instructions
Mnemonics: AND, OR, XOR, TEST, SHR, SHL, RCR, RCL … ROR, ROL

77
8086 Microprocessor
Instruction Set
4. String Manipulation Instructions

❑ String : Sequence of bytes or words

❑ 8086 instruction set includes instruction for string movement, comparison, scan, load and store.

❑ REP instruction prefix : used to repeat execution of string instructions

❑ String instructions end with S or SB or SW. S represents string, SB string byte and SW string word.

❑ Offset or effective address of the source operand is stored in SI register and that of the destination
operand is stored in DI register.

❑ Depending on the status of DF, SI and DI registers are automatically updated.

❑ DF = 0 ⇒ SI and DI are incremented by 1 for byte and 2 for word.

❑ DF = 1 ⇒ SI and DI are decremented by 1 for byte and 2 for word.

78
8086 Microprocessor
Instruction Set
4. String Manipulation Instructions
Mnemonics: REP, MOVS, CMPS, SCAS, LODS, STOS

REP Result should be zero for condition true

REPZ/ REPE While CX ≠ 0 and ZF = 1, repeat execution of string instruction

and
(Repeat CMPS or SCAS until ZF = 0) (CX) ← (CX) – 1

Result should not be zero for condition true

REPNZ/ REPNE
While CX ≠ 0 and ZF = 0, repeat execution of string instruction
(Repeat CMPS or SCAS until ZF = 1) and
(CX) ← (CX) - 1

Ex: repz movsb

Note: Always ‘REPZ’ instruction can be used in association with the string related
operations.
79
8086 Microprocessor

Instruction Set
4. String Manipulation Instructions
Mnemonics: REP, MOVS, CMPS, SCAS, LODS, STOS

MOVS

MOVSB MA = (DS) x 16 10 + (SI)

MAE = (ES) x 16 10 + (DI)

(MA E) ← (MA)

If DF = 0, then (DI) ← (DI) + 1; (SI) ← (SI) + 1

If DF = 1, then (DI) ← (DI) - 1; (SI) ← (SI) - 1

MOVSW MA = (DS) x 16 10 + (SI)

MAE = (ES) x 16 10 + (DI)

(MA E ; MA E + 1) ← (MA; MA + 1)

If DF = 0, then (DI) ← (DI) + 2; (SI) ← (SI) + 2

If DF = 1, then (DI) ← (DI) - 2; (SI) ← (SI) - 2

80
8086 Microprocessor

Instruction Set
4. String Manipulation Instructions
Mnemonics: REP, MOVS, CMPS, SCAS, LODS, STOS

Compare two string byte or string word

CMPS

CMPSB MA = (DS) x 16 10 + (SI)

MAE = (ES) x 16 10 + (DI)

Modify flags ← (MA) - (MA E)

If (MA) > (MA E), then CF = 0; ZF = 0; SF = 0

If (MA) < (MA E), then CF = 1; ZF = 0; SF = 1
CMPSW If (MA) = (MA E), then CF = 0; ZF = 1; SF = 0

For byte operation

If DF = 0, then (DI) ← (DI) + 1; (SI) ← (SI) + 1
If DF = 1, then (DI) ← (DI) - 1; (SI) ← (SI) - 1

For word operation

If DF = 0, then (DI) ← (DI) + 2; (SI) ← (SI) + 2
If DF = 1, then (DI) ← (DI) - 2; (SI) ← (SI) - 2

81
8086 Microprocessor

Instruction Set
4. String Manipulation Instructions
Mnemonics: REP, MOVS, CMPS, SCAS, LODS, STOS
Scan (compare) a string byte or word with accumulator
SCAS

SCASB MAE = (ES) x 16 10 + (DI)

Modify flags ← (AL) - (MA E)

If (AL) > (MA E), then CF = 0; ZF = 0; SF = 0

If (AL) < (MA E), then CF = 1; ZF = 0; SF = 1
If (AL) = (MA E), then CF = 0; ZF = 1; SF = 0

If DF = 0, then (DI) ← (DI) + 1

If DF = 1, then (DI) ← (DI) – 1

SCASW MAE = (ES) x 16 10 + (DI)

Modify flags ← (AL) - (MA E)

If (AX) > (MA E ; MA E + 1), then CF = 0; ZF = 0; SF = 0

If (AX) < (MA E ; MA E + 1), then CF = 1; ZF = 0; SF = 1
If (AX) = (MA E ; MA E + 1), then CF = 0; ZF = 1; SF = 0

If DF = 0, then (DI) ← (DI) + 2

82
If DF = 1, then (DI) ← (DI) – 2
8086 Microprocessor
Instruction Set
4. String Manipulation Instructions
Mnemonics: REP, MOVS, CMPS, SCAS, LODS, STOS

Load string byte in to AL or string word in to AX

LODS

LODSB MA = (DS) x 16 10 + (SI)

(AL) ← (MA)

If DF = 0, then (SI) ← (SI) + 1

If DF = 1, then (SI) ← (SI) – 1

LODSW MA = (DS) x 16 10 + (SI)

(AX) ← (MA ; MA + 1)

If DF = 0, then (SI) ← (SI) + 2

If DF = 1, then (SI) ← (SI) – 2

83
8086 Microprocessor

Instruction Set
4. String Manipulation Instructions
Mnemonics: REP, MOVS, CMPS, SCAS, LODS, STOS

Store byte from AL or word from AX in to string

STOS

STOSB MAE = (ES) x 16 10 + (DI)

(MA E) ← (AL)

If DF = 0, then (DI) ← (DI) + 1

If DF = 1, then (DI) ← (DI) – 1

STOSW MAE = (ES) x 16 10 + (DI)

(MA E ; MA E + 1 ) ← (AX)

If DF = 0, then (DI) ← (DI) + 2

If DF = 1, then (DI) ← (DI) – 2

84
8086 Microprocessor

Instruction Set
5. Processor Control Instructions
Mnemonics Explanation
STC Set CF ← 1

CLC Clear CF ← 0

CMC Complement carry CF ← CF /

STD Set direction flag DF ← 1

CLD Clear direction flag DF ← 0

STI Set interrupt enable flag IF ← 1

CLI Clear interrupt enable flag IF ← 0

NOP No operation

HLT Halt after interrupt is set

WAIT Wait for TEST pin active

ESC opcode mem/ reg Used to pass instruction to a coprocessor which shares the
address and data bus with the 8086
LOCK Lock bus during next instruction
85
8086 Microprocessor
Instruction Set
6. Control Transfer Instructions

• Transfer the control to a specific destination or target instruction

• Do not affect flags

❑ 8086 Unconditional transfers

Mnemonics Explanation
CALL reg/ mem/ disp16 Call subroutine

RET Return from subroutine

JMP reg/ mem/ disp8/ disp16 Unconditional jump

86
8086 Microprocessor

Instruction Set
6. Control Transfer Instructions

❑ 8086 signed conditional branch ❑ 8086 unsigned conditional branch

instructions instructions

• Checks flags

• If conditions are true, the program control is transferred to the new

memory location in the same segment by modifying the content of IP

87
 8086 Microprocessor

Instruction Set
6. Control Transfer Instructions

❑ 8086 signed conditional branch ❑ 8086 unsigned conditional branch

instructions instructions

Name Alternate name Name Alternate name

JE disp8 JZ disp8 JE disp8 JZ disp8
Jump if equal Jump if result is 0 Jump if equal Jump if result is 0

JNE disp8 JNZ disp8 JNE disp8 JNZ disp8

Jump if not equal Jump if not zero Jump if not equal Jump if not zero
JG disp8 JNLE disp8 JA disp8 JNBE disp8
Jump if greater Jump if not less or equal Jump if above Jump if not below or
equal
JGE disp8 JNL disp8
Jump if greater than or Jump if not less JAE disp8 JNB disp8
equal Jump if above or equal Jump if not below
JL disp8 JNGE disp8 JB disp8 JNAE disp8
Jump if less than Jump if not greater than Jump if below Jump if not above or
or equal equal
JLE disp8 JNG disp8
Jump if less than or Jump if not greater JBE disp8 JNA disp8
equal Jump if below or equal Jump if not above

Note: Before these instructions comparison instruction is to be used for comparing two operands.88
8086 Microprocessor
Instruction Set
6. Control Transfer Instructions

❑ 8086 conditional branch instructions affecting individual flags

Mnemonics Explanation

JC disp8 Jump if CF = 1

JNC disp8 Jump if CF = 0

JP disp8 Jump if PF = 1

JNP disp8 Jump if PF = 0

JO disp8 Jump if OF = 1

JNO disp8 Jump if OF = 0

JS disp8 Jump if SF = 1

JNS disp8 Jump if SF = 0

JZ disp8 Jump if result is zero, i.e, ZF = 1

JNZ disp8 Jump if result is not zero, i.e, ZF = 0

89
Iteration Control Instructions
These instructions are used to execute the given instructions for number of times.
Following is the list of instructions under this group −

LOOP − Used to loop a group of instructions until the condition satisfies, i.e., CX = 0

LOOPE/LOOPZ − Used to loop a group of instructions till it satisfies ZF = 1 & CX = 0

LOOPNE/LOOPNZ − Used to loop a group of instructions till it satisfies ZF = 0 & CX = 0

JCXZ − Used to jump to the provided address if CX = 0

Mov cx, 06h

label: add al, bl
Loop label
8086 Microprocessor

Assemble Directives
• Instructions to the Assembler regarding the program being executed.

• Control the generation of machine codes and organization of the program; but no
machine codes are generated for assembler directives.

• Also called ‘pseudo instructions’

• Used to :
› specify the start and end of a program
› attach value to variables
› allocate storage locations to input/ output data
› define start and end of segments, procedures, macros etc..

91
8086 Microprocessor

DB
Assemble Directives
• Define Byte

DW • Define a byte type (8-bit) variable

SEGMENT • Reserves specific amount of memory locations to each

ENDS variable

ASSUME • Range : 00H – FFH for unsigned value; 00H – 7FH for
positive value and 80H – FFH for negative value
ORG
END • General form : variable DB value/ values
EVEN
EQU

PROC
FAR Example:
NEAR LIST DB 7FH, 42H, 35H
ENDP
Three consecutive memory locations are reserved for the variable LIST
SHORT and each data specified in the instruction are stored as initial value in
the reserved memory location
MACRO
ENDM 92
8086 Microprocessor

DB
Assemble Directives
• Define Word

DW • Define a word type (16-bit) variable

SEGMENT • Reserves two consecutive memory locations to each variable

ENDS
• Range : 0000H – FFFFH for unsigned value; 0000H –
ASSUME 7FFFH for positive value and 8000H – FFFFH for negative
value
ORG
END • General form : variable DW value/ values
EVEN
EQU

PROC
FAR Example:
NEAR ALIST DW 6512H, 0F251H, 0CDE2H
ENDP
Six consecutive memory locations are reserved for the variable ALIST
SHORT and each 16-bit data specified in the instruction is stored in two
consecutive memory location.
MACRO
ENDM 93
8086 Microprocessor

DB
Assemble Directives
• SEGMENT : Used to indicate the beginning of a code/ data/
stack segment
DW
• ENDS : Used to indicate the end of a code/ data/ stack
SEGMENT segment
ENDS
• General form:
ASSUME

ORG
END Segnam SEGMENT
EVEN
…
EQU … Program code
… or
PROC … Data Defining Statements
…
FAR …
NEAR
ENDP Segnam ENDS

SHORT

MACRO User defined name of the

segment
ENDM 94
8086 Microprocessor

DB
Assemble Directives
• Informs the assembler the name of the program/ data
segment that should be used for a specific segment.
DW
• General form:
SEGMENT
ENDS
ASSUME segreg : segnam, .. , segreg : segnam
ASSUME

ORG
User defined name of the
END Segment Register
segment
EVEN
EQU

PROC Example:
FAR
NEAR ASSUME CS: ACODE, DS:ADATA Tells the compiler that the instructions of the
ENDP program are stored in the segment ACODE and
data are stored in the segment ADATA

SHORT

MACRO
ENDM 95
8086 Microprocessor
Assemble Directives
• ORG (Origin) is used to assign the starting address (Effective address)
DB
for a program/ data segment

DW • END is used to terminate a program; statements after END will be

ignored
SEGMENT
ENDS • EVEN : Informs the assembler to store program/ data segment
starting from an even address
ASSUME
• EQU (Equate) is used to attach a value to a variable

ORG
Examples:
END
EVEN ORG 1000H Informs the assembler that the statements following
EQU ORG 1000H should be stored in memory starting with
effective address 1000H

PROC
FAR
LOOP EQU 10FEH Value of variable LOOP is 10FEH
NEAR
ENDP
_SDATA SEGMENT In this data segment, effective address of memory
SHORT ORG 1200H location assigned to A will be 1200H and that of B will
A DB 4CH be 1202H and 1203H.
EVEN
MACRO B DW 1052H
ENDM _SDATA ENDS 96
LENGTH: LENGTH is an operator, which tells the assembler to determine the number of
elements in some named data item, such as a string or an array. When the assembler reads
the statement MOV CX, LENGTH STRING1, for example, will determine the number of
elements in STRING1 and load it into CX. If the string was declared as a string of bytes,
LENGTH will produce the number of bytes in the string. If the string was declared as a word
string, LENGTH will produce the number of words in the string.
LENGTH: Byte length of a label: This is used to refer to the length of a data array or a
string. Ex : MOV CX, LENGTH ARRAY
OFFSET: offset of a label: When the assembler comes across the OFFSET operator along
with a label, it first computing the 16-bit offset address of a particular label and replace
the string ‘OFFSET LABEL’ by the computed offset address. Ex : MOV SI, offset list

LEA : Load Effective address : loads the address of variable.

Ex: Test DB 23H, 40H, 44H

LEA AX, Test
8086 Microprocessor

Assemble Directives
• PROC Indicates the beginning of a procedure
DB
• ENDP End of procedure
DW
• FAR Intersegment call
SEGMENT
ENDS • NEAR Intrasegment call

• General form
ASSUME

ORG
procname PROC[NEAR/ FAR]
END
EVEN …
… Program statements of the procedure
EQU
…
Last statement of the procedure
PROC RET
ENDP
FAR procname ENDP
NEAR

SHORT User defined name of the

procedure
MACRO
ENDM 98
8086 Microprocessor

DB
Assemble Directives
Examples:
DW

SEGMENT ADD64 PROC NEAR The subroutine/ procedure named ADD64 is declared
ENDS as NEAR and so the assembler will code the CALL
… and RET instructions involved in this procedure as
… near call and return
ASSUME …

RET
ORG
ADD64 ENDP
END
EVEN
EQU CONVERT PROC FAR The subroutine/ procedure named CONVERT is
declared as FAR and so the assembler will code the
… CALL and RET instructions involved in this
PROC … procedure as far call and return
ENDP …
FAR
RET
NEAR CONVERT ENDP

SHORT

MACRO
ENDM 99
8086 Microprocessor

Assemble Directives
DB • Reserves one memory location for 8-bit signed displacement
in jump instructions
DW
Example:
SEGMENT
ENDS

ASSUME JMP SHORT AHEAD The directive will reserve one memory
location for 8-bit displacement named
ORG AHEAD
END
EVEN
EQU

PROC
ENDP
FAR
NEAR

SHORT

MACRO
ENDM 100
8086 Microprocessor

Assemble Directives
DB • MACRO Indicate the beginning of a macro

DW • ENDM End of a macro

SEGMENT • General form:

ENDS

ASSUME macroname MACRO[Arg1, Arg2 ...]

Program statements
… in the macro
ORG …
END …
EVEN
EQU ENDM

PROC
ENDP
FAR
NEAR User defined name of the macro

SHORT

MACRO
ENDM 101
 Procedures and Macros:
http://www.snjb.org/polytechnic/up-images/downloads/chapter%206-MAPupFile_0
58d4fa990abaa.pdf.
Define procedure : A procedure is group of instructions that usually performs one task. It is a
reusable section of a software program which is stored in memory once but can be used as
often as necessary. A procedure can be of two types. 1) Near Procedure 2) Far Procedure
Near Procedure: A procedure is known as NEAR procedure if is written(defined) in the same
code segment which is calling that procedure. Only Instruction Pointer(IP register) contents
will be changed in NEAR procedure. FAR procedure : A procedure is known as FAR procedure
if it is written (defined) in the different code segment than the calling segment. In this case
both Instruction Pointer (IP) and the Code Segment (CS) register content will be changed.

Directives used for procedure : PROC directive: The PROC directive is used to identify the
start of a procedure. The PROC directive follows a name given to the procedure. After that
the term FAR and NEAR is used to specify the type of the procedure. ENDP Directive: This
directive is used along with the name of the procedure to indicate the end of a procedure to
the assembler. The PROC and ENDP directive are used to bracket a procedure.
CALL instruction and RET instruction :

CALL instruction : The CALL instruction is used to transfer execution to a procedure. It

performs two operation. When it executes, first it stores the address of instruction after the
CALL instruction on the stack. Second it changes the content of IP register in case of Near call
and changes the content of IP register and CS register in case of FAR call.

There are two types of calls. 1)Near Call or Intra segment call. 2) Far call or Inter Segment call
Operation for Near Call : When 8086 executes a near CALL instruction, it decrements the
stack pointer by 2 and copies the IP register contents on to the stack. Then it copies address
of first instruction of called procedure.

Operation for Near Call : When 8086 executes a near CALL instruction, it decrements the
stack pointer by 2 and copies the IP register contents on to the stack. Then it copies address
of first instruction of called procedure.

Operation of FAR CALL: When 8086 executes a far call, it decrements the stack pointer by 2
and copies the contents of CS register to the stack. It the decrements the stack pointer by 2
again and copies the content of IP register to the stack. Finally it loads CS register with base
address of segment having procedure and IP with address of first instruction in procedure.
ASSUME CS:CODE, DS:DATA, SS:STACK_SEG CALL SUBTRACTION
MOV AH, 4CH
DATA SEGMENT INT 21H
NUM1 DB 50H Procedure Example
NUM2 DB 20H ADDITION PROC NEAR
ADD_RES DB ?
program: MOV AL, NUM1
SUB_RES DB ? MOV BL, NUM2
DATA ENDS ADD AL, BL
MOV ADD_RES, AL
STACK_SEG SEGMENT RET
ADDITION ENDP
DW 40 DUP(0) ; stack of 40 words, all initialized to zero
TOS LABEL WORD SUBTRACTION PROC
STACK_SEG ENDS MOV AL, NUM1
MOV BL, NUM2
CODE SEGMENT SUB AL, BL
MOV SUB_RES, AL
START: MOV AX, DATA ; initialize data segment RET
MOV DS, AX SUBTRACTION ENDP
MOV AX, STACK_SEG ; initialize stack segment
MOV SS, AX CODE ENDS
MOV SP, OFFSET TOS ; initialize stack pointer to TOS END START
CALL ADDITION
ASSUME CS:CODE, DS:DATA

DATA SEGMENT
NUM1 DW 1000H
NUM2 DW 2000H
RES DW ?
DATA ENDS MACRO program
CODE SEGMENT Example
ADDITION MACRO NO1, NO2, RESULT
MOV AX, NO1
MOV BX, NO2
ADD AX, BX
MOV RESULT, AX
ENDM

START: MOV AX, DATA ; initialize data segment

MOV DS, AX
ADDITION NUM1, NUM2, RES
MOV AH, 4CH
INT 21H

CODE ENDS
END START
Modular programming:
https://en.wikipedia.org/wiki/Modular_programming.
Modular programming is a software design technique that emphasizes separating the
functionality of a program into independent, interchangeable modules, such that each
contains everything necessary to execute only one aspect of the desired functionality.

A module interface expresses the elements that are provided and required by the module.
The elements defined in the interface are detectable by other modules.
The implementation contains the working code that corresponds to the elements declared in
the interface. Modular programming is closely related to structured
programming and object-oriented programming, all having the same goal of facilitating
construction of large software programs and systems by decomposition into smaller pieces,
and all originating around the 1960s. While the historical usage of these terms has been
inconsistent, "modular programming" now refers to high-level decomposition of the code of
an entire program into pieces: structured programming to the low-level code use of
structured control flow, and object-oriented programming to the data use of objects, a kind
of data structure.

107
Linking and relocation:
In computing, a linker or link editor is a computer utility program that takes one or
more object files generated by a compiler and combines them into a
single executable file, library file, or another 'object' file.

Computer programs typically are composed of several parts or modules; these

parts/modules need not all be contained within a single object file, and in such cases
refer to each other by means of symbols as addresses into other modules, which are
mapped into memory addresses when linked for execution. For most compilers, each
object file is the result of compiling one input source code file.
When a program comprises multiple object files, the linker combines
these files into a unified executable program, resolving the symbols as
it goes along. Linkers can take objects from a collection called
a library or runtime library. Most linkers do not include the whole
library in the output; they include only the files that are referenced by
other object files or libraries. Library linking may thus be an iterative
process, with some modules included requiring additional modules to
be linked, and so on.

Relocation is the process of assigning load addresses for

position-dependent code and data of a program and adjusting the code
and data to reflect the assigned addresses. Prior to the advent of multi
process systems, and still in many embedded systems the addresses for
objects were absolute starting at a known location, often zero. Since
multiprocessing systems dynamically link and switch between
programs it became necessary to be able to relocate objects
using position-independent code.
A linker usually performs relocation in conjunction with symbol
resolution, the process of searching files and libraries to replace
symbolic references or names of libraries with actual usable
addresses in memory before running a program. Relocation is
typically done by the linker at link time, but it can also be done
at load time by a relocating loader, or at run time by the running
program itself. Some architectures avoid relocation entirely by
deferring address assignment to run time; this is known as zero
address arithmetic.

After linking, there has to be re-allocation of the sequences of placing the

codes before actually placement of the codes in the memory. The loader
program performs the task of reallocating the codes after finding the physical
RAM addresses available at a given instant.
 8086 INTERRUPTS
Sources of Interrupts in 8086:

•Three types of interrupts sources are there in 8086:

• 1. An external signal applied to NMI or INTR
input pin (Hardware interrupt)

2. Execution of INTn (n=00H-FFH)

instruction (Software interrupt)
3. Interrupt caused by some error condition
produced in 8086 instruction execution process.

(Divide by zero, overflow errors etc)

 8086 Interrupt Processing Steps
If an interrupt has been requested, the 8086 Microprocessor processes it by
performing the following series of steps:
1. Pushes the content of the flag register onto the stack to preserve the status
of IF and TF flags, by decrementing the stack pointer (SP) by 2

2. Disables the INTR interrupt by clearing IF in the flag register

3. Resets TF in the flag register, to disable the single step or trap interrupt
4. Pushes the content of the code segment (CS) register onto
the stack by decrementing SP by 2
5. Pushes the content of the instruction pointer (IP)onto the stack by
decrementing SP by 2
6. Performs an indirect far jump to the start of the interrupt service routine
(ISR) corresponding to the received interrupt.
 cesso
Executes the Interrupt
r instruction
Jumps to the Interrupt Vector Table

Takes the CS and IP in the Vector Table

Pushes the existing CS and IP on the Stack

Loads the new CS and IP

Jumps to the ISR

Executes ISR

Comes back and continues the Main

Program
Steps involved in processing an interrupt instruction by the
processor
 Processing of an Interrupt by the
8086
Main Push flags Interrupt
Program Service
register Clear IF
Routine (ISR)
and TF Push CS Interrupt
Interrupt and IP Load CS program:
and IP :
Pop IP and CS :
Pop flags :
register :
IRE
T :
 003FF Type FFH Interrupt
H (Available)
Available
003FC
H Interrupts
Type 21H Interrupt
00084 (Available)
Type 20H Interrupt (224)
H
Interrupt Vector

(Available)
Type 1FH Interrupt
00080 (Reserved)
Reserved
H
Table (IVT)

Interrupts
0007C Type 05H Interrupt
H
00014 (27)
(Reserved)
Type 04H Interrupt (Over
H
Flow)03H Interrupt (Break
Type
00010 Point)
Type 02H Interrupt
H
0004F Type 01H Interrupt
(NMI) Dedicated
H
0000C (Trap or Single Interrupts
(05
H step)
CS 0003F
00002
C
Type 00H )
H
00008 Interrupt
IP H
00001
H S
H
00000 (Divide by Zero)
H
I
P
https://www.eeeguide.com/8086-interrupt/
Interrupt Vector Table
 2 bytes 00002H
CS LSB C S 00003H
CS MSB
Type 0 or
INT 00
2 bytes 00000H
IP LSB I P 00001H
IP MSB Interrupt
CS LSB MSB

Given a vector, where is the ISR address stored in memory ?

Offset = Type number X 4

Example:- INT 02H

Offset = 02 x 4 = 08
= 00008H
 256 Interrupts of 8086 are Divided into 3 Groups
1. Type 00 to Type 04 interrupts -
These are used for fixed operations and hence are
called dedicated interrupts

2. Type 05 to Type 31 interrupts

Not used by 8086,reserved for higher processors like
80286 80386 etc.

3. Type 32 to Type 255 interrupts

Available for user, called user defined interrupts. These can
be either H/W interrupts and activated through INTR line
or can be S/W interrupts.
¬
Type – 0 :- Divide by Zero Error Interrupt
Quotient is large, cant be fit in AL/AX or divide by zero
¬
Type –1:- Single step or Trap Interrupt
Used for executing the program in single step mode by
setting trap flag.

¬
Type – 2:- Non-Maskable Interrupt
This interrupt is used for executing ISR of NMI pin
(positive edge signal), NMI can’t be masked by S/W.

¬
Type – 3:- One-byte INT instruction interrupt
Used for providing break points in the program
¬
An example of an interrupt generated
due to overflow error in an 8086 system
 MICROCONTROLLER-8051
Features & Applications
….. Man’s glory lies in his knowledge,
his upright conduct, his praise-worthy character,
his wisdom, and not in his nationality or rank
--Baha’ullah

(From, the book The 8051 Microcontroller and Embedded systems- Mazidi )
 Overview

Introduction
Block Diagram and Pin Description of the
8051
Registers
Memory mapping in 8051
Stack in the 8051
I/O Port Programming
Timers
Interrupts & Applications
 Why do we need to learn
Microcontrollers ?
■ Its not an exaggeration if I say that , today
there is no electronic gadget on the earth
which is designed without a Microcontroller.
Ex: communication devices, digital
entertainment, portable devices etc…

Not believable ??? See the next slide

■ Personal information products: Cell phone, pager,
watch, pocket recorder, calculator
■ Laptop components:mouse, keyboard, modem,
fax card, sound card, battery charger
■ Home appliances:door lock, alarm clock,
thermostat, air conditioner, TV remote, VCR,
small refrigerator, exercise equipment,
washer/dryer, microwave oven
■ Industrial equipment: Temperature/pressure
controllers, Counters, timers, RPM Controllers
■ Toys: video games, cars, dolls, etc.
So, A good designer should always
know what type of controller he/she
is using ,their architecture, advantages ,
disadvantages , ways to reduce
production costs and product reliability
etc….

O.K ????
 Then What is a Microcontroller ?
■ A smaller computer
■ On-chip RAM, ROM, I/O ports...
■ Example ： Motorola’s 6811, Intel’s 8051,
Zilog’s Z8 and PIC 16X
CPU RAM ROM

I/O
Serial A single chip
Timer COM
Port Microcontroller
Port
 How it is different from a
Microprocessor ??
■ General-purpose microprocessor
CPU for Computers
No RAM, ROM, I/O on CPU chip itself
Example ： Intel’s x86, Motorola’s 680x0
Data Bus
CPU
General-
Serial
Purpose RAM ROM I/O Timer COM
Micro- Port
Port
processor
Address Bus
Microprocessor vs. Microcontroller
Microprocessor Microcontroller
■ CPU is stand-alone, RAM, • CPU, RAM, ROM, I/O and
ROM, I/O, timer are separate timer are all on a single chip
■ designer can decide on the • fix amount of on-chip ROM,
amount of ROM, RAM and I/ RAM, I/O ports
O ports.
• Highly bit addressable
■ expansive
• for applications in which cost,
■ versatility
power and space are critical
■ general-purpose
• single-purpose
 EVOLUTION

Flashback !!!!
In 1970 and 1971, about the same time Intel was inventing its
microprocessor, Gary Boone, an engineer at Texas Instruments was working on
a similar idea. This extraordinary breakthrough was given the rather humdrum
name of the TMS1802NC. It is named as microcontroller.

The INTEL bagged the credit of producing the first

Microcontroller 8048 with a CPU and 1K bytes of
EPROM, 64 Bytes of RAM an 8-Bit Timer and 27 I/O
pins in 1976.
 Evolution contd…
■ Then followed the most popular controller 8051
in the year 1980 with 4K bytes of ROM,128
Bytes of RAM , a serial port, two 16-bit Timers ,
and 32 I/O pins.
■ The 8051 family has many additions and
improvements over the years and remains a
most soughtafter tool for todays circuit
designers.
■ The same INTEL introduced a 16 bit controller
8096 in the year 1982
■ Later INTEL introduced 80c196 series of 16-bit
microcontrollers for mainly industrial
applications

■ Microchip, another company has introduced a

microcontroller PIC 16C64 an 8-bit in the year
1985.

■ 32-bit microcontrollers have been developed by IBM

and Motorola-MPC 505 is a 32-bit RISC controller
of Motorola
■ The 403 GA is a 32 -bit RISC embedded controller
of IBM
 ARM Controllers
■ In recent times ARM company (Advanced Risc
machines) has developed and introduced 32 bit
controllers which are highend application
devices,especially communication devices like
mobiles , ipods etc..(Refer www.arm.com)
Types of
Microcontrollers
MCS-51 “Family” of Microcontollers
Feature 8031 8051 8052 8751
ROM NO 4kB 8kB 4kB UV Eprom

RAM (Bytes) 128 128 256 128

TIMERS 2 2 3 2

I/O PINS 32 32 32 32

SERIAL PORTS 1 1 1 1

INTERRUPT 6 6 8 6
SOURCES
EPROM: Erasable programmable read-only memory
 Microcontroller Architectures
Memory
0
Address Bus
Program
CPU Data Bus + Data Von Neumann
n
Architecture
2

Memory
0
Address Bus
Program
CPU
Fetch Bus Harvard
Address Bus 0
Architecture
Data Bus Data
 Important Features of
8051
■ 4K bytes ROM
■ 128 bytes RAM
■ Four 8-bit I/O ports
■ Two 16-bit timers
■ Serial interface
■ 64K external code memory space
■ 64K data memory space
“Original” 8051 Microcontroller
Oscillator 4096 Bytes 128 Bytes Two 16 Bit
and timing Program Memory Data Memory Timer/Event
(ROM) (RAM) Counters

8051 Internal data bus

CPU

64 K Byte Bus Programmable

Programmable I/O
Expansion Serial Port Full
Control Duplex UART
Synchronous Shifter
subsystem interrupts

External interrupts Control Parallel ports Serial

Address Data Bus Serial Input
Output
I/O
pins
 Pin Description of the 8051

■ The 8051 is a 40 pin

device, but out of
these 40 pins, 32 are
used for I/O.

■ 24 of these are dual

purpose, i.e. they can
operate as I/O or a
control line or as part
of address or date
bus.
https://www.tutorialspoint.com/microprocessor/microcontrollers_8051_pin_description.htm
Pin 30 (ALE/PROG): Pin 30 is the Address Latch Enable Pin. Using this Pins,
external address can be separated from data (as they are multiplexed by 8051).

During Flash Programming, this pin acts as program pulse input (PROG).

Pin 31 (EA/VPP): Pin 31 is the External Access Enable Pin i.e. allows external
program Memory. Code from external program memory can be fetched only if this pin
is LOW. Else internal program memory and external program memory is used.

During Flash Programming, this Pin receives 12V Programming Enable Voltage
(VPP).

Flash memory is just like EEPROM: electrically erasable programmable read only
memory.

PSEN : This is an output pin. PSEN stands for “program store enable.” This pin is
used to read external program memory when ‘0’ else external data memory. If we use
an external ROM for storing the program, then logic 0 appears on it, which indicates
Microcontroller to read data from the memory.

https://www.electronicshub.org/8051-microcontroller-memory-organization/
EA :
▪ A (8-bit Accumulator). B (8-bit register for Mul & Div). PSW (8-bit Program
Status Word). SP (8-bit Stack Pointer). PC (16-bit Program Counter). DPTR
(16-bit Data Pointer)
RAM memory space allocation in the 8051

7FH

Scratch pad RAM

30H

2FH
Bit-Addressable RAM

20H
1FH Register Bank 3
18H
17H
Register Bank 2
10H
0FH Register Bank 1
08H
07H
Register Bank 0
00H
 Special Function Registers
▪ Almost all modern variants of 8051 Microcontroller have 256B of RAM. In this 256B, the
first 128B i.e. memory addresses from 00H to 7FH is divided into Working Registers
(organized
almost all modern as variants
RegisterofBanks), Bit – Addressable
8051 Microcontroller have Area
256B ofandRAM.
General
In thisPurpose
256B, theRAM first(also
128B
known as
i.e. memory Scratchpad
addresses from area).
00H Into the
7FHfirst 128B in
is divided of to
RAM (fromRegisters
Working 00H to 7FH), the first
(organized 32B i.e.
as Register
memory
Banks), from addresses
Bit – Addressable Area00H
andtoGeneral
1FH consists
Purpose ofRAM
32 Working Registers
(also known that are organized
as Scratchpad area). as
four
In the firstbanks
128Bwith 8 Registers
of RAM (from 00H in each Bank.
to 7FH), the first 32B i.e. memory from addresses 00H to 1FH
consists of 32 Working Registers that are organized as four banks with 8 Registers in each Bank.

• DATA registers
• CONTROL
registers
• Timers
• Serial ports
• Interrupt system
•Analog to Digital converter
Addresses 80h – FFh
•Digital to Analog converter
etc.. Direct Addressing is used to
access SFRs
List of Registers
(*Denotes the SFRs)
Contd…
PSW REGISTER
 PORTS OF 8051
■ 8051 has 4 Ports. Port 0, Port1, Port2 , Port3
■ Port 0 is a dual purpose port, it is located from
pin 32 to pin 39 (8 pins). To use this port as both
input/output ports each pin must be connected
externally to a 10 k ohm pull-up resistor.This is
because Port 0 is an open drain.
Simple ex: MOV A, #22
BACK MOV P0 ,A
ACALL DELAY
CPL A
SJMP BACK
 Ports….
■ Port 1 is a dedicated I/O port from pin 1 to
pin 8.Upon reset it is configured as outport.
It is generally used for interfacing to
external device thus if you need to connect to
switches or LEDs, you could make use of
these 8 pins,but it doesn’t need any pull-up
resistors as it is having internally
■ Like port 0, port 2 is a dual-purpose port.(Pins 21
through 28) It can be used for general I/O or as
the high byte of the address bus for designs with
external code memory.Like P1 ,Port2 also doesn’t
require any pull-up resistors
 Ports contd…

■ Port 3 is also dual purpose but designers generally

avoid using this port unnecessarily for I/O
because the pins have alternate functions which
are related to special features of the 8051.
Indiscriminate use of these pins may interfere with
the normal operation of the 8051.
■ However, for a programmer, it is the same to
program P0, P1, P2 and P3.
■ All the ports upon RESET are configured as
output. To use any of the ports as an input port,it
must be set(Programmed)
Alternate functions of P3
 I/O Port structure
■ The internal circuitry for the I/O port is shown in
the next slide
■ If you want to read in from a pin, you must first
give a logic ‘1’ to the port latch to turn off the
FET otherwise the data read in will always be logic
‘0’.
■ When you write to the port you are actually
writing to the latch e.g. a logic 0 given to the latch
will be inverted and turn on the FET which cause
the port pin to be connected to Gnd (logic 0).
 Addressing
Addressing
Modes Modes
♦ Eight modes of addressing are available with
the C8051F020
♦ The different addressing modes determine how the
operand byte is selected

Addressing Modes Instruction

Register MOV A, B
Direct MOV 30H,A
Indirect ADD A,@R0
Immediate Constant ADD A,#80H
Relative* SJMP AHEAD
Absolute* AJMP BACK
Long* LJMP FAR_AHEAD
Indexed MOVC A,@A+PC

* Related to program branching

instructions
 Register Addressing
♦ The register addressing instruction involves
information transfer between registers

♦ Example:
MOV R0, A

♦ The instruction transfers the accumulator content into the

R0 register. The register bank (Bank 0, 1, 2 or 3) must be
specified prior to this instruction.
 Direct Addressing
♦ This mode allows you to specify the operand by giving
its actual memory address (typically specified in
hexadecimal format) or by giving its abbreviated name
(e.g. P3)
Note: Abbreviated SFR names are defined in the “C8051F020.inc” header file

♦ Example:

MOV A, P3 ;Transfer the contents

of
MOV A, 020H ;Port 3 to the
accumulator
location 20H to the
;Transfer the contents
accumulator
of RAM
 Indirect Addressing
♦ This mode uses a pointer to hold the effective address of
the operand
♦ Only registers R0, R1 and DPTR can be used as the
pointer registers
♦ The R0 and R1 registers can hold an 8-bit address,
whereas DPTR can hold a 16-bit address

♦ Examples:
;Store the content of
;accumulator into the memory
MOV @R0,A ;location pointed to by
;register R0. R0 could have an
;8-bit address, such as 60H.

;Transfer the contents from

MOVX A,@DPTR
;the memory location
;pointed to by DPTR into the
;accumulator. DPTR could
have a
;16-bit address, such as 1234H.
 Immediate Constant Addressing
♦ This mode of addressing uses either an 8- or
16-bit constant value as the source operand
♦ This constant is specified in the instruction, rather than
in a register or a memory location
♦ The destination register should hold the same data
size which is specified by the source operand

♦ Examples:
ADD A,#030H ;Add 8-bit value of 30H to
;the accumulator register
;(which is an 8-bit register).

MOV ;Move 16-bit data constant

DPTR,#0FE00H ;FE00H into the 16-bit Data
;Pointer Register.
 Relative Addressing
♦ This mode of addressing is used with some type of jump
instructions, like SJMP (short jump) and conditional
jumps like JNZ
♦ These instructions transfer control from one part of
a program to another
♦ The destination address must be within -128 and +127
bytes from the current instruction address because an
8-bit offset is used (28 = 256)
♦ Example:

GoBack: DEC A ;Decrement A

JNZ GoBac ;If A is not zero,
k loop back
 Absolute Addressing
♦ Two instructions associated with this mode of addressing
are ACALL and AJMP instructions
♦ These are 2-byte instructions where the 11-bit absolute
address is specified as the operand
♦ The upper 5 bits of the 16-bit PC address are not modified.
The lower 11 bits are loaded from this instruction. So, the
branch address must be within the current 2K byte page of
program memory (211 = 2048)
♦ Example: ;PORT_INIT
should be
ACALL PORT_INIT
;located within 2k
bytes.

PORT_INIT: P0, #0FH ;PORT_INIT

MOV subroutine
 Long Addressing
♦ This mode of addressing is used with the LCALL and
LJMP instructions
♦ It is a 3-byte instruction and the last 2 bytes specify a
16-bit destination location where the program branches
♦ It allows use of the full 64 K code space
♦ The program will always branch to the same location
no matter where the program was previously
♦ Example:
LCALL TIMER_INIT ;TIMER_INIT address
(16-bits
;long) is specified as
the
;operand; In C, this
TIMER_INIT: ORL ;TIMER_INIT will be a
TMOD,#01H subroutine

;function call:
Timer_Init().
 Indexed Addressing

♦ The Indexed addressing is useful when there is a need to retrieve

data from a look-up table
♦ A 16-bit register (data pointer) holds the base address and
the accumulator holds an 8-bit displacement or index
value
♦ The sum of these two registers forms the effective address for a
JMP or MOVC instruction
♦ Example: ;Offset from table
MOV A,#08H start
MOV DPTR,#01F ;Table start
MOVC 00H
A,@A+DPTR address
;Gets target value from the
table;start address + offset and puts it
;in A.

♦ After the execution of the above instructions, the program will branch to
address 1F08H (1F00H+08H) and transfer into the accumulator the data
byte retrieved from that location (from the look-up table)
Keil software introduction:

https://www.youtube.com/watch?v=mhHJV21CDjs.
 Introduction
♦ A computer instruction is made up of an operation code
(op-code) followed by either zero, one or two bytes of
operands
♦ The op-code identifies the type of operation to be performed
while the operands identify the source and destination of the
data
♦ The operand can be:
The data value itself
A CPU register
A memory location
An I/O port
♦ If the instruction is associated with more than one operand,
the format is always:
Instruction Destination, Source
1
 Instruction Types
♦ The C8051F020 instructions are divided into five functional
groups:
Arithmetic operations
Logical operations
Data transfer operations
Boolean variable operations
Program branching operations

2
 Arithmetic Operations

♦ [@Ri] implies contents

of memory location
pointed to by R0 or R1

♦ Rn refers to registers
R0-R7 of the currently
selected register bank

3
 ADD A,<source-byte> ADDC A,<source-byte>
♦ ADD adds the data byte specified by the source operand to
the accumulator, leaving the result in the accumulator
♦ ADDC adds the data byte specified by the source operand,
the carry flag and the accumulator contents, leaving the
result in the accumulator
♦ Operation of both the instructions, ADD and ADDC, can
affect the carry flag (CY), auxiliary carry flag (AC) and the
overflow flag (OV)
CY=1 If there is a carryout from bit 7; cleared otherwise
AC =1 If there is a carryout from the lower 4-bit of A i.e. from bit 3;
cleared otherwise
OV=1 If the signed result cannot be expressed within the number
of bits in the destination operand; cleared otherwise

4
 SUBB A,<source-byte>
♦ SUBB subtracts the specified data byte and the carry flag together from
the accumulator, leaving the result in the accumulator
CY=1 If a borrow is needed for bit 7; cleared otherwise
AC =1 If a borrow is needed for bit 3, cleared otherwise
OV=1 If a borrow is needed into bit 6, but not into bit 7, or into bit 7,
but not into bit 6.
♦ Example:
The accumulator holds 0C1H (11000001B), Register1 holds 40H
(01000000B) and the CY=1.The instruction,

SUBB A, R1

gives the value 70H (01110000B) in the accumulator, with the CY=0 and
AC=0 but OV=1

5
 INC <byte>
♦ Increments the data variable by 1. The instruction is used in register,
direct or register direct addressing modes
♦ Example:
INC6FH
If the internal RAM location 6FH contains 30H, then the instruction
increments this value, leaving 31H in location 6FH
♦ Example:
MOVR1, #5E
INCR1
INC@R1
♦ If R1=5E (01011110) and internal RAM location 5FH contains 20H, the
instructions will result in R1=5FH and internal RAM location 5FH to
increment by one to 21H

6
 DEC <byte>
♦ The data variable is decremented by 1

♦ The instruction is used in accumulator, register, direct or

register direct addressing modes

♦ A data of value 00H underflows to FFH after the operation

♦ No flags are affected

7
 INC DPTR
♦ Increments the 16-bit data pointer by 1

♦ DPTR is the only 16-bit register that can be incremented

♦ The instruction adds one to the contents of DPTR directly

8
 MUL AB
♦ Multiplies A & B and the 16-bit result stored in [B15-8], [A7-0]

♦ Multiplies the unsigned 8-bit integers in the accumulator and the B

register

♦ The Low order byte of the 16-bit product will go to the accumulator
and the High order byte will go to the B register

♦ If the product is greater than 255 (FFH), the overflow flag is set;
otherwise it is cleared. The carry flag is always cleared.

♦ If ACC=85 (55H) and B=23 (17H), the instruction gives the product
1955 (07A3H), so B is now 07H and the accumulator is A3H. The
overflow flag is set and the carry flag is cleared.

9
 DIV AB
♦ Divides A by B

♦ THE INTEGER PART OF THE QUOTIENT IS STORED IN

A AND THE REMAINDER GOES TO THE B REGISTER

♦ If ACC=90 (5AH) and B=05(05H), the instruction leaves 18

(12H) in ACC and the value 00 (00H) in B, since 90/5 = 18
(quotient) and 00 (remainder)

♦ Carry and OV are both cleared

♦ If B contains 00H before the division operation, then the

values stored in ACC and B are undefined and an overflow
flag is set. The carry flag is cleared.

10
 DA A
♦ This is a decimal adjust instruction
♦ It adjusts the 8-bit value in ACC resulting from operations
like ADD or ADDC and produces two 4-bit digits (in packed
Binary Coded Decimal (BCD) format)
♦ Effectively, this instruction performs the decimal conversion
by adding 00H, 06H, 60H or 66H to the accumulator,
depending on the initial value of ACC and PSW
♦ If ACC bits A3-0 are greater than 9 (xxxx1010-xxxx1111), or
if AC=1, then a value 6 is added to the accumulator to
produce a correct BCD digit in the lower order nibble
♦ If CY=1, because the high order bits A7-4 is now exceeding
9 (1010xxxx-1111xxxx), then these high order bits will be
increased by 6 to produce a correct proper BCD in the high
order nibble but not clear the carry
11
 Logical Operations

♦ Logical instructions perform Boolean operations (AND, OR,

XOR, and NOT) on data bytes on a bit-by-bit basis
12
 ANL <dest-byte>,<source-byte>
♦ This instruction performs the logical AND operation on the
source and destination operands and stores the result in the
destination variable

♦ No flags are affected

♦ Example:
ANLA,R2
If ACC=D3H (11010011) and R2=75H (01110101), the
result of the instruction is ACC=51H (01010001)

♦ The following instruction is also useful when there is a need

to mask a byte

♦ Example:
ANLP1,#10111001B
13
 ORL <dest-byte>,<source-byte>
♦ This instruction performs the logical OR operation on the
source and destination operands and stores the result in the
destination variable

♦ No flags are affected

♦ Example:
ORLA,R2
If ACC=D3H (11010011) and R2=75H (01110101), the
result of the instruction is ACC=F7H (11110111)

♦ Example:
ORLP1,#11000010B
This instruction sets bits 7, 6, and 1 of output Port 1

14
 XRL <dest-byte>,<source-byte>
♦ This instruction performs the logical XOR (Exclusive OR)
operation on the source and destination operands and
stores the result in the destination variable

♦ No flags are affected

♦ Example:
XRLA,R0
If ACC=C3H (11000011) and R0=AAH (10101010), then the
instruction results in ACC=69H (01101001)

♦ Example:
XRLP1,#00110001
This instruction complements bits 5, 4, and 0 of
output Port 1
15
 CLR A and CPL A

CLR A
♦ This instruction clears the accumulator (all bits set to 0)
♦ No flags are affected
♦ If ACC=C3H, then the instruction results in ACC=00H

CPL A
♦ This instruction logically complements each bit of the
accumulator (one’s complement)
♦ No flags are affected
♦ If ACC=C3H (11000011), then the instruction results in
ACC=3CH (00111100)

16
 RL A
♦ The 8 bits in the accumulator are rotated one bit to the left.
Bit 7 is rotated into the bit 0 position.

♦ No flags are affected

♦ If ACC=C3H (11000011), then the instruction results in

ACC=87H (10000111) with the carry unaffected

17
 RLC A
♦ The instruction rotates the accumulator contents one bit to
the left through the carry flag

♦ Bit 7 of the accumulator will move into carry flag and the
original value of the carry flag will move into the Bit 0
position

♦ No other flags are affected

♦ If ACC=C3H (11000011), and the carry flag is 1, the

instruction results in ACC=87H (10000111) with the carry
flag set

18
 RR A
♦ The 8 bits in the accumulator are rotated one bit to the right.
Bit 0 is rotated into the bit 7 position.

♦ No flags are affected

♦ If ACC=C3H (11000011), then the instruction results in

ACC=E1H (11100001) with the carry unaffected

19
 RRC A
♦ The instruction rotates the accumulator contents one bit to
the right through the carry flag

♦ The original value of carry flag will move into Bit 7 of the
accumulator and Bit 0 rotated into carry flag

♦ No other flags are affected

♦ If ACC=C3H (11000011), and the carry flag is 0, the

instruction results in ACC=61H (01100001) with the carry
flag set

20
 SWAP A
♦ This instruction interchanges the low order 4-bit nibbles
(A3-0) with the high order 4-bit nibbles (A7-4) of the ACC

♦ The operation can also be thought of as a 4-bit rotate

instruction

♦ No flags are affected

♦ If ACC=C3H (11000011), then the instruction leaves

ACC=3CH (00111100)

21
 Data Transfer Instructions
Mnemonic Description
MOV @Ri, direct [@Ri] = [direct]
MOV @Ri, #data [@Ri] = immediate data
MOV DPTR, #data 16 [DPTR] = immediate data
MOVC A,@A+DPTR A = Code byte from [@A+DPTR]
MOVC A,@A+PC A = Code byte from [@A+PC]
MOVX A,@Ri A = Data byte from external ram [@Ri]
MOVX A,@DPTR A = Data byte from external ram [@DPTR]
MOVX @Ri, A External[@Ri] = A
MOVX @DPTR,A External[@DPTR] = A
PUSH direct Push into stack
POP direct Pop from stack
XCH A,Rn A = [Rn], [Rn] = A
XCH A, direct A = [direct], [direct] = A
XCH A, @Ri A = [@Rn], [@Rn] = A
XCHD A,@Ri Exchange low order digits

22
 MOV <dest-byte>,<source-byte>
♦ This instruction moves the source byte into the destination location
♦ The source byte is not affected, neither are any other registers or flags
♦ Example:

MOVR1,#60;R1=60H
MOVA,@R1 ;A=[60H]
MOVR2,#61;R2=61H
ADDA,@R2 ;A=A+[61H]
MOVR7,A ;R7=A

♦ If internal RAM locations 60H=10H, and 61H=20H, then after the

operations of the above instructions R7=A=30H. The data contents of
memory locations 60H and 61H remain intact.

23
 MOV DPTR, #data 16
♦ This instruction loads the data pointer with the 16-bit
constant and no flags are affected

♦ Example:
MOVDPTR,#1032

♦ This instruction loads the value 1032H into the data pointer,
i.e. DPH=10H and DPL=32H.

24
 MOVC A,@A + <base-reg>
♦ This instruction moves a code byte from program memory into ACC
♦ The effective address of the byte fetched is formed by adding the original 8-bit
accumulator contents and the contents of the base register, which is either the
data pointer (DPTR) or program counter (PC)
♦ 16-bit addition is performed and no flags are affected
♦ The instruction is useful in reading the look-up tables in the program memory
♦ If the PC is used, it is incremented to the address of the following instruction
before being added to the ACC
♦ Example:
CLRA
LOC1: INCA
MOVC A,@A + PC
RET
Look_up DB 10H
DB 20H
DB 30H
DB 40H
♦ The subroutine takes the value in the accumulator to 1 of 4 values
defined by the DB (define byte) directive
♦ After the operation of the subroutine it returns ACC=20H
25
 MOVX <dest-byte>,<source-byte>
♦ This instruction transfers data between ACC and a byte of external data
memory

♦ There are two forms of this instruction, the only difference between them
is whether to use an 8-bit or 16-bit indirect addressing mode to access
the external data RAM

♦ The 8-bit form of the MOVX instruction uses the EMI0CN SFR to
determine the upper 8 bits of the effective address to be accessed and
the contents of R0 or R1 to determine the lower 8 bits of the effective
address to be accessed

♦ Example:
MOV EMI0CN,#10H ;Load high byte of
;address into EMI0CN.
MOV R0,#34H ;Load low byte of
;address into R0(or R1).
MOVX A,@R0 ;Load contents of 1034H
;into ACC.

26
 MOVX <dest-byte>,<source-byte>
♦ The 16-bit form of the MOVX instruction accesses the memory location
pointed to by the contents of the DPTR register

♦ Example:
MOVDPTR,#1034H ;Load DPTR with 16 bit
;address to read (1034H).
MOVX A,@DPTR ;Load contents of 1034H
;into ACC.

♦ The above example uses the 16-bit immediate MOV DPTR instruction to
set the contents of DPTR

♦ Alternately, the DPTR can be accessed through the SFR registers DPH,
which contains the upper 8 bits of DPTR, and DPL, which contains the
lower 8 bits of DPTR

27
 PUSH Direct
♦ This instruction INCREMENTS THE STACK POINTER (SP) BY 1

♦ The contents of Direct, which is an internal memory location or a SFR,

are copied into the internal RAM location addressed by the stack pointer

♦ No flags are affected

♦ Example:
PUSH 22H
PUSH 23H

♦ Initially the SP points to memory location 4FH and the contents of

memory locations 22H and 23H are 11H and 12H respectively. After the
above instructions, SP=51H, and the internal RAM locations 50H and
51H will store 11H and 12H respectively.

28
 POP Direct
♦ This instruction reads the contents of the internal RAM location
addressed by the stack pointer (SP) and decrements the stack pointer
by 1. The data read is then transferred to the Direct address which is an
internal memory or a SFR. No flags are affected.

♦ Example:
POPDPH
POPDPL

♦ If SP=51H originally and internal RAM locations 4FH, 50H and 51H
contain the values 30H, 11H and 12H respectively, the instructions
above leave SP=4FH and DPTR=1211H

POPSP
♦ If the above line of instruction follows, then SP=30H. In this case, SP is
decremented to 4EH before being loaded with the value popped (30H)

29
 XCH A,<byte>
♦ This instruction swaps the contents of ACC with the contents
of the indicated data byte

♦ Example:
XCHA,@R0

♦ Suppose R0=2EH, ACC=F3H (11110011) and internal RAM

location 2EH=76H (01110110). The result of the above
instruction leaves RAM location 2EH=F3H and ACC=76H.

30
 XCHD A,@Ri
♦ This instruction exchanges the low order nibble of ACC (bits
0-3), with that of the internal RAM location pointed to by Ri
register

♦ The high order nibbles (bits 7-4) of both the registers remain
the same

♦ No flags are affected

♦ Example:
XCHDA,@R0

If R0=2EH, ACC=76H (01110110) and internal RAM location

2EH=F3H (11110011), the result of the instruction leaves
RAM location 2EH=F6H (11110110) and
ACC=73H (01110011)
31
 Boolean Variable Instructions
♦ The C8051F020 processor
Mnemonic Description
CLR C Clear C
can perform single bit
CLR bit Clear direct bit
operations SETB C Set C

SETB bit Set direct bit

♦ The operations include set, CPL C Complement c

clear, as well as and, or and CPL bit Complement direct bit

complement instructions ANL C,bit AND bit with C

ANL C,/bit AND NOT bit with C

ORL C,bit OR bit with C

♦ Also included are bit–level ORL C,/bit OR NOT bit with C
moves or conditional jump MOV C,bit MOV bit to C
instructions MOV bit,C MOV C to bit

JC rel Jump if C set

♦ All bit accesses use direct JNC rel Jump if C not set

JB bit,rel Jump if specified bit set

addressing
JNB bit,rel Jump if specified bit not set
if specified bit set then clear it and
JBC bit,rel
jump
32
 CLR <bit>
♦ This operation clears (reset to 0) the specified bit indicated
in the instruction

♦ No other flags are affected

♦ CLR instruction can operate on the carry flag or any

directly-addressable bit

♦ Example:
CLRP2.7
If Port 2 has been previously written with DCH (11011100),
then the operation leaves the port set to 5CH (01011100)

33
 SETB <bit>
♦ This operation sets the specified bit to 1

♦ SETB instruction can operate on the carry flag or any

directly-addressable bit

♦ No other flags are affected

♦ Example:
SETB C
SETB P2.0
♦ If the carry flag is cleared and the output Port 2 has the
value of 24H (00100100), then the result of the instructions
sets the carry flag to 1 and changes the Port 2 value to 25H
(00100101)

34
 CPL <bit>
♦ This operation complements the bit indicated by the operand

♦ No other flags are affected

♦ CPL instruction can operate on the carry flag or any

directly-addressable bit

♦ Example:
CPLP2.1
CPLP2.2
♦ If Port 2 has the value of 53H (01010011) before the start of
the instructions, then after the execution of the instructions it
leaves the port set to 55H (01010101)

35
 ANL C, <source-bit>
♦ This instruction ANDs the bit addressed with the Carry bit and stores the result in
the Carry bit itself

♦ If the source bit is a logical 0, then the instruction clears the carry flag; else the
carry flag is left in its original value

♦ If a slash (/) is used in the source operand bit, it means that the logical
complement of the addressed source bit is used, but the source bit itself is not
affected

♦ No other flags are affected

♦ Example:
MOVC,P2.0;Load C with input pin
;state of P2.0.
ANLC,P2.7;AND carry flag with ;bit 7
of P2.
MOVP2.1,C;Move C to bit 1 of Port 2.
ANLC,/OV ;AND with inverse of OV flag.

♦ If P2.0=1, P2.7=0 and OV=0 initially, then after the above instructions,
P2.1=0, CY=0 and the OV remains unchanged, i.e. OV=0
36
 ORL C, <source-bit>
♦ This instruction ORs the bit addressed with the Carry bit and stores the result in
the Carry bit itself

♦ It sets the carry flag if the source bit is a logical 1; else the carry is left in its
original value

♦ If a slash (/) is used in the source operand bit, it means that the logical
complement of the addressed source bit is used, but the source bit itself is not
affected

♦ No other flags are affected

♦ Example:
MOV C,P2.0 ;Load C with input pin
;state of P2.0.
ORL C,P2.7 ;OR carry flag with
;bit 7 of P2.
MOV P2.1,C ;Move C to bit 1 of
;port 2.
ORL C,/OV ;OR with inverse of OV
;flag.

37
 MOV <dest-bit>,<source-bit>
♦ The instruction loads the value of source operand bit into the destination
operand bit

♦ One of the operands must be the carry flag; the other may be any
directly-addressable bit

♦ No other register or flag is affected

♦ Example:
MOVP2.3,C
MOVC,P3.3
MOVP2.0,C

♦ If P2=C5H (11000101), P3.3=0 and CY=1 initially, then after the above
instructions, P2=CCH (11001100) and CY=0.

38
 JC rel
♦ This instruction branches to the address, indicated by the label, if the
carry flag is set, otherwise the program continues to the next instruction

♦ No flags are affected

♦ Example:
CLRC
SUBB A,R0
JC ARRAY1
MOVA,#20H

♦ The carry flag is cleared initially. After the SUBB instruction, if the value
of A is smaller than R0, then the instruction sets the carry flag and
causes program execution to branch to ARRAY1 address, otherwise it
continues to the MOV instruction.

39
 JNC rel
♦ This instruction branches to the address, indicated by the label, if the
carry flag is not set, otherwise the program continues to the next
instruction

♦ No flags are affected. The carry flag is not modified.

♦ Example:
CLRC
SUBB A,R0
JNCARRAY2
MOVA,#20H

♦ The above sequence of instructions will cause the jump to be taken if the
value of A is greater than or equal to R0. Otherwise the program will
continue to the MOV instruction.

40
 JB <bit>,rel
♦ This instruction jumps to the address indicated if the
destination bit is 1, otherwise the program continues to the
next instruction

♦ No flags are affected. The bit tested is not modified.

♦ Example:
JB ACC.7,ARRAY1
JB P1.2,ARRAY2

♦ If the accumulator value is 01001010 and Port 1=57H

(01010111), then the above instruction sequence will cause
the program to branch to the instruction at ARRAY2

41
 JNB <bit>,rel
♦ This instruction jumps to the address indicated if the
destination bit is 0, otherwise the program continues to the
next instruction

♦ No flags are affected. The bit tested is not modified.

♦ Example:
JNBACC.6,ARRAY1
JNBP1.3,ARRAY2

♦ If the accumulator value is 01001010 and Port 1=57H

(01010111), then the above instruction sequence will cause
the program to branch to the instruction at ARRAY2

42
 JBC <bit>,rel
♦ If the source bit is 1, this instruction clears it and branches to
the address indicated; else it proceeds with the next
instruction

♦ The bit is not cleared if it is already a 0. No flags are

affected.

♦ Example:
JBCP1.3,ARRAY1
JBCP1.2,ARRAY2

♦ If P1=56H (01010110), the above instruction sequence will

cause the program to branch to the instruction at
ARRAY2, modifying P1 to 52H (01010010)
43
 Program Branching Instructions
♦ Program branching Mnemonic Description

ACALL addr11 Absolute subroutine call

instructions are used to
LCALL addr16 Long subroutine call
control the flow of actions in RET Return from subroutine
a program RETI Return from interrupt

AJMP addr11 Absolute jump

♦ Some instructions provide

LJMP addr16 Long jump

SJMP rel Short jump

decision making JMP @A+DPTR Jump indirect

capabilities and transfer JZ rel Jump if A=0

control to other parts of the JNZ rel Jump if A NOT=0

program, e.g. conditional CJNE A,direct,rel

and unconditional branches CJNE A,#data,rel

Compare and Jump if Not Equal
CJNE Rn,#data,rel

CJNE @Ri,#data,rel

DJNZ Rn,rel
Decrement and Jump if Not
Zero
DJNZ direct,rel

NOP No Operation

44
 ACALL addr11
♦ This instruction unconditionally calls a subroutine indicated by the
address
♦ The operation will cause the PC to increase by 2, then it pushes the
16-bit PC value onto the stack (low order byte first) and increments the
stack pointer twice
♦ The PC is now loaded with the value addr11 and the program execution
continues from this new location
♦ The subroutine called must therefore start within the same 2 kB block of
the program memory

♦ No flags are affected

♦ Example:
ACALL LOC_SUB

♦ If SP=07H initially and the label “LOC_SUB” is at program memory

location 0567H, then executing the instruction at location 0230H,
SP=09H, internal RAM locations 08H and 09H will contain 32H
and 02H respectively and PC=0567H

45
 LCALL addr16
♦ This instruction calls a subroutine located at the indicated address

♦ The operation will cause the PC to increase by 3, then it pushes the

16-bit PC value onto the stack (low order byte first) and increments the
stack pointer twice

♦ The PC is then loaded with the value addr16 and the program execution
continues from this new location

♦ Since it is a Long call, the subroutine may therefore begin anywhere in

the full 64 kB program memory address space

♦ No flags are affected

♦ Example:
LCALL LOC_SUB

♦ Initially, SP=07H and the label “LOC_SUB” is at program memory

location 2034H. Executing the instruction at location 0230H,
SP=09H, internal RAM locations 08H and 09H contain 33H
and 02H respectively and PC=2034H
46
 RET
♦ This instruction returns the program from a subroutine

♦ RET pops the high byte and low byte address of PC from
the stack and decrements the SP by 2

♦ The execution of the instruction will result in the program to

resume from the location just after the “call” instruction

♦ No flags are affected

♦ Suppose SP=0BH originally and internal RAM locations 0AH

and 0BH contain the values 30H and 02H respectively. The
instruction leaves SP=09H and program execution will
continue at location 0230H

47
 RETI
♦ This instruction returns the program from an interrupt
subroutine
♦ RETI pops the high byte and low byte address of PC from
the stack and restores the interrupt logic to accept additional
interrupts
♦ SP decrements by 2 and no other registers are affected.
However the PSW is not automatically restored to its
pre-interrupt status
♦ After the RETI, program execution will resume immediately
after the point at which the interrupt is detected
♦ Suppose SP=0BH originally and an interrupt is detected
during the instruction ending at location 0213H
Internal RAM locations 0AH and 0BH contain the values 14H and
02H respectively
The RETI instruction leaves SP=09H and returns
48
program execution to location 0234H
 AJMP addr11
♦ The AJMP instruction transfers program execution to the
destination address which is located at the absolute short
range distance (short range means 11-bit address)

♦ The destination must therefore be within the same 2kB block

of program memory

♦ Example:
AJMP NEAR

♦ If the label NEAR is at program memory location 0120H, the

AJMP instruction at location 0234H loads the PC with 0120H

49
 LJMP addr16
♦ The LJMP instruction transfers program execution to the
destination address which is located at the absolute long
range distance (long range means 16-bit address)

♦ The destination may therefore be anywhere in the full 64 kB

program memory address space

♦ No flags are affected

♦ Example:
LJMP FAR_ADR

♦ If the label FAR_ADR is at program memory location 3456H,

the LJMP instruction at location 0120H loads the PC
with 3456H
50
 SJMP rel
♦ This is a short jump instruction, which increments the PC by 2
and then adds the relative value ‘rel’ (signed 8-bit) to the PC

♦ This will be the new address where the program would branch
to unconditionally

♦ Therefore, the range of destination allowed is from -128 to

+127 bytes from the instruction

♦ Example:
SJMP RELSRT

♦ If the label RELSRT is at program memory location 0120H

and the SJMP instruction is located at address 0100H,
after executing the instruction, PC=0120H.
51
 JMP @A + DPTR
♦ This instruction adds the 8-bit unsigned value of the ACC to the 16-bit
data pointer and the resulting sum is returned to the PC

♦ Neither ACC nor DPTR is altered

♦ No flags are affected

♦ Example:
MOVDPTR, #LOOK_TBL
JMP@A + DPTR
LOOK_TBL:AJMP LOC0
AJMP LOC1
AJMP LOC2
If the ACC=02H, execution jumps to LOC1

♦ AJMP is a two byte instruction

52
 JZ rel
♦ This instruction branches to the destination address if
ACC=0; else the program continues to the next instruction

♦ The ACC is not modified and no flags are affected

♦ Example:
SUBB A,#20H
JZ LABEL1
DECA

♦ If ACC originally holds 20H and CY=0, then the SUBB

instruction changes ACC to 00H and causes the program
execution to continue at the instruction identified by
LABEL1; otherwise the program continues to the DEC
instruction

53
 JNZ rel
♦ This instruction branches to the destination address if any bit
of ACC is a 1; else the program continues to the next
instruction

♦ The ACC is not modified and no flags are affected

♦ Example:
DECA
JNZLABEL2
MOVRO, A

♦ If ACC originally holds 00H, then the instructions change

ACC to FFH and cause the program execution to continue at
the instruction identified by LABEL2; otherwise the program
continues to MOV instruction

54
 CJNE <dest-byte>,<source-byte>,rel
♦ This instruction compares the magnitude of the dest-byte and the
source-byte and branches if their values are not equal

♦ The carry flag is set if the unsigned dest-byte is less than the unsigned
integer source-byte; otherwise, the carry flag is cleared

♦ Neither operand is affected

♦ Example:
CJNE R3,#50H,NEQU
… … ;R3 = 50H
NEQU: JC LOC1 ;If R3 < 50H
… … ;R7 > 50H
LOC1: … … ;R3 < 50H

55
 DJNZ <byte>,<rel-addr>
♦ This instruction is ”decrement jump not zero”
♦ It decrements the contents of the destination location and if the resulting
value is not 0, branches to the address indicated by the source operand
♦ An original value of 00H underflows to FFH
♦ No flags are affected

♦ Example:
DJNZ 20H,LOC1
DJNZ 30H,LOC2
DJNZ 40H,LOC3

♦ If internal RAM locations 20H, 30H and 40H contain the values 01H,
5FH and 16H respectively, the above instruction sequence will cause a
jump to the instruction at LOC2, with the values 00H, 5EH, and 15H in
the 3 RAM locations.
Note, the first instruction will not branch to LOC1 because the [20H] = 00H,
hence the program continues to the second instruction
Only after the execution of the second instruction (where the
location [30H] = 5FH), then the branching takes place

56
 NOP
♦ This is the no operation instruction
♦ The instruction takes one machine cycle operation time
♦ Hence it is useful to time the ON/OFF bit of an output port
♦ Example:
CLRP1.2
NOP
NOP
NOP
NOP
SETB P1.2

♦ The above sequence of instructions outputs a low-going output pulse on

bit 2 of Port 1 lasting exactly 5 cycles.
Note a simple SETB/CLR generates a 1 cycle pulse, so four additional
cycles must be inserted in order to have a 5-clock
pulse width

57
However, the relation between machine cycle and clock cycle depends upon the
manufacturer. Ex: AT89C51 by Atmel consider 12 clock cycles per machine cycle. But,
other 8051 manufactured by Dallas consider 1 clock cycles per machine cycle.

Instruction cycle: Fetch, decode, execute, write back into memory and etc.
•Note: Mnemonic will occupy 1
byte memory.

•No register will occupy memory of

RAM or ROM.

•Address will occupy memory

depending upon the number of bits.

•Data also occupy memory

depending upon number of bits.
8051 Timers
⚫ The 8051 has two timers/counters, they
can be used as
◦ Timers to generate a time delay
◦ Event counters to count events happening
outside the microcontroller
⚫ Both Timer 0 and Timer 1 are 16 bits
wide
◦ Since 8051 has an 8-bit architecture, each
16-bits timer is accessed as two separate
registers of low byte and high byte
 Timer 0 & 1 Registers
• Accessed as low byte and high byte
– The low byte register is called TL0/TL1
– The high byte register is called TH0/TH1
– Accessed like any other register
MOV TL0,#4FH
MOV R5,TH0
TMOD Register
⚫ Both timers 0 and 1 use the same
register, called TMOD (timer mode), to
set the various timer operation modes
◦ TMOD is a 8-bit register
● The lower 4 bits are for Timer 0
● The upper 4 bits are for Timer 1
● In each case, the lower 2 bits are used to set the timer
mode
● The upper 2 bits to specify the operation
 Gate
Every timer has a mean of starting and stopping.
■GATE=0
■ Internal control
■ The start and stop of the timer are controlled by way of
software.
■ Set/clear the TR for start/stop timer. SETB TR0 & CLR TR0
■ GATE=1
■ External control
■ The hardware way of starting and stopping the timer by
software and an external source.
■ Timer/counter is enabled only while the INT pin is high and the
TR control pin is set (TR).
TMod contd…
TCON Register
⚫ TCON (timer control) register is an 8-bit
register
TCON Register (cont.)
⚫ TCON register is a bit-addressable
register
GATE
⚫ Timers of 8051 do starting and stopping
by either software or hardware control
◦ In using software to start and stop the timer
where GATE=0
● The start and stop of the timer are controlled by
way of software by the TR (timer start) bits TR0
and TR1
● The SETB instruction starts it, and it is stopped by
the CLR instruction
● These instructions start and stop the timers as long as
GATE=0 in the TMOD register
GATE (cont.)
⚫ The hardware way of starting and
stopping the timer by an external source
is achieved by making GATE=1 in the
TMOD register
Mode 0 (13-bit timer mode): Mode 0 is a 13-bit timer mode for which 8-bit of THx and 5-bit of TLx (as
Prescaler) are used. It is mostly used for interfacing possible with old MCS-48 family microcontrollers.

As shown in the above figure, 8-bit of THx and lower 5-bit of TLx used to form a total 13-bit timer. Higher
3-bits of TLx should be written as zero while using timer mode0, or it will affect the result.

Example: Let's generate a square wave of 2mSec period using an AT89C51 microcontroller with timer0 in
mode0 on the P1.0 pin of port1. Assume xtal oscillator frequency of 11.0592 MHz. As the Xtal oscillator
frequency is 11.0592 MHz we have a machine cycle of 1.085uSec. Hence, the required count to generate a
delay of 1mSec. is,
Count =(1×10^-3)/(1.085×10^-6) ≈ 921
The maximum count of Mode0 is 2^13 (0 - 8191) and the Timer0 count will increment from 0 – 8191. So we
need to load value which is 921 less from its maximum count i.e. 8191. Also, here in the below program, we
need an additional 13 MC (machine cycles) from call to return of delay function. Hence value needed to be
loaded is,
Value=(8191-Count)+Function_MCycles+1 =7284= 0x1C74
So we need to load 0x1C74 value in Timer0.
1C74 = 0001 1100 0111 0100 b, now load lower 5-bit in TL0 and next 8-bit in TH0
so here we get, TL0 = 0001 0100 = 0x14 and TH0 = 1110 0011 = 0xE3
Mode 1 Programming
⚫ The following are the characteristics and
operations of mode1:
◦ It is a 16-bit timer
● It allows value of 0000 to FFFFH to be loaded into
the timer’s register TL and TH
◦ After TH and TL are loaded with a 16-bit
initial value, the timer must be started
● This is done by SETB TR0 for timer 0 and SETB
TR1 for timer 1
◦ After being started, it starts to count up
● It counts up until it reaches its limit of FFFFH
Mode 1 Programming (cont.)
● When it rolls over from FFFFH to 0000, it sets high
a flag bit called TF (timer flag)
● Each timer has its own timer flag: TF0 for timer 0, and TF1
for timer 1
● This timer flag can be monitored
● When this timer flag is raised, one option would be
to stop the timer with the instructions CLR TR0 or
CLR TR1, for timer 0 and timer 1, respectively
◦ In order to repeat the process
● TH and TL must be reloaded with the original value
● TF must be reloaded to 0
Steps to Mode 1 Program
⚫ Load the TMOD value register
◦ Indicating which timer (timer 0 or timer 1) is
to be used and which timer mode (1 or 2) is
selected
⚫ Load registers TL and TH with initial
count value
⚫ Start the timer
⚫ Keep monitoring the timer flag (TF)
◦ With the JNB TFx,target instruction to see if
it is raised
Steps to Mode 1 Program (cont.)
◦ Get out of the loop when TF becomes high
⚫ Stop the timer
⚫ Clear the TF flag for the next round
⚫ Go back to Step 2 to load TH and TL
again
https://www.electronicwings.com/8051/8051-timers
Finding the Loaded Timer Values
⚫ To calculate the values to be loaded into
the TL and TH registers:
◦ Assume XTAL = 11.0592 MHz
● Divide the desired time delay by 1.085 us
● Perform 65536 – n, where n is the decimal value
we got in Step1
● Convert the result of Step2 to hex, where yyxx is
the initial hex value to be loaded into the timer’s
register
● Set TL = xx and TH = yy
SJMP HERE
Mode 2 Programming
⚫ The following are the characteristics and
operations of mode 2:
◦ It is an 8-bit timer
● It allows only values of 00 to FFH to be loaded into
the timer’s register TH
◦ After TH is loaded with the 8-bit value, the
8051 gives a copy of it to TL
● Then the timer must be started
● This is done by the instruction SETB TR0 for timer 0 and
SETB TR1 for timer 1
Mode 2 Programming (cont.)
◦ After the timer is started, it starts to count
up by incrementing the TL register
● It counts up until it reaches its limit of FFH
● When it rolls over from FFH to 00, it sets high the
TF (timer flag)
◦ When TF is set to 1, TL is reloaded
automatically with the original value kept by
the TH register
◦ To repeat the process, we must simply clear
TF and let it go without any need by the
programmer to reload the original value
Mode 2 Programming (cont.)
⚫ Mode 2 can auto-reload, in contrast with
mode 1 in which the programmer has to
reload TH and TL
Steps to Mode 2 Program
⚫ Load the TMOD value register
◦ Indicating which timer (timer 0 or timer 1) is
to be used, and the timer mode (mode 2) is
selected
⚫ Load the TH registers with the initial
count value
⚫ Start timer
⚫ Keep monitoring the timer flag (TF)
◦ With the JNB TFx,target instruction to see
whether it is raised
Steps to Mode 2 Program (cont.)
◦ Get out of the loop when TF goes high
⚫ Clear the TF flag
⚫ Go back to Step 4
◦ Since mode 2 is auto-reload
 (253
The number 200 is )
the timer count till
the TF is set to 1
Counter Programming
⚫ Timers can also be used as counters
◦ Counting events happening outside the 8051
◦ A pulse outside of the 8051 increments the
TH, TL registers
◦ TMOD and TH, TL registers are the same as
for the timer
● Programming the timer also applies to
programming it as a counter
● Except the source of the frequency
◦ The C/T bit in the TMOD registers decides
the source of the clock for the timer
Counter Programming (cont.)
● When C/T = 1, the timer is used as a counter and
gets its pulses from outside the 8051
◦ The counter counts up as pulses are fed from
pins 14 and 15
● These pins are called T0 (timer 0 input) and T1
(timer 1 input)
Case of GATE = 1
⚫ The start and stop of the timer are done
externally through pins P3.2 and P3.3 for
timers 0 and 1, respectively
◦ Allows to start or stop the timer externally at
any time via a simple switch
Serial v/s Parallel
Communication
Serial v/s Parallel
Communication
Parallel Communication Serial Communication
Often 8 or more lines (wire conductors) The data is sent one bit at a time on a
are used to transfer data. Multiple bits single line (wire)
are transferred at a time.
Preferred for short-distance Preferred over long-distance
communication communication
Costly as more resources are required Comparatively cheaper
Speed of data transfer is high Slow
Example: SPI, I2C, UART Example: PCI
Basics of Serial Communication
• Serial communication uses single data line making it much
cheaper
• Enables two computers in different cities to communicate over the
telephone
• Byte of data must be converted to serial bits using a
parallel-in-serial- out shift register and transmitted over a single
data line
• At the receiving endthere must be a serial-in-parallel-out
shift register
• If transferred on the telephone line, it must be converted to audio
tones by modem for short distance
Modes of Serial Communication
Modes of Serial Communication
• In simplex transmissions, the computer can only send data. There
is only one wire.
• If the data can be transmittedandreceived, then it is a
duplex transmission
• Duplex transmissions can be half or full duplex depending
on whether or not the data transfer can be simultaneous
• If the communication is only one way at a time, it is half duplex
• If both sides can communicate at the same time, it is full duplex
✔ Full duplex requires two wire conductors for the data
lines (in addition to the signal ground)
Basics of Serial Communication
• Serial Communication can be
✔ Asynchronous
✔ Synchronous
Synchronous Communication
• Synchronous methods transfer a block of data (characters) at a
time
• The events are referenced to a clock
• Example: SPI bus, I2C bus
Asynchronous Communication
• Asynchronous methods transfer a single byte at a time
• There is no clock. The bytes are separated by start and stop bits.
• Example: UART
Basics of Serial Communication
• To support serial communication, special interfaces are built in
the microcontroller.
• The microcontrollers use special IC chips called UART
(universal asynchronous receiver-transmitter) and USART
(universal synchronous asynchronous
receiver-transmitter)
• 8051 chip has a built-in UART
Data Framing in Asynchronous Serial
Communication
• Data is transmitted in 0s and 1s
• To have a sense of synchronization between transmitter and
receiver and to make sense of the data, transmitter and
receiver agree on a set of rules i.e protocol, which describes
✔ how the data is packed
✔ how many bits constitute a character
✔ when the data begins and ends
Data Framing in Asynchronous Serial
Communication
Start and stop bits
• Each character is placed between start and stop bits. This is
called framing.
• Start bit is always one bit, stop bit can be one, two or one and
half bits
• In 8051 serial port, when there is no transmission, the TxD
line is held high. This is called mark.
• Start bit is always a 0 (low), stop bit(s) is 1 (high)
• LSB is sent out first
Data Framing in Asynchronous Serial
Communication
Framing ASCII
A

• The transmission begins with a start bit, followed by the

LSB(D0), then the rest of the bits until MSB (D7), and finally,
the one stop bit indicating the end of the character
• When there is no transfer, the signal is 1 (high), which is
referred
to as mark
RS232 Standards
• An interfacing standard RS232 was set by the Electronics
Industries Association (EIA) in 1960
• In RS232, a 1 ies represented by -3 ~ -25 V, while a 0 bit is +3
~
+25 V, making -3 to +3 undefined
• The standard was set long before the advent of the TTL logic
family, its input and output voltage levels are not TTL
compatible
• A microcontroller system must use voltage converters such as
MAX232 to convert the TTL logic levels to the RS232 voltage
levels, and vice versa
• MAX232 IC chips are commonly referred to as line drivers
Handshaking in Rs232
• Current terminology classifies data communication equipment
as
✔ DTE (data terminal equipment) refers to
terminal and
computers that send and receive data
✔ DCE (data communication equipment) refers to
communication equipment, such as modems
• The simplest connection between a PC and
microcontroller requires a minimum of three pins, TxD, RxD,
and ground
TxD and RxD in 8051
• 8051 has two pins that are used specifically for transferring
and receiving data serially
✔ These two pins are called TxD and RxD and are part of
the port 3 group (P3.0 and P3.1)
✔ These pins are TTL compatible; therefore, they require a
line driver to make them RS232 compatible
• We need a line driver (voltage converter) to convert the
R232’s signals to TTL voltage levels that will be acceptable
to 8051’s TxD and RxD pins
SCON Register
SCON is an 8-bit register used to program the start bit, stop bit, and data
bits of data framing, among other Things
SM0 SM1 SM2 REN TB8 RB8 TI RI

• SM0 : Serial Mode Specifier

• SM1 : Serial Mode Speceifier
• SM2 : Used for multiprocessor Communication
• REN : Set/Cleared by Software to enable/disable reception
• TB8 : not used in Mode 1
• RB8 : Not used in Mode 1
• TI : Transmit interrupt flag. Set by HW at the begin of the stop bit
mode 1. And cleared by SW
• RI : Receive interrupt flag. Set by HW at the begin of the stop bit
mode 1.
And cleared by SW
SCON Register
SM0, SM1 determine the framing of data by specifying the
number of bits per character, and the start and stop bits

SM0 SM1 Serial Mode

0 0 Mode 0
0 1 Mode 1
1 0 Mode 2
1 1 Mode 3
Serial Data Transmission
Modes
Mode 0
• In this mode, the serial port works like a shift register and the
data transmission works synchronously with a clock
frequency of fosc /12.
• Serial data is received and transmitted through RXD.
• 8 bits are transmitted/received at a time.
• Pin TXD outputs the shift clock pulses of frequency fosc /12,
which is connected to the external circuitry for
synchronization.
• The shift frequency or baud rate is always 1/12 of the
oscillator frequency.
Serial Data Transmission
Modes
Mode 1
• In mode-1, the serial port functions as a standard Universal
Asynchronous Receiver Transmitter (UART) mode.
• 10 bits are transmitted through TXD or received through RXD.
• The 10 bits consist of one start bit (which is usually '0'), 8 data
bits (LSB is sent first/received first), and a stop bit (which is
usually '1').
• Once received, the stop bit goes into RB8 in the special
function register SCON. The baud rate is variable.

TH1 = 256 - ((system frequency / (12 * 32)) / baud)

Serial Data Transmission
Modes
Mode
2• In this mode 11 -bits are transmitted through TXD or received
through
RXD.
• The various bits are as follows: a start bit (usually '0'), 8 data bits
(LSB first), a programmable 9 th (TB8 or RB8)bit and a stop bit
(usually '1').
• While transmitting, the 9 th data bit (TB8 in SCON) can be assigned
the data,
valuethe bitth goes into RB8 in 'SCON', while the stop bit is
'0' or '1'.
9
ignored.
✔
• The baudexample,
For if the information
rate is programmable of parity
to either 1/32 is
orto1/64
be transmitted, the
of the oscillator
parity bit (P) in PSW could be moved into TB8. On reception of
frequency.
• the
f baud = (2 SMOD /64) fosc.
Serial Data Transmission
Modes
Mode 3
• In this mode 11 -bits are transmitted through TXD or received
through RXD.
• The various bits are: a start bit (usually '0'), 8 data bits (LSB
first), a programmable 9 th bit and a stop bit (usually '1').
• Mode-3 is same as mode-2, except the fact that the baud rate in
mode-3 is variable (i.e., just as in mode-1).
• f baud = (2 SMOD /32) * ( fosc / 12 (256-TH1)) .
• This baud rate holds when Timer-1 is programmed in Mode-2.
Setting Baud rate in 8051
• Baud rate in the 8051 baud rate in the 8051 is programmable
Relationship between the crystal frequency and the
baud rate in the 8051 for Timer 1 use i. e ; Mode 1 and
Mode 3.
✔ 8051 divides the crystal frequency by 12 to get the machine
cycle frequency
✔ XTAL = 11.0592 MHz, the machine cycle frequency is 921.6
kHz 8051's UART divides the machine cycle frequency of
921.6 kHz by 32 once more before it is used by Timer 1 to set
the baud rate 921.6 kHz divided by 32 gives 28,800 Hz
Setting Baud rate in 8051
• Timer 1 must be programmed in mode 2, that is 8-bit,
auto-reload
 Setting Baud rate in 8051
• Timer 1 must be programmed in mode 2, that is 8-bit,
auto-reload
 SBUF Register
• A byte of data to be transferred via the TxD line must be placed in the
SBUF register
• SBUF holds the byte of data when it is received by the RxD line
• SBUF can be accessed like any other register
▪ MOV SBUF, #'D' ;load SBUF=44H, ASCII
for 'D‘ ;copy accumulator into
▪ MOV SBUF, A SBUF
✔ When▪ MOV
a byteA,is SBUF ;copy
written SBUF itinto
in SBUF, is framed by 8051 with the start
accumulator
and stop bits and transferred serially via the TxD pin
✔ When the bits are received serially via RxD, it is deframed by 8051 by
eliminating the stop and start bits, making a byte out of the data
received, and then placing it in the SBUF
✔ Framing need not be done by programmer explicitly
SBUF Register
• The special function register SBUF is physically two registers.
✔ One is, write-only and is used to hold data to be transmitted
out
of the 8051 via TXD.
✔ The other is, read-only and holds the received data from
external sources via RXD.
• Both mutually exclusive registers have the same address 099H.
• SBUF is not bit addressable
TI and RI Flags
TI (transmit interrupt)
• When 8051 finishes the transfer of the 8-bit character, it raises
the TI flag to indicate that it is ready to transfer another byte
• TI bit is raised at the beginning of the stop bit

RI (receive interrupt)
• When the 8051 receives data serially via RxD, it places the
byte in the SBUF register then raises the RI flag bit to
indicate that a byte has been received and should be picked
up before it is lost
• RI is raised halfway through the stop bit
Programming the 8051 to transfer
character bytes serially
1. TMOD register is loaded with the value 20H, indicating the use of
timer 1 in mode 2 (8-bit auto-reload) to set baud rate
2. The TH1 is loaded with one of the value to set baud rate for serial
data transfer
3. The SCON register is loaded with the value 50H, indicating serial
mode 1, where an 8- bit data is framed with start and stop bits
4. TR1 is set to 1 to start timer 1
5. TI is cleared by CLR TI instruction
6. The character byte to be transferred serially is
written intoSBUF register
7. The TI flag bit is monitored with the use of instruction JNB TI,xx
to see if the character has been transferred completely
8. To transfer the next byte, go to step 5
Steps that 8051 goes through in
transmitting a character via TxD
1. The byte character to be transmitted is written into the SBUF
register
2. The start bit is transferred
3. The 8-bit character is transferred on bit at a time
4. The stop bit is transferred
✔ It is during the transfer of the stop bit that 8051 raises the TI
flag, indicating that the last character was transmitted
5. By monitoring the TI flag, we make sure that we are not
overloading
the SBUF
✔ If we write another byte into the SBUF before TI is raised, the
untransmitted portion of the previous byte will be lost
6. After SBUF is loaded with a new byte, the TI flag bit must be
forced to
0 by CLR TI in order for this new byte to be transferred
Importance of TI Flag
• By checking the TI flag bit, we know whether or not
the 8051 is ready to transfer another byte
• If we write a byte into SBUF before the TI flag
bit is raised, we risk the loss of a portion of the
byte being transferred
Programming the 8051 to receive
character bytes serially
1. TMOD register is loaded with the value 20H, indicating the use of
timer 1 in mode 2 (8-bit auto-reload) to set baud rate
2. The TH1 is loaded with one of the value to set baud rate for serial
data transfer
3. The SCON register is loaded with the value 50H, indicating serial
mode 1, where an 8- bit data is framed with start and stop bits
4. TR1 is set to 1 to start timer 1
5. RI is cleared by CLR RI instruction
6. The RI flag bit is monitored with the use of instruction JNB RI,xx
to see if the entire character has been received yet
7. When RI is raised, SBUF has the byte, its contents are moved into
a safe place
8. To transfer the next byte, go to step 5
Steps that 8051 goes through in
receiving a character via RxD
1. It receives the start bit
✔ Indicating that the next bit is the first bit of the character byte it is
about
to receive
2. The 8-bit character is received one bit at time
3. The stop bit is received
✔ When receiving the stop bit 8051 makes RI = 1, indicating that an
entire character byte has been received and must be picked up before
it gets overwritten by an incoming character
4. By checking the RI flag bit when it is raised, we know that a character
has been received and is sitting in the SBUF register
✔ We copy the SBUF contents to a safe place in some other register or
memory before it is lost
5. After the SBUF contents are copied into a safe place, the RI flag bit
must be forced to 0 by CLR RI in order to allow the next received
character byte to be placed in SBUF
✔ Failure to do this causes loss of the received character
Importance of RI Flag
• By checking the RI flag bit, we know whether or not
the 8051 received a character byte
• If we copy SBUF into a safe place before the RI flag
bit is raised, we risk copying garbage
Steps that 8051 goes through in
receiving a character via RxD
1. It receives the start bit
✔ Indicating that the next bit is the first bit of the character byte it is
about
to receive
2. The 8-bit character is received one bit at time
3. The stop bit is received
✔ When receiving the stop bit 8051 makes RI = 1, indicating that an
entire character byte has been received and must be picked up before
it gets overwritten by an incoming character
4. By checking the RI flag bit when it is raised, we know that a character
has been received and is sitting in the SBUF register
✔ We copy the SBUF contents to a safe place in some other register or
memory before it is lost
5. After the SBUF contents are copied into a safe place, the RI flag bit
must be forced to 0 by CLR RI in order to allow the next received
character byte to be placed in SBUF
✔ Failure to do this causes loss of the received character
Note: No need to use timers in case of Mode-0 and Mode-2 operation of
serial communication since timers do not control the baud rate.
Doubling the Baud Rate in 8051
• There are two ways to increase the baud rate of data transfer
✔ To use a higher frequency crystal
✔ To set the SMOD bit in the PCON register
• PCON register is an 8-bit register, whose MSB is SMOD
• When 8051 is powered up, SMOD is zero
• We can set it to high by software and thereby double the baud
rate
• PCON is not bit-addressable register. Hence, we cannot set
SMOD bit MOV A, This;place
directly. maya be
copydone as: in
of PCON
PCON ACC
SETB ;make D7=1
ACC.7 ;changing any other bits
MOV
Doubling the Baud Rate in
8051
 8051 Interrupts

■ An interrupt is an external or internal event that

disturbs the microcontroller to inform it that a device
needs its service.
A Microcontroller can serve various devices.
■ There are two ways to do that:
■ interrupts &
■ polling.
■ The program which is associated with the interrupt is
called the interrupt service routine (ISR) or interrupt
handler.
 Steps in executing an interrupt
■ Upon receiving the interrupt signal the
Microcontroller , finish current instruction and
saves the PC on stack.
■ Jumps to a fixed location in memory depending
on type of interrupt
■ Starts to execute the interrupt service routine
until RETI (return from interrupt)
■ Upon executing the RETI the microcontroller
returns to the place where it was interrupted.
 Interrupt Sources
■ Original 8051 has 6 sources of interrupts
■ Reset
■ Timer 0 overflow
■
■ Timer 1 overflow
■ External Interrupt 0
■ External Interrupt 1
Serial Port events (buffer full, buffer empty, etc)
■ Enhanced version has 22 sources
■ More timers, programmable counter array, ADC,
more external interrupts, another serial port (UART)
 Interrupt Vectors
■ Each interrupt has a specific place in code
memory where program execution (interrupt
service routine) begins.
■ External Interrupt 0: 0003h
■ Timer 0 overflow: 000Bh
■ External Interrupt 1: 0013h
■ Timer 1 overflow: 001Bh
■ Serial : 0023h
■ Timer 2 overflow(8052+) 002bh
 Interrupt Enable Register

■ Upon reset all Interrupts are disabled & do

not respond to the Microcontroller
■ These interrupts must be enabled by software
in order for the Microcontroller to respond to
them.
■ This is done by an 8-bit register called
Interrupt Enable Register (IE).
■ EA: Global enable/disable.
■ --- : Undefined.
■ ET2 : Enable Timer 2 interrupt.
■ ES : Enable Serial port interrupt.
■ ET1 : Enable Timer 1 interrupt.
■ EX1 :Enable External 1 interrupt.
■ ET0 : Enable Timer 0 interrupt.
■ EX0 : Enable External 0 interrupt.
 Enabling and disabling an
interrupt
❑ By bit operation

❑ Recommended in the middle of program

SETB EA SETB IE.7 ;Enable All
SETB ET0 SETB IE.1 ;Enable Timer0 ovrf
SETB ET1 SETB IE.3 ;Enable Timer1 ovrf
SETB EX0 SETB IE.0 ;Enable INT0
SETB EX1 SETB IE.2 ;Enable INT1
SETB ES ;Enable Serial port
SETB IE.4

❑ By Mov instruction

❑ Recommended in the first of program

MOV IE, #10010110B
 Interrupt Priorities
■ What if two interrupt sources interrupt at the same
time?
■ The interrupt with the highest PRIORITY gets
serviced first.
■ All interrupts have a power on default priority order.
1. External interrupt 0 (INT0)
2. Timer interrupt0 (TF0)
3. External interrupt 1 (INT1)
4. Timer interrupt1 (TF1)
5. Serial communication (RI+TI)
■ Priority can also be set to “high” or “low” by IP
reg.
Interrupt Priorities (IP) Register
--- --- PT2 PS PT1 PX1 PT0 PX0

IP.7: reserved
IP.6: reserved
IP.5: Timer 2 interrupt priority bit (8052 only)
IP.4: Serial port interrupt priority bit
IP.3: Timer 1 interrupt priority bit
IP.2: External interrupt 1 priority bit
IP.1: Timer 0 interrupt priority bit
IP.0: External interrupt 0 priority bit
 Interrupt Priorities Example
--- --- PT2 PS PT1 PX1 PT0 PX0

■ MOV IP , #00000100B or SETB IP.2 gives

priority order
1. Int1
2. Int0
3. Timer0
4. Timer1
5. Serial
■ MOV IP , #00001100B gives priority
order
1. Int1
2. Timer1
3. Int0
4. Timer0
5. Serial
 Interrupt inside an interrupt
--- --- PT2 PS PT1 PX1 PT0 PX0

■ A high-priority interrupt can interrupt a low-

priority interrupy
■ All interrupt are latched internally
■ Low-priority interrupt wait until 8051 has
finished servicing the high-priority interrupt