8086/8088
Microprocessor
p
and its pin
configuration
fi ti
REFERENCES:
1. MICROPROCESSORS AND INTERFACING
PROGRAMMING AND HARDWARE, SECOND
E D I T I O N , D . V . H A L L – C H A P T E R 7 , C H A P T E R 11
Basic Features
Pin Diagram
Minimum and Maximum modes
Description of the pins
Topics
Basic Features
8086 announced in 1978; 8086 is a 16 bit
microprocessor with a 16 bit data bus
8088 announced in 1979; 8088 is a 16 bit
microprocessor with an 8 bit data bus
Both
B th manufactured
f t d usingi Hi h
High-performance
f
Metal Oxide Semiconductor (HMOS) technology
Both contain about 29000 transistors
Both
B th are packaged
k d in
i 40 pin
i dual-in-line
d l i li
package (DIP)
8086/8088 Pin Diagrams
GND 1 40 VCC GND 1 40 VCC
AD14 2 39 AD15 A14 2 39 A15
AD13 3 38 A16/S3 A13 3 38 A16/S3
AD12 4 37 A17/S4 A12 4 37 A17/S4
AD11 5 36 A18/S5 A11 5 36 A18/S5
AD10 6 35 A19/S6 A10 6 35 A19/S6
AD9 7 34 BHE/S7 A9 7 34 SS0
AD8 8 33 MN/MX A8 8 33 MN/MX
AD7
AD6
9
10
8086 32
31
RD
HOLD
AD7
AD6
9
10
8088 32
31
RD
HOLD
AD5 11 30 HLDA AD5 11 30 HLDA
AD4 12 29 WR AD4 12 29 WR
AD3 13 28 M/IO AD3 13 28 IO/M
AD2 14 27 DT/R AD2 14 27 DT/R
AD1 15 26 DEN AD1 15 26 DEN
AD0 16 25 ALE AD0 16 25 ALE
NMI 17 24 INTA NMI 17 24 INTA
INTR 18 23 TEST INTR 18 23 TEST
CLK 19 22 READY CLK 19 22 READY
GND 20 21 RESET GND 20 21 RESET
BHE has no meaning on the 8088
and has been eliminated
Multiplex of Data and Address
Li
Lines in
i 8088
Address lines A0-A7
and Data lines D0-D7 GND
A14
1
2
40
39
VCC
A15
are multiplexed in
A13 3 38 A16/S3
A12 4 37 A17/S4
A11 5 36 A18/S5
8088. These lines are
A10 6 35 A19/S6
A9 7 34 SS0
l b ll d as AD0
labelled AD0-AD7.
AD7
A8 8 33 MN/MX
AD7
AD6
9
10
8088 32
31
RD
HOLD
◦ By multiplexed we mean
AD5 11 30 HLDA
AD4 12 29 WR
that the same physical
AD3 13 28 IO/M
AD2 14 27 DT/R
AD1 15 26 DEN
pin carries an address bit AD0
NMI
16
17
25
24
ALE
INTA
at one time and the data INTR
CLK
18
19
23
22
TEST
READY
bit another
th titime GND 20 21 RESET
Multiplex of Data and Address
Li
Lines in
i 8086
Address lines A0-A15 and Data lines D0-D15
are multiplexed in 8086. These lines are
labeled as AD0-AD15.
GND 1 40 VCC
AD14 2 39 AD15
AD13 3 38 A16/S3
AD12 4 37 A17/S4
AD11 5 36 A18/S5
AD10 6 35 A19/S6
AD9 7 34 BHE/S7
AD8 8 33 MN/MX
AD7
AD6
9
10
8086 32
31
RD
HOLD
AD5 11 30 HLDA
AD4 12 29 WR
AD3 13 28 M/IO
AD2 14 27 DT/R
AD1 15 26 DEN
AD0 16 25 ALE
NMI 17 24 INTA
INTR 18 23 TEST
CLK 19 22 READY
GND 20 21 RESET
Minimum-mode and Maximum-
Minimum- Maximum-
mode Systems
8088 and 8086 microprocessors
p
can be configured to work in
either of the two modes: the
minimum mode and the
GND 1 40 VCC
AD14 2 39 AD15
maximum mode AD13
AD12
3
4
38
37
A16/S3
A17/S4
Minimum mode:
AD11 5 36 A18/S5
AD10 6 35 A19/S6
Pull MN/MX to logic 1
AD9 7 34 BHE/S7
AD8 8 33 MN/MX
Typically smaller systems and
AD7
AD6
9
10
8086 32
31
RD
HOLD
contains a single microprocessor AD5
AD4
11
12
30
29
HLDA
WR
p since all control signals
Cheaper g for AD3 13 28 M/IO
memory and I/O are generated by
AD2 14 27 DT/R
AD1 15 26 DEN
the microprocessor. AD0
NMI
16
17
25
24
ALE
INTA
Maximum mode INTR
CLK
18
19
23
22
TEST
READY
Pull MN/MX logic 0 GND 20 21 RESET
Larger systems with more than one
processor (designed to be used
when
h a coprocessor (8087) exists
i t in
i Lost Signals in
the system) Max Mode
Minimum-mode and Maximum-
Minimum- Maximum-
mode Signals
GND 1 40 VCC
GND 1 40 VCC
AD14 2 39 AD15
AD14 2 39 AD15
AD13 3 38 A16/S3
AD13 3 38 A16/S3
AD12 4 37 A17/S4
AD12 4 37 A17/S4
AD11 5 36 A18/S5
AD11 5 36 A18/S5
AD10 6 35 A19/S6
AD10 6 35 A19/S6
AD9 7 34 BHE/S7
AD9 7 34 BHE/S7
AD8 8 33 MN/MX Vcc AD8 8
8086
33 MN/MX
GND
AD7
AD6
9
10
8086 32
31
RD
HOLD
AD7
AD6
9
10
32
31
RD
RQ/GT0
AD5 11 30 RQ/GT1
AD5 11 30 HLDA
AD4 12 29 LOCK
AD4 12 29 WR
AD3 13 28 S2
AD3 13 28 M/IO
AD2 14 27 S1
AD2 14 27 DT/R
AD1 15 26 S0
AD1 15 26 DEN
AD0 16 25 QS0
AD0 16 25 ALE
NMI 17 24 QS1
NMI 17 24 INTA
INTR 18 23 TEST
INTR 18 23 TEST
CLK 19 22 READY
CLK 19 22 READY
GND 20 21 RESET
GND 20 21 RESET
Min Mode Max Mode
RESET Operation results
CPU component Contents
Flags Cleared
Instruction Pointer 0000H
CS FFFFH
DS, SS and ES 0000H
Queue Empty
S0, S1 and S2 Signals
S2 S1 S0 Characteristics
Interrupt
0 0 0
acknowledge
0 0 1 Read I/O port
0 1 0 Write I/O port
0 1 1 Halt
1 0 0 Code access
1 0 1 Read memoryy
1 1 0 Write memory
1 1 1 Inactive
A17/S4, A16/S3 Address/Status
A17/S4 A16/S3 Function
0 0 Extra segment access
0 1 Stack segment access
1 0 C d segmentt access
Code
1 1 Data segment access
A19/S6, A18/S5 Address/Status
A18/S5: The status of the interrupt
p enable flag
g bit is
updated at the beginning of each cycle. The status of the
flag is indicated through this pin.
pin
A19/S6: When Low, it indicates that 8086 is in control of
the bus.
bus During a "Hold Hold acknowledge
acknowledge" clock period,
period the
8086 tri-states the S6 pin and thus allows another bus master
t take
to t k control
t l off the
th status
t t bus.
b
QS0 and QS1 Signals
QS1 QS0 Characteristics
0 0 No operation
0 1 First byte of opcode from queue
1 0 Empty the queue
1 1 Subsequent byte from queue
INTA
◦ Interrupt Acknowledge generated by the
microprocessor in response to INTR. Causes the
interrupt vector to be put onto the data bus.
bus
BHE
◦ Bus High Enable. Enables the most significant
d t bus
data b bit (D15-D8)
bits (D15 D8) during
d i a read
d or write
it
operation.
VCC/GND
◦ Power supply (5V) and GND (0V)
MN/MX
/
◦ Select minimum (5V) or maximum mode (0V) of
operation.
RQ/GT1 and RQ/GT0
◦ Request/grant pins request/grant direct
memory accesses (DMA) during maximum
mode
d operation.
ti
LOCK
◦ Lock output is used to lock peripherals off
the system. Activated by using the LOCK:
prefix on any instruction.
INTR (input)
Hardware Interrupt Request Pin
INTR is used to request a hardware interrupt.
It is recognized by the processor only when IF =
1 otherwise
1, th i it is
i ignored
i d (STI instruction
i t ti sets t this
thi
flag bit).
The request on this line can be disabled (or
masked) by making IF = 0 (use instruction CLI)
If INTR becomes high and IF = 1, 1 the 8086
enters an interrupt acknowledge cycle (INTA
becomes active) after the current instruction has
completed execution.
NMI (input) Non-Maskable
Interrupt line
The Non Maskable Interrupt input is
similar to INTR except that the NMI
interrupt does not check to see if the IF
flag bit is at logic 1.
This interrupt cannot be masked (or
disabled) and no acknowledgment is
required.
It should be reserved for “catastrophic”
events such as power failure or memory
e o s
errors.
8086 External Interrupt Connections
NMI - Non-Maskable Interrupt INTR - Interrupt Request
Programmable
NMI Requesting Interrupt Controller
Device (part of chipset)
(p p )
NMI
8086 CPU
Intel
INTR
Interrupt Logic 8259A
PIC
Divide Single
int into
Error Step
Software Traps
TEST (input)
The TEST pin is an input that is tested by
th WAIT instruction.
the i t ti
If TEST is at logic 0, the WAIT instruction
functions as a NOP.
If TEST is at logic 1, then the WAIT
instruction causes the 8086 to idle, until
TEST input becomes a logic 0.
This pin is normally driven by the 8087 co-
processor (numeric coprocessor).
Ready (input)
This input is used to insert wait states into
processor Bus Cycle.
Cycle
If the READY pin is placed at a logic 0 level,
the microprocessor enters into wait states
and remains idle.
If the READY pin is placed at a logic 1 level,
p
it has no effect on the operation of the
processor.
It is sampled at the end of the T2 clock
pulse
U
Usually
ll ddriven
i by
b a slow
l memory device
d i
HOLD (input)
The HOLD input is used by DMA controller
to request a Direct Memory Access (DMA)
operation.
If the HOLD signalg is at logic
g 1,, the
microprocessor places its address, data and
g impedance
control bus at the high p state.
If the HOLD pin is at logic 0, the
microprocessor works normally.
HLDA (output)
Hold Acknowledge Output
Hold acknowledge is made high to indicate
to the DMA controller that the processor has
entered hold state and it can take control
over the system bus for DMA operation.
8086 Memory Addressing
Data can be accessed from the memory in four
different ways:
y
• 8 - bit data from Lower (Even) address Bank.
• 8 - bit data from Higher (Odd) address Bank.
• 16 - bit data starting from Even Address.
• 16 - bit data starting from Odd Address.
1. Accessing 8
8--bit data from
Lower (Even) address bank :
The two bank memory module of 8086
based storage system requires one bus
bus-
cycle to read/write a data-byte.
To access a Byte of data in Low-bank,
valid address is provided via address pins
A1 to A19 together with A0=’0’ and
BHE= 1 .
BHE=’1’
2. Accessing 8
8--bit data from
Higher (Odd) address bank
Similarly to access a Byte of data in High-bank,
valid address in pins A1 to A19, A0 A0=’1’
1 and
BHE=’0’ are required to access the data
through D8 to D15 of the data
data-bus.
bus.
These signals disable the Low bank and enable
the High bank to transfer (in/out) data through
D8 to D15 of the data
data-bus
bus.
3. Accessing 16 - bit data
starting from Even Address.
For even-addressed (aligned) words, only
one bus-cycle
y is needed to access the
word, as both low and high banks are
activated at the same time using A0=’0’
and
d BHE=’0’
BHE ’0’
Note
N t that
th t during
d i thi bus-cycle,
this b l all
ll 16-bit
16 bit
data is transferred via D0 to D15 of the
data bus.
bus
4. Accessing 16 - bit data
starting from Odd Address.
For odd-addressed (unaligned) words
(with odd P.A of the LSB), two bus
bus-cycles
cycles
are required to access the Word-data.
During the 1st bus-cycle, odd addressed
LSB of the word is accessed from the
High-memory-bank via D8 to D15 of data
bus
During 2nd bus-cycle
bus cycle, P.A.
P A is auto
auto-
incremented to access the even address
MSB of the word from the Low bank via
D0 to D7.
Note that A0 and BHE signals are reset
(violet) accordingly to enable the required
memory bank.
b k
Direct Memory Access (DMA)
