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Q.1) Draw and explain the Reset functional diagram of PICI 18 Fxxxx [6] (Nov-Dec 2022)

The Reset function in a PIC18Fxxxx microcontroller is a critical component that ensures the device starts
operating correctly after power-up, or when a reset condition occurs. Below is an explanation of the Reset
functional diagram.
Reset Functional Diagram Explanation
The Reset mechanism in the PIC18Fxxxx microcontroller can be triggered by various conditions:
1. Power-On Reset (POR): This occurs when the power supply is first applied to the device. The POR
circuit ensures that the device starts in a known state, typically with all registers cleared or set to a
default state.
2. Brown-Out Reset (BOR): This reset occurs if the supply voltage drops below a certain threshold,
indicating that the power is not stable. The BOR circuit monitors the voltage and resets the
microcontroller to prevent erratic operation.
3. Master Clear (MCLR) Reset: This is an external reset triggered by pulling the MCLR pin low. It
provides a manual way to reset the microcontroller externally.
4. Watchdog Timer (WDT) Reset: If the Watchdog Timer is enabled and it is not cleared within a
specified time period, a reset occurs. This is used to recover from software malfunctions.
5. Software Reset: The microcontroller can be reset through software by setting specific bits in the
Special Function Registers (SFRs).
6. Stack Overflow/Underflow Reset: This reset occurs if the stack pointer goes beyond its allocated
limit, either overflow or underflow, ensuring that the stack operates within the defined range.
Reset Sequence:
1. Reset Source Detection: The microcontroller first detects the source of the reset (POR, BOR, MCLR,
WDT, etc.). This is done by checking various status bits in the Reset Control Registers.
2. Device Initialization: After a reset condition is detected, the microcontroller initializes all hardware
and software components to a predefined state. This includes clearing or setting registers to their
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default values.
3. Reset Vector: Once the initialization is complete, the microcontroller begins executing the program
from the reset vector, a predefined memory location where the program counter (PC) is set to start
execution.
4. Normal Operation: The microcontroller resumes normal operation until another reset condition
occurs.
Reset Functional Diagram Drawing:
 Top of the diagram: Shows different reset sources like POR, BOR, MCLR, WDT, Software Reset, Stack
Overflow/Underflow.
 Middle section: All reset sources converge into a "Reset Logic Block" which determines the type of
reset.
 Bottom section: The output of the Reset Logic Block connects to a "Reset Sequence and Vector," which
initializes the system and directs the program counter to the reset vector.

Q.2) Explain functions of ALU in PICI 18Fxxxx with example. [6] (Nov-Dec 2022) (May-June 2023)
MCU unit includes: Arithmetic Logic Unit (ALU), Registers, and Control Unit
Arithmetic Logic Unit (ALU)
• WREG (8)– working register (Accumulator)
8 bit Temporary holding register. Called as Accumulator.
Cannot be access Directly
used by many instructions as source of an operand.
Destination for the result of instruction execution.
• Status register -
Reflects result of instruction execution
Contains : arithmetic status of the ALU ( CY, Z, DC)
Reset Status, bank select bits for data memory
• Instruction decoder – when the instruction is fetched it goes into the ID
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Example
ADDWF F, d, a
Add WREG to File (Data) Reg.
Save result in W if d =0
Save result in F if d = 1

• The CPU fetches instructions from memory, decodes them, and passes them to the ALU for execution.
• The arithmetic logic unit (ALU) is responsible for adding, subtracting, shifting and performing logical
operations.
• The ALU operates in conjunction with:
– A general purpose register called W register
– And f register that can be any location in datalocation
– Literal embedded in the instruction code

Q.3) Draw and explain program memory organization of PIC 18F4550. [6] (Nov-Dec22/23) (May-June24)
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Address bus: 21-bit address bus for program memory addressing capacity: 2 MB of memory
Data bus: 16-bit instruction/data bus for program memory
The program memory organization of the PIC18F4550 microcontroller is structured to allow efficient access to
program instructions and data. The program memory is a Flash memory, meaning it can be electrically erased
and reprogrammed. Below is an explanation of the memory organization .
Program Memory Organization in PIC18F4550
1. Program Memory Size:
o The PIC18F4550 microcontroller has 2MB of program memory space.
o This memory is divided into addressable locations, with each location being 16 bits wide,
allowing the storage of 16-bit instructions.
2. Memory Ranges and Banks:
o The program memory is divided into two primary address ranges:
 0000h to 7FFFh: This is the main program memory area.
 8000h to FFFFh: Reserved for special purposes, such as configuration words and vector
tables.
3. Reset Vector:
o The Reset Vector is located at the address 0000h. This is where the microcontroller begins
execution after a reset. The first instruction in the user program is typically located here.
4. Interrupt Vector:
o Interrupt vectors are located in the range 0008h to 0018h.
 0008h: High-priority interrupt vector.
 0018h: Low-priority interrupt vector.
5. Configuration Words:
o Configuration Words are located at 300000h to 30000Dh. These control various aspects of the
microcontroller, such as oscillator settings, watchdog timer settings, and code protection.
6. User Flash Memory:
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o The main program memory from 0000h to 7FFFh is used for user program storage. This is
where the main application code resides.
7. Stack:
o The PIC18F4550 has a hardware stack that is used to store return addresses during function
calls and interrupts. The stack is 31 levels deep, and each level is 21 bits wide.
8. Accessing Program Memory:
o Program memory is accessed via the Program Counter (PC), which is 21 bits wide. This allows
access to a large address space, though not all of it is used in this specific microcontroller model.
Program Memory Organization Diagram:
The diagram would typically be represented as follows:
 Top Section:
o The address 0000h marked as the Reset Vector.
o Below it, addresses 0008h and 0018h marked as High-priority Interrupt Vector and Low-
priority Interrupt Vector respectively.
 Middle Section:
o The main program memory range from 0000h to 7FFFh. This is where the user program is
stored.
 Lower Section:
o The address range 8000h to FFFFh labeled as reserved or unused.
o Below it, addresses 300000h to 30000Dh for Configuration Words.
 Stack:
o Off to the side, or in a separate section, showing the stack with 31 levels.
This diagram would help you visualize the different areas within the program memory and how they are used
in the PIC18F4550 microcontroller.

Q.4) Explain RUN mode of PIC 18F4550. [6] (Nov-Dec 2022)

 There are three categories of power-managed modes:
1. Run modes, 2)Idle modes, 3)Sleep mode
These categories define which portions of the device are clocked and sometimes, what speed.
The Run and Idle modes may use any of the three available clock sources (primary, secondary or internal
oscillator block); the Sleep mode does not use a clock source.
In the Run modes, clocks to both the core and peripherals are active. The difference between these modes is the
clock source.
A. PRI_RUN MODE:
This is also the default mode upon a device Reset. It is the normal, full-power execution mode of the
microcontroller. Depending on the primary clock source the IOFS bit may be set in Oscillator Control Register.
B. SEC_RUN MODE:
The SEC_RUN mode is the compatible mode to the “clock switching” feature offered in other PIC18 devices.
In this mode, the CPU and peripherals are clocked from the Timer1 oscillator.
This gives users the option of lower power consumption while still using a high-accuracy clock source.
C. RC_RUN MODE:
In RC_RUN mode, the CPU and peripherals are clocked from the internal oscillator block using the INTOSC
multiplexer; the primary clock is shut down. When using the INTRC source, this mode provides the best power
conservation of all the Run modes while still executing code. It works well for user applications which are not
highly timing sensitive or do not require high-speed clocks at all times.

Q.5) State Features of PIC 18F4550 [6] (Nov-Dec 2022/2023) (May-June 2023)
The PIC18F4550 is a popular microcontroller from Microchip Technology, known for its versatility and robust
feature set. Below are the key features of the PIC18F4550:
1. CPU and Memory:
 High-Performance RISC CPU:
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o 16-bit wide instructions and 8-bit wide data paths.

o Up to 12 MIPS (Million Instructions Per Second) at 48 MHz operation.
 Program Memory:
o 32KB Flash memory for storing code.
 Data Memory:
o 2KB SRAM (Static RAM) for general-purpose data storage.
 EEPROM:
o 256 Bytes of EEPROM for non-volatile data storage.
2. Operating Voltage:
 Operating Voltage Range:
o 2.0V to 5.5V.
3. USB 2.0 Interface:
 Integrated USB 2.0 Full-Speed Interface:
o Supports both Host and Device modes.
o Up to 12 Mbps data transfer rate.
o 1 KB dual access RAM for USB communication buffering.
4. Oscillator Options:
 Internal Oscillator:
o 31 kHz to 8 MHz internal oscillator options.
o Up to 48 MHz with external oscillator and PLL (Phase-Locked Loop).
5. I/O Ports:
 Digital I/O:
o 35 I/O pins, individually configurable as input or output.
o High-current sink/source capability on many pins.
 Analog-to-Digital Converter (ADC):
o 13-channel, 10-bit ADC.
o Conversion time of 2.4 μs per channel.
6. Timers:
 Timers:
o 1 x 8-bit Timer (TMR0).
o 3 x 16-bit Timers (TMR1, TMR2, TMR3).
7. Communication Modules:
 USART:
o Supports RS-232, RS-485 communication protocols.
 SPI/I2C:
o Master and Slave modes available for SPI.
o I2C Master/Slave functionality.
 USB:
o Integrated Full-Speed USB 2.0 Module.
8. CCP/ECCP Modules:
 Capture/Compare/PWM (CCP) Modules:
o 2 x CCP modules for PWM generation and other timer-related functions.
 Enhanced CCP (ECCP):
o Includes additional features such as dead-band control, auto-shutdown, and auto-restart.
9. Watchdog Timer:
 Watchdog Timer (WDT):
o Programmable period with an internal RC oscillator for safety-critical applications.
10. Power Management Features:
 Power-Saving Modes:
o Idle and Sleep modes to reduce power consumption.
 Brown-Out Reset (BOR):
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o Resets the microcontroller if the supply voltage drops below a threshold.

 Power-On Reset (POR) and Power-up Timer (PWRT):
o Ensures proper startup when power is applied.
11. In-Circuit Serial Programming (ICSP):
 ICSP Capability:
o Allows programming and debugging directly on the circuit board without removing the
microcontroller.
12. In-Circuit Debugging (ICD):
 ICD Support:
o Integrated debugging support for real-time code analysis.
13. Package Options:
 Available in Various Packages:
o PDIP, QFN, and TQFP packages with different pin counts.
These features make the PIC18F4550 suitable for a wide range of applications, including embedded systems,
USB devices, communication modules, and industrial control systems.

Q.6) Draw and explain the data memory organization of PICI 18Fxxxx. [6] (Nov-Dec 22/23) (May-June 23/24)

The data memory organization of the PIC18Fxxxx microcontroller family, including models like the
PIC18F4550, is designed to efficiently handle data storage and manipulation during program execution. This
memory is divided into several sections, each with a specific purpose. Below, I'll explain the data memory
organization .
Data Memory Organization in PIC18Fxxxx
1. General-Purpose Registers (GPR):
o The General-Purpose Registers are used to store temporary data and variables during program
execution.
o These registers are located in the data memory, starting from a specific address, depending on
the bank selected.
2. Special Function Registers (SFR):
o The Special Function Registers control the operation of the microcontroller. These registers are
mapped to specific memory locations and are used to configure the I/O ports, timers, ADCs, and
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other peripherals.
o SFRs are usually located at the beginning of the memory map.
3. Banked Memory:
o The data memory in PIC18Fxxxx microcontrollers is divided into banks to efficiently utilize the
available memory space.
o Each bank contains both GPRs and SFRs.
o The bank is selected using the Bank Select Register (BSR), which allows access to a specific
section of the data memory.
o The machine code for a PIC18 instruction has only 8 bits for a data memory address which
needs 12 bits. The Bank Select Register (BSR) supplies the other 4 bits.
o We need to use access bank letter a=1, ( Bay default a=0, which means GPRAM and SFR are
accessible
o BSTR is 8 bit register and Part of SFR [upper 4 bits are ignored and lower 4 bits are used for
bank select
o Upon power-on reset BSR=0; access GP RAM – [00-FF], and SFR [F00-FFF]

4. Access Bank:
o To simplify access to frequently used registers, an "Access Bank" is provided. This bank consists
of the first 128 bytes of memory from Bank 0 (SFRs) and the last 128 bytes from the last bank
(GPRs).
o The Access Bank allows instructions to access certain registers without explicitly specifying the
bank, reducing the code complexity.
o Consists of two parts:
1. The first 128 bytes from Bank 0 (SFRs).
2. The last 128 bytes from the highest bank (GPRs).
3. If a=0; the data memory address is between 0x000–0x07F or between 0xF80 –0xFFF,
(ignore BSR).
4. if a=1; data memory address is between 0x080 – 0xF7F, assume the ‘a’ bit is a ‘1’ (use
the BSR).
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5. Indirect Addressing:
o The PIC18Fxxxx microcontrollers support indirect addressing, which allows data to be accessed
through a pointer. This is done using File Select Registers (FSRs) and the Indirect Data Memory
Access Register (INDF).
o FSRs act as pointers to any location in the data memory, while INDF provides access to the data
at the address pointed to by the FSR.
o 3 File Select Registers (FSR) as a pointer to the data memory location that is to be read or
written.

Q.7) Describe operation of PIC18F4550 microcontroller with block diagram. [6] (Nov-Dec 2023)

The PIC18F4550 microcontroller operates by executing instructions stored in its program memory. It interacts
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with various peripherals, processes input data, performs computations, and controls outputs according to the
embedded firmware. The microcontroller's operation can be broken down into several key functional blocks:
1. Central Processing Unit (CPU):
o The CPU is the core of the microcontroller, where all processing and decision-making occur.
o It fetches instructions from the program memory, decodes them, and then executes them.
o The CPU manages data flow between the various peripherals, memory, and I/O ports.
2. Program Memory:
o This is a non-volatile memory (Flash) that stores the program code.
o The program memory holds up to 32KB of instructions, which the CPU fetches and executes.
3. Data Memory:
o The data memory consists of General-Purpose Registers (GPRs) and Special Function Registers
(SFRs).
o GPRs are used for temporary data storage, while SFRs control the operation of peripherals and
the microcontroller's core.
4. Oscillator and Clock Circuit:
o The oscillator provides the clock signal that drives the operation of the microcontroller.
o The PIC18F4550 supports multiple oscillator configurations, including internal and external
oscillators with a PLL (Phase-Locked Loop) for frequency multiplication.
5. BUS:
o Address bus: 21-bit address bus for program memory addressing capacity: 2 MB of memory
12-bit address bus for data memory addressing capacity: 4 KB of memory
o Data bus: 16-bit instruction/data bus for program memory 8-bit data bus for data memory
6. I/O Ports:
o The microcontroller has several I/O ports (PORTA, PORTB, etc.) that can be configured as digital
input or output.
o These ports interface with external devices like sensors, switches, LEDs, and more.
7. Timers and Counters:
o The microcontroller includes multiple timers (Timer0, Timer1, Timer2, etc.) that can be used for
timing operations, generating delays, and creating PWM signals.
o Timers can be 8-bit or 16-bit and can operate in different modes, including Timer, Counter, and
PWM modes.
8. Analog-to-Digital Converter (ADC):
o The PIC18F4550 has a 10-bit ADC with multiple input channels.
o The ADC converts analog signals from sensors or other analog sources into digital values that
the CPU can process.
9. USART, SPI, and I2C Modules:
o These are communication modules that allow the microcontroller to interface with other
devices.
o USART: Used for serial communication (RS-232/RS-485).
o SPI/I2C: Used for synchronous serial communication with peripherals like EEPROMs, sensors,
and other microcontrollers.
10. USB Interface:
o One of the standout features of the PIC18F4550 is its integrated USB 2.0 Full-Speed interface.
o This allows the microcontroller to communicate with a PC or other USB host devices, supporting
data transfer rates up to 12 Mbps.
11. Interrupt Controller:
o The microcontroller supports multiple interrupt sources, including external interrupts, timer
interrupts, and peripheral interrupts.
o The interrupt controller manages these interrupts, allowing the CPU to respond to critical
events promptly.
12. Power Management:
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o The PIC18F4550 has various power-saving modes like Sleep and Idle to reduce power
consumption during low activity periods.
o The Brown-Out Reset (BOR), Watchdog Timer (WDT), and Power-On Reset (POR) enhance the
reliability of the microcontroller.
13. In-Circuit Serial Programming (ICSP):
o ICSP allows the microcontroller to be programmed or reprogrammed while installed in a circuit,
facilitating development and debugging.

Q.8) Explain the POR and BOD modes of reset in PIC18F4550. [6] (Nov-Dec 2023)
In the PIC18F4550 microcontroller, the Power-On Reset (POR) and Brown-Out Detect (BOD) are two essential
reset modes that ensure the microcontroller starts and operates reliably under varying power conditions.
These mechanisms help protect the microcontroller from improper startup and operation due to power
fluctuations.
POR Power-on Reset
 The Power-On Reset (POR) ensures that the microcontroller starts in a known and stable state when
power is first applied.
 When the device is powered on, the POR circuit generates a reset signal, which holds the
microcontroller in a reset state until the supply voltage (VDD) reaches a stable and sufficient level for
reliable operation.

Operation:
 Upon application of power, the POR circuit continuously monitors the supply voltage (VDD).
 When VDD rises above a certain threshold level (usually around 1.5V), the POR circuit triggers the reset
signal.
 This reset signal is maintained for a predefined duration to ensure that VDD has stabilized and that all
internal circuitry has settled.
 Once this time elapses and VDD is stable, the POR circuit releases the reset, allowing the
microcontroller to begin executing the code from the reset vector, typically located at memory address
0000h.

BOD Brown-out detection

Mostly all microcontrollers have built in Brown-out detection(BOD) circuit, which monitors supply
voltage level during operation. BOD circuit is nothing more than comparator, which compares supply
voltage to a fixed trigger level.

Operation:
 During operation, the BOD circuit continuously monitors VDD.
 If VDD drops below the BOD threshold (which can be configured using configuration bits in the
microcontroller), the BOD circuit generates a reset signal.
 This reset ensures that the microcontroller is halted, preventing it from executing potentially corrupted
or erroneous instructions.
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 The microcontroller remains in reset until VDD rises back above the BOD threshold and stabilizes.
 Once VDD stabilizes, the microcontroller resumes normal operation, typically restarting the program
from the reset vector.
CONFIG2L Configuration Register for Reset Voltage (0x300002)(Optional we can also add in answer)
 Used to provide stable voltage and clock frequency during reset function, PWRT provides fixed delay for
stabilizing the voltage source at required value.

 Bit 0: PWRTN : Power-up Timer Enable Bit

1=Enabled,
0= Disabled
 Bit 1-2 : BOREN: Brown-out Reset Enable Bit. 1=Enabled,
0= Disabled
 Bit 4-3 : BORV1:BORV0 Brown-out reset voltage bits
 11=VBOR set to 2.0V
10=VBOR set to 2.7V
01=VBOR set to 4.2V
00=VBOR set to 4.5V
 Bit 5 : Ref Enable
 Bit 6-7 : Unused read as 0.

Q.9) Explain the flag structure (PSW) of PIC18F4550 in detail. [6] (Nov-Dec 2022) (May-June 2024)
Flags in Status Register
It is an 8-bit register referred as flag registers and all are conditional

• C (Carry Flag)
– Set when an addition or subtraction generates a carry out of B7 Bits (unsigned Nos.)
• DC (Digit Carry Flag) (Half Carry)
– Set when carry generated from B3 to B4 in an BCD arithmetic operation ( Addition or
Subtraction)
• Z (Zero Flag)
– It reflects the result of arithmetic or logic operations. If result =0, Z=1 and if result ≠0, Z=0
• OV (Overflow Flag)
– Set when result of an operation of signed numbers goes beyond 7-bits- used to represent the
errors { carry from B6 to B7 but no carry out of B7[C=0];Carry out from from B7[C=1]}
• N (Negative Flag)
– Binary representation of signed No. It is the reflection of the result of an arithmetic/logic
operation if Result B7=0 , No. is Positive , if Result B7=1 , No. is negative

Q.10) Draw and explain the block schematic of PIC18F4550 MCU unit. [6] (May-June 2023)
MCU unit includes: Arithmetic Logic Unit (ALU), Registers, and Control Unit
Arithmetic Logic Unit (ALU)
• Working Register (W):
8 bit Temporary holding register. Called as Accumulator.
Cannot be access Directly
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used by many instructions as source of an operand.

Destination for the result of instruction execution.
• Status Register:
Reflects result of instruction execution
Contains : arithmetic status of the ALU ( CY, Z, DC)
Reset Status, bank select bits for data memory
• Instruction decoder – when the instruction is fetched it goes into the ID

Registers
• Program Counter (PC) : 21-bit register functions as a pointer to program memory during program
execution, It is special function register
• Stack Pointer (SP): 5-bit register used to point to the stack 31 registers used for temporary storage of
memory addresses during execution of a program
• BSR: Bank Select Register (0 to F) : 4-bit Register
Provides upper 4-bits of 12-bit address of data memory
• FSR: File Select Registers – uses indirect addressing (INDF), Not a physical register
FSR0, FSR1, and FSR2
FSR: composed of two 8-bit registers (FSRH and FSRL)
Used as pointers for data registers bank
Holds 12-bit address of data register
• Table Pointer : 21-bit register used as a memory pointer to copy bytes between program memory and
data registers
Control Unit :
• Provides timing and control signals to various Read and Write operations Control signals : Read and
Write

Q.11) Explain the criteria for choosing PIC18F184550 Microcontroller. [6] (May-June 2023)
Criteria for choosing PIC18F184550 Microcontroller
A. Meeting Computing Needs of Task at Hand efficiently and Cost Effectively
1. Data Handling Capacity- Bits, Nibble Bytes, Words, Double words, Quad Words etc
2. Speed --- Depends on Clock
3. Amount of RAM/ ROM/ EPROM/ Flash/ Static
4. Number of I/O pins, Timers – All SFRS
5. Power consumption – Based on the modes
6. Packaging – 40 PIN DIP,/ QFP/ other– Important – Space, assembly, Prototyping the end Product
7. Added features like ADC/ DAC/ CCP, Bus support like CAN, SPI, I2C, USB.
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8. Watchdog timer, Timer modes, Data EEPROM etc.

9. Easy to upgrade --Higher Performances or low power operations
B. Availability of Software and Hardware Development Tools
1. Assembler
2. Compilers – Code efficient C language
3. Debuggers
4. Emulators
5. Technical Support
C. Wide Availability and Reliable Sources of Microcontrollers
1. More important than previous two – Since most diversified suppliers are available to cell same product
2. Motorola, Atmel, Zilog and Microchip Technology has massive dedicated resources for supply
3. All the products are Stable, Matured and single sourced.

Q.12) Compare P1C10, PIC 12, PIC 16 and PIC 18. [8] (May-June 2024)

Q.13) Draw and explain the architecture of PIC 18F4550.[8] (May-June 2024)
The PIC18F4550 is a microcontroller from Microchip Technology, part of the PIC18 family. It features a 14-bit
instruction set architecture, which is known for its ease of use and robustness. Here's an overview of its
architecture:
Architecture Diagram
1. CPU (Central Processing Unit):
o Program Counter (PC): Holds the address of the next instruction to execute.
o Instruction Register (IR): Holds the current instruction being executed.
o Status Register (SR): Contains flags that indicate the status of the CPU, such as carry, zero, and
overflow.
2. Memory:
o Flash Program Memory: Stores the executable code. It is non-volatile, meaning it retains data
even when power is off.
o EEPROM Data Memory: Used for non-volatile data storage, such as configuration settings.
o RAM Data Memory: Provides volatile memory for data storage during execution.
3. I/O Ports:
o Port A, Port B, Port C, Port D, and Port E: These are general-purpose input/output ports for
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interfacing with external devices. Each port can be configured as input or output.
4. Timers:
o Timer0, Timer1, Timer2: Used for time-related functions, such as generating delays or
counting events.
5. ADC (Analog-to-Digital Converter):
o Converts analog signals to digital values for processing.
6. USART (Universal Synchronous Asynchronous Receiver Transmitter):
o Used for serial communication, allowing data transfer between the microcontroller and other
devices.
7. USB Controller:
o Provides USB connectivity for communication with external devices.
8. Interrupt Controller:
o Manages interrupts, allowing the microcontroller to respond to external events or changes in
status.