COMSATS Institute of Electrical Engineering

Information Technology Department

February, 2018

Digital Logic Design

Course code: EEE-241 (3+1)

Prerequisites:

Basics knowledge of Physics and mathematics

Course Instructor: Engr. Khawaja Fahad Masood

E-mail: fahadmasood@ciit.net.pk

Office: Z-Block, Room 316

Course Catalog Description:

Introduction to Digital Computer and Systems, Number Systems, Binary Arithmetic,

Boolean Algebra, Algebraic Manipulation, Canonical and Standard Form &
Conversions, Logical Operations and Gates, Simplification of Functions, Karnaugh
Map Methods, Two Level Implementations, Don’t Care Conditions, Prime Implicants,
Combinational Logic Design, Arithmetic Operations and Circuits, Analysis Procedures,
Multilevel NAND/NOR Circuits, Decoders, Encoders, Multiplexers, Demultiplexers,
Memory Types, Read Only Memory, Random Access Memory, Programmable Logic
Array (PLA), Sequential Logic, Flip-Flops, Clocked Sequential Circuits, State Machine
Concept, Design of Sequential Circuits using State Machines, Counters and their
Design, Synchronous Counters, Asynchronous Counters, Shift Registers etc.

Textbook(s):

1. M. Morris Mano & Charles R. Kime, Logic and Computer Design Fundamentals (2nd
Edition Updated, Prentice Hall, 2000)

Reference Books
1. Thomas L. Floyd, Digital Fundamentals (7th Edition)

1
Lab Manual
Manually updated and printed on campus in every semester
Course learning objectives

Course Learning objectives (CLO):

1) To introduce students with basic gates and Boolean algebra on hardware

2) To explain how to implement Boolean expression and logic diagrams on hardware and software.
3) To optimize different circuits using K-map.
4) To design the different combinational circuits on the logic trainer and simulation software.
5) To realize different sequential circuits on using flip flops the logic trainer and simulation
software.
6) To design different digital systems using registers and counter.

Course Contribution to Engineering:

Students will be able to have a hands-on experience of making different digital circuits. Also, they will
have an experience of designing different combinational and sequential circuits on the Electronic
workbench tool.

Laboratory Resources:

The DLD lab in Z block have all the required resources to facilitate the needs of this
course. These include specifically designed trainers and all the relevant ICs.

Course Schedule:

3 Credit hours/week

One laboratory session/week (3 hours/session)

Assessment Plan:

Lab work Lab reports (12) 25%

2 Lab sessional 25%
Terminal exam 50%
Total (lab) 100%
Final marks Theory marks * 0.75 + Lab marks * 0.25

2
 LAB REPORT EVALUATION RUBRICS

Affective Level Rubrics

Criteria Poor Good Very Good Excellent PLOs
Did not complete Reasonably tried Completed all the Completed all the
Professional ethics (Task dressing behavior)

the given to complete the given tasks by given tasks by

experimental task given task by himself while himself without
by him/herself. himself. Serious taking help from taking much help
Non-serious attitude while a the instructor. from the instructor.
attitude while a lab lab is being Serious attitude Very serious
is being conducted. conducted. Not while a lab is attitude while a lab
Absent in the class. willing to explore being conducted. is being conducted.
Didn’t submit engineering tasks. Willing to explore Eager to learn and
CL0-1

PLO -8
A1

report. Student has Attend lab after 1- engineering tasks. explore engineering
(Ethics)
very ordinary hour class start. Attend lab within tasks. Attend lab on
dressing and is not Submit report 30 minutes class time. Submit report
aware of manners. after a week. start. Submit on a same day
Student has good report a day after. practical work
dressing. Student has good done. Student has
dressing and is very good dressing
aware of lab and is aware of lab
manners. manners and has a
good conduct.
Total
point

Total Points Earned = Lab Performance Grade

20

Psychomotor Level Rubrics

Criteria Poor Good Very Good Excellent PLOs

3
Task/Practical Implementation
Student can
Student
complete all
Student shows no Student can completed all
practical tasks
response to complete partial practical tasks
assigned with
assigned task. practical tasks assigned
less error. Used
CLO-2

Participation was assigned with without error. PLO-3

P1

time pretty well.

minimal, OR more errors. Did Used time well (Investigation)
Stayed focused
student was the lab but did in lab and
on the
hostile about not appear very focused
experiment
participating. interested. attention on the
most of the
experiment.
time.

Uses equipment Uses tools, Uses tools, Uses tools,

and materials with equipment and equipment and equipment and
limited materials with materials with materials with
competence. Had some considerable a high degree
to be asked by competence. competence. of competence.
teacher to Had to be Good job on Outstanding
equipment. Did reminded using job while
not clean up area. sometimes to equipment. utilizing
Equipment Handling

Requires constant return equipment Returned all equipment.

reminders to and related equipment Used and
return equipment. materials. appropriately. returned all
CLO-3

PLO-5
Moreover, Moreover, Moreover, equipment and
(Tool Usage)
P2

student’s work student’s work student’s work related

area while area while area while materials
utilizing utilizing utilizing appropriately
equipment in the equipment in the equipment in and
lab is not lab is organized. the lab is responsibly.
organized at all. organized. Student’s work
area in the lab
is well
organized
while utilizing
equipment.

4
 Fails to Able to Able to Able to
understand the understand the simulate simulate
logic. Unable to task but have correctly correctly
Simulate. Not able few simulation without any without any
to run a errors. Most logic errors but logic errors and
simulation. Not variables are displays displays
even able to clearly described irrelevant required
Simulation

understand the with most outputs. Can outputs. All

CLO-4

task. There is no relevant details. simulate by variables and PLO-5

P2

documentation/rep There is no using eleventh controls are (Tool Usage)

ort. Unable to documentation/r logics. There is clearly
explain eport. Try to documentation/r described with
simulation. explain eport. Can all relevant
simulation. explain details. Report
simulation is highly
organized with
additional
information.
Total
point

Total Points Earned = Lab Performance Grade 60

Cognitive Level Rubrics

Criteria Poor Good Very Good Excellent PLOs
No response/task Demonstrates Establishes Demonstrates
not attempted. little considerable complete
Student generally understanding understanding understanding
did not know of the of the of the
Measurement Techniques

how to use a measuring measuring measuring

measuring technique. technique. All technique. All
instrument. Many requirements requirements
requirements of of task are of task are
CLO-5

PLO-5
C3

task are missing included in the included in the

(Tool usage)
from the response. response.
response. Student Student have
Student generally know full grip on
generally how to use a how to use a
somehow know measuring measuring
how to use a instrument. instrument.
measuring
instrument.
Total
point

Total Points Earned = Lab Performance Grade 20

5
 MAPPING OF CLOs AND PLOs
Course Learning
CLOs CLOs PLOs Level %age
Outcomes
To evaluate the behavior
CLO-1 Professional ethics and attitude of the PLO-8 A1 100%
student
To follow the instrument
Task/Practical
CLO-2 manual to complete a PLO-3 P1 30%
Implementation
measurement task.
To able to use suitable
equipment and tools
To evaluate the ability to
apply bread board
Equipment handling PLO-5 P2
CLO-3 techniques, design and 40%
C2
construction of the
circuit should be
carefully planned.

CL0 4 To evaluate the ability to

simulate the design
Simulation PLO -5 P2 30%
correctly

To be able to report
CLO-5 relevant theory as
Measurement Techniques instructed in the PLO-10 C3 100%
assigned task. PLO10

PLO11

PLO12
PLO1

PLO2

PLO3

PLO4

PLO5

PLO6

PLO7

PLO8

PLO9

CLOs\
PLOs

CLO1 A1

CLO2 P1

CLO3 P2

CLO4 P2

CLO 5 C3

Weightage

6
 AFFECTIVE COGNITIVE PSYCHOMOTOR
20% 20% 60%

PLOs COVERAGE
PLOs 1 2 3 4 5 6 7 8 9 10 11 12
COVERAGE √ √ √

CLOs Assessment Mechanism Overall Grading

Criteria % % % %
Policy
Lab 25%
Lab Experiments 1 40 20 30 Experiments
0
Lab Project 1 40 20 30 Sessional-1 10%
0 Sessional-2 15%
Sessional-1-OBE 1 40 20 30 Final 50%
0
Sessional-2-OBE 1 40 20 30
0
Final 1 40 20 30
0
Mapping Of CLOs To Lab Experiments of digital logic design.

Sr. Lab Course Learning Outcomes (CLOs)

No Experiment
Tyoes CLO CLO CLO CLO CLO
. Title
(1) (2) (3) (4) (5)

Introduction to electronic
1
workbench and logic trainer √ √ √

2
Basic logic gates (AND, OR, NOT) √ √ √ √ √
3
Boolean analysis of logic circuits √ √ √ √ √
Boolean algebra and simplification
4 √ √ √ √ √
Typical labs

of Boolean expressions

5
Universal gates √ √ √ √ √
6
Adders and subtractors √ √ √ √ √
7
Decoders √ √ √ √ √
8
Multiplexer √ √ √ √ √
9
Flip-flops √ √ √ √ √
1
0 Synchronous sequential circuits √ √ √ √ √
1 Ope
1 n Counters √ √ √ √ √
end
1
2
ed Registers √ √ √ √ √
labs

7
1 Semester Project
3 √ √ √ √ √