Logic Families
Introduction
Logic Family Definition
• A circuit configuration or approach used to
produce a type of digital integrated circuit.
• Consequence: different logic functions,
when fabricated in the form of an IC with
the same approach, or in other words
belonging to the same logic family, will have
identical electrical characteristics.
• the set of digital ICs belonging to the same
logic family are electrically compatible with
each other
2
Common Characteristics of the
Same Logic Family
• Supply voltage range, speed of response,
power dissipation, input and output logic
levels, current sourcing and sinking
capability, fan-out, noise margin, etc.
• Consequence: choosing digital ICs from
the same logic family guarantees that
these ICs are compatible with respect to
each other and that the system as a
whole performs the intended logic
function. 3
Types of Logic Family 1
• The entire range of digital ICs is fabricated
using either bipolar devices or MOS devices
or a combination of the two.
• Bipolar families:
– Diode logic (DL).
– Resistor transistor logic (RTL).
– Diode transistor logic (DTL).
– Transistor Transistor logic (TTL).
– Emitter Coupled Logic (ECL), also known as
Current Mode Logic(CML).
– Integrated Injection logic (I2L). 4
Types of Logic Family 2
• MOS families:
– PMOS family (using P-channel MOSFETs)
– The NMOS family (using N-channel
MOSFETs)
– The CMOS family (using both N- and P-
channel devices).
– The Bi-MOS logic family uses both bipolar
and MOS devices.
5
DL Example
6
RTL Example
7
DTL Example
8
TTL Subfamilies
9
CMOS Sub families
• 4000A
• 4000B, 4000UB,
• 54/74C, 54/74HC, 54/74HCT, 54/74AC and
54/74ACT(TTL pin compatible)
10
Noise MARGIN
11
12
13
NMOS Transistors in Series/Parallel Connection
Transistors can be thought as a switch controlled by
its gate signal
NMOS switch closes when switch control input is high
A B
X Y Y = X if A and B
A
B
X Y Y = X if A or B
Source : Jan Rabaey
PMOS Transistors in Series/Parallel Connection
PMOS switch closes when switch control input is low
A B
X Y Y = X if A and B = A+B
A
B Y = X if A or B = AB
X Y
Source : Jan Rabaey
Static Complementary MOS Circuits
Structure of CMOS
VDD
In1
PMOS only
In2 PUN
InN
F(In1,In2,…InN)
In1
In2 PDN
NMOS only
InN
Pull-Up Network (PUN) and Pull-Down Network
(PDN) are dual logic networks consisting of MOS
transistors in series/parallel connection
Source : Jan Rabaey
Example: 2-input NAND
Source : Jan Rabaey
Example: 2-input NOR
Outputis in inverting form i.e. F (.......)
Source : Jan Rabaey
Design CMOS logic gates for the following functions:
a. Z = ~(A.B.C.D)
b. Z = ~(A+B+C+D)
c. Z = ~(((A.B.C)+D))
d. Z = ~((((A.B)+C).D))
e. Z = ~((A.B)+C.(A+B))
nMOS Transistor Terminal Voltages
Mode of operation depends on Vg, Vd, Vs Vg
Vgs = Vg – Vs + +
Vgd = Vg – Vd Vgs Vgd
- -
Vds = Vd – Vs = Vgs – Vgd
Vs Vd
- +
Vds
Source and drain are symmetric diffusion terminals
By convention, source is terminal at lower voltage
Hence Vds 0
nMOS body is grounded. First assume source is 0 too.
Three regions of operation
Cutoff
Linear
Saturation
nMOS in cutoff operation mode
No channel
Ids = 0
nMOS in linear operation mode
Channel forms
Current flows from D to S
e- from S to D
Ids increases with Vds
Similar to linear
resistor
nMOS in Saturation operation mode
Channel pinches off
Ids independent of Vds
We say current saturates
Similar to current source
nMOS I-V Summary
0 Vgs Vt cutoff
V V V V
I ds Vgs Vt ds ds linear
2
ds dsat
Vgs Vt
2
Vds Vdsat saturation
2
pMOS I-V Summary
first order transistor models
0 Vgs Vt cutoff
V V V V
I ds Vgs Vt ds ds linear
2
ds dsat
Vgs Vt
2
Vds Vdsat saturation
2
I-V characteristics of pMOS
Transistor
The CMOS Inverter: A First Glance
V DD
V in V out
CMOS Inverter
First-Order DC Analysis
V DD V DD
Rp
V out
V out
Rn
a) Vin is HIGH b) Vin is LOW
CMOS Inverter: Transient Response
R p= R n
VDD VDD
Rp tpHL = f(R on .C L )
= 0.69 R on C L
Vout
Vout
CL
CL
Rn
Vin 5 0 Vin 5 VDD
(a) Low-to-high (b) High-to-low
PMOS Load Lines
IDn
V in = V DD +VGSp
IDn = - IDp
V out = VDD +VDSp
Vout
IDp IDn IDn
Vin=0 Vin=0
V in=1.5 Vin=1.5
V DSp V DSp Vout
VGSp=-1
VGSp=-2.5
Vin = V DD+VGSp Vout = V DD+VDSp
IDn = - IDp
CMOS Inverter Load Characteristics
IDn
Vin = 0 Vin = 2.5
PMOS Vin = 0.5 Vin = 2 NMOS
Vin = 1 Vin = 1.5
Vin = 1.5 Vin = 1
Vin = 1.5 Vin = 1
Vin = 2 Vin = 0.5
Vin = 2.5 Vin = 0
Vout
DC Operation:
Voltage Transfer Characteristic
V(y)
V(x) V(y)
V f
OH
V(y)=V(x)
V Switching Threshold
M
VOL
VOL V V(x)
OH
Nominal Voltage Levels
Mapping between analog and digital signals
V V(y)
"1" OH
Slope = -1
V V
IH OH
Undefined
Region
Slope = -1
V
IL VOL
"0"
V
OL V V V(x)
IL IH
Definition of Noise Margins
"1"
V
OH
NMH
V
Noise Margin High IH
Undefined
Region
Noise Margin Low
NML V
IL
V
OL
"0"
Gate Output Gate Input
Delay Definitions
Vin
50%
t
t t
pHL pLH
Vout
90%
50%
10% t
tf tr
Where Does Power Go in CMOS?
• Dynamic Power Consumption
Charging and Discharging Capacitors
• Short Circuit Currents
Short Circuit Path between Supply Rails during Switching
• Leakage
Leaking diodes and transistors
Power and Energy
• Power is drawn from a voltage source
attached to the VDD pin(s) of a chip.
• Instantaneous Power:
P(t ) iDD (t )VDD
• Energy:
T T
E P(t )dt iDD (t )VDD dt
0 0
• Average Power: Pavg
E 1
T
iDD (t )VDD dt
T T 0
Design for Low Power Slide 77
Dynamic Power Dissipation Vdd
Vin Vout
CL
Energy/transition = CL * V dd2
Power = Energy/transition * f = CL * Vdd2 * f
Not a function of transistor sizes!
Need to reduce CL, Vdd, and f to reduce power.
Dynamic Power
• Dynamic power is required to charge and
discharge load capacitances when transistors
switch.
• One cycle involves a rising and falling output.
• On rising output, charge Q = CVDD is required
• On falling output, charge is dumped to GND
• This repeats Tfsw times VDD
over an interval of T i (t)
DD
C
fsw
Dynamic Power Cont.
Pdynamic
VDD
iDD(t)
C
fsw
Design for Low Power Slide 81
Dynamic Power Cont.
T
1
Pdynamic iDD (t )VDD dt
T 0
T
VDD
T 0 iDD (t )dt
VDD
TfswCVDD VDD
T iDD(t)
CVDD 2 f sw
C
fsw
Design for Low Power Slide 82
Short Circuit Current
• When transistors switch, both nMOS and
pMOS networks may be momentarily ON at
once
• Leads to a blip of “short circuit” current.
• < 10% of dynamic power if rise/fall times are
comparable for input and output
Design for Low Power Slide 83
Static Power
• Static power is consumed even when chip is
quiescent.
– Ratioed circuits burn power in fight between ON
transistors
– Leakage draws power from nominally OFF devices
Vgs Vt
Vds
I ds I ds 0e nvT
1 e
vT
V V V V
t t0 ds s sb s
Design for Low Power Slide 84
Leakage Power
VDD
Ground IG
Gate
R
Source Drain
n+ Isub n+
IPT
IGIDL ID
Bulk Si (p)
nMOS Transistor
Copyright Agrawal & Srivaths,
Low-Power Design and Test, Lecture 2 92
2007
Leakage Current Components
• Subthreshold conduction, Isub
• Reverse bias pn junction conduction, ID
• Gate induced drain leakage, IGIDL due to
tunneling at the gate-drain overlap
• Drain source punchthrough, IPT due to short
channel and high drain-source voltage
• Gate tunneling, IG through thin oxide; may
become significant with scaling
Copyright Agrawal & Srivaths,
Low-Power Design and Test, Lecture 2 93
2007
Subthreshold Current
Isub = μ0 Cox (W/L) Vt2 exp{(VGS –VTH ) / nVt }
μ0: carrier surface mobility
Cox: gate oxide capacitance per unit area
L: channel length
W: gate width
Vt = kT/q: thermal voltage
n: a technology parameter
Copyright Agrawal & Srivaths,
Low-Power Design and Test, Lecture 2 94
2007
