Unit 4 : Important topics

SR Latch
Symbol Function Table Characteristic Table
C S(t) R(t) Q(t) Q(t+1) Operation S(t) R(t) Q(t) Q(t+1)
S Q 1 0 0 0 0 0 0 0 0
1 0 0 1 1 No change 0 0 1 1
C
1 0 1 0 0 0 1 0 0
1 0 1 1 0 Reset 0 1 1 0
R Q
1 1 0 0 1 1 0 0 1
1 1 0 1 1 Set 1 0 1 1
1 1 1 0 ? 1 1 0 x
1 1 1 1 ? Undefined 1 1 1 x
0 x x x Q(t) No change

Excitation Table Characteristic Equation

R(t)
Q(t) Q(t+1) S(t) R(t)
0 0 0 x 1
0 1 1 0
1 0 0 1 S(t) 1 1 x x
1 1 x 0 Q(t)
Q(t+1) = S(t) + R(t)’•Q(t)
2
 JK Latch
Symbol Function Table Characteristic Table
C J(t) K(t) Q(t) Q(t+1) Operation J(t) K(t) Q(t) Q(t+1)
J Q 1 0 0 0 0 0 0 0 0
1 0 0 1 1 No change 0 0 1 1
C
1 0 1 0 0 0 1 0 0
K Q 1 0 1 1 0 Reset 0 1 1 0
1 1 0 0 1 1 0 0 1
1 1 0 1 1 Set 1 0 1 1
1 1 1 0 1 1 1 0 1
Complement
1 1 1 1 0 1 1 1 0
0 x x x Q(t) No change

Excitation Table Characteristic Equation

Q(t) Q(t+1) J(t) K(t) K(t)
0 0 0 x
0 1 1 x 1
1 0 x 1 J(t) 1 1 1
1 1 x 0 Q(t)
Q(t+1) = J(t)•Q(t)’+K(t)’•Q(t)
 D Latch
Symbol Function Table Characteristic Table
C D(t) Q(t) Q(t+1) Operation D(t) Q(t) Q(t+1)
D Q
1 0 0 0 0 0 0
1 0 1 0 Propagate 0 1 0
C Q 1 1 0 1 input D 1 0 1
1 1 1 1 1 1 1
0 x x Q(t) No change

Excitation Table Characteristic Equation

Q(t) Q(t+1) D(t) Q(t)
0 0 0
0 1 1
1 0 0
1 1 1 D(t) 1 1

Q(t+1) = D(t)
4
 T Latch
Symbol Function Table Characteristic Table
C T(t) Q(t) Q(t+1) Operation T(t) Q(t) Q(t+1)
T Q
1 0 0 0 0 0 0
No change
1 0 1 1 0 1 1
C Q 1 1 0 1 1 0 1
Complement
1 1 1 0 1 1 0
0 x x Q(t) No change

Excitation Table Characteristic Equation

Q(t) Q(t+1) T(t) Q(t)

0 0 0 1
0 1 1
1 0 1 T(t) 1
1 1 0
Q(t+1) = T(t)  Q(t)
 SR Flip-Flop
Symbol Function Table Characteristic Table
CLK S(t) R(t) Q(t) Q(t+1) Operation S(t) R(t) Q(t) Q(t+1)
S Q 0 0 0 0 0 0 0 0
0 0 1 1 No change 0 0 1 1
CLK
0 1 0 0 0 1 0 0
R Q 0 1 1 0 Reset 0 1 1 0
1 0 0 1 1 0 0 1
1 0 1 1 Set 1 0 1 1
- rising edge 1 1 0 ? 1 1 0 x
1 1 1 ? Undefined 1 1 1 x
- 1 or 0 or x x x Q(t) No change
falling edge

Excitation Table Characteristic Equation

R(t)
Q(t) Q(t+1) S(t) R(t) 1
0 0 0 x
0 1 1 0 S(t) 1 1 x x
1 0 0 1 Q(t)
1 1 x 0
Q(t+1) = S(t) + R(t)’•Q(t)
 JK Flip-Flop
Symbol Function Table Characteristic Table
CLK J(t) K(t) Q(t) Q(t+1) Operation J(t) K(t) Q(t) Q(t+1)
J Q 0 0 0 0 0 0 0 0
0 0 1 1 No change 0 0 1 1
CLK
0 1 0 0 0 1 0 0
K Q 0 1 1 0 Reset 0 1 1 0
1 0 0 1 1 0 0 1
1 0 1 1 Set 1 0 1 1
- rising edge 1 1 0 1 1 1 0 1
Complement
1 1 1 0 1 1 1 0
- 1 or 0 or x x x Q(t) No change
falling edge

Excitation Table Characteristic Equation

K(t)
Q(t) Q(t+1) J(t) K(t)
0 0 0 x 1
0 1 1 x J(t) 1 1 1
1 0 x 1 Q(t)
1 1 x 0
Q(t+1) = J(t)•Q(t)’+K(t)’•Q(t)
 D Flip-Flop
Symbol Function Table Characteristic Table
CLK D(t) Q(t) Q(t+1) Operation D(t) Q(t) Q(t+1)
D Q
0 0 0 0 0 0
0 1 0 Propagate 0 1 0
CLK Q 1 0 1 input D 1 0 1
1 1 1 1 1 1
x x Q(t) No change
- rising edge
- 1 or 0 or
falling edge

Excitation Table Characteristic Equation

Q(t)
Q(t) Q(t+1) D(t)
0 0 0
0 1 1
1 0 0 D(t) 1 1
1 1 1
Q(t+1) = D(t)
 T Flip-Flop
Symbol Function Table Characteristic Table
CLK T(t) Q(t) Q(t+1) Operation T(t) Q(t) Q(t+1)
T Q
0 0 0 0 0 0
No change
0 1 1 0 1 1
CLK Q 1 0 1 1 0 1
Complement
1 1 0 1 1 0
x x Q(t) No change
- rising edge
- 1 or 0 or
falling edge

Excitation Table Characteristic Equation

Q(t)
Q(t) Q(t+1) T(t)
0 0 0 1
0 1 1
1 0 1 T(t) 1
1 1 0
Q(t+1) = T(t)  Q(t)
Race Around Condition
In JK Flip-flop – For J-K flip-flop, if J=K=1, and if clk=1 for a long period of time, then Q output
will toggle as long as CLK is high, which makes the output of the flip-flop unstable or
uncertain. This problem is called race around condition in J-K flip-flop.

This problem (Race Around Condition) can be avoided by ensuring that the clock input is at
logic “1” only for a very short time. This introduced the concept of Master Slave JK flip flop.
Master Slave JK flip flop

• – The Master-Slave Flip-Flop is basically a

combination of two JK flip-flops connected together
in a series configuration. Out of these, one acts as the
“master” and the other as a “slave”. The output from
the master flip flop is connected to the two inputs of
the slave flip flop whose output is fed back to inputs
of the master flip flop. In addition to these two flip-
flops, the circuit also includes an inverter. The inverter
is connected to clock pulse in such a way that the
inverted clock pulse is given to the slave flip-flop.
• In other word,s if CP=0 for a master flip-flop, then
CP=1 for a slave flip-flop and if CP=1 for master flip
flop then it becomes 0 for slave flip flop.
 When the Clock pulse is high the output of master
is high and remains high till the clock is low
because the state is stored.
Now the output of master becomes low when the
clock pulse becomes high again and remains low
until the clock becomes high again.
Thus toggling takes place for a clock cycle.
When the clock pulse is high, the master is
operational but not the slave thus the output of the
slave remains low till the clock remains high.
When the clock is low, the slave becomes
operational and remains high until the clock again
becomes low.
Toggling takes place during the whole process
since the output is changing once in a cycle

This makes the Master-Slave J-K flip flop a Synchronous device as it only passes data with
the timing of the clock signal.
 Shift Registers
Flip flops can be used to store a single bit of binary data (1 or 0). However, in
order to store multiple bits of data, we need multiple flip-flops. N flip flops are
to be connected in order to store n bits of data. A Register is a device that is
used to store such information. It is a group of flip-flops connected in series
used to store multiple bits of data. The information stored within these
registers can be transferred with the help of shift registers.

Types of Shift Registers

• Serial In Serial Out shift register

• Serial In parallel Out shift register
• Parallel In Serial Out shift register
• Parallel In parallel Out shift register
Serial-In Serial-Out Shift Register (SISO)
Serial-In Parallel-Out Shift Register (SIPO)
Parallel-In Serial-Out Shift Register (PISO)
Parallel-In Parallel-Out Shift Register (PIPO)
 • A Counter is a device which stores (and sometimes displays) the
number of times a particular event or process has occurred, often in
relationship to a clock signal. Counters are used in digital
electronics for counting purpose, they can count specific event
happening in the circuit. For example, in UP counter a counter
increases count for every rising edge of clock. Not only counting, a
counter can follow the certain sequence based on our design like
any random sequence 0,1,3,2… .They can also be designed with the
help of flip flops. They are used as frequency dividers where the
frequency of given pulse waveform is divided. Counters are

Counters sequential circuit that count the number of pulses can be either in
binary code or BCD form. The main properties of a counter are
timing , sequencing , and counting.

• Counter works in two modes

• Up counter

• Down counter
Counter Classification

Counters are broadly divided into two categories

Asynchronous counter
Synchronous counter

1. Asynchronous Counter

In asynchronous counter we don’t use universal clock, only first flip flop is
driven by main clock and the clock input of rest of the following flip flop is
driven by output of previous flip flops. We can understand it by following
diagram-
2. Synchronous Counter

Unlike the asynchronous counter, synchronous counter has one global clock which drives each flip flop so output
changes in parallel. The one advantage of synchronous counter over asynchronous counter is, it can operate on
higher frequency than asynchronous counter as it does not have cumulative delay because of same clock is given to
each flip flop. It is also called as parallel counter.
 • Ripple counter is a cascaded arrangement of flip-flops where the
output of one flip-flop drives the clock input of the following flip-flop.
The number of flip flops in the cascaded arrangement depends upon
the number of different logic states that it goes through before it
repeats the sequence a parameter known as the modulus of the
counter. A n-bit ripple counter can count up to 2n states. It is also
known as MOD n counter. It is known as ripple counter because of
the way the clock pulse ripples its way through the flip-flops.
Ripple • Some of the features of ripple counter are:
Counter • It is an asynchronous counter.
• Different flip-flops are used with a different clock pulse.
• All the flip-flops are used in toggle mode.
• Only one flip-flop is applied with an external clock pulse
and another flip-flop clock is obtained from the output
of the previous flip-flop.
• The flip-flop applied with an external clock pulse act as
LSB (Least Significant Bit) in the counting sequence.
 A 3-bit Ripple counter using a JK flip-flop is as follows:

Truth Table is as follows:

In the circuit shown in the above figure, Q0(LSB)

will toggle for every clock pulse because JK flip-
flop works in toggle mode when both J and K are
applied 1, 1, or high input. The following counter
will toggle when the previous one changes from
1 to 0.
Let us assume that the clock is negative edge triggered so the above the counter will act as an up
counter because the clock is negative edge triggered and output is taken from Q.
Ring • A ring counter is a typical application of the Shift register. The ring
counter is almost the same as the shift counter. The only change is that
the output of the last flip-flop is connected to the input of the first flip-

Counter flop in the case of the ring counter but in the case of the shift register it is
taken as output. Except for this, all the other things are the same.
In this diagram, we can see that the clock pulse (CLK) is applied to all the flip-flops simultaneously.
Therefore, it is a Synchronous Counter. Also, here we use Overriding input (ORI) for each flip-flop.
Preset (PR) and Clear (CLR) are used as ORI. When PR is 0, then the output is 1. And when CLR is 0,
then the output is 0. Both PR and CLR are active low signal that always works in value 0.

This Preseted 1 is generated by making ORI low and that

time Clock (CLK) becomes don’t care. After that ORI is
made to high and apply low clock pulse signal as the
Clock (CLK) is negative edge triggered. After that, at each
clock pulse, the preseted 1 is shifted to the next flip-flop
and thus forms a Ring. From the above table, we can say
that there are 4 states in a 4-bit Ring Counter.
Types of Ring Counter: There are two types of Ring Counter:

Straight Ring Counter: It is also known as One hot Counter. In this counter, the output of the last flip-flop
is connected to the input of the first flip-flop. The main point of this Counter is that it circulates a single
one (or zero) bit around the ring.

Here, we use Preset (PR) in the first flip-flop and Clock (CLK) for the last three flip-flops.
Twisted Ring Counter – It is also known as a switch-tail ring counter, walking ring counter, or Johnson
counter. It connects the complement of the output of the last shift register to the input of the first
register and circulates a stream of ones followed by zeros around the ring.

Here, we use Clock (CLK) for all the flip-flops. In the Twisted Ring Counter,
the number of states = 2 X the number of flip-flops.