Logic Design

Flip Flops, Registers and Counters

 Introduction
• Combinational circuits: value of each output depends only on
the values of inputs
• Sequential Circuits: values of outputs depend on inputs and
past behavior of the circuit
– Circuit contains storage (memory) elements
• Example: an alarm system in which the alarm stays on when
triggered even if the sensor output goes to zero

Set
Sensor
Memory On Off
Alarm
element
Reset
 Basic Latch
• Simplest memory element: basic latch
• Can be built with NAND or NOR gates

Reset

Set Q
 Basic Latch
R S R Qa Qb
Qa
0 0 0/1 1/0 (no change)
0 1 0 1
1 0 1 0
Qb 1 1 0 0
S

(a) Circuit (b) Truth table

t1 t2 t3 t4 t5 t6 t7 t8 t9 t 10

1
R
0

1
S
0

1
Qa ?
0

1
Qb ?
0

Time
(c) Timing diagram
 Basic Latch
• In basic latch, the state changes when the inputs change
• In many circuits we cannot control when the inputs change
but would like the change in state happens at particular times
• We add a clock (clk) signal to the basic latch
Gated SR Latch
 Gated Latch with NAND
• Behavior of the circuit is the same as the one with NOR
• Clock is gated by NAND gates rather than AND gates
• S and R inputs are reversed

S
Q

Clk

Q
R
 D latch
• D latch is based on gated SR latch
• Instead of two inputs, has one input
D Latch
 D Latch
• Since the output of gated D latch is controlled by the level of
clock, it is called level sensitive
– In the window of clk=1, the output Q tracks the changes of input D.
This is undesirable.
• It is possible to design storage elements for which the output
changes only when clock changes from one value to the other.
• Those circuits are called edge triggered
 Propagation delay
• D latch: stores the value of D input at the time clock goes
from 1 to 0.
• It operates properly if input is stable (not changing) at the
time clk goes from 1 to 0.
t su
th

Clk

Q
 Master-slave D flip-flop
• Master-slave D flip-flop: two gated D latches
• First one, called master, changes its state when clk=1
• Second one, called slave, changes its state when clk=0
• From external point of view, master-slave flip-flop changes its
state at the negative edge of clock
 Master-slave D flip-flop

Master Slave
Qm Qs
D D Q D Q Q
Clock Clk Q Clk Q Q

(a) Circuit

Clock

D
Qm
Q = Qs
(b) Timing diagram

D Q
Q

(c) Graphical symbol

Edge-triggered D flip-flop
 D flip-flop with clear and preset
• An example of application of flip-flops: counters
• We should be able to clear the counter to zero
• We should be able to force the counter to a known initial
count
• Clear: asynchronous, synchronous
• Asynchronous clear: flip-flops are cleared without regard to
clock signal
• Synchronous clear: flip-flops are clear with the clock signal
Edge triggered D flip flop with clear & preset
T Flip-Flop
 JK flip flop
• D=JQ’+K’Q
• When J=S and K=R it will behave like a SR flip-flop
 Summary
• Basic latch- a feedback connection of two NOR or NAND
gates to store 1-bit information. S»1; R»0.
• Gated latch- a basic latch with a control (clk). clk =0: the
existing state maintains; clk=1: the existing state may change
– Gated SR latch. S»1; R»0.
– Gated D latch. The D input forces the state to be the same as D
• Flip-flop- a storage element. Its output state changes only on
the edge of clk.
– Edge-triggered flip-flop
– Master-slave flip-flop. The master is active in 1st half of a clock cycle;
The slave active in 2nd half.
– Regardless how many times the D input to the master changes, the
slave output can only change at the negative edge of clk.
 Registers
• Register: a set of n flip-flops used to store n bits of
information
• A common clock is used for all the flip-flops
• A register that provides the ability to shift its contents is
called a shift register
• To implement a shift register, it is necessary to use edge-
triggered or master-slave flip-flops
Shift register
• In computer systems it is often necessary to transfer n-bit data
• Using n separate wires: parallel transmission
• Using a single wire and performing the transfer one bit at a
time in n consecutive cycles: serial transmission
Parallel access shift register
 Counters
• Counter: a circuit that can increment or decrement a count by
1
• Applications: generating time intervals, count the number of
occurrence of an event, ….
• Counters can be build using T and D flip-flops
Up counter with T flip-flop
 Up counter with T flip-flop

Clock

Q0

Q1

Q2

Count 0 1 2 3 4 5 6 7 0
• The counter has three flip flops
• Only the first one is directly connected to the clock
• The other two respond after a delay
• For this reason it is called an asynchronous counter
Down counter with T flip-flops
 Synchronous counters
• Problem with asynchronous counters: long delays for large
number of bits
• Solution: clock all the flip-flops at the same time
(synchronous counter)
Clock cycle Q2 Q1 Q0
Q1 changes
0 0 0 0
1 0 0 1 Q2 changes
2 0 1 0
3 0 1 1
4 1 0 0
5 1 0 1
6 1 1 0
7 1 1 1
8 0 0 0
• Q0 changes on each clock cycle
• Q1 changes only when Q0=1
• Q2 changes only when Q1=1 and Q0=1

• T0=1;
• T1=Q0
• T2=Q0Q1
• T3=Q0Q1Q2
Enable and clear capability
 Synchronous counter with D flip flop
• Formal method: chapter 8

D0  Q0  Enable
D1  Q1  Q0 .Enable
D2  Q2  Q1.Q0 .Enable
D3  Q3  Q2 .Q1.Q0 .Enable


Synchronous Counter with D Flip Flop
 Counter with parallel load
• Sometimes it is desirable to start the counter with an initial
value
Counter with parallel load
 Reset Synchronization
• How can we design a counter that counts modulo some base
that is not a power of 2 (e.g., modulo-6 counter counting 0, 1,
2, 3, 4, 5, 0, 1, ….)
• Detect 5 and then load zero into the counter
 BCD counter
• In a BCD counter, the counter should be reset after the count
of 9 has been obtained
BCD Counter
 Ring Counter
• In all the previous counters the count is indicated by the state
of the flip-flops in the counter
• It is possible to design a counter in which each flip-flop
reaches the state of Qi=0 for exactly one count while for other
counts Qi=0
• This is called a ring counter and it can be built from a shift
register
Ring Counter
 Johnson Counter
• If instead of Q output we take the Q’ output of the last stage
in a ring counter and feed it back to the first stage we get a
Johnson counter.
• It counts to a sequence of length 2n
• For example for 4-bit the sequence would be: 0000, 0001,
1100, 1110, 1111, 0111, 0011, 0001, 0000.
Johnson counter