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IEEE TRANSACTIONS ON ELECTRON DEVICES 1

A Compact Virtual-Source Model for Carbon

Nanotube FETs in the Sub-10-nm
Regime—Part I: Intrinsic Elements
Chi-Shuen Lee, Eric Pop, Senior Member, IEEE, Aaron D. Franklin, Senior Member, IEEE,
Wilfried Haensch, Fellow, IEEE, and H.-S. Philip Wong, Fellow, IEEE

Abstract— We present a data-calibrated compact model of channel body, resulting in low drive current due to mobility
carbon nanotube (CNT) FETs (CNTFETs) based on the virtual- degradation (caused by the body thickness fluctuation [5]) and
source (VS) approach, describing the intrinsic current–voltage low density of states (DOS) [6].
and charge–voltage characteristics. The features of the model
include: 1) carrier VS velocity extracted from experimental By contrast to bulk 3-D materials, a single-walled CNT is
devices with gate lengths down to 15 nm; 2) carrier effective essentially a single sheet of graphene rolled into a seamless
mobility and velocity depending on the CNT diameter; 3) short cylinder with a 1–2 nm diameter. Because of the atomically
channel effect such as inverse subthreshold slope degradation thin body, the gate control of the CNTFETs is superior and
and drain-induced barrier lowering depending on the device the SCE can be overcome even for L g < 10 nm [3], [7], [8].
dimensions; and 4) small-signal capacitances including the
CNT quantum capacitance effect to account for the decreasing Furthermore, the CNTs show promise for energy-efficient
gate capacitance at high gate bias. The CNTFET model captures computation because of their high carrier velocity and near-
the dimensional scaling effects and is suitable for technology ballistic carrier transport property [9], [10]. Recent progress
benchmarking and performance projection at the sub-10-nm and challenges in the CNTFET technology can be found
technology nodes. in [1]–[3] and [11]–[15].
Index Terms— Carbon nanotube (CNT), CNTFET, compact For all emerging technologies, early assessment based on
model, technology assessment. both experimental observation and theoretical study is of great
value as it facilitates identification of the most promising
I. I NTRODUCTION
options and allows resources to be focused on them.

C ARBON nanotube (CNT) FETs (CNTFETs) based on

single-walled semiconducting CNTs have been among
the foremost candidates to complement Si and extend CMOS
Nonequilibrium Green’s function (NEGF) formalism [16] has
been extensively employed to simulate the quantum transport
in CNTFETs and assess their performance [7], [8], [17].
technology scaling in the sub-10-nm technology nodes [1]–[3]. However, the NEGF is too computationally expensive for
One of the dominant factors impeding further scaling of performance assessment at the application level. Compact
Si MOSFETs is the short-channel effect (SCE), which causes modeling based on the Landauer formula for ballistic transport
FETs at short gate lengths to be difficult to turn OFF, in the CNTs is another efficient approach for performance
consequently consuming too much power [4]. Further scaling assessment [18]–[20]. However, the effects of dimensional
the gate length (L g ) of Si-MOSFETs requires an ultrathin scaling, series resistance (Rs ), and tunneling leakage current
have not been well captured in these compact models.
Manuscript received March 17, 2015; accepted July 14, 2015. This work was
supported in part by the Network for Computational Nanotechnology–Nano- Attempts were made to address these issues by lumping the
Engineered Electronic Device Simulation Program funded by the National scaling and parasitic effects into constant input parameters
Science Foundation under Contract 1227020-EEC and by the Semiconductor [e.g., constant Rs and subthreshold slope (SS)] independent
Research Corporation, in part by the Systems on Nanoscale Information
Fabrics (SONIC), one of the six Semiconductor Research Corporation STAR- of the device design [18]. As a result, the dimensional scaling
net Centers through the Microelectronics Advanced Research Corporation effect and variations cannot be studied.
and Defense Advanced Research Projects Agency, in part by the member In this paper, we describe a data-calibrated compact
companies of the Initiative for Nanoscale Materials and Processes (INMP)
through Stanford University, Stanford, CA, USA, and in part by IBM through CNTFET model based on the virtual-source (VS)
the SystemX Alliance and the Center for Integrated Systems, Stanford approach [21]. This VS-CNTFET model captures device
University. The review of this paper was arranged by Editor G. L. Snider. parasiticand dimensional scaling effects, and has been
C.-S. Lee, E. Pop, and H.-S. P. Wong are with the Department of
Electrical Engineering, Stanford University, Stanford, CA 94305 USA (e-mail: implemented in Verilog-A [22] available online [23]. The
chishuen@stanford.edu; epop@stanford.edu; hspwong@stanford.edu). motivation of developing the model is twofold.
A. D. Franklin is with the Department of Electrical and 1) Assess the performance of CNTFET and study the
Computer Engineering, Duke University, Durham, NC 27708 USA (e-mail:
aaron.franklin@duke.edu). design tradeoffs, including device parasitic and process
W. Haensch is with the IBM Thomas J. Watson Research Center, Yorktown variations, at the extremely scaled dimensions.
Heights, NY 10598 USA (e-mail: whaensch@us.ibm.com). 2) Identify the required improvement in the current
Color versions of one or more of the figures in this paper are available
online at http://ieeexplore.ieee.org. CNTFET technology to achieve performance advantage
Digital Object Identifier 10.1109/TED.2015.2457453 over similarly scaled FETs.
0018-9383 © 2015 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
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2 IEEE TRANSACTIONS ON ELECTRON DEVICES

In the VS-CNTFET model, the VS parameters described in

Section II are connected to the CNTFET dimensions and
the CNT diameter to capture the scaling effect. A similar
concept has been reported in [24], but it did not include sev-
eral important effects: 1) small-signal capacitances were not
properly modeled; 2) the CNT quantum capacitance was not
considered; 3) the internal VS parameters were independent
of the CNT diameter; and 4) iterations and numerical inte-
gral were needed. These deficiencies are addressed in this
two-part paper.
Several premises are relied on in this paper. Fig. 1. Representative gate-all-around CNTFET device structure used in the
VS-CNTFET model with the critical dimensions labeled.
1) We focus purely on the MOSFET-like CNTFETs with
Ohmic metal-CNT contacts, because they provide better
performance and could be realized by heavily doping the inversion, and between nonsaturation and saturation regions,
source/drain (S/D) extensions [25]. Previous efforts on respectively. In this section, the VS parameters are associated
modeling the Schottky-barrier CNTFETs can be found with the device dimensions and CNT diameter (d), which is
in [26]. a crucial parameter because it determines the CNT band
2) The n-type CNTFETs are discussed throughout this structure and the bandgap (E g ). In this paper, the CNT
paper. Although the CNTFETs in ambient air are usually E g = 2E p acc /d is derived from the Hückel tight-binding
p-type based on the preferred injection of holes at the model [31], where E p = 3 eV is the tight-binding parameter
contacts, the n-type CNTFETs have been achieved by and acc = 0.142 nm is the carbon–carbon distance in the
contact or interface engineering [27], [28], and from a CNTs, indicating E g ≈ 0.85/d eV with d in nanometer.
physical and mathematical point of view the operation Corrections to the model of E g could be made due to bandgap
of n-type and p-type CNTFETs is symmetric due to the renormalization induced by many-body interaction [32] or
symmetry of conduction and valence bands. substrate-induced polarization effects [33], but they do not
3) Only the first subband in CNTs is considered because alter the essence of the VS model presented here.
most digital applications call for a low-power supply A representative Gate-All-Around (GAA)-CNTFET device
voltage, but higher subbands can be easily included with structure used in the VS-CNTFET model is shown in Fig. 1
proper modification of the charge model. with the critical dimensions labeled. By calibrating the
This paper is organized as follows. Analytical expressions VS-CNTFET model to the experimental data and rigorous
that connect the VS parameters to the CNTFET design as numerical simulations, it becomes possible to make predictive
well as the model calibration are described in Section II. estimates of device behavior as the dimensions scale down.
The charge model used to derive the small-signal capaci- Although the VS model was not originally meant to be
tances is introduced in Section III. In Section IV, the impact predictive because the VS parameters need to be extracted
of CNT diameter on the intrinsic CNTFET performance is from the current–voltage (I –V ) and capacitance–voltage (C–
presented. Finally, in Section V, the issues pertaining to the V ) measurements, it has clear physical meaning connecting
VS parameter extraction from the CNTFETs are discussed. to the Landauer approach [34], and thus provides a physically
Due to the limited space, the complete derivation of all meaningful trend. As will be manifest in Part II [29], in the
the equations is detailed in [23]; here, we only discuss the sub-10-nm technology nodes where the space becomes very
physics and key results. Models for the contact resistance and limited, the device parasitic, tunneling leakage, and the
tunneling leakage current, and demonstration of the use of the SCE become so significant that the device has to be carefully
model will be introduced in Part II of this two-part paper [29]. designed. Therefore, the emphasis of this paper is on the
scaling trend rather than the accuracy in absolute values.
II. V IRTUAL S OURCE M ODEL FOR CNTFETs
The VS model is a semiempirical model with only a few
physical parameters, originally developed for short-channel A. Inversion Gate Capacitance (Cinv )
Si MOSFETs that have a gate-controlled source-injection In a MOSFET, the mobile charge density in strong inver-
barrier [21], [30]. Based on the VS approach, the drain sion at the VS, where the gradual channel approximation
current (Id ) of a MOSFET is the product of the mobile charge applies [34], can be approximated as Q xo ≈ −Cinv · (Vgs −Vt ),
density and the carrier velocity at the VS, defined as the where Cinv = Cox · Cs (Cox + Cs ), Cox is the gate oxide
top of the energy barrier near the source in the ON-state. capacitance, and Cs is the semiconductor capacitance [35].
There are ten VS parameters: 1) gate length (L g ); 2) gate In planar bulk semiconductor materials, the DOS is usually
capacitance in strong inversion region (Cinv ); 3) low-field so large that Cs  Cox and Cinv ≈ Cox ; however, for CNTs,
effective mobility (μ); 4) threshold voltage (Vt ); 5) inverse the CNT quantum capacitance (Cq ) needs to be considered
SS factor (n ss ); 6) drain-induced barrier lowering (DIBL) because Cq is comparable with Cox due to the relatively
coefficient (δ); 7) series resistance (Rs ); 8) VS carrier low DOS. Strictly speaking, Cq is bias-dependent [36].
velocity (vxo ); 9) fitting parameter α; and 10) fitting parame- However, the numerical simulation in Fig. 2(a) shows that
ter β used to smooth the transitions between weak and strong the linear relation between Q xo and Vgs −Vt in the inversion
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LEE et al.: COMPACT VS MODEL FOR CNTFETs 3

Fig. 2. (a) Comparison of the VS carrier density Q xo versus Vgs between

the numerical simulation [37] and the model (see Section II-A and [23]). Fig. 3. Low-field mobility versus L g for different CNT diameters and
EOT = 0.7 nm. (b) Effective CNT quantum capacitance Cqeff versus temperatures. The symbols are the peak mobility given by (3) and lines
√ represent the model given by (2). The mobility decreases toward smaller L g ,
(qEg /k B T ) extracted from the numerical simulation [37] for various
temperatures, EOT’s, and CNT diameters. as the conductance becomes constant with quasi-ballistic transport, see (3).

region is still retained over a reasonable range of Vgs and Q xo , where d is normalized to d00 = 1 nm to become
implying the viability of having a constant effective Cq (Cqeff ) dimensionless, and tμ , tλ , μ00 , λ00 , and cμ are empirical
to account for the effect of quantum capacitance in the calcu- fitting parameters to capture the dependence on temperature,
lation of Cinv . In the VS-CNTFET model, Cinv is calculated gate length, and CNT diameter. To validate (2) and determine
as follows: the fitting parameters, the 1-D quantum transport theory at low
fields is used, written here for the lowest subband [16], [38]
Cinv = Cox Cqeff /(Cox + Cqeff ) (1a)   
 4q 2 ∞ λi (E, T, d) ∂ f (E, E F )
Cqeff = cqa q · E g /(k B T ) + cqb (1b) G= − dE (3)
h Ec L g + λi (E, T, d) ∂E
Cox = 2πkox ε0 /{ln[(2tox + d)/d]} (1c) where G is the CNT conductance, h is Planck’s constant,
where q is the elementary charge, T is the temperature in E c is the conduction band edge, E is the energy of free
Kelvin, k B is Boltzmann’s constant, cqa and cqb are the electrons, E F is the Fermi level, f is the Fermi–Dirac
empirical fitting parameters, Cox is the gate oxide capacitance distribution function, and λi is the MFP in CNTs representing
of a GAA structure, ε0 is the permittivity in vacuum, and the aggregate effect of optical and acoustic phonon scattering.
tox and kox are the thickness and the relative dielectric constant The expression for λi , its experimental validation, and
of the gate oxide, respectively. Equation (1b) is inspired treatment across multiple subbands have been detailed
by the theory that the maximum CNT Cq is approximately in [38] (only the lowest subband is considered here). Due
proportional to (E g /T )1/2 [36], and cqa = 0.087 fF/μm and to the complex expression for λi , (3) cannot be integrated
cqb = 0.16 fF/μm are determined empirically in Fig. 2(b) by analytically; therefore, (2) is employed in the VS-CNTFET
fitting (1b) to the Cqeff extracted from a numerical simulator model instead to avoid the use of a numerical integral. Fig. 3
provided by [37], which simulates a GAA-CNTFET with shows the comparison between the analytical model given
heavily doped S/D regions, and the carrier transport is simu- by (2) and the data-calibrated numerical model given by (3)
lated based on the NEGF formalism. In Fig. 2(a), the modeled for different L g , d, and T , where tμ = 3.38 cm2 V−1 s−1 K−1 ,
Q xo is calculated by substituting (1) into the equations in tλ = 0.05 nm/K, μ00 = 2388 cm2 V−1 s−1 , λ00 = 77 nm,
[23, eq. (1.3)] and compared with the numerical simulation and cμ = 1.37 are extracted. The long-channel peak mobility
for different CNT diameters. decreases linearly with increasing temperature, consistent
with the experimental observation in [39].
It should be noted that for device configurations similar
B. Carrier Mobility (μ) to Fig. 1, the source and drain are in fact separated by
As L g scales down to nanoscale, the carrier transport L g + 2L ext rather than L g . However, since the extensions are
approaches the ballistic limit and carrier scattering in the not gated and have higher doping densities than the region
channel becomes less significant. In this paper, the mobility is under the gate (thus different MFPs), we treat the extensions
the so-called apparent mobility [34], a concept that connects in [29] as extrinsic elements and confine the scope of intrinsic
the ballistic and diffusive regimes. The apparent mobility elements (described by the VS model) to the region under
could also be understood as another way to express the the gate, leading to a hierarchical model. In the experimental
mean free path (MFP). As device dimensions become smaller measurements, however, it is not easy to separate the region
than the MFP, the carriers travel across the channel nearly under the gate from the extensions and the contacts; hence, any
without scattering and scatter only at the source and drain. extraction of mobility for a short-channel CNTFET from the
In this context, the MFP becomes the channel length. In the I –V measurements is actually a reflection of the commingled
VS-CNTFET model, μ is modeled empirically as follows: behaviors of contact injection and carrier transport in the
extensions and the channel. Therefore, the use of apparent
μ = μ0 L g (d/d00 )cμ /(λμ + L g ) (2a)
mobility [34] in the VS model can be viewed as a convenience
μ0 = μ00 − tμ T (2b) for describing the experimental I –V curves in a hierarchical
λμ = λ00 − tλ T (2c) model. We note that the apparent mobility approaches zero as
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4 IEEE TRANSACTIONS ON ELECTRON DEVICES

Fig. 5. Comparison of the scale length λ between the solution to (5) and
Fig. 4. Comparison of the conduction band profile between the numerical the model given by (6) for d = 1 nm and kox = 16. Good agreement is
simulation [37] (symbols) and the model (line) given by (4) and (6). observed for tox > d/2, while the approximation given in [42] works better
for tox < d/2.

the channel length (which limits the MFP) approaches zero,

consistent with the ballistic limit. where z 0 ≈ 2.405 is the first zero of J0 . Derivation of (6)
is detailed in [23, eqs. (15)–(19)]. Equation (6) is compared
C. SCE Parameters (SS, DIBL, Vt Roll-Off) with the numerical solution to (5) in Fig. 5, showing good
The SCE is essentially the phenomenon of decreasing Vt agreement when tox > d/2. When tox  d, (6) can be
and increasing the SS and DIBL as L g scales down. In this simplified to λ ≈ (d + 2tox )/z 0 ; on the other hand, when
paper, the SCE parameters are derived from a GAA cylindrical tox  d, it has been shown in [42] that λ ≈ (d + 2γ · tox )/z 0 .
structure based on the scale length theory [40]. The first step is In both the extreme cases, λ increases linearly with d and tox .
to model the E c profile along the channel. In the subthreshold In this paper, kcnt = 1 is used, assuming it is air inside
region, where the mobile charge in the channel is negligible, the CNT [43]. However, different values of kcnt from
the E c profile can be obtained by solving the Laplace equation, 5 to 10 for semiconducting CNTs have been reported both
and the resulting E c can be expressed as theoretically [44] and experimentally [45]. Nonetheless, we
can show that (6) holds for a wide range of kcnt (from 1 ∼ 20).
E c (x) = a1 e−x/λ + a2 e x/λ − Vgs + E g /2 (4) By substituting (6) into (4), the E c profile is calculated
where x is the direction along the channel, λ is the electro- and compared with the numerical simulation [37] in Fig. 4,
static scale length (also known as the screening length), and showing good agreement in the gate region. Although the
a1 and a2 are coefficients determined by the boundary condi- potential tails extending into the S/D extensions are not
tions: 1) E c (−L of − L g /2) = −E fsd and 2) E c (L of + L g /2) = captured by (4), this will not affect the calculation of the
−E fsd − Vds , where L of is an empirical parameter functioning SCE parameters, since only the top of the E c (E cmax )
like an extension of the L g that captures the finite Debye matters. Modeling of the tails will be discussed in [29] when
length at the gate-to-S/D junctions, and E fsd is the energy calculating the tunneling currents. Once the E c profile is
difference from the Fermi level to the E c at the S/D extensions known, the SCE parameters can be derived as
(see Fig. 4). All energies are referenced to the Fermi level at 
the source (i.e., E fs = 0). n ss = −∂ E c max /∂ Vgs V =0 = (1 − e−η )−1 (7a)
ds
In a GAA cylindrical structure, λ is a solution to the Laplace δ = −∂ E c max /∂ Vds |Vds =0 = e−η (7b)

equation in cylindrical coordinates satisfying the boundary − Vt = E g /2 − E c max V =0 = (2E fsd + E g )e−η (7c)
condition at the CNT/oxide interface ds

Y1 (ζ ) Y0 (ζ ) Y0 (ζ + tox /λ) where η ≡ (L g + 2L of )/2λ, and E cmax is calculated by

=γ + (1 − γ ) (5)
J1 (ζ ) J0 (ζ ) J0 (ζ + tox /λ) substituting x = −λ/2· ln(a2 /a1 ) into (4). Equation (7)
where Jm and Ym are Bessel functions of the first kind and is compared with the numerical simulation in Fig. 6.
second kind of order m, γ ≡ kcnt /kox , kcnt is the relative Empirically, L of ≈ tox /3 is found to achieve the best fitting
dielectric constant of the CNT, and ζ ≡ d/(2λ). Equation (5) is results. A physical interpretation of the relation between
a transcendental equation, which has no closed form solution L of and tox is that when tox becomes larger, the fringe field
for λ. Analytical approximations of λ in GAA-MOSFETs from the gate to the S/D extensions will extend, making L of
have been derived in [41] by assuming that the E c profile is longer. Nevertheless, in general, L of should be viewed as a
parabolic in the transverse direction; however for CNTFETs, fitting parameter. Note that (7) is a direct result of solving
d is often smaller than tox , so the approximation made in [41] Poisson’s equation without considering nonidealities such as
fails. When tox > d/2, we show that λ can be approximated as oxide-CNT interface states. Therefore, SS ≈ 60 mV/decade
and DIBL = 0 for long-channel devices. More discussion on
d + 2tox
λ= [1 + b(γ − 1)] the oxide-CNT interface is included in [29]. Although (7) is
2z 0
  derived from a GAA structure, other device structures such
b = 0.41 ζ0 /2 − ζ03 /16 (πζ0 /2) as top gate and bottom gate should follow the same trend as
ζ0 = z 0 d/(d + 2tox ) (6) long as a proper model for λ is used.
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LEE et al.: COMPACT VS MODEL FOR CNTFETs 5

Fig. 6. Comparison of (a) SS, (b) DIBL, and (c) Vt roll-off between the numerical simulation [37] and the model given by (7) for different gate oxide
thickness and d = 1.3 nm. Tunneling currents are excluded.

Fig. 7. Extraction of VS carrier velocity. The symbols are experimental data from [49]. (a) vxo = 3.8 × 107 cm/s for L g = 15 nm. (b) vxo = 1.7 × 107 cm/s
for L g = 300 nm. (c) vxo = 0.47 × 107 cm/s for L g = 3 μm. Note that the polarity of Vgs and Vds are flipped compared to the original data to become
n-type FETs.

D. Virtual Source Carrier Velocity (vxo ) TABLE I

VS PARAMETERS FOR D ATA F ITTING
The VS carrier velocity (vxo ), also known as the injection
velocity, is one of the key metrics for the transistor technol-
ogy [46]. vxo can be associated with L g through the theory of
back scattering of carriers in the channel [47]
λv
vxo = vB (8)
λv + 2l
where v B is the carrier velocity in the ballistic limit, λv is the
carrier MFP, and l is the critical length defined as the distance
over which the electric potential drops by k B T /q from the
top of the energy barrier in the channel. Strictly speaking,
l is proportional to L g and dependent on Vds , as described two parameters are susceptible to the oxide-CNT and air-CNT
in [48]. However, since using a bias-independent vxo can fit the interface properties and may suffer from different degrees of
experimental Id −Vds data fairly well for different values of L g the hysteresis effect [13]. In fact, the extracted vxo is not
(as will be seen shortly) and only a small range of L g is of our sensitive to the choice for DIBL and Vt . Finally, vxo is treated
interest (e.g., 5 nm < L g < 30 nm), here l ≈ L g is assumed as a free parameter to achieve the best fitting result as shown in
for the sake of simplicity and λv is thus empirical. To extract Fig. 7, with the VS parameters summarized in Table I. If uncer-
v B and λv , the VS model [24] is fitted to the Id −Vds data tainty exists in the exact value of d due to the measurement,
from [49], where three CNTFETs on the same substrate with the values of Cox and μ would be adjusted accordingly and
identical structures but different gate lengths were measured. the extracted vxo could be slightly different, but the change
The extraction flow of vxo involves: 1) d = 1.2 nm, will be minor and the scaling trend will remain the same.
L g = 15 nm/300 nm/3 μm, Rs = 5.5 k , and SS = By fitting (8) to the extracted values of vxo , λv = 440 nm and
135 mV/decade according to the reported experimental data v B = 4.1 × 107 cm/s are extracted. vxo for other materials
in [49]; 2) estimating, due to lack of C–V data, Cox = has been extracted from devices at various values of L g ,
0.156 fF/μm by simulating a metallic cylinder placed on including 1.35 × 107 cm/s for 32-nm L g Si MOSFET [21]
a 10-nm-thick HfO2 with a back gate using TCAD and 3.2 × 107 cm/s for 30-nm L g III–V HFET [51].
Sentaurus [50]; 3) μ = 255/103/2.1×103 cm2 V−1 s−1 for To model the dependence of vxo on CNT diameter, we
L g = 15 nm/300 nm/3 μm, respectively, estimated by (3); refer to the carrier transport theory in MOSFETs [52]: the
4) α = 3.5 and β = 1.8 as suggested in [21]; and 5) the maximum value of vxo is approximately the equilibrium
DIBL and Vt are treated as free parameters because the unidirectional thermal velocity vTi . For the nondegenerate
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6 IEEE TRANSACTIONS ON ELECTRON DEVICES

Fig. 8. Theoretical carrier velocity in the ballistic limit (symbols) versus the
square-root of CNT diameter (dotted lines) for different carrier densities (n s ). Fig. 9. Comparison of small-signal gate capacitances Cgg between the
The symbols are calculated by (9). numerical simulation [37] and the model given by (10) at Vds = 0. The dashed
lines represent the case where CNT quantum capacitance is not considered.

case, vTi = 2k B T /(πm ∗ ), where m ∗ = h 2 /(9π 2 acc E p d) is

the effective mass in CNTs [36]. Therefore, we can express The decrease in Cq is because of the rapid drop of CNT
v B = v B0 (d/d0 )1/2 , where v B0 = 4.1 × 107 cm/s and DOS after the van Hove singularity [31]. The effect of Cq is
d0 = 1.2 nm are extracted from [49] set as reference points. not considered in the VS charge model originally developed
To examine the validity of the linear relation between for silicon MOSFETs. While an analytical model for
v B and d 1/2 , the 1-D Landauer formula [16] is used to Cq of CNTs has been developed in [19], the equations
calculate the theoretical ballistic velocity vBth are relatively complex, making analytical expressions for
 qs and qd hard to obtain. Here, the terminal charge is modeled
4q
IdB = [ f S (E) − f D (E)] d E phenomenologically rather than from the first principles to
h account for the effect of Cq
⎡ ψ −E /2q
⎤
4q 1 + exp sk B Tg/q
= k B T ln ⎣ ⎦ (9) qch = −L g (Q xo − Q xob ) (10a)
h ψ −E /2q−Vds
1 + exp s g k B T /q Q xob = (Cinv − Cinvb ) · n ss φt
  
where IdB is the drain current in the ballistic limit calculated Vgs − Vtb − α · φt · F f (Vtb )
· ln 1 + exp (10b)
by the 1-D Landauer formula, and vBth = IdB /n s , where n s is n ss · φt
calculated by (2b). Fig. 8 shows vBth versus d 1/2 for different Cinvb = Cox · Cqinf /(Cox + Cqinf ) (10c)
carrier densities, indicating that the linear relation between
vBth and d 1/2 holds for a wide range of d and n s . where qch is the total channel charge proportional to qs and qd
(see [26, eqs. (44) and (50)]), φt = k B T /q is the thermal
III. T ERMINAL C HARGE M ODEL voltage, Q xob serves to gradually decrease the absolute
value of qch around Vtb , and Vtb is a fitting parameter to
Proper modeling of the terminal charges is required to be determined. Here, we discuss a special case of Vds = 0
account for the dynamic operation of an FET. Under quasi- to demonstrate how the model works. At Vds = 0,
static conditions, the partitioning of charges at the source (qs ) qs = qd = qch /2, and the small-signal gate capacitance
and the drain (qd ) is accomplished through the Ward-Dutton Cgg = −1/L g · (∂qch /∂ Vgs ). When Vgs < Vt , Q xo ≈ 0,
charge-partitioning scheme [53], and the derivative of Q xob ≈ 0, and qch ≈ 0; as Vgs increases to Vt < Vgs < Vtb ,
terminal charges with respect to the terminal voltage gives the |Q xob |  |Q xo |, so qch ≈ −L g Q xo ≈ −L g Cinv (Vgs −Vt ), and
small-signal capacitances [54]. In a short-channel MOSFET, Cgg approaches the peak value Cinv ; when Vgs  Vtb , Q xob
the carrier transport generally falls somewhere in between the becomes appreciable and qch ≈ −L g {Cinv · (Vtb −Vt ) + Cinvb ·
drift-diffusion regime and the ballistic transport regime. (Vgs−Vtb )}, and Cgg ≈ Cinvb , as expected when Vgs
The charge model employed in this paper is similar to the approaches infinity. The modeled Cgg is compared with the
VS charge model introduced in [55], in which carrier numerical simulation [37] in Fig. 9, where Vtb = 0.7E g /
transport is assumed to be diffusive when Vds approaches q + 0.13 is determined empirically to achieve the best fitting
zero and ballistic when Vds approaches infinity. The charges result. Compared with the case, where quantum capacitance
in the two extreme cases are computed separately and then is not considered, the Cgg including the quantum capacitance
combined through a Vds -dependent smoothing function. Due is lower and gradually decreases at high Vgs . The resulting
to the limited space, the complete derivation of the charge charge model is consistent with the current model because
model is detailed in [23, pp. 21–24]. This section focuses they share the same Vt and Q xo .
on a correction term in the charge model to account for the
effect of CNT Cq .
As described in [36, Ch. 6.7], the CNT Cq increases as IV. CNTFET I NTRINSIC P ERFORMANCE
AND CNT D IAMETER
Vgs increases from zero to Vt , reaches a maximum, and
finally decreases asymptotically to Cqinf ≡ 8q 2/(3acc π E p ) In this section, the impact of CNT diameter on the intrinsic
as Vgs → ∞, when only the first subband is considered. CNTFET performance is evaluated based on the model
 This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.

LEE et al.: COMPACT VS MODEL FOR CNTFETs 7

and the very small capacitance (aF range) of the

1-D channels [58], [59]. In this paper, numerical simulation by
Sentaurus [50] is used to estimate the Cinv as a compromise
for the extraction of vxo in Fig. 7. In [24], vxo = 3 × 107 cm/s
was extracted from a CNTFET with L g = 9 nm [3],
smaller than the vxo = 3.8 × 107 cm/s extracted from the
L g = 15 nm CNTFET in Fig. 7(a). While the contradiction
(i.e., vxo of a 9-nm-CNTFET is smaller than that of
a 15-nm-CNTFET) might be attributed to the differences
in gate oxide, fabrication conditions, CNT quality, or the
Fig. 10. Intrinsic on-state current Ion and gate delay τint versus CNT diameter
at L g = 8 nm and Vdd = 0.71 V. A 2-nm diameter CNT has 27% higher Ion
long-range Coulomb interactions described in [60], the
and 21% lower τint than a 1-nm diameter CNT due to higher mobility, carrier unexpected trend highlights the necessity for a larger number
velocity, and gate capacitance. of consistent and systematic characterization of devices to
extract vxo in CNTFETs (e.g., CNTFETs built on the same
CNT with different gate lengths below 100 nm). These high-
described in Sections II and III. Inputs to the VS-CNTFET quality device data are often not readily available because of
model are: 1) L g = 8 nm; 2) supply voltage Vdd = 0.71 V; the difficulties in device fabrication and the hysteresis and
and 3) equivalent oxide thickness (EOT) = 0.51 nm, selected instability of experimental devices.
from the 2023 node of the 2013 International Technology
Roadmap for Semiconductors projections [56] which predicts VI. C ONCLUSION
the metal-1 pitch will be scaled down to 25.2 nm in 2023 The intrinsic elements of a compact CNTFET model
for high performance logic; a GAA structure is assumed; and based on the VS approach have been developed in this
Rs = R Q /2 = h/(2q 2 ) ≈ 3.3 k per CNT is added to the paper. A VS carrier velocity of 3.8 × 107 cm/s is extracted
source and the drain terminals (see Fig. 1) to account for the from recent experimental CNTFET with 15-nm gate length,
quantum resistance associated with the interfaces between providing evidence of the superior potential of CNTFETs for
the 1-D CNT channel with the metal S/D contacts (including future transistor technology. The model captures dimensional
the lowest band double degeneracy with two spins) [36]. scaling effects and is used to study the impact of CNT
In Fig. 10, the ON-state current Ion ≡ Id (Vgs = Vds = Vdd ) diameter on the intrinsic CNTFET performance, showing
per CNT and the intrinsic delay τint ≡ L g Cinv Vdd /Ion are that a 2-nm-diameter CNT can deliver 27% higher intrinsic
plotted against the CNT diameter at a fixed OFF-state current drive current than a 1-nm-diameter CNT at L g = 8 nm. The
Ioff ≡ Id (Vgs = 0, Vds = Vdd ) = 1 nA per CNT. As shown VS-CNTFET model has been implemented in Verilog-A and
in Fig. 10, a 2-nm-diameter CNT can deliver 27% higher Ion is available online [23]. The model runs smoothly in the
and 21% lower τint than a 1-nm-diameter CNT. While μ ∼ d 2 SPICE environment (as illustrated in [61]) because all the
has been observed experimentally in CNTFETs with relatively equations are analytical with no numerical iterations, and
long channels (L g > 4 μm) [39], here, we predict the ratio the output current is differentiable throughout all regions of
of Ion (d = 2 nm) over Ion (d = 1 nm) to be 1.27, much operation. A more comprehensive analysis including nonideal
smaller than 22 /1 = 4, because the channel has become nearly contacts and tunneling leakage is carried out in [29].
ballistic at L g = 8 nm. The increase in Ion for large-diameter
CNTs is attributed to higher carrier mobility, velocity, and gate ACKNOWLEDGMENT
capacitance. The advantage of large-diameter CNTs in τint is The authors would like to thank Prof. L. Wei from
not as prominent as in Ion , since the gate capacitance is also the University of Waterloo, Prof. S. Rakheja from New York
higher. As will be seen in [29], the CNT diameter has greater University, and G. Hills and Prof. S. Mitra from Stanford
impacts on the parasitic contact resistance and the tunneling University for their useful discussions.
leakage currents in a highly scaled CNTFET.
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LEE et al.: COMPACT VS MODEL FOR CNTFETs 9

[55] L. Wei, O. Mysore, and D. Antoniadis, “Virtual-source-based Aaron D. Franklin (M’09–SM’15) received the
self-consistent current and charge fet models: From ballistic to Ph.D. degree in electrical engineering from Purdue
drift-diffusion velocity-saturation operation,” IEEE Trans. Electron University, West Lafayette, IN, USA, in 2008.
Devices, vol. 59, no. 5, pp. 1263–1271, May 2012. He is currently an Associate Professor with the
[56] (2013). International Technology Roadmap for Semiconductors. Department of Electrical and Computer Engineering,
[Online]. Available: http://www.itrs.net/Links/2013ITRS/Home2013.htm Duke University, Durham, NC, USA. His current
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short-channel MOSFETs,” IEEE Trans. Electron Devices, vol. 61, no. 2, tronic devices and low-cost printed electronics.
pp. 351–358, Feb. 2014.
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Instrum., vol. 82, no. 5, p. 053904, May 2011.
[60] M. V. Fischetti and S. E. Laux, “Performance degradation of small
silicon devices caused by long-range Coulomb interactions,” Appl. Phys.
Lett., vol. 76, no. 16, pp. 2277–2279, Apr. 2000. Wilfried Haensch (F’12) received the Ph.D. degree
[61] G. Hills et al., “Rapid exploration of processing and design guidelines from the Technical University of Berlin, Berlin,
to overcome carbon nanotube variations,” in Proc. Design Autom. Germany, in 1981.
Conf. (DAC), 2013, pp. 1–10. He started his career in Si technology at SIEMENS
Corporate Research Munich, Munich, Germany,
in 1984, where he was involved in high field trans-
Chi-Shuen Lee received the B.S. degree in port in MOSFETs. In 2001, he joined the IBM
electrical engineering from National Taiwan Research, Armonk, NY, USA. He has authored a
University, Taipei, Taiwan, in 2011, and the text book on transport physics, and has authored or
M.S. degree in electrical engineering from Stanford co-authored over 175 publications.
University, Stanford, CA, USA, in 2014, where he
is currently pursuing the Ph.D. degree.
His current research interests include modeling
and simulation of nanoscale MOSFETs and CMOS
technology assessment and benchmarking.

H.-S. Philip Wong (F’11) received the B.Sc. (Hons.)

Eric Pop (M’99–SM’11) received the B.S. and degree from The University of Hong Kong,
M.S. degrees from the Massachusetts Institute Hong Kong, the M.S. degree from Stony Brook
of Technology, Cambridge, MA, USA, and the
University, Stony Brook, NY, USA, and the
Ph.D. degree from Stanford University, Stanford, Ph.D. degree from Lehigh University, Bethlehem,
CA, USA. PA, USA.
He is currently an Associate Professor of Electrical
He joined Stanford University, Stanford, CA,
Engineering with Stanford University. His current USA, in 2004, as a Professor of Electrical Engi-
research interests include energy efficient electronics neering, where he is currently the Willard R. and
and data storage, novel 2-D and 1-D devices and Inez Kerr Bell Professor with the School of
materials, and energy conversion and harvesting.
Engineering.