Dear Editor:

Enclosed for your consideration is the revised manuscript of the paper MS# 5245R, entitled "A
Compact SPICE Model for Carbon Nanotube Field Effect Transistors Including
Non-Idealities and Its Application — Part I: Model of the Intrinsic Channel Region". As
such it belongs to the “Devices and Process Modeling” or the “Nanoelectronics” category.

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Author 1:

Jie Deng
Room CISX 300
Center for Integrated Systems
Stanford University
Stanford, CA 94305
Phone: 650-799-0121
Email: jdeng@stanford.edu

Author 2:

Prof. H.-S. Philip Wong

Center for Integrated Systems, CISX 312
Stanford University
Stanford, CA 94305
Phone: 650-725-0982
Fax: 650-725-7731
Email: hspwong@stanford.edu

Sincerely yours,
Jie Deng and H.-S. Philip Wong
 The estimated number of pages: 6

A Compact SPICE Model for Carbon Nanotube Field Effect Transistors

Including Non-Idealities and Its Application — Part I: Model of the Intrinsic
Channel Region
Jie Deng, student member, IEEE and H.-S. Philip Wong*, Fellow, IEEE

Center for Integrated Systems and Dept. of Electrical Engineering, Stanford, CA 94305
{jdeng, hspwong}@stanford.edu

Abstract. This paper presents a circuit-compatible compact model for the intrinsic channel

region of MOSFET-like single-walled Carbon Nanotube Field-Effect Transistors (CNFETs). This

model is valid for CNFET with a wide range of chiralities and diameters, and CNFET with either

metallic or semiconducting CNT conducting channel. The modeled non-idealities include the

quantum confinement effects on both circumferential and axial directions, the acoustical/optical

phonon scattering in the channel region, and the screening effect by the parallel CNTs for

CNFET with multiple CNTs. In order to be compatible with both large signal (digital)

applications and small signal (analog) applications, a complete trans-capacitance network is

implemented to deliver the real time dynamic response. This model is implemented with

HSPICE. Using this model, we project a 13× CV/I improvement of intrinsic CNFET with (19,0)

CNT over bulk n-type MOSFET at the 32 nm node. The model described in this paper serves as

a starting point towards the complete CNFET device model incorporating additional

device/circuit level non-idealities and multiple CNTs reported in [1].

Index Terms: CNFET, Compact Model, Analytical Model, Carbon Nanotube, SPICE, Intrinsic,

Ballistic, Screening Effect.

*
Author to whom correspondence should be addressed, Email: hspwong@stanford.edu

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1. Introduction

As one of the promising new transistors, CNFET avoids most of the fundamental limitations

for traditional silicon MOSFETs. With ultra long (~1μm) mean-free-path (MFP) for elastic

scattering, ballistic or near-ballistic transport can be obtained with intrinsic CNT under low

voltage bias to achieve the ultimate device performance [2,3,4,5]. The quasi-1D structure

provides better electrostatic control over the channel region than 3D device (e.g. bulk CMOS)

and 2D device (e.g. fully depleted SOI) structures [6].

Efforts have been made in recent years on modeling semiconducting CNFET [7,8,9,10] for

digital logic applications and CNT for interconnects [11,12] in order to evaluate the potential

performance at the device level. The reported compact models to date [7,8,9,10] used one or

more lumped static gate capacitances and an ideal ballistic transport model. These simplifications

make it questionable when evaluating the transient response and device dynamic performance.

The integral function used in [7,8] requires intensive calculation efforts and thereby makes it

difficult to implement in circuit simulators, e.g. HSPICE [13]. The polynomial fitting approach

used in [9] improves the run time significantly, but it makes evaluating CNFET performance

with different device parameters inconvenient. The simple coaxial or planer gate structures

utilized in [7,8,10] differ from the typical realistic CNFET gate structure that consists of high-k

gate oxide on top of SiO2 insulating bulk. For a CNFET with multiple parallel CNTs [3], these

published models cannot examine the multiple CNT-to-CNT screening effect on both the driving

current and the effective gate capacitance. To evaluate CNFET circuit performance with

improved accuracy, a CNFET device model with a more complete circuit-compatible structure

and also incorporating the typical device/circuit non-idealities is necessary.

Considering both the fabrication feasibility [14] and superior device performance of the

MOSFET-like CNFET as compared to the SB-controlled FET, we choose to focus on

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MOSFET-like CNFETs in this work. This paper models the intrinsic channel region of the

CNFET which serves as the first level modeling of the complete device model. This model

includes the quantum confinement on both the circumferential and the axial directions, the

acoustical/optical phonon scattering in the channel region, the screening effect by the parallel

CNTs for CNFET with multiple CNTs, and the intrinsic ac behavior which is delivered by a

dynamic gate capacitance network. The complete device model that includes the channel elastic

scattering, the doped source/drain region, Schottky barrier (SB) resistance, multiple CNTs per

device and other device/circuit non-idealities, and its applications are reported in [1]+. The

modeling approach and methodology described in this work is generally applicable to other 1-D

device, e.g. silicon nanowire FET [6], provided that the appropriate equations for the band

structure and/or density of states (DOS) are used.

This paper is organized as follows: First, we describe the device structure used for the

modeling. Next, we show both the mathematical expressions and the circuit representations of

each major component. Finally we will discuss the application of this model for a complete

device model for circuit simulation [1].

2. Device Structure

A typical layout of a MOSFET-like CNFET device is illustrated in Figure 1. The CNT

channel region is undoped, and the other regions are heavily doped, acting as both the

source/drain extension region and/or interconnects between two adjacent devices (un-contacted

source-gate/gate-drain configurations).

This paper describes the modeling of one single intrinsic channel of CNFET, as shown in

Figure 1 inset, which is a starting point towards the complete device model reported in [1]. For

MOSFET-like CNFET, since pFET behavior is similar to nFET, we only describe the equations

+
The model is available at https://www.stanford.edu/group/nanoelectronics/model_downloads.htm

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for nFET in this paper, though we implemented both nFET and pFET for the SPICE simulations.

3. Model of the Intrinsic Channel Region

This part models the intrinsic channel region of CNFET with near-ballistic transport, and

without any parasitic capacitance and parasitic resistance. The equivalent circuit model is shown

as Figure 2. Figure 2(a) is the equivalent circuit implemented with HSPICE, and Figure 2(b, c)

are the other two possible implementations for the trans-capacitance network which will be

discussed in Section 3.2.

The Fermi level profiles and the energy band diagram in the channel region with ballistic

transport are illustrated in Figure 3(a). The potential differences μs-μs’ and μd-μd’ are determined

by both the applied bias and the property of the source/drain extension regions. We will treat the

non-ballistic transport and the potential drop at the source/drain extension region and the

contacts in the complete device model [1]. We assume near-ballistic transport and ideal

(reflectionless) contacts in this paper, i.e. eVDS ≈ μd−μs, so μs (μd) remains almost constant in the

source-channel (drain-channel) region (Fig. 3(a)).

3.1 Current Sources

The single-walled carbon nanotube (SWCNT) is treated as quasi 1-D quantum wire in this

work. For SWCNT with chiralities (n1, n2), the diameter (DCNT) is given by (a = 2.49 Å is the

lattice constant) [15],

a n12 + n1n2 + n22

DCNT = (1)
π
SWCNTs can be grouped as either metallic nanotubes or semiconducting nanotubes [15].

For SWCNT with a finite length (Lg) and a finite diameter (DCNT), applying the Born-von

Karman boundary condition on both the circumferential direction and the axial (channel length)

direction, the E-k dispersion relation is quantized into discrete sub-states. We denote (m,l) as the

lth sub-state at the mth sub-band, km as the wave-number of the mth sub-band in circumferential

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th
direction, and kl as the wave-number of the l sub-state in current flow direction. We define the

sub-bands with positive band gap as “semiconducting sub-bands”, and the sub-bands with zero

or negative band gap as “metallic sub-bands”. Thus the band structure of metallic nanotubes can

be treated as a summation of metallic sub-bands and semiconducting sub-bands.

The wave numbers related with semiconducting sub-bands are given by [15,16],
2π
km = ⋅λ (2a)
a n12 + n1n2 + n22

 6m − 3 − (−1) m
 m = 1,2,... , mod(n1 − n2 ,3) ≠ 0
λ= 12 (2b)
 m m = 0,1,... , mod(n1 − n2 ,3) = 0

2π
kl = l , l = 0,1,2,... (2c)
Lg

m=0 is reserved for the metallic sub-band. kl approaches continuous values for large Lg.

Around the Fermi point with carrier energy Em,l << Vπ (~3.033eV, the carbon π-π bond energy in

the tight bonding model), CNT E-k dispersion relation can be approximated as [15],

3
Em ,l ≈ aVπ km2 + kl2 (3)
2
Em,l is the carrier energy at the (m,l) sub-state above the intrinsic level Ei, and Em,0 is the half

band gap of the mth sub-band.

We consider three current sources in CNFET model: (1) the thermionic current contributed

by the semiconduting sub-bands (Isemi) with the classical band theory, (2) the current contributed

by the metallic sub-bands (Imetal), and (3) the leakage current (Ibtbt) caused by the band to band

tunneling mechanism through the semiconducting sub-bands.

Isemi: For semiconducting sub-bands, we only consider the electron current for the nFET because

the hole current is suppressed by the n-type heavily doped source/drain. The current contributed

by the sub-state (m,l) is given by,

J m ,l (Vxs , ∆Φ B ) = 2envF (4)

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Vxs is potential difference between node x and source. The Fermi velocity vF=1/ћ∙∂E/∂kl.

The factor of 2 is due to electron spin degeneracy, e is the unit electronic charge, and n is the

number of electrons that occupy the sub-state (m,l), given by,

f FD( Em ,l + eVxs − ∆Φ B )
n= (5a)
Lg

1
f FD( E ) = (5b)
1 + e E / kT
∆ΦB is the channel surface potential change with gate/drain bias. fFD(E) is the Fermi-Dirac

distribution function. k is the Boltzmann constant and T is the temperature in Kelvin. Em,l is the

carrier energy at the substate (m, l).

With equations (4, 5), we obtain,

2e 3aπVπ kl 1
J m ,l (Vxs , ∆Φ B ) = ( Em ,l + eVxs − ∆Φ B ) / kT
(6)
h Lg k + k 1+ e
2
m l
2

The total current contributed by all sub-states is equal to the current flowing from the drain

to the source (+k branch) minus the current flowing from the source to the drain (-k branch),

I semi (Vch ,DS ,Vch ,GS ) = 2∑∑ [TLR J m,l (0, ∆Φ B ) +k − TRL J m ,l (Vch,DS , ∆Φ B ) −k ]
M L
(7)
km kl
m =1 l =1

Vch,DS and Vch,GS denotes the Fermi potential differences near source side within the channel.

The factor of 2 is due to the double-degeneracy of the sub-band. M and L are the number of

sub-bands and the number of sub-states, respectively. For typical devices with appropriate

diameter range (DCNT < 3nm) and short gate length (Lg ≤ 100nm), only the first 2 or 3 sub-bands

and the first 10~15 sub-states have a significant impact on the current using a sub-1V power

supply. Including more sub-bands should be done with more caution due to two limitations: (1)

the band structure model used in this work requires Em,l << Vπ, (2) the complex phonon modes at

high energy level. For long channel devices (Lg > 100nm), one can either approximate the current

for short device equation (7) by setting Lg=100nm in equations (2c, 5a, 6), or use the long

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channel model introduced in equation (14) below. TLR and TRL are the transmission probability of

the carriers at the sub-state (m,l) in +k branch and –k branch, respectively. We consider three

typical scattering mechanisms in the channel region: (1) acoustic phonon scattering (near elastic

process [5]), (2) optical phonon scattering (inelastic process [4]), and (3) elastic scattering. The

elastic scattering probability is assumed to be independent of the carrier energy, and will be

treated in the complete device modeling [1]. Both the acoustic phonon scattering and optical

phonon scattering depend on the carrier energy. Only intra-band scatterings are considered in this

paper. Random angle scatterings are suppressed and only backscattering and forward scattering

can occur in a 1-D quantum wire due to the Pauli’s Exclusion principle and the confined k-space

[17]. A scattering event from the sub-state (m,l1) in +/-k branch to the sub-state (m,l2) in -/+k

branch can occur only if two conditions are satisfied: (1) the sub-state (m,l1) is filled with

electrons. (2) the sub-state (m,l2) is empty so it can accept the scattered carrier from (m,l1).

Assuming the optical phonon scattering mean free path (MFP) (λop ~ 15 nm [18]) and the

acoustic phonon scattering MFP (λap ~ 500 nm [19]) are constant if both conditions are met, we

normalize the effective acoustic phonon scattering MFP (lap) and the effective optical phonon

scattering MFP (lop) of the semiconducting sub-bands to the available target empty states,

λap Do
lap (Vxs , m, l ) = (8a)
D ( Em ,l )[1 − f FD ( Em,l − ∆Φ B + eVxs )]

λop Do
lop (Vxs , m, l ) = (8b)
D ( Em ,l − hΩ)[1 − f FD ( Em ,l − hΩ − ∆Φ B + eVxs )]

ħΩ (~0.16eV [18]) is the optical phonon energy that a carrier attains before a optical phonon

scattering can occur. Optical phonon scattering becomes more significant at high Vch,DS bias. Do

is a constant 8/(3πVπ∙d) where d is the carbon-carbon bond distance, about 0.144 nm. D(E) is the

CNT universal density of states (DOS) which is valid in the range Em,l << Vπ [15],

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D ⋅ E / E 2 − E 2 E > Em , 0
D(E ) =  0 m, 0
(9)
 0 E ≤ Em , 0

The effective phonon scattering MFP is in the form of,

1 1 1
= + (10)
leff (Vxs , m, l ) lap (Vxs , m, l ) lop (Vxs , m, l )

It is reasonable to assume that the phonon back-scattered carriers are not likely to be

back-scattered again due to the energy loss and/or the occupied states. Thus the transmission

probabilities in equation (7) are given by,

leff (Vch ,DS , m, l )

TLR = (11a)
leff (Vch ,DS , m, l ) + Lg

leff (0, m, l )
TRL = (11b)
leff (0, m, l ) + Lg

The key parameter for evaluating CNFET current is ∆ΦB, the channel surface potential

change in response to changes in gate and source/drain bias. As shown in Figure 3(b), there are

three electrostatic coupling capacitors assuming the channel material is with infinite DOS: the

capacitance (Cox) between the gate and channel, the capacitance (Csub) between channel and

substrate, and the capacitance (Cc) between channel and external drain (D’) / source (S’). ∆ΦB is

dynamically affected by the drain bias. βCc is a fitting parameter that describes this effect due to

two mechanisms: (1) the surface potential lowering due to the electrostatic coupling between the

channel region and the external drain electrode through fringing electric field; (2) the surface

potential lowering due to non-uniform channel surface potential profile caused by DIBL effect.

Operationally, the parameters Cc and β are chosen to fit the sub-threshold slope and the measured

short channel effect. For a semiconducting channel with a finite DOS, the channel surface

potential ∆ΦB changes with the gate bias at a rate ∆ΦB/ΔVGS < 1, a phenomenon known as the

effect of quantum capacitance. We calculate ∆ΦB using the charge conservation equations,

Qcap = QCNT (12a)

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∆Φ B
Qcap = Cox (Vch,GS − VFB ) + C subVch,BS + β CcVch,D 'S + (1 − β )CcVch,S 'S − (Cox + Csub + Cc ) (12b)
e
4e M L
 1 1 
QCNT =
Lg
∑∑ 1 + e ( Em , l −∆Φ B ) / kT
+
1+ e
( Em ,l − ∆Φ B + eVDS ) / kT 
(12c)
km kl
m =m 0 l =0

1 , mod(n1 − n2 ,3) ≠ 0
m0 =  (12d)
0 , mod(n1 − n2 ,3) = 0
The factor of 4 includes both the spin degeneracy and the double-degeneracy of the

sub-band. VFB is the flat band voltage, and VBS is the potential difference between substrate and

source. Qcap is the charge induced by the electrodes, and QCNT is the total charge induced on

SWCNT surface. We solve equation (12) iteratively using a construct in HSPICE (Fig. 2(a)).

The front gate capacitance Cox is modeled as a planar gate structure with high-k gate

dielectric on top of SiO2 insulating layer (Fig. 1). For the device with multiple SWCNTs in

parallel, Cox is grouped into the capacitance between gate and SWCNT at the two ends (Cox_e),

and the capacitance between gate and SWCNT in the middle (Cox_m) [20]. For SWCNT of 1.5 nm

diameter with 4 nm thick HfO2 (k1=16) and 5 nm inter-CNT spacing, Cox_e = 246 aF/μm and

Cox_m = 186 aF/μm. The substrate to gate capacitance Csub can either be calculated similarly if a

double gate device is desired, or be calculated with the simple equation, Csub = 2πk2ε0/ln(2Hsub/r).

For a long channel device (Lg >> 100 nm), the wave number kl can be represented as a

continuous variable. By replacing the inner summation with the integral function and assuming

TLR=TRL=Tm, equation (7) can be simplified as,

4e 2 M  kT  1 + e m , 0 B
( E −∆Φ ) / kT

I semi (Vch ,DS , Vch ,GS ) ≈ ∑ Tm ⋅ Vch,DS + e ln  1 + e( Em ,0 −∆ΦB +eVch ,DS ) / kT
 
 (14)
h km
m =1
  

The above equations utilize the approximated SWCNT band structure (Equ. 2, 3) which is

valid in the range Em,l << Vπ. A more accurate model can be obtained by replacing the simplified

band-structure with the tight binding model [21] at the cost of more intensive calculations (~3x),

or an exact analytical form valid only for achiral CNTs [22]. Little difference is found for both

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the E-k relationship and the current drive in low energy range (Fig. 4). The chirality difference

for SWCNTs with the same diameter can also be ignored for our purpose, in the range where the

carrier energy is less than 1.0 eV (Fig. 4).

Imetal: For metallic sub-bands of metallic nanotubes, the current includes both the electron
current and the hole current,

[ ]
L
I metal = 2(1 − m0)Tmetal ∑ J ele _ 0 ,l + J hole _ 0,l (15a)
kl
l =1

2e 3aπVπ
J ele _ 0,l = ( f FD( E0,l − ∆Φ B ) − f FD( E0,l + eVch,DS − ∆Φ B ) ) (15b)
h Lg

2e 3aπVπ
J hole _ 0,l = ( f FD(− E0,l − ∆Φ B ) − f FD(− E0,l + eVch,DS − ∆Φ B )) (15c)
h Lg

The transmission probability Tmetal is given by,

λap λop
Tmetal = (16)
λap λop + (λap + λop ) ⋅ Lg

If the summation function is replaced with an integral, equation (15) can be simplified to,

4e 2
I metal = (1 − m0) TmetalVch , DS (17)
h

Thus Imetal is independent of the channel surface potential change ∆ΦB as expected because

the DOS of metallic CNT is independent of the carrier energy. For metallic CNTs of less than 3

nm in diameter, the half band-gap of the first semiconducting subband is larger than 0.43 eV.

Considering the large quantum capacitance of metallic CNT and the typical gate electrostatic

capacitance discussed in Section 4, the semiconducting subbands in a metallic CNT are not likely

to be populated in and thereby contribute to the current with sub-1V power supply.

Ibtbt: In the sub-threshold region, especially with negative gate bias (nFET), the

band-to-band tunneling (BTBT) current from drain to source becomes significant. As shown in

Figure 5, there are two possible tunneling regions: the “n” shape region 1 and the “L” shape

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region 2. With Vch,DS > E1,0, the tunneling through the drain junction in region 1 causes holes

(electrons) pile up in the nFET (pFET) channel region because the source junction prohibits the

holes (electrons) from escaping away. The hole (electron) pile up results in surface potential

lowering and thereby a higher current and worse sub-threshold behavior [23]. Little such effect is

observed for well-tempered devices [14]. To simplify the modeling, we ignore this effect in this

work. Because the tunneling through the source junction in region 1 is prohibited, we only

consider the BTBT current through the drain junction in region 2. Assuming ballistic transport

for the tunneling process, the BTBT current is approximated by the BTBT tunneling probability

(Tbtbt) times the maximum possible tunneling current integrating from the conduction band at

drain side up to the valance band at source side,

M   1 + e (eVch , DS − Em , 0 −E f ) / kT  max( eVch, DS − 2 Em, 0 ,0) 

4e
I btbt = kT ⋅ ∑ Tbtbt ln  ( Em , 0 − E f ) / kT
⋅
  (18)
h 
km   1+ e  eVch ,DS − 2 Em , 0 
m =1

Ef is the Fermi level of the doped source/drain nanotube in units of eV. Following the work

of Kane [24,25], the WKB-like transmission coefficient is given by,

π2  πm*(1 / 2 ) (η m 2 Em, 0 )3 / 2 
Tbtbt ≈ exp − 
 (19)
9  2 3/ 2
e ⋅ h ⋅ F 
ηm is a fitting parameter, set to 0.5 in this work, which represents the band gap narrowing
effect under high electrical field [26,27]. F = (Vch,DS + (Ef − ∆ФB)/e)/lrelax is the electrical field
triggering the tunneling process near the drain side junction. The potential drop across
channel-drain junction is assumed to relax over the distance lrelax which affects both BTBT
current slope and its magnitude. m* is the effective electron mass, defined as ћ2/(∂2Em,l/∂kl2) +.
3.2 Trans-Capacitance Network

To model the intrinsic ac response of CNFET device, we use a controlled trans-capacitance

array among the four electrodes (G, S, D, B) with the Meyer capacitor model [28]. CIJ is the

mathematically derived trans-capacitance per unit gate length (Lg) between the node i and node j,

+
m* is about 0.05mo and 0.10mo for the carriers in the 1st and the 2nd (semiconducting) sub-band, respectively, where
mo is the electron rest mass.

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defined as |∂QI/∂VJ|. The actual trans-capacitance in the channel region is Cij = CIJLg (Fig. 2(a)).

First, we consider the source/drain capacitance with respect to gate/substrate voltage

variation. There are two methods to assign the charges in channel region to the source and the

drain: (1) assuming near-ballistic transport in the channel, the carrier distribution along the

channel should be almost uniform, i.e. Qs,ch ≈ Qd,ch=Qcap/2=QCNT/2; (2) all the carriers from +k

branches are assigned to the source and all the carriers from −k branches are assigned to the drain.

The first approach is more reasonable in representing the physical meaning of the capacitor (a

carrier reservoir which does not distinguish where the carriers come from), while it may result in

Cij ≠ Cji. We first discuss the former (charge separation) approach which results in the equivalent

circuit model in Figure 2(a). All the carriers in both the channel region and the source/drain

nodes (Fig. 3(b)) come from the (external) source and drain electrodes, thus QS = Lg∙ (Qcap/2 +

(1−β)Cc∙∆ΦB) and QD = Lg∙(Qcap/2 + βCc(∆ΦB−VDS)). We denote the total electrostatic coupling

capacitance per unit length between channel and other electrodes as Ctot=Cox+Csub+Cc. Taking the

partial dirivative of QS and QD over VG, we obtain,

Lg  1 Ctot − 2(1 − β )Cc 

C sg =  Cox −  (20a)
2  e ∂VG / ∂∆Φ B 

Lg  1 Ctot − 2β Cc 
Cdg =  Cox −  (20b)
2  e ∂VG / ∂∆Φ B 

∂VG/∂∆ΦB can be calculated by equating ∂Qcap/∂∆ΦB and ∂QCNT/∂∆ΦB with fixed Vch,S, Vch,D

and VB using Equ. (12b, 12c),

∂VG
=
1
∂∆Φ B eCox
(Ctot + CQs + CQd ) (21a)

4e 2 M L  e( Em ,l −∆Φ B ) / kT 
CQs =
Lg ⋅ kT
∑∑  (1 + e( Em ,l −∆ΦB ) / kT ) 2  (21b)
k m kl  
m =m 0 l = 0

4e 2 M L  e ( Em ,l −∆Φ B +eVch , DS ) / kT 
CQd =
Lg ⋅ kT
∑∑  (1 + e( Em,l −∆ΦB +eVch,DS ) / kT ) 2  (21c)
k m kl  
m =m 0 l = 0

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We define CQs and CQd as the quantum capacitance due to the carriers from source (+k

branch) and drain (−k branch), respectively. With small gate bias (Em,0>>∆ΦB), ∂VG/∂∆ΦB ≈

Ctot/(eCox), thus the channel acts as a linear voltage divider which has little dependence on

quantum capacitance. With large gate bias (Em,0 < ΔΦB), ∂VG/∂∆ΦB > Ctot/(eCox), thus the surface

potential will be limited by the quantum capacitance. With equations (20, 21), we obtain,

Lg Cox CQs + CQd + 2(1 − β )Cc

C sg = (22a)
2 Ctot + CQs + CQd

Lg Cox CQs + CQd + 2 β Cc

Cdg = (22b)
2 Ctot + CQs + CQd

We can follow a similar approach to calculate the capacitance Csb and Cdb as

Csb=Csg∙(Csub/Cox) and Cdb=Cdg∙(Csub/Cox), respectively.

The charges accumulated on the gate and substrate (back gate) electrodes are given by

QG=Lg∙Cox∙(VGS−VFB−∆ΦB) and QB= Lg∙Csub∙(VBS−∆ΦB), respectively. With a similar approach,

the coupling capacitance between the gate and the substrate is derived as,

Lg C sub Cox
Cbg = C gb = (23)
Ctot + CQs + CQd

Next, we consider the gate/substrate capacitance due to source/drain voltage variation. With

the similar approach as above, we obtain,

Lg Cox [CQs + (1 − β )Cc ]

C gs = (24a)
Ctot + CQs + CQd

Lg Cox (CQd + β Cc )
C gd = (24b)
Ctot + CQs + CQd

C sub
Cbs = C gs (24c)
Cox

C sub
Cbd = C gd (24d)
Cox
The above equations give the values of the 9 capacitors in Figure 2(a). If we use the second

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 The estimated number of pages: 6

channel charge separation approach (+k carriers for source and −k carriers for drain),

reciprocality is guaranteed and Csg=Cgs, Cdg=Cgd, Csb=Cbs, and Cdb=Cbd, thus the gate

capacitance network can be simply represented by the 5-capacitor model in Fig. 2(b), or by the

6-capacitor model, as shown in Fig. 2(c), that shows explicitly the electrostatic capacitance and

the quantum capacitance with the same transfer function as the 5-capacitor model.

4. Discussion

Figure 6 shows the intrinsic channel current with incremental non-idealities. Assuming

ballistic transport, there is little difference (< 3%) between the on-current for an infinitely long

gate length and the on-current for a 100 nm gate length device, thus it is reasonable to assume

the ideal device current drive with gate length longer than 100 nm to be independent of the gate

length. With 32 nm gate length, the on-current is about 90% of the long channel value. This

slight ballistic current drop from long channel device to short channel device is due to the energy

quantization (kl quantization) in the axial direction. Phonon scattering in the 32 nm long channel

region further reduces the on-current by ~7%. BTBT current is only significant with high Vds

bias, and the sub-threshold slope gets worse with larger electrostatic capacitance between the

channel and the substrate (the inset in Fig. 6).

The intrinsic on-current (Ion@Vds=Vgs=0.9V) dependence on the gate length is illustrated in

Figure 7. With ideal ballistic transport, the on-current is almost constant with respect to the gate

length except for a slight current drop for short gate lengths (Lg < 100 nm) due to the energy

quantization in the axial direction. This small current drop is likely to be smeared out by phonon

scattering in practice. Optical phonon scattering depends on the carrier energy. A smaller current

means a smaller number of high-energy carriers, and therefore there is less chance that optical

phonon scattering can occur. As a result, the current reduction rate with only optical phonon

scattering becomes smaller as Lg increases because optical phonon scattering rate decreases as

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current decreases. Optical phonon scattering is important for short channel device due to its short

MFP (~15nm). Acoustic phonon scattering with longer MFP (~500nm) continues to be important

as Lg increases as the acoustic phonon energy is small (assuming zero in the model), and

therefore acoustic phonon scattering has a weak dependence on the carrier energy. Diffusive

transport (Ion ∝ 1/Lg) dominates as Lg increases and acoustic phonon scattering increases.

For the device with multiple CNTs, screening by the parallel CNTs affects both the gate to

channel capacitance and the current drive (Fig. 8). With a typical realistic gate structure (3 nm

thick HfO2), the currents carried by the individual CNTs are almost identical if the inter-CNT

pitch is larger than 20 nm. A factor of 2 reduction in current can be observed for dense CNT

array (~ 2.5 nm inter-CNT pitch). The screening effect should be seriously taken into account

when designing high-performance CNFET circuits to avoid overestimating the circuit

performance.

Two types of CNFET device connections and the resultant trans-capacitances are illustrated

by Figure 9. All the capacitances are non-linear components which depend on the bias due to the

energy-dependent DOS. With MOS-CAP connection (Fig. 9(b)), the two peaks correspond to the

position of the first two sub-bands (~0.3eV for the 1st subband and ~0.6eV for the 2nd subband,

for (19,0) CNT). This property can potentially be used to determine the nanotube diameter once

the gate capacitance is measured [29]. The CNFET effective gate capacitance for one CNT per

gate is about 3.6 aF with 18 nm physical gate length, which is about 4% of the bulk CMOS gate

capacitance (predictive BSIM model [30,31,32]) with minimum gate width (48 nm) at the 32 nm

node. Considering the large drive current which can be delivered by a single CNT

(~35μA@Vdd=0.9V, ~50% of the bulk n-type MOSFET on-current with 48 nm gate width), the

CV/I improvement of intrinsic CNFET over bulk MOSFET device is about 13× better. This large

improvement comes from both the much higher carrier velocity of CNT with ballistic transport

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(the Fermi velocity vF,CNT ≈ 8.0×107 cm/s, vF,si ≈ 2.5×107 cm/s), and the large parasitic gate

capacitance of MOSFET device. We will show in [1] that this optimistic performance advantage

is not achievable in a practical device structure and will be significantly degraded by the

device/circuit non-idealities, including the series resistance of doped source/drain region, the

Schottky barrier (SB) resistance at the metal/CNT interface, the gate outer-fringe capacitance,

and the interconnect wiring capacitance.

5. Summary

We present a circuit-compatible compact model of the intrinsic channel region of

MOSFET-like single-walled Carbon Nanotube Field-Effect Transistors (CNFETs) including

some channel region non-idealities. Comparison with a more accurate device model using the

tight binding band structure model shows that this model is valid for CNFET with a wide range

of chiralities and diameters. This model uses a sub-state summation approach, instead of the

integral, to calculate the parameters. This approach makes the modeling methodology described

in this paper is generally applicable to other 1-D devices, e.g. silicon nanowire FET, and requires

less computation efforts, thereby is more compatible with a circuit simulator. The complete

dynamic gate capacitance network makes the model suitable for both small signal (analog) and

large signal (digital) applications. This model serves as a start point towards the complete

CNFET device model including device/circuit level non-idealities and multiple CNTs which is

reported in [1].

Acknowledgements
This work is supported in part by a grant from the SRC. The support and encouragement of Dr. J. Hutchby

(SRC) and Dr. W. Haensch (IBM) are gratefully acknowledged. We thank N. Patil, G. C. Wan, A. Lin, and Prof. S.

Mitra at Stanford University for many useful discussions.

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Figure Captions:

Figure 1. The 3-D device structure of CNFETs with multiple channels, high-k gate dielectric

material, and the related parasitic gate capacitances. In this example, three CNFETs are

fabricated along one single CNT. The channel region of CNTs is un-doped, and the other regions

of CNTs are heavily doped. The inset shows the 3-D device structure of CNFET that is modeled

in this paper, with only the intrinsic channel region.

Figure 2. The equivalent circuit model for the intrinsic channel region of CNFET. (a) The

9-capacitor model assuming the carrier distribution along the channel is uniform. Exxx is the

voltage controlled voltage source, and the potential of Vxxx equals to the controlling voltage

source. Rdummy is a large value (>1E15) resistor to keep the circuit stable. (b) The 5-capacitor

model, and (c) the 6-capacitor model, assuming all the carriers from +k branches are assigned to

the source and all the carriers from −k branches are assigned to the drain.

Figure 3. (a) Ideal CNFET with ballistic (intrinsic) channel. Superposed are the Fermi level

profiles (solid arrows) from source to drain and the energy band diagram (dashed lines) with bias

VDS = (μd−μs)/e. (b) The electrostatic capacitor model used to calculate the channel surface

potential change ΔΦB before and after Gate/Source/Drain/Substrate bias. All the node potentials

are referred to the input source Fermi level. Superposed is the energy band diagram (only the

first sub-band shown) from the external source node S’ to the external drain node D’.

Figure 4. The comparison of the band structure calculated by the simple model used in this work

(the dotted curves) and the corresponding results calculated using tight binding models with the

same CNT diameter (1.5nm) for three different chiralities (the solid curve is for (19,0) CNT, the

dot-dashed curve is for (18,2) CNT, and the dashed curve is for (16,5) CNT). The simple model

matches well with the tight banding models for the first two subbands with Em,l < 1.0 eV, and

significant discrepancies among the four models are found for the 3rd and higher subbands with

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 The estimated number of pages: 6

Em,l > 1.0 eV.

Figure 5. Energy band diagram (only the first sub-band is shown) and the associated Fermi levels

at source/drain side for CNFET with moderate gate and drain bias. There are two possible

tunneling regions: region 1 and region 2, which are shaded on the plot. We only consider the

tunneling through region 2 in this work.

Figure 6. The drain current @ (Vgs=0.9V, VFB=0V) for (19, 0) chirality CNFET with incremental

non-idealities. The front gate dielectric material is 3 nm thick HfO2 on top of 10 μm thick SiO2

insulating layer. Inset plot shows the drain current as a function of Vgs with different channel to

substrate electrostatic capacitance.

Figure 7. The on-current @ (Vgs=Vds=0.9V) as a function of the gate length Lg. With ballistic

transport, the on-current is almost constant for long gate (Lg > 100 nm) CNFET, and there is a

slight drop in on-current for short gate (Lg < 100 nm) CNFET due to energy quantization in the

axial direction. Optical phonon scattering is important for shorter gate lengths because of its

short MFP (~15nm). Acoustic phonon scattering continues to be important as Lg increases.

Figure 8. For CNFET with multiple parallel CNTs, the CNT to CNT screening reduces both the

gate to channel electrostatic capacitance (inset) and the drain current. For a typical gate structure

with 3 nm thick HfO2 gate dielectric material, the screening effect is easily observable when the

inter-CNT pitch is smaller than 20 nm.

Figure 9. (a) The trans-capacitances CIJ per unit length as a function of Vds @ (Vgs=0.9V), and (b)

the gate and substrate node capacitances (Cgg and Cbb) per unit length as a function of the

channel surface potential ΔΦB, for (19,0) semiconducting CNFET at room temperature (T=300K).

The flat band voltage is zero. The front gate dielectric is 3 nm thick HfO2 on top of 10 μm thick

SiO2 insulting layer.

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Figures:

Intrinsic CNT channel

Gate

Substrate
Cgtg
CNTs
Cof_e
Metal Cof_m
Cof_e
Gate
HfO2

Lg Lsd
Gate Dielectric k1
Bulk Dielectric k2
Substrate

Figure 1.

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(a)

(b)

(c)

Figure 2.

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Doped CNT
Metal Gate
S Intrinsic CNT D
μs
μ s’
μd ’ Ec
μd
Chemical potential difference
EV across the channel

Substrate
(a)

∆ΦB
e

(b)

Figure 3.

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1.5

1 3rd
E (eV)

2nd

0.5
(16,5)

1st
(18,2)
(19,0)
0
-1 -0.5 0 0.5 1
Kl 9
x 10

Figure 4.

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μs
Ef
μd’
1
μs’
Ef
2 μs-μs’-2E1,0 μd

2E1,0

Figure 5.

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 The estimated number of pages: 6

Different non-idealities Infinite channel length

50
100 nm channel length
32 nm channel length
ap scattering
40 (MFP=500nm)
op scattering
(MFP=15nm)
-4
10
30 Csub=20aF/μm
I d (μA)

-6
10

-8

20 10 Ibtbt Csub=200aF/μm
I d (A)

-10
10

Vds =0.9V
10 10
-12
Vds =50mV

-0.2 0 0.2 0.4 0.6 0.8

V gs (V)
0
0 0.2 0.4 0.6 0.8
V (V)
ds

Figure 6.

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Short channel Long channel

45
ap E
40 μs
μd
35
k
30
I (μA)

25 Limited by Limited by
d

op scattering ap scattering
20 op
Ideal, Ballistic E
15 ap Scattering μd μs
10 op Scattering
ap+op Scattering k
5 -7 -6 -5
10 10 10
L (m)
g

Figure 7.

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 The estimated number of pages: 6

40 On-Current: Edge
On-Current: Middle
35

300
30
Id (μA)

C gc (aF/μm)

250
25 3nm
C N T HfO2
200 SiO2
20
C
edge
150 C
15 mid

5 10 15 20
Inter-CNT Pitch (nm)
10
5 10 15 20
Inter-CNT Pitch (nm)

Figure 8.

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 The estimated number of pages: 6

250
Cdg, Csg
Capacitance (aF/μm) 200

150 Vds
Cgs 0.9V
100 CNFET

50 Cdb, Csb Cgd

0
Cgb
0 0.2 0.4 0.6 0.8
V ds (V)

(a)
2nd subband
250 1st subband
Capacitance (aF/μm)

200

150 Cgg
= Cgs + Cgd
100

Cgb
50 Cbb = Cbs + Cbd

0
0 0.2 0.4 0.6
Surface Potential ΔΦB (eV)

(b)

Figure 9.

30