Unit-3

Control Unit

Computer Organization & Architecture(BMC-105) Slides Prepared By- Prof Asheesh Pandey
 Lecture-1
Instructions, Instruction Types and Instruction Format

Computer Organization & Architecture(BMC-105) Slides Prepared By- Prof Asheesh Pandey
Control Unit:- It effectively is the nerve center that sends signals to other units and senses their states. The actual timing
signals that govern the transfer of data between input unit, processor, memory and output unit are generated by the control
unit. To perform a given task, an appropriate program consisting of a list of instructions is stored in the memory. Individual
instructions are brought from the memory into the processor, which executes the specified operations.
Examples: - Add LOCA Ro
This instruction requires the performance in several steps:-
1. First the instruction is fetched from the memory into the processor.
2. The operand at LOCA is fetched and added to the contents of R0.
3. Finally, the resulting sum is stored in the register R0.

In different computers, same operation can be performed by “separate instructions” for performance reasons.-
1. Load LOCA R1
2. Add R1 R0

Register:- It is a special, high-speed storage area within the CPU. All data must be represented in a register before it can be
processed. For example, if two numbers are to be multiplied, both numbers must be in registers, and the resultant is also
placed in a register. (The register can contain the address of a memory location where data is stored rather than the actual
data itself.)
The number of registers that a CPU has and the size of each (number of bits) help determine the power and speed of a CPU.
For example, a 32-bit CPU is one in which each register is 32 bits wide. Therefore, each CPU instruction can manipulate 32
bits of data. In high-level languages, the compiler is responsible for translating high-level operations into low-level operations
that access registers.
Computer Organization & Architecture(BMC-105) Slides Prepared By- Prof Asheesh Pandey
INSTRUCTION- Instruction is a command to the processor to perform a given task on specified data. A computer instruction
refers to a binary code that controls how a computer performs micro-operations in a series. They are saved in the memory.
Every computer has its own set of instructions.
INSTRUCTION FORMAT- An instruction format or instruction code is a group of bits used to perform a particular operation on
the data stored in computer.
• Processor fetches an instruction from memory and decodes the bits to execute the instruction.
• Different computers may have their OWN instruction set.
• Suppose in a 16 bit instruction, First 12 bits (0-11) specify an address.
• Next 3 bits specify operation cod (opcode).
• Left most bit specify the addressing model I = 0 for direct address I = 1 for indirect address.

Computer Organization & Architecture(BMC-105) Slides Prepared By- Prof Asheesh Pandey
Computer Organization & Architecture(BMC-105) Slides Prepared By- Prof Asheesh Pandey
Computer Organization & Architecture(BMC-105) Slides Prepared By- Prof Asheesh Pandey
Computer Organization & Architecture(BMC-105) Slides Prepared By- Prof Asheesh Pandey
 Lecture-2
Types of Instructions, Instruction Cycle &
Sub Cycles (Fetch and Execute)

Computer Organization & Architecture(BMC-105) Slides Prepared By- Prof Asheesh Pandey
The number of address fields in the instruction format of a computer depends on the internal organization of its registers.
Mostly computers fall into one of three types of CPU organizations:-
1. Single accumulator organization 2. General register organization. 3 Stack organization.
The instruction can be classified as three, two, one address instruction or zero address instruction, depending on the number
of address fields. Four types of instructions are available on the basis of referenced address fields :
THREE-ADDRESS INSTRUCTIONS- Computers with three-address instruction formats can use each address field to specify
either a processor register or a memory operand. The program in assembly language that evaluates X = (A + B) ∗ (C + D) is
shown below:-
ADD R1, A, B R1 ← M [A] + M [B]
ADD R2, C, D R2 ← M [C] + M [D]
MUL X, R1, R2 M [X] ← R1 ∗ R2 OR MUL R3, R1, R2 R3 ← R1 ∗ R2
It is assumed that the computer has two processor registers, R1 and R2. The symbol M [X] denotes the operand at memory
address symbolized by X.
TWO-ADDRESS INSTRUCTIONS- Two address instructions are the most common in commercial computers. Here again each
address field can specify either a processor register or a memory word. The program to evaluate X = (A + B) ∗ (C + D) is as
follows:-
MOV R1, A R1 ← M [A]
ADD R1, B R1 ← R1 + M [B]
MOV R2, C R2 ← M [C]
ADD R2, D R2 ← R2 + M [D]
MUL R1, R2 R1 ← R1∗ R2
MOV X, R1 M [X] ← R1
The MOV instruction moves the operands to and from memory and processor registers.
Computer Organization & Architecture(BMC-105) Slides Prepared By- Prof Asheesh Pandey
ONE-ADDRESS INSTRUCTIONS- One-address instructions use an implied Accumulator (AC) register for all data manipulation. For
multiplication and division there is a need for a second register. However, here we will neglect the second and assume that the
AC contains the result of all operations. The program to evaluate X = (A + B) ∗ (C + D) is-
LOAD A AC ← M [A]
ADD B AC ← A C + M [B] All operations are done between the AC register and a memory
STORE T M [T] ← AC operand. T is the address of a temporary memory location
LOAD C AC ← M [C] required for storing the intermediate result.
ADD D AC ← AC + M [D]
MUL T AC ← AC ∗ M [T]
STORE X M [X] ← AC

ZERO-ADDRESS INSTRUCTIONS- A stack-organized computer does not use an address field for the instructions ADD and MUL.
The PUSH and POP instructions need an address field to specify the operand that communicates with the stack. The following
program shows how X = (A + B) ∗ (C + D) will be written for a stack organized computer.
PUSH A TOS ← A
PUSH B TOS ← B
ADD TOS ← (A + B) To evaluate arithmetic expressions in a stack computer, it is necessary to
PUSH C TOS ← C convert the expression into Reverse Polish Notation RPN. The name “zero-
PUSH D TOS ← D address” is given to this type of computer because of the absence of an
ADD TOS ← (C + D) address field in the computational instructions.
MUL TOS ← (C + D) ∗ (A +B)
POP X M [X] ← TOS
Computer Organization & Architecture(BMC-105) Slides Prepared By- Prof Asheesh Pandey
➢ Advantages of Zero-Address, One-Address, Two-Address and Three-Address Instructions-
Zero-address instructions-
• They are simple and can be executed quickly since they do not require any operand fetching or addressing. They also take up
less memory space.
One-address instructions-
• They allow for a wide range of addressing modes, making them more flexible than zero-address instructions. They also require
less memory space than two or three-address instructions.
Two-address instructions-
• They allow for more complex operations and can be more efficient than one address instructions since they allow for two
operands to be processed in a single instruction. They also allow for a wide range of addressing modes.
Three-address instructions-
• They allow for even more complex operations and can be more efficient than two-address instructions since they allow for
three operands to be processed in a single instruction. They also allow for a wide range of addressing modes.
➢ Disadvantages of Zero-Address, One-Address, Two-Address and Three-Address Instructions-
Zero-address instructions-
• They can be limited in their functionality and do not allow for much flexibility in terms of addressing modes or operand types.
One-address instructions-
• They can be slower to execute since they require operand fetching and addressing.
Two-address instructions-
• They require more memory space than one-address instructions and can be slower to execute since they require operand
fetching and addressing.
Three-address instructions-
• They require even more memory space than two-address instructions and can be slower to execute since they require
operand fetching and addressing.
Computer Organization & Architecture(BMC-105) Slides Prepared By- Prof Asheesh Pandey
INSTRUCTION CYCLE:-
1. A program residing in the memory unit of the computer consists of a sequence/set of instructions.
2. The program is executed in the computer is going through a cycle for each instruction.
3. Each instruction cycle is subdivided into a sequence of sub cycles or phases. From fetching of instruction to the completion of
execution of instruction whatever happens is called instruction cycle.
4. The instruction cycle (also known as the fetch–decode–execute cycle, or simply the fetch-execute cycle) is the cycle that the
central processing unit (CPU) follows from boot-up until the computer has shut down in order to process instructions.
5. The reason we called this cycle because it will happen for every instruction.

Each instruction cycle consists of the following phases:

• Fetch an instruction from memory.
• Decode the instruction.
• Read the effective address from memory
• Execute the instruction.

Computer Organization & Architecture(BMC-105) Slides Prepared By- Prof Asheesh Pandey
Instruction Fetch and Decode-

• The instruction fetch and decode phases are the same for all instructions, so the control functions and micro-
operations will be independent of the instruction code.
• Everything that happens in this phase is driven entirely by timing variables T0, T1, T2 and T3 etc.
Hence, all control inputs in the CPU during fetch and decode are functions of these three variables alone.
T0: AR ← PC
T1: IR ← M[AR], PC ← PC + 1
T2: AR ← IR(0-11), D0-7 ← decoded IR(12-14), I ← IR(15) For every timing cycle, we assume SC ← SC -1 unless it is
stated that SC ← 0.
The operation D0-7 ← decoded IR(12-14) is not a register transfer like most of our micro-operations, but
is consequence of loading a value into the IR register. Since the IR outputs 12-14 are directly connected to a
decoder, the outputs of that decoder will change as soon as the new values of IR(12-14) propagate through the
decoder.
Normal execution of a program may be preempted/temporarily interrupted, if some devices require
urgent servicing, to do this one device raises an Interrupt signal. An interrupt is a request signal from an I/O
device for service by the processor. The processor provides the requested service by executing an appropriate
interrupt service routine.
The Diversion may change the internal stage of the processor its state must be saved in the memory location before
interruption. When the interrupt-routine service is completed the state of the processor is restored so that the interrupted
program may continue.
Computer Organization & Architecture(BMC-105) Slides Prepared By- Prof Asheesh Pandey
Computer Organization & Architecture(BMC-105) Slides Prepared By- Prof Asheesh Pandey
 Lecture-3
1. Reduced Instruction Set Computer (RISC)
2. Complex Instruction Set Computer (CISC)
(Advantages and Characteristics)
3. Differences between RISC and CISC

Computer Organization & Architecture(BMC-105) Slides Prepared By- Prof Asheesh Pandey
 RISC and CISC in short-
RISC is the way to make hardware simpler whereas CISC is the single instruction that handles multiple work.
Reduced Instruction Set Computer (RISC)-
• Computers which use fewer instructions with simple constructs so they can be executed much faster within the CPU without
having to use memory as often are classified as RISC.
• Relatively few instructions and few addressing modes.
• Memory access limited to LOAD and STORE instructions as all operations done within the registers of the CPU.
• Fixed-length, easily decoded instruction format, single-cycle instruction execution.
• Hardwired rather than microprogrammed control.
• The small set of instructions of a typical RISC processor consists mostly of register-to-register operations, Thus, each
operand is brought into a processor register with a LOAD instruction. All computations are done among the data stored in
processor registers. Results are transferred to memory by means of store instructions.
• RISC is the most efficient CPU architecture
technology. This architecture is an evolution
and alternative to Complex Instruction Set
Computing (CISC).
• The main idea behind this is to simplify
hardware by using an instruction set
composed of a few basic steps for loading
and storing operations just like a load
command will load data, a store
command will store the data.

Computer Organization & Architecture(BMC-105) Slides Prepared By- Prof Asheesh Pandey
Characteristics of RISC-
•Simpler instruction, hence simple instruction decoding.
•Instruction comes undersize of one word.
•Instruction takes a single clock cycle to get executed.
•More general-purpose registers.
•Simple Addressing Modes.
•Fewer Data types.
•A pipeline can be achieved.

Advantages of RISC-
•Simpler instructions: RISC processors use a smaller set of simple instructions, which makes them easier to
decode and execute quickly. This results in faster processing times.
•Faster execution: Because RISC processors have a simpler instruction set, they can execute instructions faster
than CISC processors.
•Lower power consumption: RISC processors consume less power than CISC processors, making them ideal for
portable devices.

Disadvantages of RISC-
•More instructions required: RISC processors require more instructions to perform complex tasks than CISC
processors.
•Increased memory usage: RISC processors require more memory to store the additional instructions needed to
perform complex tasks.
•Higher cost: Developing and manufacturing RISC processors can be more expensive than CISC processors.
Computer Organization & Architecture(BMC-105) Slides Prepared By- Prof Asheesh Pandey
 Complex Instruction Set Computer (CISC)- The main idea is that a single instruction will do all loading, evaluating, and
storing operations just like a multiplication command will do stuff like loading data, evaluating, and storing it, hence it’s
complex.
Characteristics of CISC-
•Complex instruction, hence complex instruction decoding.
•Variable sized instructions set.
•Instructions are larger than one-word size.
•Instruction may take more than a single clock cycle to get executed.
•Less number of general-purpose registers as operations get performed in memory itself.
•Complex Addressing Modes.
Advantages of CISC-
•Reduced code size: CISC processors use complex instructions that can perform multiple operations, reducing the
amount of code needed to perform a task.
•More memory efficient: Because CISC instructions are more complex, they require more instructions to perform
complex tasks, which can result in more memory-efficient code.
•Widely used: CISC processors have been in use for a longer time than RISC processors, so they have a larger
user base and more available software.
Disadvantages of CISC-
•Slower execution: CISC processors take longer to execute instructions because they have more complex
instructions and need more time to decode them.
•More complex design: CISC processors have more complex instruction sets, which makes them more difficult to
design and manufacture.
•Higher power consumption: CISC processors consume more power than RISC processors because of their more
complex instruction sets. Computer Organization & Architecture(BMC-105) Slides Prepared By- Prof Asheesh Pandey
Differences Between RISC Vs CISC-

Computer Organization & Architecture(BMC-105) Slides Prepared By- Prof Asheesh Pandey
 Lecture-4

1. Hardwired v/s Micro-programmed Control Unit

2. Differences between Hardwired & Micro-programmed Control Unit
3. Program Control Instructions

Computer Organization & Architecture(BMC-105) Slides Prepared By- Prof Asheesh Pandey
Hardwired v/s Micro-programmed Control Unit-
➢ To execute an instruction, the control unit of the CPU must generate the required control signal in the proper sequence.
➢ There are two approaches used for generating the control signals in proper sequence as “Hardwired Control unit” and
“Micro-programmed control unit.”

Hardwired Control Unit –The control hardware can be viewed as a state machine that changes from one state to another in
every clock cycle, depending on the contents of the instruction register, the condition codes and the external inputs.
❑ The outputs of the state machine are the control signals.
❑ The sequence of the operation carried out by this machine is determined by the wiring of the logic elements and hence
named as “hardwired”.
❑ Fixed logic circuits that correspond directly to the Boolean expressions are used to generate the control signals.
❑ Hardwired control is faster than micro-programmed control.
❑ A controller that uses this approach can operate at high speed.
Characteristics:-
1. It uses flags, decoder, logic gates and other digital circuits.
2. As name implies it is a hardware control unit.
3. On the basis of input signal, output is generated.
4. Difficult to design, test and implement.
5. Hard to modify.
6. Faster mode of operation.
7. Expensive and high error.
8. Used in RISC processor.
Computer Organization & Architecture(BMC-105) Slides Prepared By- Prof Asheesh Pandey
Micro-programmed Control Unit –
1. The control signals associated with operations are stored in special memory units inaccessible by the programmer as
Control Words.
2. Control signals are generated by a program and are similar to machine language programs.
3. Micro-programmed control unit is slower in speed because of the time it takes to fetch micro instructions from the control
memory

Characteristics-
1. It uses sequence of micro-instructions in micro programming
language.
2. It generates a set of control signals on the basis of control
line.
3. Easy to design, test and implement. It is mid-way between
Hardware and Software.
4. Flexible to modify.
5. Slower mode of operation.
6. Cheaper and less error.
7. Used in CISC processor

Computer Organization & Architecture(BMC-105) Slides Prepared By- Prof Asheesh Pandey
Differences between Hardwired & Micro-programmed Control Unit-

Characteristics Hardwired Micro-programmed Control

1. Speed -Fast -Slow
2. Implementation -Hardware -Software
3. Flexibility -Not Flexible -Flexible
4. Ability to handle
Complex instruction set -Difficult -Easier
5. Design process -Difficult for more operation -Easy
6. Memory -Not Used -Control memory used
7. Chip efficiency -Uses less area -Uses more area
8. Used in -RISC -CISC

Computer Organization & Architecture(BMC-105) Slides Prepared By- Prof Asheesh Pandey
Program Control Instructions:- It’s the machine code that are used by machine or in assembly language by user to command the
processor act accordingly. These instructions are of various types. These are used in assembly language by user also. But in level
language, user code is translated into machine code and thus instructions are passed to instruct the processor do the task.
Types of Program Control Instructions:-
There are different types of Program Control Instructions as given below-
1. Compare Instruction:-Compare instruction is specifically provided, which is similar to a subtract instruction except the result is
not stored anywhere, but flags are set according to the result . Example: CMP R1, R2;
2. Unconditional Branch Instruction:- It causes an unconditional change of execution sequence to a new location.
Example: JUMP L2; Mov R3, R1; goto L2
3. Conditional Branch Instruction:- A conditional branch instruction is used to examine the values stored in the condition code
register to determine whether the specific condition exists and to branch if it does. Example: Assembly Code : BE R1, R2, L1
Compiler allocates R1 for x and R2 for y
4. Halting Instructions:- High Level Code: if (x==y) goto L1;
• NOP Instruction – NOP is “no operation.” It causes no change in the processor state other than an advancement of the PC
program counter. It can be used to synchronize timing.
• HALT – It brings the processor to an orderly halt and remains in an idle state until restarted by interrupt, trace, reset or
external action.
5. Interrupt Instructions:-
Interrupt is a mechanism by which an I/O or an instruction can suspend the normal execution of processor and get itself serviced.
a) RESET – It reset the processor. This may include any or all setting registers to an initial value or setting program counter to
standard starting location.
b) TRAP – It is non-maskable edge and level triggered interrupt. TRAP has the highest priority and vectored interrupt.
c) INTR – It is maskable edge and level triggered interrupt. It has the lowest priority. It can be disabled by resetting the
processor.
6. Subroutines:-
A subroutine is a program fragment that lives in memory space, performs a well-defined task. It is invoked by another user
program and RETURNS controlComputerto the CALLING
Organization program when finished.
& Architecture(BMC-105) Example:
Slides Prepared By- Prof AsheeshCALL
Pandey and RET
 Lecture-5
(21/11/24)

Microprogram Sequencer

Computer Organization & Architecture(BMC-105) Slides Prepared By- Prof Asheesh Pandey
Microprogram Sequencer-
1. A microprogram sequencer uses address to determine the next micro-instruction needs to be executed.
2. The address selection part is called a microprogram sequencer and process is known as microprogram
sequencing.
3. Microprogram sequencer is either an independent address range generator or a component of a CPU's
control unit.
4. The primary function of the control unit is to inform ALU, input/output device and computer’s memory about
how to respond or answer the given set of instructions. The Control unit does not involve in any processing
tasks.
5. Control unit only controls and directs the task. It acts as the supervisor of the computer, controlling all
activities of the computer including fetching instructions from the main memory and then executing them.

Functions of a microprogram sequencer:-

a) The basic components of a microprogrammed control unit are the control memory and the circuits which
select the next address.
b) The purpose of a microprogram sequencer is to present an address to the control memory so that a
microinstruction may be read and executed.
c) A micro-program sequencer's typical functions include incrementing the control address register by one,
loading an address from control memory into the control address register, transferring an external address,
and loading a starting address to initiate control operations.
Computer Organization & Architecture(BMC-105) Slides Prepared By- Prof Asheesh Pandey
Advantages-
The advantages of microprogram sequencing are as
following:-
a. The execution of instruction can be easily controlled by
microprogram sequencing.
b. It is easily modifiable due to how simple it is to update the
code.
c. It can also handle complicated instructions with ease.
d. A microprogram sequencing implementation is less
expensive.

Disadvantages-
The disadvantages of microprogram sequencing are as
following:-
1. It is a bit slower.
2. Larger storage spaces are made possible with the aid of
distinct micro routines for each device command.
3. More time was required for the branching instruction
implementation.

The block diagram of the microprogram sequencer is shown

in figure. →

Computer Organization & Architecture(BMC-105) Slides Prepared By- Prof Asheesh Pandey
 Lecture-6
(22/11/24)

Horizontal and Vertical Micro programmed Control Units

Computer Organization & Architecture(BMC-105) Slides Prepared By- Prof Asheesh Pandey
➢ The Control Unit plays a fundamental role in the management of instruction execution by regulating the use of
the processor, memory, and I/O devices.
➢ There exist mainly two methods for designing micro-programmed control units. These are-

1. Horizontal Micro programmed Control Units 2.Vertical Micro programmed Control Units.

Horizontal Micro-Programmed Control Unit- In this, the control signals are represented in the decoded binary
format, i.e., 1 bit/Control Signal. Here ‘n’ control signals require n bit encoding.
Features-

➢ Control Signals are Explicit: In this, every control signal is specified by a separate bit in the control word. It means, there is
direct control over all the microoperations and thus makes for a more flexible system and a faster system.
➢ Wide Control Word: In this, signals are specified individually. This results in longer instruction words, but it provides for
control over individual operations.
➢ Sequential Execution: More than one control signal can be excited simultaneously, due to which more parallel operations can
be performed in this system and hence it results in higher efficiency in executing instructions.

Advantages -
•It leads to faster implementation of the instructions since the control process is more parallel.
•Control signals for every control operation are explicitly specified hence it is easier to control complex micro-operations.

Drawbacks-
•High Memory Requirement: More memory is needed to store the microprograms since the size of the word is large.
•Complex Design: More lines in the control word leads to complexity both while designing and debugging.
Computer Organization & Architecture(BMC-105) Slides Prepared By- Prof Asheesh Pandey
Vertical Micro-Programmed Control Unit-

➢ Vertical Micro-programmed Control Unit uses encoded form of control signals.

➢ Instead of one bit per control signal in horizontal micro programmed control, in this multiple signals are encoded
into a shorter control word.
➢ In this unit, the control signals are represented in the encoded binary format. Here ‘n’ control signals require
log2n bit encoding.
Features-

•Encoded Control Signals: The control signals are compressed into fewer bits, and decoders are used to produce
actual control signals. This leads to control words that are shorter in length.
•Narrow control word: The length of control word is vertical micro-programming shorter as compared to horizontal
since it uses fewer bits due to the encoding of control signals. Since only few control signals are activated at any
given time, generally, vertical micro-programming results in operations as being more sequential.
Advantages-
•Less memory is needed: Shorter control word results in lesser memory to be used for storing of microprograms.
•Easier designing: Lesser number of control signals results in an easier and manageable system.

Disadvantages-
The Speed is Low: Because of the fact that control signals have been encoded and then decoded, it takes more time
than that of the horizontal micro-programming.
•Less Flexible: The control signals have been encoded; hence parallelism is limited and the flexibility of control over
several micro-operations simultaneously gets reduced.
Computer Organization & Architecture(BMC-105) Slides Prepared By- Prof Asheesh Pandey
 The micro-programmed control
unit can be classified into two
types, Differences between them
are-
Horizontal Micro-Program Control Unit-
• The horizontal micro-programmed
provides higher degree of parallelism
& it is suitable in multi-processor
system for multi tasking.
• It requires more bits for control
word.
Vertical Micro-Program Control Unit-
• The vertical micro-programming
reduces the size of control words by
encoding control signal before it is
stored in control memory.
• Vertical-programming has also the
lower degree of parallelism.

Computer Organization & Architecture(BMC-105) Slides Prepared By- Prof Asheesh Pandey
 Lecture-7
(20/11/24)

1. Pipelining-
2. Arithmetic Pipeline
3. Instruction Pipeline
4. Pipeline Hazards & Advantages of Pipeline

Computer Organization & Architecture(BMC-105) Slides Prepared By- Prof Asheesh Pandey
Pipelining-
1. Pipelining is a technique of decomposing a sequential process into sub-operations, with each sub-process being executed
in a special dedicated segment that operates concurrently with all other segments.
2. The processor executes a program by fetching and executing instructions, one after another.
3. Let Fi and Ei refer to the fetch and execute steps for instruction Ii .
4. Execution of a program consists of a sequence of fetch and execute steps as
shown into Fig. →
To better understand the pipeline organization, consider an
example of a combined multiplication and addition operation.
A stream of numbers is used to perform the combined
multiplication and addition operation, such as:
for i = 1, 2, 3, ……., 7
Ai* Bi + Ci The operation to be done on the numbers is
broken down into sub-operations, each of which is
implemented in a segment of a pipeline. We can define the
sub-operations performed in every segment of the pipeline
as:
R1 ← Ai, R2 ← Bi Input Ai, and Bi
R3 ← R1 * R2, R4 ← Ci Multiply, and input Ci
R5 ← R3 + R4 Add Ci to the product
The combined and sub-operations conducted in each leg of
the pipeline are depicted in the block diagram below:→Slides Prepared By- Prof Asheesh Pandey
Computer Organization & Architecture(BMC-105)
5. Now consider a computer that has two separate hardware units, one for fetching instructions and another for
executing them, as shown in Fig→
6. The instruction fetched by the fetch unit is deposited in an intermediated storage buffer Bi.
7. The results of execution are deposited in the destination location (Execution Unit) specified by the
instructions.
8. For these purposes, we assume that both the source and destination of the data operated in by the
instructions are inside the block labelled “Execution unit.”

Computer Organization & Architecture(BMC-105) Slides Prepared By- Prof Asheesh Pandey
1.Arithmetic Pipeline :- Example- A=263.69x105 , B=45826x103 A-B=?
• An arithmetic pipeline divides an arithmetic
problem into various sub problems for execution
in various pipeline segments.
• It is used for floating point operations,
multiplication and various other computations.
• The process or flowchart arithmetic pipeline for
floating point addition is shown in the diagram.
Floating point addition using arithmetic pipeline :
The following sub operations are performed in this
case:
1.Compare the exponents.
2.Align the mantissas.
3.Add or subtract the mantissas.
4.Normalize the result

Steps-
• First of all, the two exponents are compared and the
larger of two exponents is chosen as the result exponent.
• The difference in the exponents then decides how many
times we must shift the smaller exponent to the right.
• Then after shifting of exponent, both the mantissas get
aligned.
• Finally, the addition of both numbers take place followed
by normalization of the result in the last segment.
Computer Organization & Architecture(BMC-105) Slides Prepared By- Prof Asheesh Pandey
2. Instruction Pipeline :-

• In this pipelining, instructions can be executed by overlapping

fetch, decode and execute phases of an instruction cycle.
• This type of technique is used to increase the throughput of
the computer system.
• An instruction pipeline reads instruction from the memory
while previous instructions are being executed in other
segments of the pipeline.
• Thus, we can execute multiple instructions simultaneously.
• The pipeline will be more efficient if the instruction cycle is
divided into segments of equal duration.

In the most general case computer needs to process each

instruction in following sequence of steps:-

1.Fetch the instruction from memory (FI)

2.Decode the instruction (DA)
3.Calculate the effective address
4.Fetch the operands from memory (FO)
5.Execute the instruction (EX)
6.Store the result in the proper place

The flowchart for instruction pipeline is shown in fig.→

Computer Organization & Architecture(BMC-105) Slides Prepared By- Prof Asheesh Pandey
 Pipeline Hazards:- Pipeline Hazard is a potential discrepancy in the execution flow of a pipeline that manifests
when several instructions overlap during execution inside the pipeline, leading to conditions that can interrupt the
operation of the pipeline.

Different Types of Pipeline Hazards:-

•Structural Hazards: These occur when the same hardware resource is desired by multiple instructions at the
same time.
•Data Hazards: They come into play when the execution of one instruction depends on the completion of another.
•Control Hazards: These result from the pipelining of branches and other instructions that change the PC.

Advantages of pipelining:-
• The biggest advantage of pipelining is that it reduces the processor's cycle time.
• It increases the processor's overall throughput.
• It can process more instructions simultaneously, while reducing the delay between completed instructions.
• Pipelining doesn't reduce the time taken to perform an instruction. This would still depend on its size, priority and
complexity.

Computer Organization & Architecture(BMC-105) Slides Prepared By- Prof Asheesh Pandey